stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.

129 files changed, 94346 insertions, 92385 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 2bd7abaa8..b894ed506 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.887179                       # Number of seconds simulated
-sim_ticks                                1887179292000                       # Number of ticks simulated
-final_tick                               1887179292000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.886196                       # Number of seconds simulated
+sim_ticks                                1886195993000                       # Number of ticks simulated
+final_tick                               1886195993000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 271909                       # Simulator instruction rate (inst/s)
-host_op_rate                                   271909                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9140545464                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373988                       # Number of bytes of host memory used
-host_seconds                                   206.46                       # Real time elapsed on the host
-sim_insts                                    56138893                       # Number of instructions simulated
-sim_ops                                      56138893                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 256659                       # Simulator instruction rate (inst/s)
+host_op_rate                                   256659                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8626071053                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 374008                       # Number of bytes of host memory used
+host_seconds                                   218.66                       # Real time elapsed on the host
+sim_insts                                    56121694                       # Number of instructions simulated
+sim_ops                                      56121694                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           1052544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24858944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1049728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24850240                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25912448                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1052544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1052544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7556224                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7556224                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16446                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388421                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25900928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1049728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1049728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7553600                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7553600                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16402                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388285                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404882                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118066                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118066                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               557734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13172540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                404702                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118025                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118025                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               556532                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13174792                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13730782                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          557734                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             557734                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4003978                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4003978                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4003978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              557734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13172540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13731833                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          556532                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             556532                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4004674                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4004674                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4004674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              556532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13174792                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17734760                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404882                       # Number of read requests accepted
-system.physmem.writeReqs                       159618                       # Number of write requests accepted
-system.physmem.readBursts                      404882                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     159618                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25905920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8528320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25912448                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10215552                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   26335                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            157                       # Number of requests that are neither read nor write
+system.physmem.bw_total::total               17736507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404702                       # Number of read requests accepted
+system.physmem.writeReqs                       118025                       # Number of write requests accepted
+system.physmem.readBursts                      404702                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118025                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25894272                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7551808                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25900928                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7553600                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          41706                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               25487                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25681                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25706                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25753                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25164                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25107                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24789                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24544                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25200                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25299                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25393                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24991                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24525                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25570                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25834                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25728                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25822                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25769                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25085                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25016                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24650                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24524                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25293                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25190                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25398                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24986                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24522                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25563                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25828                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              25737                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8901                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8465                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9022                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8725                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8062                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8096                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7614                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7482                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8269                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7671                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8104                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7830                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8200                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9100                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8920                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8794                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7820                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7688                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8067                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7737                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7011                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6646                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6392                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7401                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6804                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7278                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6972                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7052                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8008                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7983                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7942                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          50                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1887170570500                       # Total gap between requests
+system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1886187226500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404882                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404702                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 159618                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402496                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        68                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118025                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2193                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        66                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -148,201 +148,188 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       78                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64763                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      531.696185                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     324.957517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.417041                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14664     22.64%     22.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11016     17.01%     39.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5432      8.39%     48.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3093      4.78%     52.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2464      3.80%     56.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1908      2.95%     59.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1486      2.29%     61.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1430      2.21%     64.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23270     35.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64763                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4906                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        82.503669                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3015.330482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           4903     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7084                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8808                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5494                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63594                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      525.931377                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     320.890659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     414.200803                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14460     22.74%     22.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10997     17.29%     40.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4933      7.76%     47.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3625      5.70%     53.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2479      3.90%     57.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1827      2.87%     60.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1418      2.23%     62.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1367      2.15%     64.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22488     35.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63594                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5295                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.408121                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2902.928186                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5292     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4906                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4906                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.161639                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.352681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       61.394400                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4666     95.11%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              49      1.00%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               4      0.08%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               5      0.10%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95               7      0.14%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              1      0.02%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127             2      0.04%     96.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             7      0.14%     96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            21      0.43%     97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            22      0.45%     97.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191             9      0.18%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            10      0.20%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             3      0.06%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             2      0.04%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.04%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.06%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.04%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.04%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             3      0.06%     98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            19      0.39%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             9      0.18%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             5      0.10%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383            13      0.26%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.06%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.02%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.02%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             3      0.06%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             5      0.10%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             3      0.06%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             8      0.16%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.04%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             3      0.06%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.02%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             3      0.06%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             3      0.06%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::816-831             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4906                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2145475500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9735100500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023900000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5300.35                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5295                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5295                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.284608                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.797942                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.673735                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4676     88.31%     88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             227      4.29%     92.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              77      1.45%     94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              16      0.30%     94.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              14      0.26%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               6      0.11%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               7      0.13%     94.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               9      0.17%     95.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               7      0.13%     95.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              34      0.64%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            171      3.23%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            10      0.19%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.02%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             5      0.09%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             3      0.06%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.04%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.08%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             4      0.08%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             8      0.15%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.04%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             7      0.13%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5295                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2213284250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9799496750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2022990000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5470.33                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24050.35                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24220.33                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.73                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.52                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.73                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363650                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109622                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.25                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3343083.38                       # Average gap between requests
-system.physmem.pageHitRate                      87.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  239016960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  130416000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577401800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                430058160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           123261212880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            60604997490                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1079143932000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1265387035290                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.518464                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1795039940480                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63016980000                       # Time in different power states
+system.physmem.avgWrQLen                        24.19                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363516                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95485                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.85                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.90                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3608360.06                       # Average gap between requests
+system.physmem.pageHitRate                      87.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  233845920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  127594500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1576231800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                379449360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           123197134320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            60326866845                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1078799265750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1264640388495                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.471373                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1794467110750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62984220000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     29120110770                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28744633000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  250591320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136731375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579882200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                433434240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           123261212880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61665698520                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1078213500750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1265541051285                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.600071                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1793490285480                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63016980000                       # Time in different power states
+system.physmem_1.actEnergy                  246924720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134730750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1579632600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385171200                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           123197134320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61494025635                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1077775442250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1264813061475                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.562919                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1792762379750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62984220000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30669779520                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30449364000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                15009390                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13017239                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            373223                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9937559                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5199343                       # Number of BTB hits
+system.cpu.branchPred.lookups                15004879                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13013312                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            375549                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10036322                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5207234                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             52.320122                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  808599                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              32086                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             51.883887                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  808293                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              31321                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9244571                       # DTB read hits
-system.cpu.dtb.read_misses                      17796                       # DTB read misses
+system.cpu.dtb.read_hits                      9242647                       # DTB read hits
+system.cpu.dtb.read_misses                      17811                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   766653                       # DTB read accesses
-system.cpu.dtb.write_hits                     6387559                       # DTB write hits
-system.cpu.dtb.write_misses                      2314                       # DTB write misses
+system.cpu.dtb.read_accesses                   766734                       # DTB read accesses
+system.cpu.dtb.write_hits                     6385782                       # DTB write hits
+system.cpu.dtb.write_misses                      2309                       # DTB write misses
 system.cpu.dtb.write_acv                          160                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298430                       # DTB write accesses
-system.cpu.dtb.data_hits                     15632130                       # DTB hits
-system.cpu.dtb.data_misses                      20110                       # DTB misses
+system.cpu.dtb.write_accesses                  298407                       # DTB write accesses
+system.cpu.dtb.data_hits                     15628429                       # DTB hits
+system.cpu.dtb.data_misses                      20120                       # DTB misses
 system.cpu.dtb.data_acv                           371                       # DTB access violations
-system.cpu.dtb.data_accesses                  1065083                       # DTB accesses
-system.cpu.itb.fetch_hits                     4016391                       # ITB hits
-system.cpu.itb.fetch_misses                      6902                       # ITB misses
-system.cpu.itb.fetch_acv                          656                       # ITB acv
-system.cpu.itb.fetch_accesses                 4023293                       # ITB accesses
+system.cpu.dtb.data_accesses                  1065141                       # DTB accesses
+system.cpu.itb.fetch_hits                     4016387                       # ITB hits
+system.cpu.itb.fetch_misses                      6834                       # ITB misses
+system.cpu.itb.fetch_acv                          689                       # ITB acv
+system.cpu.itb.fetch_accesses                 4023221                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -355,39 +342,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        180739367                       # number of cpu cycles simulated
+system.cpu.numCycles                        180216793                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56138893                       # Number of instructions committed
-system.cpu.committedOps                      56138893                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2514465                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5513                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3593619217                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.219504                       # CPI: cycles per instruction
-system.cpu.ipc                               0.310607                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56121694                       # Number of instructions committed
+system.cpu.committedOps                      56121694                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2519198                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5577                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3592175193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.211179                       # CPI: cycles per instruction
+system.cpu.ipc                               0.311412                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211474                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74790     40.94%     40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211471                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74788     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     133      0.07%     41.01% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105866     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182688                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73423     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105864     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182686                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73421     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73423     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148878                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1834553179500     97.21%     97.21% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                80704500      0.00%     97.22% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               676355500      0.04%     97.25% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             51868058000      2.75%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1887178297500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good::31                    73422     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148877                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1833775262000     97.22%     97.22% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                81341000      0.00%     97.23% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               679703500      0.04%     97.26% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             51658703500      2.74%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1886195010000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981722                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693547                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814930                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693550                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814934                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -426,112 +413,112 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4172      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175529     91.23%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6805      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175525     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5127      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192412                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5872                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192408                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5868                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2092                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1907                      
 system.cpu.kern.mode_good::user                  1739                      
 system.cpu.kern.mode_good::idle                   168                      
-system.cpu.kern.mode_switch_good::kernel     0.324762                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.324983                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393074                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36563872500      1.94%      1.94% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4128201000      0.22%      2.16% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1846486214000     97.84%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080114                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.393034                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36513483500      1.94%      1.94% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4123557000      0.22%      2.15% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1845557959500     97.85%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4173                       # number of times the context was actually changed
-system.cpu.tickCycles                        84425844                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        96313523                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1395605                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.981737                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13777018                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1396117                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.868097                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          90985250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.981737                       # Average occupied blocks per requestor
+system.cpu.tickCycles                        84408299                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        95808494                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1395428                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.981685                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13773051                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395940                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.866506                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          90850500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.981685                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63673578                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63673578                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7816852                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7816852                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5578390                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5578390                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182745                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182745                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       198996                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       198996                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13395242                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13395242                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13395242                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13395242                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1201883                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201883                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       573228                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573228                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17271                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17271                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1775111                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1775111                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1775111                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1775111                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33009196500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33009196500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22459728804                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22459728804                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    231661750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    231661750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55468925304                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55468925304                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55468925304                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55468925304                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9018735                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9018735                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6151618                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6151618                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200016                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200016                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       198996                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       198996                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15170353                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15170353                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15170353                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15170353                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133265                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133265                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093183                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093183                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086348                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086348                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117012                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117012                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117012                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117012                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31248.144653                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31248.144653                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63660654                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63660654                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7815445                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7815445                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5575784                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5575784                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       182800                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182800                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       198989                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       198989                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13391229                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13391229                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13391229                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13391229                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1201797                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201797                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       574153                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       574153                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17210                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17210                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1775950                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775950                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1775950                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775950                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32866409500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32866409500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  22318082000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  22318082000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    230873000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    230873000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55184491500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55184491500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55184491500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55184491500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9017242                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9017242                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6149937                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6149937                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200010                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200010                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       198989                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       198989                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15167179                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15167179                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15167179                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15167179                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133278                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133278                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093359                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093359                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086046                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086046                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.117092                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117092                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117092                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117092                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31073.223627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31073.223627                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -540,129 +527,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838424                       # number of writebacks
-system.cpu.dcache.writebacks::total            838424                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127263                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127263                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       268960                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       268960                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       838228                       # number of writebacks
+system.cpu.dcache.writebacks::total            838228                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127318                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127318                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269861                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269861                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       396223                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       396223                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       396223                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       396223                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074620                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074620                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304268                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304268                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17268                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17268                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378888                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378888                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378888                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378888                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9619                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9619                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16549                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16549                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29346931250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29346931250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11233755093                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11233755093                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205574750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205574750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  40580686343                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  40580686343                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40580686343                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  40580686343                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1433335500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1433335500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2017328500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2017328500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3450664000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3450664000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119154                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119154                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049461                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049461                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090894                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090894                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090894                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090894                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27309.124388                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27309.124388                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36920.593335                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36920.593335                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.954251                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.954251                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29430.009067                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29430.009067                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29430.009067                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29430.009067                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206830.519481                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206830.519481                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209723.308036                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209723.308036                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208511.934256                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208511.934256                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       397179                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       397179                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       397179                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       397179                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074479                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074479                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304292                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304292                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17207                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17207                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378771                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378771                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378771                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378771                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29864669500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29864669500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11367980000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11367980000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    213500500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    213500500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41232649500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41232649500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41232649500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41232649500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1451443000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1451443000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2042111500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2042111500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3493554500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3493554500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119158                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119158                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049479                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049479                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086031                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086031                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090905                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090905                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090905                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090905                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27794.558572                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27794.558572                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37358.786955                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37358.786955                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12407.770094                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12407.770094                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29905.364633                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29905.364633                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29905.364633                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29905.364633                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209322.613210                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209322.613210                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212255.638707                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212255.638707                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211027.151918                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211027.151918                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1458527                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.440030                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18957390                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1459038                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.993075                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       33850944250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.440030                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995000                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995000                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1459012                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.459740                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18968780                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1459523                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.996561                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       33609211500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.459740                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995039                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995039                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          401                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21875821                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21875821                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18957393                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18957393                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18957393                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18957393                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18957393                       # number of overall hits
-system.cpu.icache.overall_hits::total        18957393                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1459214                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1459214                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1459214                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1459214                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1459214                       # number of overall misses
-system.cpu.icache.overall_misses::total       1459214                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20146503654                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20146503654                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20146503654                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20146503654                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20146503654                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20146503654                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20416607                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20416607                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20416607                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20416607                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20416607                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20416607                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071472                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071472                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071472                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071472                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071472                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071472                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13806.407870                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13806.407870                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13806.407870                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13806.407870                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13806.407870                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13806.407870                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          21888175                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21888175                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18968783                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18968783                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18968783                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18968783                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18968783                       # number of overall hits
+system.cpu.icache.overall_hits::total        18968783                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1459696                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1459696                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1459696                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1459696                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1459696                       # number of overall misses
+system.cpu.icache.overall_misses::total       1459696                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20145975000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20145975000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20145975000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20145975000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20145975000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20145975000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20428479                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20428479                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20428479                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     20428479                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071454                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071454                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071454                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::cpu.inst     0.071454                       # miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.486748                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13801.486748                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.486748                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13801.486748                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.486748                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13801.486748                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -671,135 +658,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1459214                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1459214                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1459214                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1459214                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1459214                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1459214                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17950426346                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17950426346                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17950426346                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17950426346                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17950426346                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17950426346                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071472                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071472                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071472                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071472                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071472                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071472                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12301.435119                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12301.435119                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12301.435119                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12301.435119                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12301.435119                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12301.435119                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071454                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12801.486748                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           339383                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65314.882486                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2982705                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404543                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.373023                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6335415750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54442.497002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5830.422847                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5041.962637                       # Average occupied blocks per requestor
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-system.cpu.l2cache.Writeback_hits::writebacks       838424                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       838424                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
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+system.cpu.l2cache.demand_miss_latency::cpu.inst   1324497500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  28662523500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  29987021000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1324497500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  28662523500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  29987021000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       838228                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       838228                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           20                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304302                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304302                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1459636                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1459636                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091656                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1091656                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1459636                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1395958                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2855594                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1459636                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1395958                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2855594                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.800000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.800000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382955                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.382955                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011238                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011238                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249327                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249327                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011238                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.278456                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.141868                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011238                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.278456                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141868                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15812.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15812.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76680.385124                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76680.385124                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80747.271841                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80747.271841                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72476.757942                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72476.757942                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80747.271841                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73736.982041                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74020.826134                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80747.271841                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73736.982041                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74020.826134                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -808,115 +801,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76554                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76554                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16447                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       272188                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288635                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           18                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16447                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388850                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405297                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16447                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388850                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405297                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9619                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9619                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16549                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16549                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1115769250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16346505000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  17462274250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       421016                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       421016                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7497021141                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23843526141                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  24959295391                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23843526141                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  24959295391                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1336297500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1336297500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1892281000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1892281000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3228578500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3228578500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.011272                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.249288                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113145                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818182                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011272                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278519                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141946                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011272                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278519                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141946                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943                       # average overall mshr uncacheable latency
+system.cpu.l2cache.writebacks::writebacks        76513                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76513                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          317                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          317                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       431000                       # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1160467500                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3296217500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2558177                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2558144                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       838424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41594                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304274                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304274                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6934                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2558426                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9621                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9621                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       956270                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2277118                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304302                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304302                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1459696                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091829                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2918365                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3663990                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6582355                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93385664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143064988                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          236450652                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       41986                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3752110                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.011132                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.104918                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4377747                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219297                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8597044                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93416704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143041221                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          236457925                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422839                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6149292                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.068727                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.252990                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3710343     98.89%     98.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41767      1.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5726669     93.13%     93.13% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             422623      6.87%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3752110                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2698405000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::total        6149292                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3706373000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2192449154                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2189771045                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2195119407                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2105677995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -930,44 +934,43 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51171                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9619                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5094                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7107                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7107                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51173                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51173                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5104                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33098                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33110                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116560                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20416                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44316                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44357                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705924                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4705000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705965                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              4712000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -981,7 +984,7 @@ system.iobus.reqLayer23.occupancy            13484000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
@@ -989,23 +992,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           242104189                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216063756                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23479000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23489000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42024001                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.302269                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.294607                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1729988196000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.302269                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081392                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081392                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1729988854000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.294607                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.080913                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.080913                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1013,49 +1016,49 @@ system.iocache.tags.tag_accesses               375525                       # Nu
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21714383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21714383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8768796805                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8768796805                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21714383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21714383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21714383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21714383                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21637883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21637883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907200873                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4907200873                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21637883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21637883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21637883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21637883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125516.664740                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125516.664740                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125516.664740                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         73108                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125074.468208                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125074.468208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125074.468208                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 9982                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.323983                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1063,83 +1066,85 @@ system.iocache.writebacks::writebacks           41512                       # nu
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12562383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12562383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6608090807                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6608090807                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12562383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12562383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12562383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12562383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12987883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12987883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829600873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2829600873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12987883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12987883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12987883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12987883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72614.930636                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72614.930636                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              295738                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295722                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
-system.membus.trans_dist::Writeback            118066                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              159                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             159                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116521                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116521                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6934                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295673                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9621                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9621                       # Transaction distribution
+system.membus.trans_dist::Writeback            118025                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262175                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              156                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             156                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116394                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116394                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288755                       # Transaction distribution
 system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       886877                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33110                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920007                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1044811                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30810944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30855260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36172316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181774                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1306591                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44357                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30796800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30841157                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33498885                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
-system.membus.snoop_fanout::samples            581705                       # Request fanout histogram
+system.membus.snoop_fanout::samples            843789                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  581705    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  843789    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              581705                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29342000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              843789                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29576000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1229889311                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1318697936                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy               20500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160670093                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160007596                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           42495999                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72031934                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index dad37454b..e5b1b4540 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.904438                       # Number of seconds simulated
-sim_ticks                                1904437574000                       # Number of ticks simulated
-final_tick                               1904437574000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.907980                       # Number of seconds simulated
+sim_ticks                                1907980084000                       # Number of ticks simulated
+final_tick                               1907980084000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 149880                       # Simulator instruction rate (inst/s)
-host_op_rate                                   149880                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5044505517                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380636                       # Number of bytes of host memory used
-host_seconds                                   377.53                       # Real time elapsed on the host
-sim_insts                                    56583768                       # Number of instructions simulated
-sim_ops                                      56583768                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 144634                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144633                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4918211693                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 381420                       # Number of bytes of host memory used
+host_seconds                                   387.94                       # Real time elapsed on the host
+sim_insts                                    56109384                       # Number of instructions simulated
+sim_ops                                      56109384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           878144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24662016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           107328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           745792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           744000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24138496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           236608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1227584                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26394240                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       878144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       107328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          985472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7983616                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7983616                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13721                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            385344                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1677                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11653                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26347648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       744000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       236608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          980608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7952896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7952896                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            377164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3697                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             19181                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                412410                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124744                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               124744                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              461104                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12949763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56357                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              391607                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13859336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         461104                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56357                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517461                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4192112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4192112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4192112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             461104                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12949763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56357                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             391607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18051448                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        412410                       # Number of read requests accepted
-system.physmem.writeReqs                       166296                       # Number of write requests accepted
-system.physmem.readBursts                      412410                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     166296                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26387648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9015296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26394240                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10642944                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   25417                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4739                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25681                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26031                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26262                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25929                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25778                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25597                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26273                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25295                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25970                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               26150                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25721                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25208                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25640                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25768                       # Per bank write bursts
+system.physmem.num_reads::total                411682                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124264                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               124264                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              389941                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12651335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              124010                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              643395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13809184                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         389941                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         124010                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             513951                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4168228                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4168228                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4168228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             389941                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12651335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             124010                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             643395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17977412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        411682                       # Number of read requests accepted
+system.physmem.writeReqs                       124264                       # Number of write requests accepted
+system.physmem.readBursts                      411682                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     124264                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26340672                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7951552                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26347648                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7952896                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          45002                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25908                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25789                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26010                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25614                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25643                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25797                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25922                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25550                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25897                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25701                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25484                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25508                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25696                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25817                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              25547                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25457                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9358                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9077                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9200                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8756                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8419                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8251                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9072                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8046                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8692                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8978                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8574                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8968                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8555                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9260                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8896                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8762                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25690                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7970                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7556                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7711                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7606                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7633                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7951                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7934                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7815                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8060                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8044                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7565                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7446                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7634                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8000                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7754                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7564                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          50                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1904433039500                       # Total gap between requests
+system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1907975777500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  412410                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  411682                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 166296                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     39027                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30801                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124264                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     38583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29989                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     25130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        71                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
@@ -158,200 +158,204 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       92                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66375                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      533.371902                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     326.032515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.702689                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14841     22.36%     22.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11366     17.12%     39.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5910      8.90%     48.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2909      4.38%     52.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2416      3.64%     56.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1747      2.63%     59.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1634      2.46%     61.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1312      1.98%     63.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24240     36.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66375                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5272                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        78.206942                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2891.855588                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5269     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3880                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    10048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      233                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::59                       87                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       46                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65129                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      526.524774                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     320.940318                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     415.518091                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14691     22.56%     22.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11476     17.62%     40.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5283      8.11%     48.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3332      5.12%     53.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2563      3.94%     57.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1696      2.60%     59.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1442      2.21%     62.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1386      2.13%     64.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        23260     35.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65129                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5620                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        73.233096                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2814.761745                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5617     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5272                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5272                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        26.719272                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.348145                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       60.306865                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5026     95.33%     95.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              55      1.04%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               6      0.11%     96.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               3      0.06%     96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95               6      0.11%     96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              3      0.06%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127             3      0.06%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             6      0.11%     96.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            24      0.46%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            10      0.19%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191             9      0.17%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            16      0.30%     98.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             2      0.04%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             3      0.06%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             3      0.06%     98.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             4      0.08%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             1      0.02%     98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             4      0.08%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             6      0.11%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            11      0.21%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            13      0.25%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             7      0.13%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383            10      0.19%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.06%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.02%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             2      0.04%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495            11      0.21%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             3      0.06%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             5      0.09%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             3      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.02%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             2      0.04%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             2      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             3      0.06%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-911             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5272                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4111304500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11842060750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2061535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9971.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5620                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5620                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.107295                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.769658                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.265728                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4863     86.53%     86.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             151      2.69%     89.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             190      3.38%     92.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              20      0.36%     92.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              26      0.46%     93.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              52      0.93%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.25%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.12%     94.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               2      0.04%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.04%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.11%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.12%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               8      0.14%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.09%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.05%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.05%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               8      0.14%     95.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               8      0.14%     95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              26      0.46%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              16      0.28%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           144      2.56%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            12      0.21%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.04%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             4      0.07%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.04%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.04%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.05%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             6      0.11%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             7      0.12%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             2      0.04%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             5      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5620                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4128600500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11845594250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2057865000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10031.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28721.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.86                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.86                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.59                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28781.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.27                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     371693                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    115102                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.15                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3290847.23                       # Average gap between requests
-system.physmem.pageHitRate                      88.00                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  251551440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  137255250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1613398800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                454759920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124388181840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            57693505320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1092050470500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1276589123070                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.325620                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1816548038492                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63593140000                       # Time in different power states
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         2.21                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.72                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     370844                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99842                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.35                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3560014.96                       # Average gap between requests
+system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  245019600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  133691250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1608188400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                402589440                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124619576640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            57486510675                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1094357699250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1278853275255                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.267627                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1820391723000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63711440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     24290182758                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23872193000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  250137720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136483875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1602190200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                457604640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124388181840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            57661176915                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1092078837000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1276574612190                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.317995                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1816597555496                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63593140000                       # Time in different power states
+system.physmem_1.actEnergy                  247287600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134928750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1601652000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                402194160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124619576640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            57648050955                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1094215997250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1278869687355                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.276229                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1820158780750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63711440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     24242350004                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     24103898000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups               16050181                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14012515                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           321303                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             9883832                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5384164                       # Number of BTB hits
+system.cpu0.branchPred.lookups               11788808                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         10301623                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           235567                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             7623393                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4144660                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            54.474459                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 809394                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             17633                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            54.367655                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 590548                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             12472                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9185685                       # DTB read hits
-system.cpu0.dtb.read_misses                     31794                       # DTB read misses
-system.cpu0.dtb.read_acv                          464                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  674724                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5856177                       # DTB write hits
-system.cpu0.dtb.write_misses                     6642                       # DTB write misses
-system.cpu0.dtb.write_acv                         308                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 220970                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15041862                       # DTB hits
-system.cpu0.dtb.data_misses                     38436                       # DTB misses
-system.cpu0.dtb.data_acv                          772                       # DTB access violations
-system.cpu0.dtb.data_accesses                  895694                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1413849                       # ITB hits
-system.cpu0.itb.fetch_misses                    27924                       # ITB misses
-system.cpu0.itb.fetch_acv                         522                       # ITB acv
-system.cpu0.itb.fetch_accesses                1441773                       # ITB accesses
+system.cpu0.dtb.read_hits                     7021210                       # DTB read hits
+system.cpu0.dtb.read_misses                     28922                       # DTB read misses
+system.cpu0.dtb.read_acv                          549                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  680178                       # DTB read accesses
+system.cpu0.dtb.write_hits                    4516223                       # DTB write hits
+system.cpu0.dtb.write_misses                     6969                       # DTB write misses
+system.cpu0.dtb.write_acv                         383                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 234540                       # DTB write accesses
+system.cpu0.dtb.data_hits                    11537433                       # DTB hits
+system.cpu0.dtb.data_misses                     35891                       # DTB misses
+system.cpu0.dtb.data_acv                          932                       # DTB access violations
+system.cpu0.dtb.data_accesses                  914718                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1192769                       # ITB hits
+system.cpu0.itb.fetch_misses                    29243                       # ITB misses
+system.cpu0.itb.fetch_acv                         632                       # ITB acv
+system.cpu0.itb.fetch_accesses                1222012                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -364,595 +368,598 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       115311619                       # number of cpu cycles simulated
+system.cpu0.numCycles                        94258709                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          26308115                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      70327057                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   16050181                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6193558                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     81501759                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1071492                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       564                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               28477                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      1405877                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       453989                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          199                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8110639                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               231031                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         110234726                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.637976                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.938280                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          18560589                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      53027757                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   11788808                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           4735208                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     69979824                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                 806070                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       422                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               25803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      1456351                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       296845                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          178                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  6342869                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               170274                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          90723047                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.584501                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.854201                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                97059343     88.05%     88.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  844439      0.77%     88.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1832569      1.66%     90.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  778966      0.71%     91.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2587591      2.35%     93.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  590382      0.54%     94.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  655112      0.59%     94.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  842956      0.76%     95.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 5043368      4.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                80634947     88.88%     88.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  672953      0.74%     89.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1448081      1.60%     91.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  584574      0.64%     91.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2111688      2.33%     94.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  463915      0.51%     94.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  450869      0.50%     95.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  614781      0.68%     95.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3741239      4.12%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           110234726                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.139190                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.609887                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                21404943                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             78060690                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8511786                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1756604                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                500702                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              518589                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                35397                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              61724420                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               110442                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                500702                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                22241314                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               51035680                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      18875449                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9340106                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              8241473                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              59592973                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               194522                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2018079                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                142482                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               4327383                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           39868450                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             72416227                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        72269697                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           136600                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             34997307                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4871143                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1466604                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        213801                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12439963                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9310742                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6112181                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1342468                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          951279                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  53110388                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1887245                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 52243998                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            50112                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6621677                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2924940                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1298251                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    110234726                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.473934                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.210494                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            90723047                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.125069                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.562577                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                14977569                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             67686915                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  6257157                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1423439                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                377966                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              370983                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                25389                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              46677806                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                79994                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                377966                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                15660908                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               46083028                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      14369152                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6948168                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7283823                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              45068314                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               191995                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1547824                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                115834                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               4229403                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           30289226                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             55138176                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        55047778                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            82793                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             26689501                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 3599717                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1126936                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        168790                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 10038208                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7066684                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            4739993                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1073845                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          760534                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  40346624                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1418133                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 39715880                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            51531                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        4979263                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2318512                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        978590                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     90723047                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.437771                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.168840                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           88757561     80.52%     80.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9303542      8.44%     88.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3888317      3.53%     92.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2690563      2.44%     94.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2829805      2.57%     97.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1399486      1.27%     98.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             891988      0.81%     99.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             364157      0.33%     99.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             109307      0.10%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           74240349     81.83%     81.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            7278177      8.02%     89.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3014429      3.32%     93.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2002130      2.21%     95.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2057446      2.27%     97.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1059416      1.17%     98.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             709655      0.78%     99.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             273899      0.30%     99.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              87546      0.10%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      110234726                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       90723047                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 184539     19.02%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                463483     47.76%     66.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               322428     33.22%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 128942     17.20%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     17.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                362987     48.42%     65.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               257779     34.38%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             4481      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             35873428     68.67%     68.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57323      0.11%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              30345      0.06%     68.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               2234      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9533353     18.25%     87.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5924969     11.34%     98.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            817865      1.57%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3788      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             27155018     68.37%     68.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               40485      0.10%     68.48% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.48% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              25259      0.06%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             7282480     18.34%     86.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            4576355     11.52%     98.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            630612      1.59%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              52243998                       # Type of FU issued
-system.cpu0.iq.rate                          0.453068                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     970450                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.018575                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         215148578                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         61357419                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     50866456                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             594706                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            279378                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       273817                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              52889876                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 320091                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          579148                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              39715880                       # Type of FU issued
+system.cpu0.iq.rate                          0.421350                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     749708                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018877                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         170597233                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         46586090                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     38643243                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             358812                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            172505                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       165745                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              40269961                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 191839                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          469267                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1102308                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4274                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        17841                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       488268                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads       864378                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3380                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        14864                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       401917                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18769                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       362429                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        11804                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       365714                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                500702                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               47770294                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               975694                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           58389413                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           117266                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9310742                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6112181                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1666926                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 38737                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               734939                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         17841                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        161758                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       354564                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              516322                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             51738600                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9239994                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           505398                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                377966                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               43619498                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               675796                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           44202753                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            88904                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7066684                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             4739993                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1257449                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 23012                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               538948                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         14864                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        117466                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       265776                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              383242                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             39342618                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              7067139                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           373261                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3391780                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    15116199                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8225133                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5876205                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.448685                       # Inst execution rate
-system.cpu0.iew.wb_sent                      51252595                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     51140273                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26435135                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36676301                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      2437996                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    11599884                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 6171265                       # Number of branches executed
+system.cpu0.iew.exec_stores                   4532745                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.417390                       # Inst execution rate
+system.cpu0.iew.wb_sent                      38908729                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     38808988                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 20149850                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 27578035                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.443496                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.720769                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.411728                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.730649                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6957791                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         588994                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           471378                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    109009912                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.470894                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.405994                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        5183738                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         439543                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           349838                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     89803768                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.433386                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.354442                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     90895183     83.38%     83.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7166067      6.57%     89.96% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3956975      3.63%     93.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2029230      1.86%     95.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1623676      1.49%     96.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       582620      0.53%     97.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       429957      0.39%     97.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       432812      0.40%     98.26% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1893392      1.74%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     76032999     84.67%     84.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      5542678      6.17%     90.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      2869062      3.19%     94.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1578965      1.76%     95.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1284314      1.43%     97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       412798      0.46%     97.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       324191      0.36%     98.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       314453      0.35%     98.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1444308      1.61%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    109009912                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            51332073                       # Number of instructions committed
-system.cpu0.commit.committedOps              51332073                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     89803768                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            38919724                       # Number of instructions committed
+system.cpu0.commit.committedOps              38919724                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13832347                       # Number of memory references committed
-system.cpu0.commit.loads                      8208434                       # Number of loads committed
-system.cpu0.commit.membars                     200823                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7767218                       # Number of branches committed
-system.cpu0.commit.fp_insts                    270478                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 47526784                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              660195                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2960587      5.77%      5.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        33426068     65.12%     70.88% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          56116      0.11%     70.99% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.99% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         30044      0.06%     71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          2234      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8409257     16.38%     87.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5629902     10.97%     98.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       817865      1.59%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      10540382                       # Number of memory references committed
+system.cpu0.commit.loads                      6202306                       # Number of loads committed
+system.cpu0.commit.membars                     144405                       # Number of memory barriers committed
+system.cpu0.commit.branches                   5839773                       # Number of branches committed
+system.cpu0.commit.fp_insts                    162063                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 36166381                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              471449                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2138002      5.49%      5.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        25394964     65.25%     70.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          39484      0.10%     70.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         24801      0.06%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        6346711     16.31%     87.22% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       4343267     11.16%     98.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       630612      1.62%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         51332073                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1893392                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   165216916                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  117798939                       # The number of ROB writes
-system.cpu0.timesIdled                         506110                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5076893                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3693292578                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   48375955                       # Number of Instructions Simulated
-system.cpu0.committedOps                     48375955                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.383656                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.383656                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.419524                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.419524                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                67964697                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               37032803                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   135608                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  136877                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1822860                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                821150                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          1283357                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.867544                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10588066                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1283792                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.247493                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         26416000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.867544                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988023                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988023                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          435                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          435                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.849609                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         56965784                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        56965784                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6531926                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6531926                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3699481                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3699481                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       164387                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       164387                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       189172                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       189172                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10231407                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10231407                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10231407                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10231407                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1592146                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1592146                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1718300                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1718300                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20836                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20836                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2478                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         2478                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3310446                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3310446                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3310446                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3310446                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39294199360                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  39294199360                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  76231824796                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  76231824796                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    326020750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    326020750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20798848                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     20798848                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 115526024156                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 115526024156                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8124072                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8124072                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5417781                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5417781                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       185223                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       185223                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       191650                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       191650                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13541853                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13541853                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13541853                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13541853                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.195979                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.195979                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.317159                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.317159                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.112491                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.112491                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.012930                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.012930                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244460                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.244460                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244460                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.244460                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8393.401130                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8393.401130                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      4226969                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         4392                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           103766                       # number of cycles access was blocked
+system.cpu0.commit.op_class_0::total         38919724                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1444308                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   132264444                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   89122078                       # The number of ROB writes
+system.cpu0.timesIdled                         337516                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3535662                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3721701460                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   36785489                       # Number of Instructions Simulated
+system.cpu0.committedOps                     36785489                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.562388                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.562388                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.390261                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.390261                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                51878765                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               28204778                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    81728                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   81429                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1387632                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                636485                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           898491                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          481.994698                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            8012262                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           899003                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.912386                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         26393500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.994698                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.941396                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.941396                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          236                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         43230678                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        43230678                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5046736                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5046736                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      2679789                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       2679789                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       129628                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       129628                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149296                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149296                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7726525                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         7726525                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7726525                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        7726525                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1067598                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1067598                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1496200                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1496200                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12202                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        12202                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          769                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          769                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2563798                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2563798                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2563798                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2563798                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  32014122500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  32014122500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  69455032918                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  69455032918                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    190587000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    190587000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      5445000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      5445000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 101469155418                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 101469155418                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6114334                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6114334                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4175989                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4175989                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       141830                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       141830                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       150065                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       150065                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     10290323                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     10290323                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     10290323                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     10290323                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.174606                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.174606                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.358286                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.358286                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086033                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086033                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.005124                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.005124                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.249147                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.249147                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.249147                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.249147                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7080.624187                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7080.624187                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      4094264                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         5021                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           103728                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets             94                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.735588                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    46.723404                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    39.471155                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    53.414894                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       752753                       # number of writebacks
-system.cpu0.dcache.writebacks::total           752753                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       572031                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       572031                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1457971                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1457971                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4881                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4881                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2030002                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2030002                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2030002                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2030002                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1020115                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1020115                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       260329                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       260329                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15955                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15955                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2477                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         2477                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1280444                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1280444                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1280444                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1280444                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7039                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7039                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17071                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17071                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  28982142208                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  28982142208                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11887451669                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11887451669                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    177873500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    177873500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     17082652                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     17082652                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  40869593877                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  40869593877                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  40869593877                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  40869593877                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1464167000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1464167000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2129748498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2129748498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3593915498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3593915498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125567                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125567                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048051                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048051                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086139                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086139                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.012925                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.012925                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094555                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.094555                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094555                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.094555                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6896.508680                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6896.508680                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       426068                       # number of writebacks
+system.cpu0.dcache.writebacks::total           426068                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       384761                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       384761                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1282051                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1282051                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3514                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3514                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1666812                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1666812                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1666812                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1666812                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       682837                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       682837                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       214149                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       214149                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8688                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8688                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          769                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          769                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       896986                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       896986                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       896986                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       896986                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         4777                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         4777                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         8020                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         8020                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        12797                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        12797                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25205904500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25205904500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10851652245                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10851652245                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    107603000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    107603000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4676000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4676000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36057556745                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  36057556745                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36057556745                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  36057556745                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1013290500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1013290500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1707574498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1707574498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2720864998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2720864998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.111678                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.111678                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051281                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051281                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061256                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061256                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.005124                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.005124                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.087168                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.087168                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.087168                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.087168                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6080.624187                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6080.624187                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           911417                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.418391                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7153262                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           911929                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.844100                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      28352545250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.418391                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994958                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994958                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           615978                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.684225                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            5692804                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           616490                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             9.234220                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      28149663500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.684225                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.993524                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.993524                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          430                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          9022750                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         9022750                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7153262                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7153262                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7153262                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7153262                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7153262                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7153262                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       957376                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       957376                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       957376                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        957376                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       957376                       # number of overall misses
-system.cpu0.icache.overall_misses::total       957376                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13452406105                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13452406105                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13452406105                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13452406105                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13452406105                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13452406105                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8110638                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8110638                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8110638                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8110638                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8110638                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8110638                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.118040                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.118040                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.118040                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.118040                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.118040                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.118040                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14051.329995                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14051.329995                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         5687                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          6959538                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         6959538                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      5692804                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        5692804                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      5692804                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         5692804                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      5692804                       # number of overall hits
+system.cpu0.icache.overall_hits::total        5692804                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       650065                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       650065                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       650065                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        650065                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       650065                       # number of overall misses
+system.cpu0.icache.overall_misses::total       650065                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9309214992                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   9309214992                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   9309214992                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   9309214992                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   9309214992                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   9309214992                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      6342869                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      6342869                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      6342869                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      6342869                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      6342869                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      6342869                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.102488                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.102488                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.102488                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.102488                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.102488                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.102488                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14320.437175                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14320.437175                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3481                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              195                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              166                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.164103                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    20.969880                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45264                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        45264                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        45264                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        45264                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        45264                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        45264                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       912112                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       912112                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       912112                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       912112                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       912112                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       912112                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11511971092                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11511971092                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11511971092                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11511971092                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11511971092                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11511971092                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.112459                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.112459                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.112459                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.112459                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.112459                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.112459                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        33396                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        33396                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        33396                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        33396                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        33396                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        33396                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       616669                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       616669                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       616669                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       616669                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       616669                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       616669                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8251915495                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   8251915495                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8251915495                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   8251915495                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8251915495                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   8251915495                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.097222                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.097222                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.097222                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                3445639                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3003437                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            69264                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             1910439                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 836162                       # Number of BTB hits
+system.cpu1.branchPred.lookups                7710185                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          6710334                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           163097                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             4502045                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                2070765                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            43.768055                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 167186                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              4809                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            45.996097                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 394984                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             11166                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1858276                       # DTB read hits
-system.cpu1.dtb.read_misses                     10905                       # DTB read misses
-system.cpu1.dtb.read_acv                           64                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  300263                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1193771                       # DTB write hits
-system.cpu1.dtb.write_misses                     2902                       # DTB write misses
-system.cpu1.dtb.write_acv                         104                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 125157                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3052047                       # DTB hits
-system.cpu1.dtb.data_misses                     13807                       # DTB misses
-system.cpu1.dtb.data_acv                          168                       # DTB access violations
-system.cpu1.dtb.data_accesses                  425420                       # DTB accesses
-system.cpu1.itb.fetch_hits                     529068                       # ITB hits
-system.cpu1.itb.fetch_misses                     7485                       # ITB misses
-system.cpu1.itb.fetch_acv                         158                       # ITB acv
-system.cpu1.itb.fetch_accesses                 536553                       # ITB accesses
+system.cpu1.dtb.read_hits                     4026297                       # DTB read hits
+system.cpu1.dtb.read_misses                     14233                       # DTB read misses
+system.cpu1.dtb.read_acv                            6                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  293572                       # DTB read accesses
+system.cpu1.dtb.write_hits                    2497972                       # DTB write hits
+system.cpu1.dtb.write_misses                     2408                       # DTB write misses
+system.cpu1.dtb.write_acv                          37                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 109195                       # DTB write accesses
+system.cpu1.dtb.data_hits                     6524269                       # DTB hits
+system.cpu1.dtb.data_misses                     16641                       # DTB misses
+system.cpu1.dtb.data_acv                           43                       # DTB access violations
+system.cpu1.dtb.data_accesses                  402767                       # DTB accesses
+system.cpu1.itb.fetch_hits                     750930                       # ITB hits
+system.cpu1.itb.fetch_misses                     5383                       # ITB misses
+system.cpu1.itb.fetch_acv                          53                       # ITB acv
+system.cpu1.itb.fetch_accesses                 756313                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -965,570 +972,564 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        14296923                       # number of cpu cycles simulated
+system.cpu1.numCycles                        34369930                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           5827989                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      13624759                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3445639                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1003348                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      7312463                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 270756                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                       304                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               25051                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       299772                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        60327                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1551048                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                55046                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          13661307                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.997325                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.404073                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          13361598                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      30714280                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    7710185                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2465749                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     18120966                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 547594                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                        46                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               23797                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       211021                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       198154                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           54                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  3304195                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               117193                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          32189433                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.954173                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.349586                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                11273523     82.52%     82.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  149434      1.09%     83.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  236962      1.73%     85.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  182278      1.33%     86.68% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  319422      2.34%     89.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  124907      0.91%     89.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  138046      1.01%     90.95% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  169812      1.24%     92.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1066923      7.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                26750456     83.10%     83.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  307184      0.95%     84.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  618506      1.92%     85.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  382121      1.19%     87.17% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  801179      2.49%     89.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  249293      0.77%     90.43% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  334783      1.04%     91.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  403446      1.25%     92.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 2342465      7.28%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            13661307                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.241006                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.952985                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 4848979                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              6756897                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1724085                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               202692                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                128653                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              104901                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 6833                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              11127112                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                21450                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                128653                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 4991483                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 690115                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       5206241                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1784475                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               860338                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              10551561                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3558                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 63390                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 12017                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                381484                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            6914568                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             12620115                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        12571129                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            43721                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              5829921                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1084639                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            430965                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         39644                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  1821487                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             1910201                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1273290                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           221141                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          146764                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                   9284732                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             487174                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                  9053277                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            20996                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1564088                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       731721                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        360528                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     13661307                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.662695                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.384311                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            32189433                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.224329                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.893638                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                11124412                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16339992                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  3934359                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               534571                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                256098                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              250042                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                17822                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              25897409                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                55799                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                256098                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                11423416                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                4918911                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       9329125                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  4131002                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2130879                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              24789451                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 5724                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                540758                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 43054                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                820253                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           16289258                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             29487961                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        29391972                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            88964                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             13777657                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2511601                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            753305                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         82405                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  4252225                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             4127805                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            2629581                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           507300                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          331297                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  21789875                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             948507                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 21283611                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            28389                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        3414486                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1484281                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        680406                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     32189433                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.661199                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.387208                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0            9895925     72.44%     72.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1648518     12.07%     84.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             704790      5.16%     89.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             494622      3.62%     93.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             437905      3.21%     96.49% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             233549      1.71%     98.20% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             155573      1.14%     99.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              64890      0.47%     99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              25535      0.19%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           23533399     73.11%     73.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            3630192     11.28%     84.39% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1573878      4.89%     89.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1186258      3.69%     92.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            1178148      3.66%     96.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             546160      1.70%     98.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             337865      1.05%     99.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             151957      0.47%     99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              51576      0.16%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       13661307                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       32189433                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  22279      8.85%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                136629     54.29%     63.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                92774     36.86%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  80499     16.46%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     16.46% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                246874     50.47%     66.92% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               161807     33.08%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             2817      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              5609130     61.96%     61.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               14890      0.16%     62.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd               8778      0.10%     62.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1408      0.02%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             1940639     21.44%     83.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1217689     13.45%     97.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            257926      2.85%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3518      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             14071465     66.11%     66.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               30174      0.14%     66.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              13456      0.06%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             4194422     19.71%     86.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            2532925     11.90%     97.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            435892      2.05%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total               9053277                       # Type of FU issued
-system.cpu1.iq.rate                          0.633233                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     251682                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.027800                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          31870123                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         11259293                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      8718718                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             170415                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             80938                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        78899                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses               9210850                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                  91292                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           92092                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              21283611                       # Type of FU issued
+system.cpu1.iq.rate                          0.619251                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     489180                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.022984                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          74907239                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         25989017                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     20583813                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             366985                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            171482                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       168729                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              21571772                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 197501                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          207443                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       283440                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          879                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4333                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       136775                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       572592                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1888                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         7837                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       247159                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          421                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        73078                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads         7441                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       131088                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                128653                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 295868                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               364148                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           10275512                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            29401                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              1910201                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1273290                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            443383                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  3815                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               359581                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4333                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         31404                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        95843                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              127247                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              8933578                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              1876162                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           119698                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                256098                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                4050515                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               319306                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           24169619                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            59065                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              4127805                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             2629581                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            846465                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 33159                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               202940                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          7837                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         80858                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       187737                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              268595                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             21021510                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              4051663                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           262101                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       503606                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3078439                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1318456                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1202277                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.624860                       # Inst execution rate
-system.cpu1.iew.wb_sent                       8830913                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      8797617                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  4148200                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  5856949                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                      1431237                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     6560061                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 3322997                       # Number of branches executed
+system.cpu1.iew.exec_stores                   2508398                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.611625                       # Inst execution rate
+system.cpu1.iew.wb_sent                      20805592                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     20752542                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 10210202                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 14612629                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.615350                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.708253                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.603799                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.698725                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1592161                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         126646                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           116539                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     13369044                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.644454                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.620421                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        3582987                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         268101                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           243613                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     31565232                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.650241                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.623237                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     10245809     76.64%     76.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1446725     10.82%     87.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       518907      3.88%     91.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       315988      2.36%     93.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       242120      1.81%     95.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        97246      0.73%     96.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6        91600      0.69%     96.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       106270      0.79%     97.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       304379      2.28%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     24282945     76.93%     76.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      2976975      9.43%     86.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1587723      5.03%     91.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       771361      2.44%     93.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       532421      1.69%     95.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       258990      0.82%     96.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       207817      0.66%     97.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       189047      0.60%     97.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       757953      2.40%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     13369044                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             8615735                       # Number of instructions committed
-system.cpu1.commit.committedOps               8615735                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     31565232                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            20524993                       # Number of instructions committed
+system.cpu1.commit.committedOps              20524993                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       2763276                       # Number of memory references committed
-system.cpu1.commit.loads                      1626761                       # Number of loads committed
-system.cpu1.commit.membars                      39485                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1225974                       # Number of branches committed
-system.cpu1.commit.fp_insts                     77544                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  7995429                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              135018                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       410738      4.77%      4.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         5119196     59.42%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          14466      0.17%     64.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd          8774      0.10%     64.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1408      0.02%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1666246     19.34%     83.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1136981     13.20%     97.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       257926      2.99%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       5937635                       # Number of memory references committed
+system.cpu1.commit.loads                      3555213                       # Number of loads committed
+system.cpu1.commit.membars                      92415                       # Number of memory barriers committed
+system.cpu1.commit.branches                   3082130                       # Number of branches committed
+system.cpu1.commit.fp_insts                    166998                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 18893824                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              318960                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass      1204616      5.87%      5.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        12808497     62.40%     68.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          29745      0.14%     68.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     68.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         13451      0.07%     68.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     68.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     68.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     68.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1759      0.01%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3647628     17.77%     86.26% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       2383405     11.61%     97.88% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       435892      2.12%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total          8615735                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               304379                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    23176968                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   20704388                       # The number of ROB writes
-system.cpu1.timesIdled                         112605                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         635616                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3794578226                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    8207813                       # Number of Instructions Simulated
-system.cpu1.committedOps                      8207813                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.741868                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.741868                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.574096                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.574096                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                11535994                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                6250844                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    43175                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   42684                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 891820                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                203240                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           102439                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          489.756832                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            2417231                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           102951                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.479432                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1034185261500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   489.756832                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.956556                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.956556                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         11476458                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        11476458                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1494681                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1494681                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       855193                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        855193                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        29899                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        29899                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        28520                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        28520                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2349874                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2349874                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2349874                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2349874                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       181396                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       181396                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       244262                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       244262                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4731                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         4731                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2607                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         2607                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       425658                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        425658                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       425658                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       425658                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2290258065                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2290258065                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9952106154                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   9952106154                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     46237999                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     46237999                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     22188385                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     22188385                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  12242364219                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12242364219                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  12242364219                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12242364219                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1676077                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1676077                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1099455                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1099455                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        34630                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        34630                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        31127                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        31127                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      2775532                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      2775532                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      2775532                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      2775532                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.108227                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.108227                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.222166                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.222166                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.136616                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.136616                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.083754                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.083754                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.153361                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.153361                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.153361                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.153361                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9773.409216                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9773.409216                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8511.079785                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8511.079785                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       574336                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          346                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            18255                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              8                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    31.461846                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    43.250000                       # average number of cycles each access was blocked
+system.cpu1.commit.op_class_0::total         20524993                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               757953                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    54833276                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   48835744                       # The number of ROB writes
+system.cpu1.timesIdled                         276866                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2180497                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3780899978                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   19323895                       # Number of Instructions Simulated
+system.cpu1.committedOps                     19323895                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.778623                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.778623                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.562233                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.562233                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                27142723                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               14810250                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    88193                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   88824                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                1272248                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                377130                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           561653                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          496.197725                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4717582                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           561970                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs             8.394722                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      37149185000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   496.197725                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.969136                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.969136                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          317                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          317                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.619141                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         24916279                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        24916279                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2844065                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2844065                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1751257                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1751257                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        62172                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        62172                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        69860                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        69860                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      4595322                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         4595322                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      4595322                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        4595322                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       792097                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       792097                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       552973                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       552973                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14160                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        14160                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          786                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          786                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      1345070                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       1345070                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      1345070                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      1345070                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  10154789500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  10154789500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  16820667860                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  16820667860                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    217520000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    217520000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6395000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      6395000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  26975457360                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  26975457360                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  26975457360                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  26975457360                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3636162                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3636162                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2304230                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2304230                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        76332                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        76332                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        70646                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        70646                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      5940392                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5940392                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      5940392                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      5940392                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.217839                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.217839                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.239982                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.239982                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.185505                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.185505                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.011126                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.011126                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.226428                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.226428                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.226428                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.226428                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8136.132316                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8136.132316                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       765854                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          810                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            36939                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             18                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.732938                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets           45                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        70134                       # number of writebacks
-system.cpu1.dcache.writebacks::total            70134                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       110614                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       110614                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       203686                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       203686                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          700                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          700                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       314300                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       314300                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       314300                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       314300                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        70782                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        70782                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        40576                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        40576                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4031                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4031                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2607                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         2607                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       111358                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       111358                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       111358                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       111358                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          158                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total          158                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2893                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2893                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3051                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3051                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    815361518                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    815361518                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1580599049                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1580599049                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     32399501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     32399501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     18277115                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     18277115                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2395960567                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2395960567                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2395960567                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2395960567                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     29330000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     29330000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    630993000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    630993000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    660323000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    660323000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036906                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036906                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.116402                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.116402                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.083754                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.083754                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.040121                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.040121                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.040121                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.040121                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8037.583974                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8037.583974                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7010.784427                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7010.784427                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136                       # average overall mshr uncacheable latency
+system.cpu1.dcache.writebacks::writebacks       435263                       # number of writebacks
+system.cpu1.dcache.writebacks::total           435263                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       332265                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       332265                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       455576                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       455576                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         2707                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         2707                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       787841                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       787841                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       787841                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       787841                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       459832                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       459832                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        97397                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        97397                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11453                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11453                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          786                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          786                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       557229                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       557229                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       557229                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       557229                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2425                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2425                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4340                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4340                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         6765                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         6765                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5761115500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5761115500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2818212839                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2818212839                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    135759000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    135759000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5609000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5609000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8579328339                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   8579328339                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8579328339                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   8579328339                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    499447000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    499447000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    957710500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    957710500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1457157500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1457157500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.126461                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.126461                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.042269                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.042269                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.150042                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.150042                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.011126                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.011126                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.093803                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.093803                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.093803                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.093803                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7136.132316                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7136.132316                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           211356                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          472.195820                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1331062                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           211865                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             6.282595                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1880244277250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   472.195820                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.922257                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.922257                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          392                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          1762968                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         1762968                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1331062                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1331062                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1331062                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1331062                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1331062                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1331062                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       219986                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       219986                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       219986                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        219986                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       219986                       # number of overall misses
-system.cpu1.icache.overall_misses::total       219986                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2974295730                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   2974295730                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   2974295730                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   2974295730                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   2974295730                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   2974295730                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1551048                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1551048                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1551048                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1551048                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1551048                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1551048                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.141831                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.141831                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.141831                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.141831                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.141831                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.141831                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13520.386434                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13520.386434                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          613                       # number of cycles access was blocked
+system.cpu1.icache.tags.replacements           499853                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          504.618896                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            2783346                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           500364                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             5.562642                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      48744804500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.618896                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.985584                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.985584                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          3804626                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         3804626                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      2783351                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        2783351                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      2783351                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         2783351                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      2783351                       # number of overall hits
+system.cpu1.icache.overall_hits::total        2783351                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       520843                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       520843                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       520843                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        520843                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       520843                       # number of overall misses
+system.cpu1.icache.overall_misses::total       520843                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7005360499                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7005360499                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7005360499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7005360499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7005360499                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7005360499                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      3304194                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      3304194                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      3304194                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      3304194                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      3304194                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      3304194                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.157631                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.157631                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.157631                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.157631                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.157631                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.157631                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13450.042525                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13450.042525                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs         1720                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               40                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               65                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.325000                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    26.461538                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         8066                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         8066                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         8066                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         8066                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         8066                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         8066                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       211920                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       211920                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       211920                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       211920                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       211920                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       211920                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2567742004                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   2567742004                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2567742004                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   2567742004                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2567742004                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   2567742004                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.136630                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.136630                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.136630                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.136630                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.136630                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.136630                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        20411                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        20411                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        20411                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        20411                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        20411                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        20411                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       500432                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       500432                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       500432                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       500432                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       500432                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       500432                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6297993499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   6297993499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6297993499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   6297993499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6297993499                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   6297993499                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.151454                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.151454                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.151454                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1542,54 +1543,53 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7375                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7375                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54477                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              12925                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11660                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               53912                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              53912                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10518                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          172                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18142                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        46640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        39124                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  122578                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        42072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          149                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9071                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        72837                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2734485                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             11011000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        68315                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2729939                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              9868000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              148000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13500000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -1601,285 +1601,291 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           242105442                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216085248                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27319000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            26764000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42037503                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41698                       # number of replacements
-system.iocache.tags.tagsinuse                0.483577                       # Cycle average of tags in use
+system.iocache.tags.replacements                41701                       # number of replacements
+system.iocache.tags.tagsinuse                0.804902                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41717                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1711318407000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.483577                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.030224                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.030224                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1711319254000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.804902                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.050306                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.050306                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375570                       # Number of tag accesses
-system.iocache.tags.data_accesses              375570                       # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::tsunami.ide          178                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               178                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          178                       # number of overall misses
-system.iocache.overall_misses::total              178                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22300881                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22300881                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8783600058                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8783600058                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     22300881                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     22300881                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     22300881                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     22300881                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          178                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             178                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          178                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            178                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
+system.iocache.tags.data_accesses              375543                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
+system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
+system.iocache.overall_misses::total              175                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     25392883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     25392883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907312365                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4907312365                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     25392883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     25392883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     25392883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     25392883                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125285.848315                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125285.848315                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125285.848315                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         73351                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145102.188571                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145102.188571                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145102.188571                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10036                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.308788                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          178                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          178                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          178                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          178                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12879885                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12879885                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6622894060                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6622894060                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12879885                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12879885                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12879885                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12879885                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           41526                       # number of writebacks
+system.iocache.writebacks::total                41526                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     16642883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16642883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829712365                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2829712365                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     16642883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16642883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     16642883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16642883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72358.904494                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72358.904494                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 95102.188571                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 95102.188571                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   346915                       # number of replacements
-system.l2c.tags.tagsinuse                65246.496404                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2614060                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   412065                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.343805                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7589002750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53536.501359                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5301.488199                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6124.882413                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      215.988746                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       67.635688                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.816902                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.080894                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.093458                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003296                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001032                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995583                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65150                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          223                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2446                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5392                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7744                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        49345                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994110                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27379617                       # Number of tag accesses
-system.l2c.tags.data_accesses                27379617                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             898215                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             742471                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             210198                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              63927                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1914811                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          822887                       # number of Writeback hits
-system.l2c.Writeback_hits::total               822887                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             176                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             246                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 422                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            53                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                83                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           152332                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            25116                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               177448                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              898215                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              894803                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              210198                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               89043                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2092259                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             898215                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             894803                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             210198                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              89043                       # number of overall hits
-system.l2c.overall_hits::total                2092259                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13731                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           273058                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1686                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              819                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289294                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2683                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1043                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3726                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          349                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          386                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             735                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         112818                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          10944                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             123762                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13731                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            385876                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1686                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             11763                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                413056                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13731                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           385876                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1686                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            11763                       # number of overall misses
-system.l2c.overall_misses::total               413056                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst   1146699750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  19948507750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    143666750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     75193250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    21314067500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1596458                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      5835814                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      7432272                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1194963                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       187494                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      1382457                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   9983790515                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1229173205                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11212963720                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1146699750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  29932298265                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    143666750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1304366455                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     32527031220                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1146699750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  29932298265                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    143666750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1304366455                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    32527031220                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         911946                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1015529                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         211884                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          64746                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2204105                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       822887                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           822887                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2859                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1289                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4148                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          402                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          416                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           818                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       265150                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        36060                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           301210                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          911946                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1280679                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          211884                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          100806                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2505315                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         911946                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1280679                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         211884                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         100806                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2505315                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015057                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.268883                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007957                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.012649                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.131252                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.938440                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.809154                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.898264                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.868159                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.927885                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.898533                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.425487                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.303494                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.410883                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015057                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.301306                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007957                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.116689                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.164872                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015057                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.301306                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007957                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.116689                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.164872                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 91811.050061                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73676.147794                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   595.027208                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5595.219559                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1994.705314                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3423.962751                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   485.735751                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1880.893878                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88494.659673                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112314.803088                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90601.022285                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 83511.743500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 77569.732932                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85211.595492                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 110887.227323                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78747.267247                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 83511.743500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 77569.732932                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 110887.227323                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78747.267247                       # average overall miss latency
+system.l2c.tags.replacements                   346141                       # number of replacements
+system.l2c.tags.tagsinuse                65297.340756                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4025883                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   411324                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.787620                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7535768000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   53443.709143                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.data      575.898345                       # Average occupied blocks per requestor
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+system.l2c.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         2225                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5965                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6968                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        49797                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 38794162                       # Number of tag accesses
+system.l2c.tags.data_accesses                38794162                       # Number of data accesses
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+system.l2c.overall_avg_miss_latency::total 78580.635505                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1888,239 +1894,253 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.writebacks::total                    83224                       # number of writebacks
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+system.l2c.writebacks::total                    82738                       # number of writebacks
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 system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13722                       # number of ReadReq MSHR misses
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+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 68708.781073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 68708.781073                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              296650                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296572                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12925                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12925                       # Transaction distribution
-system.membus.trans_dist::Writeback            124744                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             9402                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           5001                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4742                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            123808                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           123481                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           78                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       927766                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       968166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1092983                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        72837                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31719616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31792453                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                37110021                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            10437                       # Total snoops (count)
-system.membus.snoop_fanout::samples            614132                       # Request fanout histogram
+system.membus.trans_dist::ReadReq                7202                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296546                       # Transaction distribution
+system.membus.trans_dist::WriteReq              12360                       # Transaction distribution
+system.membus.trans_dist::WriteResp             12360                       # Transaction distribution
+system.membus.trans_dist::Writeback            124264                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262871                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             5279                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           1481                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            3452                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122900                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           122774                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289774                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          430                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39124                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1179542                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          860                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1219526                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124833                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124833                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1344359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        68315                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31641920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31710235                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2658624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                34368859                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3872                       # Total snoops (count)
+system.membus.snoop_fanout::samples            867863                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  614132    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  867863    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              614132                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36342500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              867863                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            35224999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1279237311                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1361324691                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              100000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              531000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2197321028                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2190703579                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           42525497                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72073655                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2231372                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2231278                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12925                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12925                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           822887                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        41587                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            9543                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          5084                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          14627                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302295                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302295                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           78                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1824058                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3369862                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       423804                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       296769                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5914493                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     58364544                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    130195442                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     13560576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     10962579                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              213083141                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           72565                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3425693                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.012192                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.109741                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq               7202                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2275897                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             12360                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            12360                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           985613                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1602095                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            5338                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          1555                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           6893                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           317171                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          317171                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1117101                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1152039                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError          430                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1728214                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2704934                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1334787                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1622621                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7390556                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     39458944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     84672718                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     32025024                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     62527373                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              218684059                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          464381                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5618153                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.076464                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.265739                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3383928     98.78%     98.78% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41765      1.22%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                5188566     92.35%     92.35% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                 429587      7.65%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3425693                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2521355915                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           243000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5618153                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3461836914                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           240000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1371805405                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2024294017                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         925515973                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1363977262                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         318303496                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         751744303                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         173244936                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         856189885                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2154,171 +2174,161 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6519                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    185119                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   65685     40.48%     40.48% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    132      0.08%     40.56% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1924      1.19%     41.75% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    154      0.09%     41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  94359     58.16%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              162254                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    64617     49.22%     49.22% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     132      0.10%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1924      1.47%     50.78% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     154      0.12%     50.90% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   64464     49.10%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               131291                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1861341200000     97.74%     97.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               60253000      0.00%     97.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              540538500      0.03%     97.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               69963500      0.00%     97.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            42290129000      2.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1904302084000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.983741                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    4815                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    139340                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   45519     38.89%     38.89% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    133      0.11%     39.01% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1927      1.65%     40.65% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                     16      0.01%     40.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  69446     59.33%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              117041                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    44932     48.88%     48.88% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     133      0.14%     49.02% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1927      2.10%     51.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                      16      0.02%     51.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   44917     48.86%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total                91925                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1870471244000     98.03%     98.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               61392000      0.00%     98.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              548913500      0.03%     98.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                8511500      0.00%     98.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            36889187000      1.93%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1907979248000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.987104                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.683178                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.809170                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         6      2.79%      2.79% # number of syscalls executed
-system.cpu0.kern.syscall::3                        18      8.37%     11.16% # number of syscalls executed
-system.cpu0.kern.syscall::4                         3      1.40%     12.56% # number of syscalls executed
-system.cpu0.kern.syscall::6                        29     13.49%     26.05% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.47%     26.51% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.47%     26.98% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.19%     31.16% # number of syscalls executed
-system.cpu0.kern.syscall::19                        6      2.79%     33.95% # number of syscalls executed
-system.cpu0.kern.syscall::20                        4      1.86%     35.81% # number of syscalls executed
-system.cpu0.kern.syscall::23                        2      0.93%     36.74% # number of syscalls executed
-system.cpu0.kern.syscall::24                        4      1.86%     38.60% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.26%     41.86% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.93%     42.79% # number of syscalls executed
-system.cpu0.kern.syscall::45                       35     16.28%     59.07% # number of syscalls executed
-system.cpu0.kern.syscall::47                        4      1.86%     60.93% # number of syscalls executed
-system.cpu0.kern.syscall::48                        7      3.26%     64.19% # number of syscalls executed
-system.cpu0.kern.syscall::54                        9      4.19%     68.37% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.47%     68.84% # number of syscalls executed
-system.cpu0.kern.syscall::59                        5      2.33%     71.16% # number of syscalls executed
-system.cpu0.kern.syscall::71                       32     14.88%     86.05% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.40%     87.44% # number of syscalls executed
-system.cpu0.kern.syscall::74                        9      4.19%     91.63% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.47%     92.09% # number of syscalls executed
-system.cpu0.kern.syscall::90                        1      0.47%     92.56% # number of syscalls executed
-system.cpu0.kern.syscall::92                        7      3.26%     95.81% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.93%     96.74% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.93%     97.67% # number of syscalls executed
-system.cpu0.kern.syscall::132                       2      0.93%     98.60% # number of syscalls executed
-system.cpu0.kern.syscall::144                       1      0.47%     99.07% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.93%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   215                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.646790                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.785409                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
+system.cpu0.kern.syscall::6                        33     14.67%     28.44% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.44%     28.89% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.00%     32.89% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.44%     37.33% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.67%     40.00% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.44%     40.44% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.33%     41.78% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.11%     44.89% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.89%     45.78% # number of syscalls executed
+system.cpu0.kern.syscall::45                       36     16.00%     61.78% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.33%     63.11% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.44%     67.56% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.44%     72.00% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.44%     72.44% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.67%     75.11% # number of syscalls executed
+system.cpu0.kern.syscall::71                       25     11.11%     86.22% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.33%     87.56% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.67%     90.22% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.44%     90.67% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.33%     92.00% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.00%     96.00% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.89%     96.89% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.89%     97.78% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.44%     98.22% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.89%     99.11% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  255      0.15%      0.15% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.15% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.15% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.15% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3502      2.05%      2.20% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      43      0.03%      2.23% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.23% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               155594     91.14%     93.38% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6351      3.72%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4450      2.61%     99.71% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 347      0.20%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     148      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                170714                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6908                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1181                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  104      0.08%      0.08% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.09% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.09% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.09% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 2293      1.85%      1.93% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.04%      1.97% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.01%      1.98% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               110963     89.30%     91.28% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6296      5.07%     96.35% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.35% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.35% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.36% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.36% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4002      3.22%     99.58% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 382      0.31%     99.89% # number of callpals executed
+system.cpu0.kern.callpal::imb                     138      0.11%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                124254                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5723                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1342                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1181                      
-system.cpu0.kern.mode_good::user                 1181                      
+system.cpu0.kern.mode_good::kernel               1341                      
+system.cpu0.kern.mode_good::user                 1342                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.170961                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.234318                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.292001                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1901823094000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1927479500      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.379759                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1905987592000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1991648000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3503                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    2294                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2448                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     54000                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   16487     36.42%     36.42% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1922      4.25%     40.66% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    255      0.56%     41.23% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  26607     58.77%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               45271                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    16178     47.20%     47.20% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1922      5.61%     52.80% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     255      0.74%     53.55% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   15923     46.45%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                34278                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1872287559000     98.31%     98.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              533777500      0.03%     98.34% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              116465000      0.01%     98.35% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            31498958000      1.65%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1904436759500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.981258                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    3855                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     98215                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   36112     40.36%     40.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1925      2.15%     42.52% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    104      0.12%     42.63% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  51325     57.37%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               89466                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    35322     48.67%     48.67% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1925      2.65%     51.33% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     104      0.14%     51.47% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   35218     48.53%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                72569                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1870768654000     98.07%     98.07% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              540231000      0.03%     98.10% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               48911000      0.00%     98.10% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            36277143500      1.90%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1907634939500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.978124                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.598452                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.757173                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         2      1.80%      1.80% # number of syscalls executed
-system.cpu1.kern.syscall::3                        12     10.81%     12.61% # number of syscalls executed
-system.cpu1.kern.syscall::4                         1      0.90%     13.51% # number of syscalls executed
-system.cpu1.kern.syscall::6                        13     11.71%     25.23% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.41%     30.63% # number of syscalls executed
-system.cpu1.kern.syscall::19                        4      3.60%     34.23% # number of syscalls executed
-system.cpu1.kern.syscall::20                        2      1.80%     36.04% # number of syscalls executed
-system.cpu1.kern.syscall::23                        2      1.80%     37.84% # number of syscalls executed
-system.cpu1.kern.syscall::24                        2      1.80%     39.64% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.60%     43.24% # number of syscalls executed
-system.cpu1.kern.syscall::45                       19     17.12%     60.36% # number of syscalls executed
-system.cpu1.kern.syscall::47                        2      1.80%     62.16% # number of syscalls executed
-system.cpu1.kern.syscall::48                        3      2.70%     64.86% # number of syscalls executed
-system.cpu1.kern.syscall::54                        1      0.90%     65.77% # number of syscalls executed
-system.cpu1.kern.syscall::59                        2      1.80%     67.57% # number of syscalls executed
-system.cpu1.kern.syscall::71                       22     19.82%     87.39% # number of syscalls executed
-system.cpu1.kern.syscall::74                        7      6.31%     93.69% # number of syscalls executed
-system.cpu1.kern.syscall::90                        2      1.80%     95.50% # number of syscalls executed
-system.cpu1.kern.syscall::92                        2      1.80%     97.30% # number of syscalls executed
-system.cpu1.kern.syscall::132                       2      1.80%     99.10% # number of syscalls executed
-system.cpu1.kern.syscall::144                       1      0.90%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   111                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.686176                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.811135                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
+system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.94%     26.73% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.97%     29.70% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.97%     32.67% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.96%     36.63% # number of syscalls executed
+system.cpu1.kern.syscall::45                       18     17.82%     54.46% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.97%     57.43% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.99%     58.42% # number of syscalls executed
+system.cpu1.kern.syscall::71                       29     28.71%     87.13% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.90%     97.03% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  154      0.33%      0.33% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.33% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.33% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1023      2.18%      2.52% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      10      0.02%      2.54% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.55% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                40053     85.39%     87.95% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2403      5.12%     93.07% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.07% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     93.08% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.00%     93.08% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.09% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3040      6.48%     99.57% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 168      0.36%     99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb                      32      0.07%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1949      2.12%      2.14% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      2.14% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.15% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                84230     91.49%     93.64% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2466      2.68%     96.32% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.32% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.00%     96.32% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     96.33% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3206      3.48%     99.81% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 133      0.14%     99.95% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.05%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 46904                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1413                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                554                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2352                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                733                      
-system.cpu1.kern.mode_good::user                  554                      
-system.cpu1.kern.mode_good::idle                  179                      
-system.cpu1.kern.mode_switch_good::kernel     0.518754                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 92064                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2331                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                395                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2054                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                461                      
+system.cpu1.kern.mode_good::user                  395                      
+system.cpu1.kern.mode_good::idle                   66                      
+system.cpu1.kern.mode_switch_good::kernel     0.197769                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.076105                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.339430                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        4023798000      0.21%      0.21% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           775821000      0.04%      0.25% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1899637132500     99.75%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1024                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.032132                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.192887                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       42837305000      2.25%      2.25% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           697376000      0.04%      2.28% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1863790118000     97.72%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1950                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 038a204b1..156f5647f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,112 +1,112 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.861006                       # Number of seconds simulated
-sim_ticks                                1861005569500                       # Number of ticks simulated
-final_tick                               1861005569500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.861005                       # Number of seconds simulated
+sim_ticks                                1861005347500                       # Number of ticks simulated
+final_tick                               1861005347500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152837                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152837                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5373256396                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 376300                       # Number of bytes of host memory used
-host_seconds                                   346.35                       # Real time elapsed on the host
-sim_insts                                    52934565                       # Number of instructions simulated
-sim_ops                                      52934565                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 149955                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149955                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5267476367                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 376564                       # Number of bytes of host memory used
+host_seconds                                   353.30                       # Real time elapsed on the host
+sim_insts                                    52979113                       # Number of instructions simulated
+sim_ops                                      52979113                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            968000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24876864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            965824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24879488                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25845824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       968000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          968000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7517248                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7517248                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388701                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25846272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       965824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          965824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7524416                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7524416                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15091                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388742                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403841                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117457                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117457                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               520149                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13367431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403848                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117569                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117569                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               518980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13368843                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13888096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          520149                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             520149                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4039347                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4039347                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4039347                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              520149                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13367431                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13888338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          518980                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518980                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4043200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4043200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4043200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              518980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13368843                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17927443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403841                       # Number of read requests accepted
-system.physmem.writeReqs                       159009                       # Number of write requests accepted
-system.physmem.readBursts                      403841                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     159009                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bw_total::total               17931538                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403848                       # Number of read requests accepted
+system.physmem.writeReqs                       117569                       # Number of write requests accepted
+system.physmem.readBursts                      403848                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117569                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                 25839488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6336                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8519424                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25845824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10176576                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       99                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   25870                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            189                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25748                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25559                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25508                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25346                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25393                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24806                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25027                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25127                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24925                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25034                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25436                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24774                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24551                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25233                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25663                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25612                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9148                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8514                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8998                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8298                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8214                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7705                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7696                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7707                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8055                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7602                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8149                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7799                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8377                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9062                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8903                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8889                       # Per bank write bursts
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7523328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25846272                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7524416                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          41759                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25651                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25422                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25567                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25497                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25384                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24734                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24943                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25079                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24928                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25027                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25572                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24872                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24489                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25240                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25741                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25596                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7944                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7514                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7965                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7518                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7330                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6666                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6776                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6716                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7141                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6711                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7422                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6968                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7145                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7857                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8054                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7825                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          85                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1861000236500                       # Total gap between requests
+system.physmem.numWrRetry                          23                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1860999975500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403841                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403848                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 159009                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    314763                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117569                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    314964                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     36182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24147                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -148,199 +148,190 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5789                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5988                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1519                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      323                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62685                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      548.114030                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     339.010384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.134053                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13424     21.42%     21.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10425     16.63%     38.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5386      8.59%     46.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2710      4.32%     50.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2462      3.93%     54.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1644      2.62%     57.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1512      2.41%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1300      2.07%     62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23822     38.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62685                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4847                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        83.295234                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3032.862596                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           4844     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1537                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       41                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61779                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      540.028683                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     331.823835                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.833229                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13638     22.08%     22.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10412     16.85%     38.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4989      8.08%     47.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3229      5.23%     52.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2263      3.66%     55.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1516      2.45%     58.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1526      2.47%     60.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1289      2.09%     62.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22917     37.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61779                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5213                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.447919                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2924.392219                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5210     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4847                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4847                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.463586                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.516932                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       62.014286                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4601     94.92%     94.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              56      1.16%     96.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               4      0.08%     96.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               1      0.02%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              13      0.27%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              3      0.06%     96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127             3      0.06%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             6      0.12%     96.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            21      0.43%     97.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            18      0.37%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191             8      0.17%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            12      0.25%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             2      0.04%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             4      0.08%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.02%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.04%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             5      0.10%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            17      0.35%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            13      0.27%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             3      0.06%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383            11      0.23%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             4      0.08%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             2      0.04%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             2      0.04%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             4      0.08%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             4      0.08%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             4      0.08%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.04%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.04%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             8      0.17%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             2      0.04%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::624-639             2      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             2      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4847                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3741904500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11312067000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.rdPerTurnAround::total            5213                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5213                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.549779                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.928650                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.456391                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4618     88.59%     88.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             208      3.99%     92.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              74      1.42%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              17      0.33%     94.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               8      0.15%     94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               5      0.10%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              10      0.19%     94.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              10      0.19%     94.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               7      0.13%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              32      0.61%     95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            168      3.22%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            10      0.19%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.04%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             5      0.10%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             2      0.04%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             2      0.04%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             3      0.06%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.04%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             5      0.10%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.06%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.08%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231            12      0.23%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5213                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3805918000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11376080500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2018710000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9268.06                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9426.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28018.06                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28176.61                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.58                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.89                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.47                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.48                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.77                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364326                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109846                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.24                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.50                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3306387.56                       # Average gap between requests
-system.physmem.pageHitRate                      88.32                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  235516680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  128506125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1579609200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                429494400                       # Energy for write commands per rank (pJ)
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.30                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364169                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95345                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.20                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.10                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3569120.25                       # Average gap between requests
+system.physmem.pageHitRate                      88.15                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  232515360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126868500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1577760600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                378619920                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           121551434160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            56182721175                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1067316698250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1247423979990                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.297807                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1775410357162                       # Time in different power states
+system.physmem_0.actBackEnergy            56250477360                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1067257263000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1247374938900                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.271455                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1775312455750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     62142860000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     23446441588                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23544343000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  238381920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  130069500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1569531600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                433097280                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  234533880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  127969875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1571380200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                383117040                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           121551434160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            56034129015                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1067447050500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1247403693975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.286901                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1775626000168                       # Time in different power states
+system.physmem_1.actBackEnergy            55982569095                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1067492278500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1247343282750                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.254439                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1775708219250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     62142860000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23231077332                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23148593250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17721924                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15403228                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            380344                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11703979                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5913014                       # Number of BTB hits
+system.cpu.branchPred.lookups                17721018                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15408782                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            378784                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12470436                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5897235                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             50.521400                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  923784                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21447                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             47.289726                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  918220                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21032                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10269214                       # DTB read hits
-system.cpu.dtb.read_misses                      41261                       # DTB read misses
-system.cpu.dtb.read_acv                           507                       # DTB read access violations
-system.cpu.dtb.read_accesses                   967301                       # DTB read accesses
-system.cpu.dtb.write_hits                     6648637                       # DTB write hits
-system.cpu.dtb.write_misses                      9303                       # DTB write misses
-system.cpu.dtb.write_acv                          402                       # DTB write access violations
-system.cpu.dtb.write_accesses                  342644                       # DTB write accesses
-system.cpu.dtb.data_hits                     16917851                       # DTB hits
-system.cpu.dtb.data_misses                      50564                       # DTB misses
-system.cpu.dtb.data_acv                           909                       # DTB access violations
-system.cpu.dtb.data_accesses                  1309945                       # DTB accesses
-system.cpu.itb.fetch_hits                     1769158                       # ITB hits
-system.cpu.itb.fetch_misses                     36068                       # ITB misses
-system.cpu.itb.fetch_acv                          660                       # ITB acv
-system.cpu.itb.fetch_accesses                 1805226                       # ITB accesses
+system.cpu.dtb.read_hits                     10294388                       # DTB read hits
+system.cpu.dtb.read_misses                      42024                       # DTB read misses
+system.cpu.dtb.read_acv                           506                       # DTB read access violations
+system.cpu.dtb.read_accesses                   968687                       # DTB read accesses
+system.cpu.dtb.write_hits                     6648521                       # DTB write hits
+system.cpu.dtb.write_misses                      9456                       # DTB write misses
+system.cpu.dtb.write_acv                          408                       # DTB write access violations
+system.cpu.dtb.write_accesses                  343243                       # DTB write accesses
+system.cpu.dtb.data_hits                     16942909                       # DTB hits
+system.cpu.dtb.data_misses                      51480                       # DTB misses
+system.cpu.dtb.data_acv                           914                       # DTB access violations
+system.cpu.dtb.data_accesses                  1311930                       # DTB accesses
+system.cpu.itb.fetch_hits                     1769476                       # ITB hits
+system.cpu.itb.fetch_misses                     36155                       # ITB misses
+system.cpu.itb.fetch_acv                          662                       # ITB acv
+system.cpu.itb.fetch_accesses                 1805631                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -353,258 +344,258 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        122572361                       # number of cpu cycles simulated
+system.cpu.numCycles                        122272854                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29541441                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       78093998                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17721924                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6836798                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      84630340                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1254210                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1349                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                26888                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1745325                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       441267                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          294                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9051182                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                273719                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          117014009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.667390                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.979034                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29542399                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       77951342                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17721018                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6815455                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      84318662                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1251172                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1032                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27002                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1751503                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       450615                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          220                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9037094                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                274713                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116717019                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.667866                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.979948                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                102427448     87.53%     87.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   934169      0.80%     88.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1984138      1.70%     90.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   910061      0.78%     90.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2793690      2.39%     93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   647956      0.55%     93.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   739168      0.63%     94.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1007210      0.86%     95.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5570169      4.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                102159840     87.53%     87.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   935001      0.80%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1975635      1.69%     90.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   907890      0.78%     90.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2798283      2.40%     93.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   634657      0.54%     93.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   731012      0.63%     94.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1008696      0.86%     95.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5566005      4.77%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            117014009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.144583                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.637126                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24038562                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              80987042                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9497307                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1906242                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 584855                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               586733                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42672                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68295720                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                134238                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 584855                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24961940                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                51456440                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20841952                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10391328                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8777492                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65857652                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                204161                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2078785                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 153522                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4578470                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43917673                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79850033                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79669145                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168436                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38142428                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5775237                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1690640                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         240974                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13460579                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10430513                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6961741                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1496363                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1107333                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58622970                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2136022                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57539781                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             62715                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7824422                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3554737                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1474907                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     117014009                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.491734                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.229968                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            116717019                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.144930                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.637520                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24051579                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              80690981                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9487535                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1903773                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 583150                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               586842                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42848                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68182155                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                134674                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 583150                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24974215                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50913599                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20868972                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10381558                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8995523                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65764072                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                201455                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2078667                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 157006                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4811107                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43858088                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79749030                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79568293                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168286                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38179356                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5678724                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1691117                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         241700                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13523739                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10414999                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6951257                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1489090                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1076371                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58557437                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2137330                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57550552                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             58383                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7715649                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3482179                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1476201                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116717019                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.493078                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.231262                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            93391037     79.81%     79.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10179390      8.70%     88.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4310458      3.68%     92.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3008329      2.57%     94.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3082993      2.63%     97.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1515380      1.30%     98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1001151      0.86%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              403458      0.34%     99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              121813      0.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            93076852     79.75%     79.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10193735      8.73%     88.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4312708      3.70%     92.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3021195      2.59%     94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3081764      2.64%     97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1495449      1.28%     98.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1007889      0.86%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              403235      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              124192      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       117014009                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116717019                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  210088     18.84%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 537781     48.22%     67.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                367354     32.94%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  208462     18.43%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 547266     48.38%     66.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                375475     33.19%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39070075     67.90%     67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61902      0.11%     68.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38396      0.07%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10678994     18.56%     86.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6730550     11.70%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             948942      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39056911     67.87%     67.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61891      0.11%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38552      0.07%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10704988     18.60%     86.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6728388     11.69%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             948900      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57539781                       # Type of FU issued
-system.cpu.iq.rate                           0.469435                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1115223                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019382                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          232558248                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          68266797                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55883323                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              713260                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             336497                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       329169                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58264569                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  383149                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           636979                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57550552                       # Type of FU issued
+system.cpu.iq.rate                           0.470673                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1131203                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019656                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          232294841                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          68093775                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55871823                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              712867                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336544                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       329026                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58291729                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  382740                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           634925                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1345105                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3404                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20302                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       587155                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1322411                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3516                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20331                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       573217                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18243                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        442853                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18302                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        483316                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 584855                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                48003305                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1105875                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64465821                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            144286                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10430513                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6961741                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1886655                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  45598                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                856452                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20302                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         189944                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       410798                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               600742                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56947023                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10338131                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            592757                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 583150                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                47678109                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                871068                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64398227                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            142430                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10414999                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6951257                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1888726                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  44438                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                623782                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20331                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         186400                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       411798                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               598198                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56961347                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10364061                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            589204                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3706829                       # number of nop insts executed
-system.cpu.iew.exec_refs                     17011176                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8976912                       # Number of branches executed
-system.cpu.iew.exec_stores                    6673045                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.464599                       # Inst execution rate
-system.cpu.iew.wb_sent                       56353404                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56212492                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28792537                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  40027235                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3703460                       # number of nop insts executed
+system.cpu.iew.exec_refs                     17037134                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8968929                       # Number of branches executed
+system.cpu.iew.exec_stores                    6673073                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.465854                       # Inst execution rate
+system.cpu.iew.wb_sent                       56337909                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56200849                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28756133                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  39912635                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.458607                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.719324                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.459635                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.720477                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8228560                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661115                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            549076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    115576332                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.485596                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.428292                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         8112704                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661129                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            547326                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    115294268                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.487187                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.430320                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     95814381     82.90%     82.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7848857      6.79%     89.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4272055      3.70%     93.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2211253      1.91%     95.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1764306      1.53%     96.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615369      0.53%     97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       473669      0.41%     97.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       490996      0.42%     98.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2085446      1.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     95501177     82.83%     82.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7867272      6.82%     89.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4280982      3.71%     93.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2233083      1.94%     95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1745854      1.51%     96.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       611445      0.53%     97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       482985      0.42%     97.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       468960      0.41%     98.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2102510      1.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    115576332                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56123349                       # Number of instructions committed
-system.cpu.commit.committedOps               56123349                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    115294268                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56169836                       # Number of instructions committed
+system.cpu.commit.committedOps               56169836                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15459994                       # Number of memory references committed
-system.cpu.commit.loads                       9085408                       # Number of loads committed
-system.cpu.commit.membars                      226308                       # Number of memory barriers committed
-system.cpu.commit.branches                    8435685                       # Number of branches committed
-system.cpu.commit.fp_insts                     324451                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  51974864                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740049                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3196057      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36183700     64.47%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60673      0.11%     70.27% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.27% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd          38087      0.07%     70.34% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.34% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.34% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.34% # Class of committed instruction
+system.cpu.commit.refs                       15470628                       # Number of memory references committed
+system.cpu.commit.loads                       9092588                       # Number of loads committed
+system.cpu.commit.membars                      226333                       # Number of memory barriers committed
+system.cpu.commit.branches                    8440353                       # Number of branches committed
+system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  52019375                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740552                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3197996      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36217639     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60667      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.35% # Class of committed instruction
@@ -627,411 +618,417 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9311716     16.59%     86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6380538     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        948942      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9318921     16.59%     86.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6383992     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        948900      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56123349                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2085446                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    177593268                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130137832                       # The number of ROB writes
-system.cpu.timesIdled                          572499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5558352                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3599438779                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52934565                       # Number of Instructions Simulated
-system.cpu.committedOps                      52934565                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.315545                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.315545                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.431864                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.431864                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74599299                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40560409                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    167171                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167579                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2029670                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939349                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1403663                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994456                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11858482                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1404175                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.445160                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          26416000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994456                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total          56169836                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2102510                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    177224791                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129983616                       # The number of ROB writes
+system.cpu.timesIdled                          573073                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5555835                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3599737842                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52979113                       # Number of Instructions Simulated
+system.cpu.committedOps                      52979113                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.307945                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.307945                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.433286                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.433286                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74622251                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40551917                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    167069                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167545                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2028916                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939321                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1404299                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994455                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11844191                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1404811                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.431163                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          26393500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994455                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          413                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          412                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63936372                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63936372                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7267066                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7267066                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4189300                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4189300                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186111                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186111                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215710                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215710                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11456366                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11456366                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11456366                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11456366                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1796718                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1796718                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1954848                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1954848                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23269                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23269                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           27                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           27                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3751566                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3751566                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3751566                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3751566                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  41841354315                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  41841354315                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  80890725520                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  80890725520                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376182249                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    376182249                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       455005                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       455005                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 122732079835                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 122732079835                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 122732079835                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 122732079835                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9063784                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9063784                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6144148                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6144148                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209380                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209380                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215737                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215737                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15207932                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15207932                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15207932                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15207932                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.198230                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.198230                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318164                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318164                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111133                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111133                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000125                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000125                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.246685                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.246685                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.246685                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.246685                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32714.892883                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32714.892883                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      4477894                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         2036                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            123579                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    36.235072                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    88.521739                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          63926076                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63926076                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7252822                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7252822                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4188714                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4188714                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186644                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186644                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215706                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215706                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11441536                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11441536                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11441536                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11441536                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1804157                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1804157                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1958890                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1958890                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23354                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23354                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           29                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3763047                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3763047                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3763047                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3763047                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  41750233000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  41750233000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  80527676066                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  80527676066                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    377889000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    377889000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       498500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       498500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 122277909066                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 122277909066                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 122277909066                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 122277909066                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9056979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9056979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147604                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147604                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209998                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209998                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215735                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215735                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15204583                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15204583                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15204583                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15204583                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199201                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.199201                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318643                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318643                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111211                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111211                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000134                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000134                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247494                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247494                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247494                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247494                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23141.130733                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23141.130733                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41108.830034                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41108.830034                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16180.911193                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16180.911193                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17189.655172                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17189.655172                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32494.387943                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32494.387943                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32494.387943                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32494.387943                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4529793                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         2677                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            135335                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              25                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.470965                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   107.080000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842087                       # number of writebacks
-system.cpu.dcache.writebacks::total            842087                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       701160                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       701160                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664055                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1664055                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5272                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5272                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2365215                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2365215                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2365215                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2365215                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1095558                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1095558                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290793                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290793                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17997                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17997                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           27                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           27                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1386351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1386351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1386351                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1386351                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       842762                       # number of writebacks
+system.cpu.dcache.writebacks::total            842762                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       708195                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       708195                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1668077                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1668077                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5151                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5151                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2376272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2376272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2376272                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2376272                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1095962                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1095962                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290813                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290813                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18203                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18203                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           29                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1386775                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1386775                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1386775                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1386775                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9597                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9597                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16527                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16527                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29996933023                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29996933023                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12482529124                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12482529124                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214354001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214354001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       414495                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       414495                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42479462147                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  42479462147                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42479462147                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  42479462147                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1433706500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1433706500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011966000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011966000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3445672500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3445672500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120872                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120872                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047328                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047328                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085954                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085954                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000125                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000125                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091160                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091160                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091160                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091160                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30575992000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30575992000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12635842717                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12635842717                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    226273500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    226273500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       469500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       469500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43211834717                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  43211834717                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43211834717                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  43211834717                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1451037500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1451037500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2035928998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2035928998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3486966498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3486966498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121007                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121007                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047305                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047305                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086682                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086682                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000134                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000134                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091208                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091208                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091208                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091208                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1032757                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.197301                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7965141                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1033265                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.708711                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       28360334250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.197301                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994526                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1035158                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.238634                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7947846                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1035666                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.674140                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       28148361500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.238634                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994607                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994607                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          304                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10084699                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10084699                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7965142                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7965142                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7965142                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7965142                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7965142                       # number of overall hits
-system.cpu.icache.overall_hits::total         7965142                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1086038                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1086038                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1086038                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1086038                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1086038                       # number of overall misses
-system.cpu.icache.overall_misses::total       1086038                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15222356868                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15222356868                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15222356868                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15222356868                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15222356868                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15222356868                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9051180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9051180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9051180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9051180                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9051180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9051180                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119989                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.119989                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.119989                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.119989                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.119989                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.119989                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14016.412748                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14016.412748                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5848                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10073023                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10073023                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7947847                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7947847                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7947847                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7947847                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7947847                       # number of overall hits
+system.cpu.icache.overall_hits::total         7947847                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1089244                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1089244                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1089244                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1089244                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1089244                       # number of overall misses
+system.cpu.icache.overall_misses::total       1089244                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15223822993                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15223822993                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15223822993                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15223822993                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15223822993                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15223822993                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9037091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9037091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9037091                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9037091                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9037091                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9037091                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120530                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.120530                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.120530                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.120530                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.120530                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.120530                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13976.503881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13976.503881                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5247                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               208                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.115385                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    27.328125                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        52519                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        52519                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        52519                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        52519                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        52519                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        52519                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1033519                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1033519                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1033519                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1033519                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1033519                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1033519                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13013904297                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13013904297                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13013904297                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13013904297                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13013904297                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13013904297                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114186                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114186                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114186                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114186                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114186                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114186                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53312                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1035932                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13551519997                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total  13551519997                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114631                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114631                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114631                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338332                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65331.413764                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2572439                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403497                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.375361                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5986676750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5347.510273                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6335.411477                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.818611                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081597                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::total     0.996878                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           338333                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65329.899668                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4170748                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403498                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.336478                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5937880000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53646.073919                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5370.196877                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65165                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          491                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3500                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3327                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          490                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3506                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3328                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2403                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55444                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994339                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26943938                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26943938                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::total        1846951                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       842087                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       842087                       # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total           31                       # number of UpgradeReq hits
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-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           27                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014639                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.607595                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.607595                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.185185                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627                       # average ReadReq miss latency
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-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000                       # average SCUpgradeReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910                       # average overall miss latency
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+system.cpu.l2cache.tags.data_accesses        39732941                       # Number of data accesses
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1257093500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1257093500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19996128500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  19996128500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1257093500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30299336500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  31556430000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1257093500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30299336500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  31556430000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       842762                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       842762                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           82                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           82                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           29                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           29                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.data      1404897                       # number of demand (read+write) accesses
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.646341                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.646341                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.206897                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.206897                       # miss rate for SCUpgradeReq accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014572                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014572                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248213                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248213                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014572                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.277067                       # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014572                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.277067                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.165671                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  8018.867925                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  8018.867925                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89278.696764                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89278.696764                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83289.836348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83289.836348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73019.611387                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73019.611387                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83289.836348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77840.099319                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78043.522347                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83289.836348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77840.099319                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78043.522347                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1040,130 +1037,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75945                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75945                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        76057                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76057                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15126                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273931                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       289057                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           48                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           48                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.data       389207                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404333                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15126                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389207                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404333                       # number of overall MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          307                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          307                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           53                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           53                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            6                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            6                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15092                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15092                       # number of ReadCleanReq MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273846                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9597                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9597                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16527                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16527                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1075826749                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16607896000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  17683722749                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1000544                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1000544                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        89005                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        89005                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total  26545366637                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25469539888                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26545366637                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1336686500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1336686500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1887182500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887182500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3223869000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3223869000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014638                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248428                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.135326                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.607595                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.607595                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.185185                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.185185                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382198                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382198                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014638                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277160                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165872                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014638                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277160                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        17801                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        17801                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1250500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1250500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       124500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       124500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9149158000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9149158000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1106078000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1106078000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17268105500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17268105500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1106078000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26417263500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27523341500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1106078000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26417263500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27523341500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364412500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364412500                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3289960000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3289960000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.646341                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.646341                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.206897                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.206897                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382611                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382611                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014571                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248213                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248213                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277067                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.165671                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277067                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165671                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        20750                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        20750                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2143279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2143168                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2146205                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       842087                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41601                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           27                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          106                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301613                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301613                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           94                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2066871                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3684049                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5750920                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66134528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143814956                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          209949484                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       42097                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3338284                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.012514                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.111162                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::Writeback       960354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1857372                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           82                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           29                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          111                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       301625                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       301625                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1035932                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1103445                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           85                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3106451                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4246137                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7352588                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66287680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143898860                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          210186540                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422109                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5318690                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.079299                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.270205                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3296510     98.75%     98.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41774      1.25%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4896924     92.07%     92.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             421766      7.93%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3338284                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2495140999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::total        5318690                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3296022500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1554402947                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1555343104                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2190379636                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2119169250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1180,8 +1188,7 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9597                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1236,21 +1243,21 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           242053963                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216065006                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42024003                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.259192                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.259177                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1711311066000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.259192                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         1711311931000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.259177                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.078699                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.078699                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1260,49 +1267,49 @@ system.iocache.tags.tag_accesses               375525                       # Nu
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21719383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21719383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8765491577                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8765491577                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21719383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21719383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21719383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21719383                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21637883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21637883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4909206123                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4909206123                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21637883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21637883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21637883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21637883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125545.566474                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125545.566474                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125545.566474                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         73146                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125074.468208                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125074.468208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125074.468208                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10015                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.303645                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1310,84 +1317,86 @@ system.iocache.writebacks::writebacks           41512                       # nu
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12567383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12567383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6604781583                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6604781583                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12567383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12567383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12567383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12567383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12987883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12987883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2831606123                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2831606123                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12987883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12987883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12987883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12987883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72643.832370                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72643.832370                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              296160                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296066                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295956                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback            117457                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              187                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              5                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             192                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115137                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115137                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           94                       # Transaction distribution
+system.membus.trans_dist::Writeback            117569                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261797                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              204                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             210                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115254                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115254                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289111                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           85                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884252                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          188                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917494                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1042298                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1146198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          170                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179422                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1304239                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30705344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30749484                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36066540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30712960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30757100                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33414828                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              435                       # Total snoops (count)
-system.membus.snoop_fanout::samples            580180                       # Request fanout histogram
+system.membus.snoop_fanout::samples            842203                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  580180    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  842203    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              580180                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29181000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              842203                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29160500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1226050062                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1313577675                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              118000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              109500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2139458813                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2139558790                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           42497997                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72030935                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -1421,28 +1430,28 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6445                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     210982                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74654     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     210978                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74652     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105549     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182213                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73287     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105547     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182209                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73285     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73287     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148584                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817355802000     97.65%     97.65% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                62075500      0.00%     97.66% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               532990500      0.03%     97.69% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             43053863500      2.31%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1861004731500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981689                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73285     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148580                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1817522630000     97.66%     97.66% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                62579500      0.00%     97.67% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               533633500      0.03%     97.70% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             42885651500      2.30%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1861004494500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981688                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694341                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815441                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694335                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815437                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1478,11 +1487,11 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.18%      2.18% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175098     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6783      3.53%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175094     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
@@ -1490,20 +1499,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.98% # nu
 system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191942                       # number of callpals executed
+system.cpu.kern.callpal::total                 191938                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1911                      
-system.cpu.kern.mode_good::user                  1741                      
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1907                      
+system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326667                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.325983                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394509                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29153631500      1.57%      1.57% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2692582500      0.14%      1.71% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1829158509500     98.29%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.393886                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29174464500      1.57%      1.57% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2684090500      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1829145931500     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index e143de192..8b67c053c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,131 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.841539                       # Number of seconds simulated
-sim_ticks                                1841538755500                       # Number of ticks simulated
-final_tick                               1841538755500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.841548                       # Number of seconds simulated
+sim_ticks                                1841548033500                       # Number of ticks simulated
+final_tick                               1841548033500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 221997                       # Simulator instruction rate (inst/s)
-host_op_rate                                   221997                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5796715531                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 374488                       # Number of bytes of host memory used
-host_seconds                                   317.69                       # Real time elapsed on the host
-sim_insts                                    70525499                       # Number of instructions simulated
-sim_ops                                      70525499                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 218310                       # Simulator instruction rate (inst/s)
+host_op_rate                                   218310                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5702515722                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 375536                       # Number of bytes of host memory used
+host_seconds                                   322.94                       # Real time elapsed on the host
+sim_insts                                    70500110                       # Number of instructions simulated
+sim_ops                                      70500110                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           467648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20091072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2148032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           308096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2634304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           465600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20057408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           147136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2156416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           307456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2656704                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25797120                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       467648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       308096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          922752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7481856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7481856                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7307                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            313923                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             33563                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4814                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             41161                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25791680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       465600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       147136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       307456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          920192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7484672                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7484672                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7275                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            313397                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2299                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             33694                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             41511                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403080                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116904                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116904                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              253944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10909937                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               79829                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1166433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              167304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1430491                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                402995                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116948                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116948                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              252831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10891602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1170980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              166955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1442647                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14008459                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         253944                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          79829                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         167304                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             501077                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4062828                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4062828                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4062828                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             253944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10909937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              79829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1166433                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             167304                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1430491                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                14005434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         252831                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79898                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         166955                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             499684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4064337                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4064337                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4064337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             252831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10891602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1170980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             166955                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1442647                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18071287                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         81850                       # Number of read requests accepted
-system.physmem.writeReqs                        64472                       # Number of write requests accepted
-system.physmem.readBursts                       81850                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      64472                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5236928                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   3416192                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5238400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4126208                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       23                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   11076                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             49                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4878                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4919                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4947                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                4947                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5010                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5136                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5318                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5111                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5349                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4830                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5530                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5119                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4880                       # Per bank write bursts
+system.physmem.bw_total::total               18069771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         82323                       # Number of read requests accepted
+system.physmem.writeReqs                        47461                       # Number of write requests accepted
+system.physmem.readBursts                       82323                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      47461                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5267264                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   3035584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5268672                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                3037504                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          17348                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                4998                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5047                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4951                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                4902                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5135                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5137                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5321                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5238                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5355                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                4827                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5539                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5124                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4881                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               5044                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5637                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5172                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                3097                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                3264                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                3389                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3378                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3165                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                3060                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                3647                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                3165                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3847                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                3079                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3680                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3339                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2997                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               3248                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3739                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3284                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5631                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5171                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2712                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2869                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2967                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                2927                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                2992                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2769                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                3293                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2918                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3398                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2634                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3325                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2913                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2642                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2800                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3388                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2884                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1840526879500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1840536161000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   81850                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   82323                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  64472                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     63937                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7813                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5603                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      4447                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  47461                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     64278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7820                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      4551                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -153,9 +153,9 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        47                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        41                       # What write queue length does an incoming req see
@@ -164,185 +164,194 @@ system.physmem.wrQLenPdf::7                        39                       # Wh
 system.physmem.wrQLenPdf::8                        38                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     2163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     2056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     2250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     2237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     3121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        22135                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      390.924780                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     222.627349                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     384.024543                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7145     32.28%     32.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4994     22.56%     54.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1972      8.91%     63.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1000      4.52%     68.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          834      3.77%     72.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          471      2.13%     74.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          534      2.41%     76.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          337      1.52%     78.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4848     21.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          22135                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          1909                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        42.863279                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1017.016663                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           1907     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     2418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     2764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     2856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     3843                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     3517                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     2960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     3353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     3003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21805                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      380.777253                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     217.097266                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     378.211296                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7203     33.03%     33.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4880     22.38%     55.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2010      9.22%     64.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1038      4.76%     69.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          857      3.93%     73.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          538      2.47%     75.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          425      1.95%     77.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          372      1.71%     79.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4482     20.55%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21805                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2075                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        39.654458                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      980.113813                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2073     99.90%     99.90% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            1909                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          1909                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.961236                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.965205                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       62.780578                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               45      2.36%      2.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            1768     92.61%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              14      0.73%     95.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               2      0.10%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95               2      0.10%     95.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              1      0.05%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127             1      0.05%     96.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             2      0.10%     96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            11      0.58%     96.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            12      0.63%     97.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191             5      0.26%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207             8      0.42%     98.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             1      0.05%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.05%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.10%     98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             2      0.10%     98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             6      0.31%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             5      0.26%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             2      0.10%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             2      0.10%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.05%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.05%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.10%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.10%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.16%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             4      0.21%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             2      0.10%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            1909                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      884680000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2418936250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    409135000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10811.59                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2075                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.858313                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.353134                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.870235                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                34      1.64%      1.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.34%      1.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                2      0.10%      2.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.24%      2.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1736     83.66%     85.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              36      1.73%     87.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              80      3.86%     91.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              17      0.82%     92.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              12      0.58%     92.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              17      0.82%     93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               5      0.24%     94.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.05%     94.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.05%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.10%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               3      0.14%     94.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.05%     94.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.19%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.05%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.10%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.05%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.14%     94.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               9      0.43%     95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.19%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            65      3.13%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.14%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             3      0.14%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.05%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             2      0.10%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.05%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.05%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.05%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.10%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.10%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.10%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.05%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             3      0.14%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.05%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             4      0.19%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2075                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      914891250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2458035000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    411505000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11116.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29561.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.24                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29866.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.86                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.86                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.65                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.99                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      70087                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     42983                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.50                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12578606.63                       # Average gap between requests
-system.physmem.pageHitRate                      83.62                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   81814320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   44558250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 314074800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                169549200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89055975840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            35647575705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           798651060750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             923964608865                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.989912                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1309028017250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45529640000                       # Time in different power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         2.86                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      70476                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     37451                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14181533.63                       # Average gap between requests
+system.physmem.pageHitRate                      83.17                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   81194400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   44195250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 317686200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                151936560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89056992960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            35637705585                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           799850646000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             925140356955                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.881529                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1309035077000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45530160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9101184500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9110965500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   85526280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   46513500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 324175800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                176340240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89055975840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35475772860                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           801505403250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             926669707770                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.770193                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1309231204000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45529640000                       # Time in different power states
+system.physmem_1.actEnergy                   83651400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   45474000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 324261600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                155416320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89056992960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35441943930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           803933138250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             929040878460                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.556246                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1309294919000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45530160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8903896000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      8868165750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4781172                       # DTB read hits
-system.cpu0.dtb.read_misses                      6058                       # DTB read misses
-system.cpu0.dtb.read_acv                          118                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  428328                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3391530                       # DTB write hits
-system.cpu0.dtb.write_misses                      675                       # DTB write misses
-system.cpu0.dtb.write_acv                          82                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 163639                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8172702                       # DTB hits
-system.cpu0.dtb.data_misses                      6733                       # DTB misses
-system.cpu0.dtb.data_acv                          200                       # DTB access violations
-system.cpu0.dtb.data_accesses                  591967                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2720050                       # ITB hits
-system.cpu0.itb.fetch_misses                     3046                       # ITB misses
-system.cpu0.itb.fetch_acv                          99                       # ITB acv
-system.cpu0.itb.fetch_accesses                2723096                       # ITB accesses
+system.cpu0.dtb.read_hits                     4775602                       # DTB read hits
+system.cpu0.dtb.read_misses                      5966                       # DTB read misses
+system.cpu0.dtb.read_acv                          109                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  428378                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3387346                       # DTB write hits
+system.cpu0.dtb.write_misses                      667                       # DTB write misses
+system.cpu0.dtb.write_acv                          80                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 163776                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8162948                       # DTB hits
+system.cpu0.dtb.data_misses                      6633                       # DTB misses
+system.cpu0.dtb.data_acv                          189                       # DTB access violations
+system.cpu0.dtb.data_accesses                  592154                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2717036                       # ITB hits
+system.cpu0.itb.fetch_misses                     3019                       # ITB misses
+system.cpu0.itb.fetch_acv                          97                       # ITB acv
+system.cpu0.itb.fetch_accesses                2720055                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -355,87 +364,87 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       930048733                       # number of cpu cycles simulated
+system.cpu0.numCycles                       930055234                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31504183                       # Number of instructions committed
-system.cpu0.committedOps                     31504183                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             29439494                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                162688                       # Number of float alu accesses
-system.cpu0.num_func_calls                     792913                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4107229                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    29439494                       # number of integer instructions
-system.cpu0.num_fp_insts                       162688                       # number of float instructions
-system.cpu0.num_int_register_reads           41004383                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21582488                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84172                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              85625                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8202083                       # number of memory refs
-system.cpu0.num_load_insts                    4802046                       # Number of load instructions
-system.cpu0.num_store_insts                   3400037                       # Number of store instructions
-system.cpu0.num_idle_cycles              907048310.649553                       # Number of idle cycles
-system.cpu0.num_busy_cycles              23000422.350447                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.024730                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.975270                       # Percentage of idle cycles
-system.cpu0.Branches                          5154717                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1560474      4.95%      4.95% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 21056937     66.82%     71.78% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31354      0.10%     71.88% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.88% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12843      0.04%     71.92% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1601      0.01%     71.92% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.92% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4932088     15.65%     87.57% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3403118     10.80%     98.37% # Class of executed instruction
-system.cpu0.op_class::IprAccess                512701      1.63%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   31475732                       # Number of instructions committed
+system.cpu0.committedOps                     31475732                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             29412106                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                162586                       # Number of float alu accesses
+system.cpu0.num_func_calls                     792411                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4104277                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    29412106                       # number of integer instructions
+system.cpu0.num_fp_insts                       162586                       # number of float instructions
+system.cpu0.num_int_register_reads           40967178                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          21562005                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               84110                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              85570                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8192042                       # number of memory refs
+system.cpu0.num_load_insts                    4796241                       # Number of load instructions
+system.cpu0.num_store_insts                   3395801                       # Number of store instructions
+system.cpu0.num_idle_cycles              907058327.289346                       # Number of idle cycles
+system.cpu0.num_busy_cycles              22996906.710654                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024726                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975274                       # Percentage of idle cycles
+system.cpu0.Branches                          5151040                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1559860      4.95%      4.95% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 21040910     66.83%     71.79% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31347      0.10%     71.89% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.89% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12827      0.04%     71.93% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1598      0.01%     71.93% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.93% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4926196     15.65%     87.58% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3398883     10.80%     98.38% # Class of executed instruction
+system.cpu0.op_class::IprAccess                510933      1.62%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  31511116                       # Class of executed instruction
+system.cpu0.op_class::total                  31482554                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6421                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211361                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74795     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6422                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211358                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105682     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182558                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73428     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31                 105680     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182555                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73428     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148937                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1818811073000     98.77%     98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38572000      0.00%     98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              355311500      0.02%     98.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22333065000      1.21%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1841538021500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1818800243000     98.76%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38808500      0.00%     98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              357216000      0.02%     98.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22351032000      1.21%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1841547299500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694801                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815834                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694805                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815836                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -474,7 +483,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175301     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175298     91.20%     93.41% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
@@ -483,7 +492,7 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # nu
 system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192212                       # number of callpals executed
+system.cpu0.kern.callpal::total                192209                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle               2093                       # number of protection mode switches
@@ -494,429 +503,429 @@ system.cpu0.kern.mode_switch_good::kernel     0.321851                       # f
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      0.080745                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     0.390894                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29730845000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2571229000      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1809235945500     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel       29750547000      1.62%      1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2575384000      0.14%      1.76% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1809221366500     98.24%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements          1393219                       # number of replacements
+system.cpu0.dcache.tags.replacements          1393348                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13266024                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393731                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.518353                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           13255372                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393860                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.509830                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   178.252416                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   164.663502                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   169.081899                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.348149                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.321608                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.330238                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   177.816582                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   164.221248                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   169.959986                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.347298                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.320745                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.331953                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63377040                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63377040                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      3961674                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1077685                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2542197                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7581556                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3105087                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       828848                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1366589                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5300524                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113741                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19662                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51148                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184551                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122328                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21764                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55225                       # number of StoreCondReq hits
+system.cpu0.dcache.tags.tag_accesses         63362265                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63362265                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      3956098                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1080024                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2536463                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7572585                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3101293                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       830391                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1367001                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5298685                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113681                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19703                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51298                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184682                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122268                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21809                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55240                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       199317                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7066761                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1906533                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3908786                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12882080                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7066761                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1906533                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3908786                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12882080                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       706841                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        96965                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       557653                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1361459                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       162721                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        43998                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       642629                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       849348                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9135                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2231                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7695                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19061                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data           11                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       869562                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       140963                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1200282                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2210807                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       869562                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       140963                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1200282                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2210807                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2267399500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8210771504                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  10478171004                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1754611010                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19498280034                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  21252891044                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29510000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    125540000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    155050000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       185002                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       185002                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4022010510                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27709051538                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31731062048                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4022010510                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27709051538                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31731062048                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4668515                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1174650                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3099850                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8943015                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3267808                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       872846                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2009218                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6149872                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       122876                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21893                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58843                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203612                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122328                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21764                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55236                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199328                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      7936323                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2047496                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5109068                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15092887                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      7936323                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2047496                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5109068                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15092887                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151406                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082548                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.179897                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.152237                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049795                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050408                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.319840                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.138108                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.074343                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.101905                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130772                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093614                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000199                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000055                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109567                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068847                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234932                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146480                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109567                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.068847                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234932                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146480                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23383.689991                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14723.800471                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  7696.280978                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39879.335652                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30341.425666                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25022.595031                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13227.252353                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16314.489929                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8134.410577                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16818.363636                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16818.363636                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28532.384455                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23085.451201                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14352.705617                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28532.384455                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23085.451201                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14352.705617                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       977120                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         1794                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            54184                       # number of cycles access was blocked
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+system.cpu0.dcache.overall_accesses::total     15089055                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151575                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082670                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181519                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152881                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049749                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050464                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.320460                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.138402                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.074372                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.101878                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093447                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000181                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000050                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109649                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068944                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.236209                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.146980                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109649                       # miss rate for overall accesses
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+system.cpu0.dcache.overall_miss_rate::total     0.146980                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23304.257593                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  7683.163025                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8117.402952                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        17050                       # average StoreCondReq miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1019885                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         1764                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            60259                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets             18                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.033368                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    99.666667                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.925024                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets           98                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835707                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835707                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       287560                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       287560                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       546849                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       546849                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1691                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1691                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       834409                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       834409                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       834409                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       834409                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        96965                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       270093                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       367058                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43998                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        95780                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       139778                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2231                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6004                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8235                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       140963                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       365873                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       506836                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       140963                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       365873                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       506836                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1102                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1563                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2665                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1382                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2131                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3513                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2484                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3694                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6178                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2114965000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4270329509                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6385294509                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1680467990                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3020406043                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4700874033                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26161500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72039750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     98201250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       168498                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       168498                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3795432990                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7290735552                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11086168542                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3795432990                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7290735552                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11086168542                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    222473500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    331326000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    553799500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    293979000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    446199000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    740178000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    516452500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    777525000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1293977500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082548                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087131                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041044                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050408                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047670                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022729                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.101905                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.102034                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040445                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000199                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068847                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071612                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.033581                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068847                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071612                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.033581                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        15318                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        15318                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       835740                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835740                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       292598                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       292598                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548626                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       548626                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1690                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1690                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       841224                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       841224                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       841224                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       841224                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        97332                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269929                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       367261                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44132                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        96028                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       140160                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2235                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5978                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8213                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           10                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       141464                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       365957                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       507421                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       141464                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       365957                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       507421                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1108                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1559                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2667                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1387                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2128                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3515                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2495                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3687                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6182                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2170918000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4426676000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6597594000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1708808000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3106661815                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4815469815                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     27324000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     74701500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102025500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       160500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       160500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3879726000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7533337815                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11413063815                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3879726000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7533337815                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11413063815                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    226454500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    334463500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    560918000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298425500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    450956500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    749382000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    524880000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    785420000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1310300000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082670                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087102                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041084                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050464                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047736                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022791                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.101878                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.101380                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040315                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000181                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000050                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068944                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071607                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033628                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068944                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071607                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033628                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        16050                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        16050                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           964809                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.919385                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           41279952                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           965320                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            42.762972                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10189587250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   147.730782                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   136.243694                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   226.944909                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.288537                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.266101                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.443252                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997889                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           965393                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.914113                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           41264625                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           965904                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            42.721249                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10188445500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.904249                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   135.394605                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   228.615259                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286922                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.264443                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.446514                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997879                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43227698                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43227698                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     31004099                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7794052                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2481801                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       41279952                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     31004099                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7794052                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2481801                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        41279952                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     31004099                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7794052                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2481801                       # number of overall hits
-system.cpu0.icache.overall_hits::total       41279952                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       507017                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       128848                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       346369                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       982234                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       507017                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       128848                       # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total        982234                       # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total       982234                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1839260250                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4838788318                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6678048568                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1839260250                       # number of demand (read+write) miss cycles
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-system.cpu0.icache.demand_miss_latency::total   6678048568                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1839260250                       # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total   6678048568                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     31511116                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::cpu0.inst     31511116                       # number of overall (read+write) accesses
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-system.cpu0.icache.overall_accesses::total     42262186                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016090                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016263                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122471                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023241                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016090                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016263                       # miss rate for demand accesses
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-system.cpu0.icache.demand_miss_rate::total     0.023241                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016090                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122471                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023241                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14274.651139                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13970.038652                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6798.836701                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14274.651139                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13970.038652                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6798.836701                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14274.651139                       # average overall miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total  6798.836701                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4002                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         43213951                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        43213951                       # Number of data accesses
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+system.cpu0.icache.ReadReq_miss_latency::total   6678558488                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_rate::total     0.023273                       # miss rate for ReadReq accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::total  6792.557989                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::total  6792.557989                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total  6792.557989                       # average overall miss latency
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 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              225                       # number of cycles access was blocked
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.786667                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.738095                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16722                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16722                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16722                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16722                       # number of demand (read+write) MSHR hits
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-system.cpu0.icache.overall_mshr_hits::total        16722                       # number of overall MSHR hits
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-system.cpu0.icache.demand_mshr_misses::total       458495                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::total       458495                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1645092750                       # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::total   5793571146                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_latency::total   5793571146                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016263                       # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010849                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016263                       # mshr miss rate for demand accesses
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-system.cpu0.icache.demand_mshr_miss_rate::total     0.010849                       # mshr miss rate for demand accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090                       # average ReadReq mshr miss latency
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780                       # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_mshr_hits::total        17108                       # number of ReadReq MSHR hits
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+system.cpu0.icache.ReadReq_mshr_misses::total       459347                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       129019                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       330328                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       459347                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       129019                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       330328                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       459347                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1710963500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4315526491                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6026489991                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1710963500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4315526491                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6026489991                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1710963500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4315526491                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6026489991                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010873                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010873                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010873                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1194215                       # DTB read hits
-system.cpu1.dtb.read_misses                      1316                       # DTB read misses
+system.cpu1.dtb.read_hits                     1196955                       # DTB read hits
+system.cpu1.dtb.read_misses                      1325                       # DTB read misses
 system.cpu1.dtb.read_acv                           35                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  141030                       # DTB read accesses
-system.cpu1.dtb.write_hits                     894755                       # DTB write hits
+system.cpu1.dtb.read_accesses                  141268                       # DTB read accesses
+system.cpu1.dtb.write_hits                     896481                       # DTB write hits
 system.cpu1.dtb.write_misses                      169                       # DTB write misses
 system.cpu1.dtb.write_acv                          22                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  57515                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2088970                       # DTB hits
-system.cpu1.dtb.data_misses                      1485                       # DTB misses
+system.cpu1.dtb.write_accesses                  57742                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2093436                       # DTB hits
+system.cpu1.dtb.data_misses                      1494                       # DTB misses
 system.cpu1.dtb.data_acv                           57                       # DTB access violations
-system.cpu1.dtb.data_accesses                  198545                       # DTB accesses
-system.cpu1.itb.fetch_hits                     856400                       # ITB hits
-system.cpu1.itb.fetch_misses                      653                       # ITB misses
-system.cpu1.itb.fetch_acv                          34                       # ITB acv
-system.cpu1.itb.fetch_accesses                 857053                       # ITB accesses
+system.cpu1.dtb.data_accesses                  199010                       # DTB accesses
+system.cpu1.itb.fetch_hits                     858438                       # ITB hits
+system.cpu1.itb.fetch_misses                      659                       # ITB misses
+system.cpu1.itb.fetch_acv                          35                       # ITB acv
+system.cpu1.itb.fetch_accesses                 859097                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -929,64 +938,64 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953255662                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953273349                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7921357                       # Number of instructions committed
-system.cpu1.committedOps                      7921357                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7380748                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 45896                       # Number of float alu accesses
-system.cpu1.num_func_calls                     207012                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1022630                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7380748                       # number of integer instructions
-system.cpu1.num_fp_insts                        45896                       # number of float instructions
-system.cpu1.num_int_register_reads           10351742                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5363285                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24726                       # number of times the floating registers were read
+system.cpu1.committedInsts                    7930565                       # Number of instructions committed
+system.cpu1.committedOps                      7930565                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7389333                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 45920                       # Number of float alu accesses
+system.cpu1.num_func_calls                     207460                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1022605                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7389333                       # number of integer instructions
+system.cpu1.num_fp_insts                        45920                       # number of float instructions
+system.cpu1.num_int_register_reads           10362144                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5369975                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24736                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes              25085                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2096070                       # number of memory refs
-system.cpu1.num_load_insts                    1198996                       # Number of load instructions
-system.cpu1.num_store_insts                    897074                       # Number of store instructions
-system.cpu1.num_idle_cycles              923177922.874727                       # Number of idle cycles
-system.cpu1.num_busy_cycles              30077739.125273                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031553                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968447                       # Percentage of idle cycles
-system.cpu1.Branches                          1296149                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               410448      5.18%      5.18% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  5236817     66.10%     71.28% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8727      0.11%     71.39% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     71.39% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5162      0.07%     71.45% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     71.45% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     71.45% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     71.45% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    810      0.01%     71.46% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.46% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1228055     15.50%     86.96% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 898300     11.34%     98.30% # Class of executed instruction
-system.cpu1.op_class::IprAccess                134580      1.70%    100.00% # Class of executed instruction
+system.cpu1.num_mem_refs                      2100568                       # number of memory refs
+system.cpu1.num_load_insts                    1201762                       # Number of load instructions
+system.cpu1.num_store_insts                    898806                       # Number of store instructions
+system.cpu1.num_idle_cycles              922154358.750069                       # Number of idle cycles
+system.cpu1.num_busy_cycles              31118990.249931                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.032644                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.967356                       # Percentage of idle cycles
+system.cpu1.Branches                          1296677                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               410840      5.18%      5.18% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  5240708     66.07%     71.25% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8731      0.11%     71.36% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     71.36% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5176      0.07%     71.42% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     71.42% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     71.42% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     71.42% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    810      0.01%     71.43% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.43% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1230901     15.52%     86.95% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 900034     11.35%     98.30% # Class of executed instruction
+system.cpu1.op_class::IprAccess                134916      1.70%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7922899                       # Class of executed instruction
+system.cpu1.op_class::total                   7932116                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1004,35 +1013,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups               10412478                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9668294                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           126557                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             8251745                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6275895                       # Number of BTB hits
+system.cpu2.branchPred.lookups               10402334                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          9657881                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           126933                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             8330137                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                6272162                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            76.055368                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 302998                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7851                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            75.294824                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 302639                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7723                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3529660                       # DTB read hits
-system.cpu2.dtb.read_misses                     12347                       # DTB read misses
-system.cpu2.dtb.read_acv                          141                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  225697                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2155841                       # DTB write hits
-system.cpu2.dtb.write_misses                     2820                       # DTB write misses
-system.cpu2.dtb.write_acv                         143                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  84900                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5685501                       # DTB hits
-system.cpu2.dtb.data_misses                     15167                       # DTB misses
-system.cpu2.dtb.data_acv                          284                       # DTB access violations
-system.cpu2.dtb.data_accesses                  310597                       # DTB accesses
-system.cpu2.itb.fetch_hits                     538073                       # ITB hits
-system.cpu2.itb.fetch_misses                     5955                       # ITB misses
-system.cpu2.itb.fetch_acv                         169                       # ITB acv
-system.cpu2.itb.fetch_accesses                 544028                       # ITB accesses
+system.cpu2.dtb.read_hits                     3549115                       # DTB read hits
+system.cpu2.dtb.read_misses                     12776                       # DTB read misses
+system.cpu2.dtb.read_acv                          157                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  225358                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2157791                       # DTB write hits
+system.cpu2.dtb.write_misses                     2831                       # DTB write misses
+system.cpu2.dtb.write_acv                         142                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  84650                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5706906                       # DTB hits
+system.cpu2.dtb.data_misses                     15607                       # DTB misses
+system.cpu2.dtb.data_acv                          299                       # DTB access violations
+system.cpu2.dtb.data_accesses                  310008                       # DTB accesses
+system.cpu2.itb.fetch_hits                     538598                       # ITB hits
+system.cpu2.itb.fetch_misses                     5991                       # ITB misses
+system.cpu2.itb.fetch_acv                         159                       # ITB acv
+system.cpu2.itb.fetch_accesses                 544589                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1045,304 +1054,304 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        30702821                       # number of cpu cycles simulated
+system.cpu2.numCycles                        30759536                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9319148                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      39738878                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   10412478                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6578893                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     19243837                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 412304                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                       656                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                9648                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1927                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       233877                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       108804                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          445                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2828172                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                93139                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          29124256                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.364460                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.368556                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9338114                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      39735788                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   10402334                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           6574801                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     19282744                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 413720                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                       277                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                9678                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1944                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       234903                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       108900                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          473                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2833173                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                93993                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          29183655                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.361577                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.367035                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                20002999     68.68%     68.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  306830      1.05%     69.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  477568      1.64%     71.37% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4658363     15.99%     87.37% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  855343      2.94%     90.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  200502      0.69%     90.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  234860      0.81%     91.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  433547      1.49%     93.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1954244      6.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20063773     68.75%     68.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  307542      1.05%     69.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  477296      1.64%     71.44% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4654234     15.95%     87.39% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  859104      2.94%     90.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  198525      0.68%     91.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  235442      0.81%     91.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  432653      1.48%     93.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1955086      6.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            29124256                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.339138                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.294307                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7666487                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             12991565                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  7744961                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               527663                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                193001                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              177358                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13514                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36364188                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                42851                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                193001                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7942048                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4601261                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6305683                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  7969678                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2112012                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35538074                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                62867                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                396006                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 59218                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1045972                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           23773076                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             44310063                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        44249815                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56335                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             21846032                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1927044                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            532665                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         63556                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3796199                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3529311                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2248768                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           470664                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          333419                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32987424                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             681806                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 32666998                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            16031                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2569271                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1151235                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        487594                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     29124256                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.121642                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.623821                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            29183655                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.338182                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.291820                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7672062                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13049396                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  7739525                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               528158                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                193789                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              177139                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13443                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36353966                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                42512                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                193789                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7950274                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4574250                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6325048                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  7961138                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2178432                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              35523870                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                60190                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                394243                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 57916                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1115509                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           23763436                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             44289897                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        44229633                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56339                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             21842362                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1921074                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            535035                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         63809                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3839801                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3528507                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2250963                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           468940                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          330687                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32977065                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             683079                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 32678030                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            15337                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2566331                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1147551                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        488786                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     29183655                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.119737                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.624192                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17381860     59.68%     59.68% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2746661      9.43%     69.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1371662      4.71%     73.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5386342     18.49%     92.32% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1029310      3.53%     95.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             605779      2.08%     97.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             390861      1.34%     99.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             167562      0.58%     99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              44219      0.15%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17436459     59.75%     59.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2753806      9.44%     69.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1377159      4.72%     73.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5375832     18.42%     92.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1030141      3.53%     95.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             601956      2.06%     97.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             392573      1.35%     99.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             169204      0.58%     99.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              46525      0.16%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       29124256                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       29183655                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  85214     22.02%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     22.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                179569     46.41%     68.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               122132     31.57%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  85386     21.51%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.51% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                184726     46.54%     68.05% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               126802     31.95%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2450      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             26477502     81.05%     81.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21078      0.06%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20355      0.06%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1225      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3659635     11.20%     92.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2180799      6.68%     99.07% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            303954      0.93%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             26465043     80.99%     80.99% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21101      0.06%     81.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20515      0.06%     81.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3679518     11.26%     92.39% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2182790      6.68%     99.07% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            305379      0.93%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              32666998                       # Type of FU issued
-system.cpu2.iq.rate                          1.063974                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     386915                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.011844                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          94607462                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         36124516                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     32054290                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             253736                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            119890                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       117198                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              32915380                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 136083                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          205891                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              32678030                       # Type of FU issued
+system.cpu2.iq.rate                          1.062371                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     396914                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.012146                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          94697637                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         36112111                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     32047154                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             254329                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            120282                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       117366                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              32936079                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 136409                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          206083                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       443704                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1465                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6049                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       180746                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       440040                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1257                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6058                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       180485                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         5094                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       200289                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         5073                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       225988                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                193001                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3976817                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               219021                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           35063617                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            53776                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3529311                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2248768                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            606766                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 12977                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               164349                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6049                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         63932                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       135830                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              199762                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             32464526                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3550760                       # Number of load instructions executed
+system.cpu2.iew.iewSquashCycles                193789                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3993186                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               173385                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           35054322                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            55127                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3528507                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2250963                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            608084                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 13021                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               119091                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6058                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         64339                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       136180                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              200519                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             32475558                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3570784                       # Number of load instructions executed
 system.cpu2.iew.iewExecSquashedInsts           202472                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1394387                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5714159                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7350868                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2163399                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.057379                       # Inst execution rate
-system.cpu2.iew.wb_sent                      32215343                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     32171488                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 18756374                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 22505351                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1394178                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5736169                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 7344406                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2165385                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.055788                       # Inst execution rate
+system.cpu2.iew.wb_sent                      32207740                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     32164520                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 18733989                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 22461298                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.047835                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.833418                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.045676                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.834056                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2693673                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         194212                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           181849                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     28653786                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.128143                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.870801                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2690484                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         194293                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           182480                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     28713100                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.125605                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.869287                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18143596     63.32%     63.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2243135      7.83%     71.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1187950      4.15%     75.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5112990     17.84%     93.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       566123      1.98%     95.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       201198      0.70%     95.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       164794      0.58%     96.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       163684      0.57%     96.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       870316      3.04%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18196306     63.37%     63.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2254505      7.85%     71.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1188955      4.14%     75.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      5110402     17.80%     93.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       563606      1.96%     95.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       199238      0.69%     95.82% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       165515      0.58%     96.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       164290      0.57%     96.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       870283      3.03%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     28653786                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            32325567                       # Number of instructions committed
-system.cpu2.commit.committedOps              32325567                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     28713100                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            32319619                       # Number of instructions committed
+system.cpu2.commit.committedOps              32319619                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5153629                       # Number of memory references committed
-system.cpu2.commit.loads                      3085607                       # Number of loads committed
-system.cpu2.commit.membars                      68228                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7176692                       # Number of branches committed
-system.cpu2.commit.fp_insts                    115672                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 30802580                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              241655                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1228058      3.80%      3.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        25528107     78.97%     82.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20647      0.06%     82.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     82.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20076      0.06%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1225      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     82.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3153835      9.76%     92.66% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2069665      6.40%     99.06% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       303954      0.94%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5158945                       # Number of memory references committed
+system.cpu2.commit.loads                      3088467                       # Number of loads committed
+system.cpu2.commit.membars                      68233                       # Number of memory barriers committed
+system.cpu2.commit.branches                   7171529                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115750                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 30796114                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              241665                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1228262      3.80%      3.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        25515212     78.95%     82.75% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20642      0.06%     82.81% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     82.81% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20078      0.06%     82.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     82.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     82.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     82.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     82.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3156700      9.77%     92.64% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2072118      6.41%     99.06% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       305379      0.94%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         32325567                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               870316                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    62726939                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   70507401                       # The number of ROB writes
-system.cpu2.timesIdled                         178497                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1578565                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1745106872                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   31099959                       # Number of Instructions Simulated
-system.cpu2.committedOps                     31099959                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.987230                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.987230                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.012935                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.012935                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                42640475                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22658201                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    70901                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   71243                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5010785                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                273099                       # number of misc regfile writes
+system.cpu2.commit.op_class_0::total         32319619                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               870283                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                    62775514                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   70489103                       # The number of ROB writes
+system.cpu2.timesIdled                         177769                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1575881                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1745050657                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   31093813                       # Number of Instructions Simulated
+system.cpu2.committedOps                     31093813                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              0.989249                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.989249                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.010867                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.010867                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                42649325                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               22654905                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    71051                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   71293                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                5005090                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                273836                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1358,8 +1367,7 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51362                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9810                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51362                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5192                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1398,7 +1406,7 @@ system.iobus.reqLayer1.occupancy               105000                       # La
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5364000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5370000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             1863000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
@@ -1408,21 +1416,21 @@ system.iobus.reqLayer27.occupancy                7000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           100878274                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy            89820170                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             8843000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             8849000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17495500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17468000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254165                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.254241                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693892917000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254165                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078385                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078385                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1693892852000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.254241                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078390                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078390                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1430,49 +1438,49 @@ system.iocache.tags.tag_accesses               375525                       # Nu
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9444962                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9444962                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   3667270812                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   3667270812                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide      9444962                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total      9444962                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide      9444962                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total      9444962                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide      9418962                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9418962                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   2040792208                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2040792208                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide      9418962                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total      9418962                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide      9418962                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total      9418962                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 54595.156069                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 54595.156069                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 54595.156069                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31008                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54444.867052                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 54444.867052                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 54444.867052                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 4243                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.308037                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1480,237 +1488,243 @@ system.iocache.writebacks::writebacks           41512                       # nu
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17280                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        17280                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        17280                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5749962                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      5749962                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2768710812                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2768710812                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide      5749962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      5749962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide      5749962                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      5749962                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5918962                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      5918962                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1176792208                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1176792208                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide      5918962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      5918962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide      5918962                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      5918962                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82142.314286                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82142.314286                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 160226.320139                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 160226.320139                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82142.314286                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82142.314286                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82142.314286                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82142.314286                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 84556.600000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 84556.600000                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   337569                       # number of replacements
-system.l2c.tags.tagsinuse                65419.566617                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2487366                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402731                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.176247                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337481                       # number of replacements
+system.l2c.tags.tagsinuse                65419.198683                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4010491                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402643                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.960414                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54619.974232                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2262.532885                       # Average occupied blocks per requestor
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1719,209 +1733,222 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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-system.l2c.overall_mshr_miss_rate::cpu2.data     0.110945                       # mshr miss rate for overall accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        18001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        18001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 67183.160187                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 67183.160187                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187881.578947                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197980.806142                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193804.690432                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 199719.971056                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196384.795870                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 197696.840307                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 194467.995169                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 197060.097455                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 196017.886047                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_mshr_misses::cpu1.data        17974                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        24645                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         42619                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2299                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4804                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         7103                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data        15769                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        16968                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        32737                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2299                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        33743                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4804                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        41613                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            82459                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2299                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        33743                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4804                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        41613                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           82459                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         1108                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         1559                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         2667                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         1387                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2128                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total         3515                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2495                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3687                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total         6182                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       607000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       607000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        41500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        41500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1188211000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1946917000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3135128000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    163468500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    346786500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    510255000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1011322500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1095840500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   2107163000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    163468500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2199533500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    346786500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3042757500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5752546000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    163468500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2199533500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    346786500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3042757500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5752546000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    212604500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    314976000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    527580500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    282475000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    426484500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    708959500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    495079500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    741460500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1236540000                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.709677                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.511628                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407287                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.255964                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.140765                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007353                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.158376                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.061563                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.030004                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.234819                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.111891                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034942                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.234819                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.111891                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034942                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        20750                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        20750                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69762.500152                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69762.500152                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              295002                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294996                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
+system.membus.trans_dist::ReadResp             294958                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9810                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9810                       # Transaction distribution
-system.membus.trans_dist::Writeback            116904                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              145                       # Transaction distribution
+system.membus.trans_dist::Writeback            116948                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262295                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              165                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             147                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115657                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115657                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             167                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115610                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115610                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        287819                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       882256                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       916176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124907                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124907                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1041083                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1144349                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           10                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1178267                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125023                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       125023                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1303290                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30632256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30677824                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5323648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5323648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36001472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30629632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30675200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2664320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33339520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              157                       # Total snoops (count)
-system.membus.snoop_fanout::samples            579090                       # Request fanout histogram
+system.membus.snoop_fanout::samples            841413                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  579090    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  841413    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              579090                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11072500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              841413                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11052000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           412860298                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           394258327                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy                8000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy                7000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          438835201                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          441332932                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           17657500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           29902743                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2063715                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2063694                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2064402                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq              9810                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp             9810                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           835707                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        17293                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              31                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             42                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302749                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302749                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1930984                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3657230                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5588214                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61790208                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142733184                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              204523392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           41934                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3253691                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012828                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.112532                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback           883212                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1574760                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              43                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             53                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302767                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302767                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        966109                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1091169                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        17280                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2897413                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4214892                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7112305                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61827200                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142743552                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              204570752                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          141567                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4877075                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.028983                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.167759                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3211953     98.72%     98.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  41738      1.28%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                4735723     97.10%     97.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 141352      2.90%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3253691                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1080719000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4877075                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1372572500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy            82500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         689338845                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         689392754                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         790311532                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         777864461                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index c18c16475..b25b92aa6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,160 +1,164 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.846034                       # Number of seconds simulated
-sim_ticks                                2846033690500                       # Number of ticks simulated
-final_tick                               2846033690500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.846047                       # Number of seconds simulated
+sim_ticks                                2846047385500                       # Number of ticks simulated
+final_tick                               2846047385500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 166502                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201645                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3701777010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 652712                       # Number of bytes of host memory used
-host_seconds                                   768.83                       # Real time elapsed on the host
-sim_insts                                   128011279                       # Number of instructions simulated
-sim_ops                                     155030352                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 159625                       # Simulator instruction rate (inst/s)
+host_op_rate                                   193311                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3563510303                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654020                       # Number of bytes of host memory used
+host_seconds                                   798.66                       # Real time elapsed on the host
+sim_insts                                   127487011                       # Number of instructions simulated
+sim_ops                                     154390534                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         8384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         7424                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1665600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1328952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8468032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           219456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           635604                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       399104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1468992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1221616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8255360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         2560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           381888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           706136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       588160                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12726924                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1665600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       219456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1885056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8843968                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12633224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1468992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       381888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1850880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8928128                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8861532                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          131                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8945692                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26025                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       132313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3429                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9952                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6236                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22953                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             19610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       128990                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           40                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5967                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11055                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         9190                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                199403                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138187                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                197938                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          139502                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142578                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               143893                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2609                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              585236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              466949                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2975380                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               77109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              223330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       140232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              516152                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              429232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2900640                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              134182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              248111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       206659                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4471811                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         585236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          77109                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             662345                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3107471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4438866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         516152                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         134182                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             650334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3137027                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3113643                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3107471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3143199                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3137027                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2609                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             585236                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             473106                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2975380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              77109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             223344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       140232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             516152                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             435390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2900640                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             134182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             248125                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       206659                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7585453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        199403                       # Number of read requests accepted
-system.physmem.writeReqs                       178802                       # Number of write requests accepted
-system.physmem.readBursts                      199403                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     178802                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12754816                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9923392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12726924                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               11179868                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23728                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          14293                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12446                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12462                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12648                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12635                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15144                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12384                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13114                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13234                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12297                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12473                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12152                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11219                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11569                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12199                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11629                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11689                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9980                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10101                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10187                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9953                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9212                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9585                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10195                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10328                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9559                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9737                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9778                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9524                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9387                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9312                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9249                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8966                       # Per bank write bursts
+system.physmem.bw_total::total                7582065                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197938                       # Number of read requests accepted
+system.physmem.writeReqs                       143893                       # Number of write requests accepted
+system.physmem.readBursts                      197938                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     143893                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12658432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8958080                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12633224                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8945692                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          51249                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12124                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12298                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12956                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12344                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15465                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12573                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12691                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13082                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12243                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12357                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11723                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11147                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12049                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11871                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11344                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11521                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8574                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8801                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9504                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8801                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8786                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8838                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9085                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9267                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8941                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8908                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8524                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8283                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8972                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8287                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8306                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8093                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          44                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2846033184500                       # Total gap between requests
+system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2846046899000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  198820                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  197356                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 174411                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     98514                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     48367                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13227                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9811                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6331                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5269                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4641                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3767                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 139502                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::1                     48975                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::9                       751                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::11                      262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      280                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -184,195 +188,191 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1516                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                     1870                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53                      226                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::55                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      183                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       96                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       62                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        91619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      247.526648                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     138.939609                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     308.892335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          48258     52.67%     52.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17913     19.55%     72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6311      6.89%     79.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3675      4.01%     83.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2817      3.07%     86.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1472      1.61%     87.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1018      1.11%     88.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1004      1.10%     90.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9151      9.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          91619                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6524                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.547670                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      556.789065                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6523     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6524                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6524                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.766554                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.625948                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       41.024429                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            6179     94.71%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              85      1.30%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              25      0.38%     96.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              12      0.18%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              31      0.48%     97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             34      0.52%     97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            24      0.37%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            11      0.17%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            15      0.23%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             5      0.08%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            12      0.18%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            17      0.26%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            13      0.20%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             5      0.08%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             4      0.06%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.05%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             4      0.06%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.03%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.06%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.05%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             3      0.05%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            16      0.25%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.03%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             4      0.06%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::880-895             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6524                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5653495532                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9390258032                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    996470000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28367.62                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::63                       93                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        90544                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      238.739707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.462322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     300.134416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          48559     53.63%     53.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17642     19.48%     73.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6276      6.93%     80.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3581      3.95%     84.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2857      3.16%     87.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1437      1.59%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          927      1.02%     89.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1107      1.22%     90.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8158      9.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          90544                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6994                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.279525                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      555.958801                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6993     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6994                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6994                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.012868                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.560049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.293161                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5872     83.96%     83.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             361      5.16%     89.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             205      2.93%     92.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              59      0.84%     92.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              60      0.86%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             157      2.24%     96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              22      0.31%     96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               8      0.11%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              14      0.20%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.10%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.09%     96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.11%     96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             162      2.32%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.04%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.10%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               9      0.13%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.04%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            12      0.17%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6994                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5635724944                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9344249944                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    988940000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28493.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47117.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.49                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.47                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47243.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.45                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.06                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165654                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97073                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  62.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7525107.24                       # Average gap between requests
-system.physmem.pageHitRate                      74.14                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  361662840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  197335875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 811722600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                515425680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185888851200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83071861560                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1634748153750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1905595013505                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.562437                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2719423686494                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95035200000                       # Time in different power states
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.58                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     164502                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82711                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  59.08                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8325888.81                       # Average gap between requests
+system.physmem.pageHitRate                      73.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  356257440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  194386500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 807557400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                464330880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185889868320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83150566875                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634688457500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1905551424915                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.543458                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719326804644                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95035720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31571473506                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31683407856                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  330976800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  180592500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 742762800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                489317760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185888851200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82401250860                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1635336408750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1905370160670                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.483431                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2720410023695                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95035200000                       # Time in different power states
+system.physmem_1.actEnergy                  328255200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179107500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 735181200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                442674720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185889868320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82066427730                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635639456750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1905280971420                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.448430                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2720915660225                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95035720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30588353805                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30095909775                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               20699653                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13612367                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1051860                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            13249801                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                9339959                       # Number of BTB hits
+system.cpu0.branchPred.lookups               19568417                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         12741959                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           982246                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            12413476                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8819135                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            70.491315                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3411685                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            215338                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.044847                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3284365                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            198035                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -403,58 +403,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    70748                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               70748                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47364                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23384                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        70748                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          70748    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        70748                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6854                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean  9215.640648                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  8072.361115                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6078.265155                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6652     97.05%     97.05% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          190      2.77%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151            4      0.06%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            6      0.09%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6854                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    328505000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      328505000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    328505000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5278     77.01%     77.01% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1576     22.99%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6854                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        70748                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    67683                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               67683                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        45041                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22642                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        67683                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          67683    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        67683                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6748                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9555.209008                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5781.304513                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6579     97.50%     97.50% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          156      2.31%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687            2      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6748                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    327753000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      327753000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    327753000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5177     76.72%     76.72% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1571     23.28%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6748                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67683                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        70748                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6854                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67683                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6748                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6854                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        77602                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6748                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        74431                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    17365788                       # DTB read hits
-system.cpu0.dtb.read_misses                     64419                       # DTB read misses
-system.cpu0.dtb.write_hits                   14563883                       # DTB write hits
-system.cpu0.dtb.write_misses                     6329                       # DTB write misses
+system.cpu0.dtb.read_hits                    16473000                       # DTB read hits
+system.cpu0.dtb.read_misses                     62137                       # DTB read misses
+system.cpu0.dtb.write_hits                   13870452                       # DTB write hits
+system.cpu0.dtb.write_misses                     5546                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3519                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1310                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1951                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3508                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1130                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1591                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      572                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                17430207                       # DTB read accesses
-system.cpu0.dtb.write_accesses               14570212                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      561                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                16535137                       # DTB read accesses
+system.cpu0.dtb.write_accesses               13875998                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         31929671                       # DTB hits
-system.cpu0.dtb.misses                          70748                       # DTB misses
-system.cpu0.dtb.accesses                     32000419                       # DTB accesses
+system.cpu0.dtb.hits                         30343452                       # DTB hits
+system.cpu0.dtb.misses                          67683                       # DTB misses
+system.cpu0.dtb.accesses                     30411135                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -484,39 +484,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3844                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3844                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walks                     3854                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3854                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3537                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3844                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3844    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3844                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2412                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean  9287.312604                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  8105.691907                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5199.777734                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          996     41.29%     41.29% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1373     56.92%     98.22% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575            5      0.21%     98.42% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2412                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    328041000                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      328041000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    328041000                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2112     87.56%     87.56% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          300     12.44%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2412                       # Table walker page sizes translated
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3547                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3854                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3854    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3854                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2418                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9918.433232                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7783.469031                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767         2416     99.92%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2418                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    327059500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      327059500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    327059500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2118     87.59%     87.59% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          300     12.41%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2418                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3844                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3844                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3854                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3854                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2412                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2412                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6256                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    38673096                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3844                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2418                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2418                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6272                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    36667532                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3854                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -525,131 +522,131 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2215                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2221                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7305                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7326                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                38676940                       # ITB inst accesses
-system.cpu0.itb.hits                         38673096                       # DTB hits
-system.cpu0.itb.misses                           3844                       # DTB misses
-system.cpu0.itb.accesses                     38676940                       # DTB accesses
-system.cpu0.numCycles                       164345884                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                36671386                       # ITB inst accesses
+system.cpu0.itb.hits                         36667532                       # DTB hits
+system.cpu0.itb.misses                           3854                       # DTB misses
+system.cpu0.itb.accesses                     36671386                       # DTB accesses
+system.cpu0.numCycles                       154642199                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   79729346                       # Number of instructions committed
-system.cpu0.committedOps                     95953153                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      5189304                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1865                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5527748141                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.061297                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.485131                       # IPC: instructions per cycle
+system.cpu0.committedInsts                   75578579                       # Number of instructions committed
+system.cpu0.committedOps                     90977347                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      4937651                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     2060                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5537489017                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.046111                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.488732                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1866                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      127709647                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       36636237                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           716917                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          500.984031                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           30425669                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           717429                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            42.409310                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        346166500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.984031                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978484                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.978484                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    2062                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      120829876                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       33812323                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           679563                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          486.133146                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28909958                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           680075                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            42.509956                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        345411000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   486.133146                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949479                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.949479                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63847334                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63847334                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15827695                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15827695                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     13439418                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      13439418                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       321505                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       321505                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365521                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       365521                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361496                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       361496                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     29267113                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        29267113                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     29588618                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       29588618                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       465920                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       465920                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       577900                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       577900                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       136723                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       136723                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21141                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21141                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20265                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20265                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1043820                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1043820                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1180543                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1180543                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6144584831                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6144584831                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9172351028                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   9172351028                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    319190979                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    319190979                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    453656289                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    453656289                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       133500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       133500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  15316935859                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  15316935859                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  15316935859                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  15316935859                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     16293615                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     16293615                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     14017318                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     14017318                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       458228                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       458228                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386662                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       386662                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381761                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381761                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     30310933                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     30310933                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     30769161                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     30769161                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028595                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028595                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041228                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.041228                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.298373                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.298373                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054676                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054676                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053083                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053083                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034437                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.034437                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038368                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.038368                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13188.068404                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13188.068404                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15871.865423                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15871.865423                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15098.196821                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15098.196821                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22386.197335                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22386.197335                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         60679422                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        60679422                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     14995018                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       14995018                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     12788335                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      12788335                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306891                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       306891                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356622                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       356622                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352102                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       352102                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27783353                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27783353                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     28090244                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       28090244                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       441719                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       441719                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       557349                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       557349                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131939                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       131939                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21205                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21205                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21309                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        21309                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       999068                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        999068                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1131007                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1131007                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5838844500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5838844500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8827018500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8827018500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    323291000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    323291000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    480994000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    480994000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       412000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       412000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  14665863000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  14665863000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  14665863000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  14665863000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     15436737                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     15436737                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13345684                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13345684                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438830                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       438830                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377827                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       377827                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373411                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       373411                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     28782421                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     28782421                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     29221251                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     29221251                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028615                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.028615                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041762                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.041762                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300661                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300661                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056124                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056124                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.057066                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.057066                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034711                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.034711                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038705                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.038705                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13218.459020                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13218.459020                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15837.506661                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15837.506661                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15245.979722                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15245.979722                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22572.340326                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22572.340326                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14673.924488                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14673.924488                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12974.483656                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12974.483656                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -658,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       515635                       # number of writebacks
-system.cpu0.dcache.writebacks::total           515635                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        72452                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        72452                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       253659                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       253659                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14673                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14673                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       326111                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       326111                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       326111                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       326111                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       393468                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       393468                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324241                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       324241                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       103543                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       103543                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6468                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6468                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20265                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20265                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       717709                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       717709                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       821252                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       821252                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20388                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19084                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39472                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4430984378                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4430984378                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4926577100                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4926577100                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1621170703                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1621170703                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96485758                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96485758                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    422555211                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    422555211                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       127500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       127500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9357561478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9357561478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10978732181                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10978732181                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4278812500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4278812500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3259105000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3259105000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7537917500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7537917500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024149                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024149                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023131                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023131                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225964                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225964                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016728                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016728                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053083                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053083                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023678                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023678                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026691                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026691                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11261.358936                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11261.358936                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15194.183031                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15194.183031                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15656.980221                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15656.980221                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14917.402288                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14917.402288                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20851.478460                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20851.478460                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       493293                       # number of writebacks
+system.cpu0.dcache.writebacks::total           493293                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69842                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        69842                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244235                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       244235                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15018                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15018                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       314077                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       314077                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       314077                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       314077                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371877                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       371877                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       313114                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       313114                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99356                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        99356                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6187                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6187                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21309                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        21309                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       684991                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       684991                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       784347                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       784347                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18002                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18002                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16758                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16758                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34760                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34760                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4380232500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4380232500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4918203500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4918203500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1623471000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1623471000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94288500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94288500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459695000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459695000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       402000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       402000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9298436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9298436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10921907000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10921907000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3751545500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3751545500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2725656000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725656000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6477201500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6477201500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024090                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024090                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023462                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023462                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226411                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226411                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016375                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016375                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.057066                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.057066                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023799                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023799                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026842                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026842                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13038.099673                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13038.099673                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13368.286690                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13368.286690                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209869.163233                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209869.163233                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170776.828757                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170776.828757                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190968.724666                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190968.724666                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1965366                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.785087                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           36699580                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1965878                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            18.668290                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6403533250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785087                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999580                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999580                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1878063                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.785549                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           34781277                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1878575                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            18.514713                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6156628000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785549                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999581                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999581                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         79296841                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        79296841                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     36699580                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       36699580                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     36699580                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        36699580                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     36699580                       # number of overall hits
-system.cpu0.icache.overall_hits::total       36699580                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1965894                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1965894                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1965894                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1965894                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1965894                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1965894                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18549717200                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  18549717200                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  18549717200                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  18549717200                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  18549717200                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  18549717200                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     38665474                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     38665474                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     38665474                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     38665474                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     38665474                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     38665474                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050844                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050844                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050844                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050844                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050844                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050844                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9435.766730                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9435.766730                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9435.766730                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9435.766730                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9435.766730                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9435.766730                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         75198332                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        75198332                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     34781277                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       34781277                       # number of ReadReq hits
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+system.cpu0.icache.demand_hits::total        34781277                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     34781277                       # number of overall hits
+system.cpu0.icache.overall_hits::total       34781277                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1878593                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1878593                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1878593                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu0.inst      1878593                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1878593                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17494191500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17494191500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  17494191500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17494191500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  17494191500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17494191500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     36659870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     36659870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     36659870                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     36659870                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     36659870                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     36659870                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051244                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.051244                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051244                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.051244                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051244                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.051244                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9312.390443                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9312.390443                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9312.390443                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9312.390443                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9312.390443                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9312.390443                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -809,426 +806,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1965894                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1965894                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1965894                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1965894                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1965894                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1965894                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3367                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3367                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16574456804                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16574456804                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16574456804                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16574456804                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16574456804                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16574456804                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    310652000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    310652000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050844                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.050844                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.050844                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8431.002284                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8431.002284                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8431.002284                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1878593                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1878593                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1878593                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1878593                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1878593                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1878593                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3426                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3426                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16554895500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16554895500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16554895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16554895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16554895500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16554895500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    314279000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    314279000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051244                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.051244                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.051244                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8812.390709                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8812.390709                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8812.390709                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1838784                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1838936                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          132                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1765882                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1765970                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           77                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       233824                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          299625                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16147.057230                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2915503                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          315876                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            9.229897                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       224118                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          286262                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16059.277635                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           4797112                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          302498                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           15.858326                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6737.365934                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    57.298987                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.096459                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5766.699762                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1949.490017                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1636.106070                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.411216                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003497                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.351971                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.118987                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.099860                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.985538                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1040                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15197                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          337                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          404                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          285                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks  8723.236364                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    43.341002                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.066911                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4602.822845                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1559.466000                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1130.344513                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.532424                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002645                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.280934                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.095182                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068991                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.980181                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1044                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15177                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          332                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          429                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          270                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4113                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7946                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2792                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.063477                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927551                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        55342545                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       55342545                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        81587                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3892                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1894938                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       403004                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       2383421                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       515632                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       515632                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28611                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28611                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1830                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1830                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       223241                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       223241                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        81587                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3892                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1894938                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       626245                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2606662                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        81587                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3892                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1894938                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       626245                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2606662                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          835                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          121                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        70956                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data       100469                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       172381                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26947                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26947                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18435                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18435                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        45449                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        45449                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          835                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          121                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        70956                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       145918                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       217830                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          835                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          121                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        70956                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       145918                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       217830                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     28533998                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2724498                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   3265841724                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   3007886164                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   6304986384                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    501041294                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    501041294                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    372688311                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    372688311                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       123500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       123500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2240726575                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2240726575                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     28533998                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2724498                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3265841724                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5248612739                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   8545712959                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     28533998                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2724498                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3265841724                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5248612739                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   8545712959                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        82422                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4013                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1965894                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       503473                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      2555802                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       515632                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       515632                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55558                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55558                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20265                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20265                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268690                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       268690                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        82422                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4013                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1965894                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       772163                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2824492                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        82422                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4013                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1965894                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       772163                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2824492                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.036094                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.199552                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.067447                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.485025                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.485025                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.909697                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.909697                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169150                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169150                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.036094                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.188973                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.077122                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.036094                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.188973                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.077122                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46026.294098                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29938.450308                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36575.877759                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18593.583479                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18593.583479                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20216.344508                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20216.344508                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49301.999494                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49301.999494                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46026.294098                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35969.604429                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 39231.111229                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46026.294098                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35969.604429                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 39231.111229                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           33                       # number of cycles access was blocked
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4328                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7768                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2750                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.063721                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000916                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.926331                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        85339399                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       85339399                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        80048                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4433                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         84481                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       493290                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       493290                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28251                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28251                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1773                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1773                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       213027                       # number of ReadExReq hits
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+system.cpu0.l2cache.ReadCleanReq_hits::total      1814336                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376020                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        80048                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::total       2487864                       # number of overall hits
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+system.cpu0.l2cache.ReadReq_misses::total          837                       # number of ReadReq misses
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+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19535                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
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+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43989                       # number of ReadExReq misses
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+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        64257                       # number of ReadCleanReq misses
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+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101397                       # number of ReadSharedReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          723                       # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          723                       # number of overall misses
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+system.cpu0.l2cache.overall_misses::total       210480                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     24794500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2781500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     27576000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    513504000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    513504000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    395434500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    395434500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       385999                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       385999                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2149567499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2149567499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2872366000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2872366000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2916301996                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2916301996                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     24794500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2781500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2872366000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   5065869495                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   7965811495                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     24794500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2781500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2872366000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   5065869495                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   7965811495                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        80771                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_accesses::total        85318                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       493290                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       493290                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56102                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56102                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21308                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        21308                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257016                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       257016                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1878593                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1878593                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477417                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       477417                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        80771                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        80771                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.data       734433                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2698344                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.009810                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.496435                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.496435                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.916792                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.916792                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171153                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171153                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034205                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034205                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.212387                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.212387                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034205                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197957                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.078003                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034205                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197957                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.078003                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32946.236559                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18437.542638                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18437.542638                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20242.359867                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20242.359867                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       385999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       385999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48866.023301                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48866.023301                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44701.215432                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44701.215432                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28761.225638                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28761.225638                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44701.215432                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34844.273142                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 37845.930706                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44701.215432                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34844.273142                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 37845.930706                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           68                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           33                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       200378                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          200378                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           74                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          391                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          465                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3005                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         3005                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           74                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3396                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         3470                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           74                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3396                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         3470                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          835                       # number of ReadReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        70882                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       100078                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total       171916                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245909                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       245909                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26947                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26947                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18435                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18435                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42444                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        42444                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          835                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          121                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70882                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142522                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       214360                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          835                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          121                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70882                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142522                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245909                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       460269                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23755                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19084                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42839                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2794111276                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2333241113                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   5152380389                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14425244211                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14425244211                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    543842959                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    543842959                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    270479823                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    270479823                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data        97500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        97500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1625124729                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1625124729                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2794111276                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3958365842                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6777505118                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2794111276                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3958365842                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14425244211                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  21202749329                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4115441500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4397586000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3115690500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3115690500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7231132000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7513276500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.198775                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.067265                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.writebacks::writebacks       196466                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          196466                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2877                       # number of ReadExReq MSHR hits
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+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           67                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           67                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          395                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          395                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           67                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3272                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          723                       # number of ReadReq MSHR misses
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+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9399                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         9399                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       235023                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       235023                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27851                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27851                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19535                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19535                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        64190                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101002                       # number of ReadSharedReq MSHR misses
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+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          723                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        18002                       # number of ReadReq MSHR uncacheable
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16758                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
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+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of ReadReq MSHR miss cycles
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14138051507                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14138051507                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    556929500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    556929500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298503500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298503500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       325999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       325999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1579585500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1579585500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2485678500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2485678500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2287922496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2287922496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2097500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2485678500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3867507996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   6375740496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2097500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2485678500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3867507996                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14138051507                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  20513792003                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3607450000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3894320500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2599707500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2599707500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6207157500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6494028000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009810                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.485025                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.485025                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.909697                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.909697                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.157966                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.157966                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.184575                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075893                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.184575                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.496435                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.496435                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.916792                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.916792                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159959                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159959                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034169                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.211559                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.211559                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193502                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076766                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193502                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162956                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23314.226034                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29970.336612                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58660.903875                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20181.948232                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20181.948232                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14672.081530                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14672.081530                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38288.679884                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.679884                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27773.718037                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31617.396520                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27773.718037                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46065.994731                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201856.067294                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185122.542623                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163261.920981                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163261.920981                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183196.493717                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175384.030906                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163865                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       325999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       325999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       2719039                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2643816                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31019                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19084                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       515632                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       304029                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        89544                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42988                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       112734                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       297842                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       284446                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3938521                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2392407                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11394                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       176554                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6518876                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    126032640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86683880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        16052                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       329688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         213062260                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     679431                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4036359                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.164506                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.370735                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        136409                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2524037                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        16758                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       866064                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2177189                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       293784                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        92828                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43742                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114509                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       285377                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       271332                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1878593                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603707                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5608538                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2465365                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11948                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       171096                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          8256947                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120449152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82718835                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        18188                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       323084                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         203509259                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1215113                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      6486372                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.185022                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.388316                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           3372352     83.55%     83.55% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2            664007     16.45%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           5286248     81.50%     81.50% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1200124     18.50%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4036359                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2262112239                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       6486372                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3193659992                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115872000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113350499                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2959359198                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2823287977                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1234268849                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1167322846                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7386992                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7403495                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     94142746                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     90327994                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               19410315                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          6222605                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           754773                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            10046576                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                7244167                       # Number of BTB hits
+system.cpu1.branchPred.lookups               20515510                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          7101066                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           968769                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            10637682                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                7757881                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.105830                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                8699318                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            540404                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.928303                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                8827818                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            689615                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1258,60 +1292,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    26225                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               26225                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19144                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7081                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        26225                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          26225    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        26225                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2726                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean  9368.766324                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  8408.351420                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5475.622761                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         1046     38.37%     38.37% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1544     56.64%     95.01% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575           68      2.49%     97.51% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           59      2.16%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959            2      0.07%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            5      0.18%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                    30617                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               30617                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22895                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7722                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        30617                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          30617    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        30617                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2694                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9833.978032                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6170.794386                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191          858     31.85%     31.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1697     62.99%     94.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575           63      2.34%     97.18% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           63      2.34%     99.52% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151            7      0.26%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.04%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303            4      0.15%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2726                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1584726764                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1584726764    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1584726764                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         2009     73.70%     73.70% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          717     26.30%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2726                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        26225                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         2694                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1565807264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1565807264    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1565807264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         2001     74.28%     74.28% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          693     25.72%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2694                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30617                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        26225                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2726                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30617                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2694                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2726                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        28951                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2694                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        33311                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    11340769                       # DTB read hits
-system.cpu1.dtb.read_misses                     24844                       # DTB read misses
-system.cpu1.dtb.write_hits                    7074140                       # DTB write hits
-system.cpu1.dtb.write_misses                     1381                       # DTB write misses
+system.cpu1.dtb.read_hits                    12131046                       # DTB read hits
+system.cpu1.dtb.read_misses                     27925                       # DTB read misses
+system.cpu1.dtb.write_hits                    7724726                       # DTB write hits
+system.cpu1.dtb.write_misses                     2692                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
 system.cpu1.dtb.flush_entries                    2067                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      202                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   452                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.align_faults                      318                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   531                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      283                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                11365613                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7075521                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      287                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12158971                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7727418                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         18414909                       # DTB hits
-system.cpu1.dtb.misses                          26225                       # DTB misses
-system.cpu1.dtb.accesses                     18441134                       # DTB accesses
+system.cpu1.dtb.hits                         19855772                       # DTB hits
+system.cpu1.dtb.misses                          30617                       # DTB misses
+system.cpu1.dtb.accesses                     19886389                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1341,42 +1375,39 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     2259                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2259                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2078                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2259                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2259    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2259                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1118                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean  9560.375671                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  8643.967571                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  4716.413998                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095          181     16.19%     16.19% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          171     15.30%     31.48% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          489     43.74%     75.22% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          245     21.91%     97.14% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     97.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      1.34%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           14      1.25%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1118                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1584152264                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1584152264    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1584152264                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          950     84.97%     84.97% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          168     15.03%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1118                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     2297                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2297                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2115                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2297    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1122                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5206.907244                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          274     24.42%     24.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383          814     72.55%     96.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575            4      0.36%     97.33% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           27      2.41%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            2      0.18%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1122                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1565238764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1565238764    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1565238764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          953     84.94%     84.94% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          169     15.06%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1122                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2259                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2259                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2297                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2297                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1118                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1118                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3377                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    39752348                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2259                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1122                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1122                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         3419                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    41950603                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2297                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1385,130 +1416,130 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1156                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1160                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1892                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1848                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                39754607                       # ITB inst accesses
-system.cpu1.itb.hits                         39752348                       # DTB hits
-system.cpu1.itb.misses                           2259                       # DTB misses
-system.cpu1.itb.accesses                     39754607                       # DTB accesses
-system.cpu1.numCycles                       114648497                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                41952900                       # ITB inst accesses
+system.cpu1.itb.hits                         41950603                       # DTB hits
+system.cpu1.itb.misses                           2297                       # DTB misses
+system.cpu1.itb.accesses                     41952900                       # DTB accesses
+system.cpu1.numCycles                       125141481                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48281933                       # Number of instructions committed
-system.cpu1.committedOps                     59077199                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      5147990                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2790                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5576811814                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.374563                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.421130                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   51908432                       # Number of instructions committed
+system.cpu1.committedOps                     63413187                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      5363692                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2715                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5566331294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.410812                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.414798                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2790                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       97744251                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       16904246                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           195096                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          474.102569                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           17976294                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           195460                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            91.969170                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      90457158500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.102569                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.925982                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.925982                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           50                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         36856215                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        36856215                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     10952474                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       10952474                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      6779584                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       6779584                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50047                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        50047                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80034                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        80034                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71497                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        71497                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     17732058                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        17732058                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     17782105                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       17782105                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       158503                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       158503                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       144597                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       144597                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30804                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30804                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16970                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16970                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23713                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23713                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       303100                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        303100                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       333904                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       333904                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2370328398                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2370328398                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3872727461                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3872727461                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    316464239                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    316464239                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    558424163                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    558424163                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       271500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       271500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6243055859                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6243055859                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6243055859                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6243055859                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11110977                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11110977                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      6924181                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      6924181                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80851                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        80851                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        97004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95210                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        95210                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     18035158                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     18035158                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     18116009                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     18116009                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.014265                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.014265                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020883                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.020883                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380997                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380997                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174941                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174941                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249060                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249060                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.016806                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.016806                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.018431                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.018431                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14954.470250                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14954.470250                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26782.903248                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26782.903248                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18648.452504                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18648.452504                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23549.283642                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23549.283642                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2717                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      105428618                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       19712863                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           231919                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          484.812111                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           19337078                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           232252                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            83.259038                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      90437090000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   484.812111                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.946899                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.946899                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          333                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          279                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           54                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.650391                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         39720944                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39720944                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     11670097                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       11670097                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7386354                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7386354                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66295                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        66295                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88787                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        88787                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80732                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        80732                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19056451                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19056451                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19122746                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19122746                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       184750                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       184750                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       167503                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       167503                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35001                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        35001                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17741                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17741                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23478                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23478                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       352253                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        352253                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       387254                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       387254                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2719987000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2719987000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4150031500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4150031500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    326839500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    326839500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548823500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    548823500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       416500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       416500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6870018500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6870018500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6870018500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6870018500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11854847                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11854847                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      7553857                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      7553857                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101296                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       101296                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106528                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       106528                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       104210                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       104210                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     19408704                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     19408704                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     19510000                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     19510000                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015584                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.015584                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022174                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.022174                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.345532                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.345532                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166538                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166538                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225295                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225295                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018149                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.018149                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019849                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.019849                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20597.346945                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20597.346945                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18697.158042                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18697.158042                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1517,148 +1548,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       119832                       # number of writebacks
-system.cpu1.dcache.writebacks::total           119832                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16048                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        16048                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52216                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        52216                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12045                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12045                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        68264                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        68264                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        68264                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        68264                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       142455                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       142455                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92381                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        92381                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29949                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        29949                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23713                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23713                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       234836                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       234836                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       264785                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       264785                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14604                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14604                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11935                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26539                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26539                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1925101376                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1925101376                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2304194019                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2304194019                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    483540014                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    483540014                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     80690501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     80690501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521529337                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521529337                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       262500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       262500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4229295395                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4229295395                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4712835409                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4712835409                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2321932001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2321932001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1843920001                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1843920001                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4165852002                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4165852002                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.012821                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.012821                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013342                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013342                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.370422                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.370422                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050771                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050771                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249060                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249060                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013021                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.013021                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014616                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.014616                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13513.750841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13513.750841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24942.293534                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24942.293534                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16145.447728                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16145.447728                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.858071                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.858071                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21993.393371                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21993.393371                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       138789                       # number of writebacks
+system.cpu1.dcache.writebacks::total           138789                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18309                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        18309                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62144                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        62144                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12262                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12262                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        80453                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        80453                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        80453                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        80453                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166441                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       166441                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105359                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       105359                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33489                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        33489                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5479                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5479                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23478                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23478                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       271800                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       271800                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       305289                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       305289                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17142                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17142                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14413                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14413                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31555                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31555                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2292018500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2292018500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2517101000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2517101000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    540422500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    540422500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93861500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93861500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    525354500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    525354500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       407500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       407500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4809119500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4809119500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5349542000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5349542000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2935336500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2935336500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2447202500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2447202500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5382539000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5382539000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014040                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014040                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013948                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013948                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.330605                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.330605                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051432                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051432                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225295                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225295                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014004                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.014004                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015648                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.015648                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18009.570062                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18009.570062                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17798.725037                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17798.725037                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158992.878732                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158992.878732                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154496.858065                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154496.858065                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156970.948491                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156970.948491                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           948604                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.330921                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           38801180                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           949116                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            40.881389                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72079277000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.330921                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975256                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975256                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          1046573                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.334165                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           40901496                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          1047085                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.062250                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      72079197500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.334165                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975262                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975262                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          467                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           45                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         80449708                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        80449708                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     38801180                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       38801180                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     38801180                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        38801180                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     38801180                       # number of overall hits
-system.cpu1.icache.overall_hits::total       38801180                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       949116                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       949116                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       949116                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        949116                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       949116                       # number of overall misses
-system.cpu1.icache.overall_misses::total       949116                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8198295158                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   8198295158                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   8198295158                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   8198295158                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   8198295158                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   8198295158                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     39750296                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     39750296                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     39750296                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     39750296                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     39750296                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     39750296                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023877                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.023877                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023877                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.023877                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023877                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.023877                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8637.822098                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8637.822098                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8637.822098                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8637.822098                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8637.822098                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8637.822098                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         84944247                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        84944247                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     40901496                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       40901496                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     40901496                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        40901496                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     40901496                       # number of overall hits
+system.cpu1.icache.overall_hits::total       40901496                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      1047085                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      1047085                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      1047085                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       1047085                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      1047085                       # number of overall misses
+system.cpu1.icache.overall_misses::total      1047085                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9273780500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   9273780500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   9273780500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   9273780500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   9273780500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   9273780500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     41948581                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     41948581                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     41948581                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     41948581                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     41948581                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     41948581                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024961                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024961                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024961                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024961                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024961                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024961                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8856.759957                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8856.759957                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8856.759957                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8856.759957                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8856.759957                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8856.759957                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1667,423 +1698,451 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       949116                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       949116                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       949116                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       949116                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       949116                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       949116                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7247841842                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7247841842                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7247841842                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7247841842                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7247841842                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7247841842                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10378250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10378250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10378250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10378250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023877                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.023877                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.023877                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7636.413085                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  7636.413085                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  7636.413085                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92662.946429                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92662.946429                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1047085                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      1047085                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      1047085                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      1047085                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      1047085                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      1047085                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total          113                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total          113                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8750238000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8750238000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8750238000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8750238000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8750238000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8750238000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10154500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10154500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10154500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10154500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024961                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024961                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024961                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8356.759957                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8356.759957                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8356.759957                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89862.831858                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89862.831858                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       197332                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       197391                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           51                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       270311                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       270335                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        58593                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           54928                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15357.291554                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1177888                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           69820                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           16.870352                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        70297                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           69395                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15632.228782                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           2434679                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           84293                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           28.883525                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  7821.827388                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    38.231580                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.097899                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4362.380441                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2262.649841                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   872.104404                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.477406                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002333                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.266259                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.138101                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.053229                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.937335                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1066                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           49                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13777                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          657                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          409                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks  6105.214353                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    60.591846                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.935526                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5648.623425                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2320.323151                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1496.540481                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.372633                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003698                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000057                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.344765                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.141621                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.091342                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.954116                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1218                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           62                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13618                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          684                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          526                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6108                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7366                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.065063                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002991                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.840881                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        22523169                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       22523169                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        28304                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2558                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       928097                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       105681                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       1064640                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       119832                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       119832                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1525                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1525                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          984                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          984                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27488                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        27488                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        28304                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2558                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       928097                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       133169                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        1092128                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        28304                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2558                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       928097                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       133169                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       1092128                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          652                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          213                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst        21019                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        71648                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        93532                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28424                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28424                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22729                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22729                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34944                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        34944                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          652                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          213                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        21019                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       106592                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       128476                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          652                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          213                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        21019                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       106592                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       128476                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14243728                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4276499                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    737905240                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1619303994                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   2375729461                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    539163396                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    539163396                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    459339096                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    459339096                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       256500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       256500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1382755927                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1382755927                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14243728                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4276499                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    737905240                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3002059921                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3758485388                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14243728                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4276499                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    737905240                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3002059921                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3758485388                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        28956                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2771                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       949116                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data       177329                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total      1158172                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       119832                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       119832                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29949                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29949                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23713                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23713                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62432                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        62432                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        28956                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2771                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       949116                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       239761                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1220604                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        28956                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2771                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       949116                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       239761                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1220604                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.022146                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.404040                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.080758                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.949080                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.949080                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.958504                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.958504                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.559713                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.559713                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.022146                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.444576                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.105256                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.022146                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.444576                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.105256                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35106.581664                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22600.826178                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25400.178132                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18968.596820                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18968.596820                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20209.384311                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20209.384311                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           28                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6069                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7234                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074341                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003784                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.831177                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        43042452                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       43042452                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33942                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2703                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         36645                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       138788                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       138788                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2017                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2017                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1035                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total         1035                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37928                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        37928                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1019439                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      1019439                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131721                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       131721                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33942                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2703                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      1019439                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       169649                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        1225733                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33942                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2703                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      1019439                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       169649                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       1225733                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          703                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          221                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          924                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29293                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29293                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22443                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22443                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36124                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        36124                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27646                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        27646                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73685                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        73685                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          703                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          221                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        27646                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       109809                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       138379                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          703                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          221                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        27646                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       109809                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       138379                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17833500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4520500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     22354000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    553092500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    553092500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    450276000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    450276000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       393500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       393500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1418705500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1418705500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1071948000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1071948000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1752324498                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1752324498                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17833500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4520500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1071948000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3171029998                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4265331998                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17833500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4520500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1071948000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3171029998                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4265331998                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        34645                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2924                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        37569                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       138788                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       138788                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31310                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        31310                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23478                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23478                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74052                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        74052                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1047085                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      1047085                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205406                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       205406                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        34645                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2924                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      1047085                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       279458                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1364112                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        34645                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2924                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      1047085                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       279458                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1364112                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.024595                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.935580                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.935580                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.955916                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.955916                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.487819                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.487819                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026403                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026403                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.358729                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.358729                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026403                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.392936                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.101443                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026403                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.392936                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.101443                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24192.640693                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18881.388045                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18881.388045                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20063.093169                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20063.093169                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39570.625200                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39570.625200                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35106.581664                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28164.026578                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 29254.377378                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35106.581664                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28164.026578                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 29254.377378                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          106                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39273.211715                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39273.211715                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38774.072199                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38774.072199                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23781.291959                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23781.291959                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38774.072199                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28877.687603                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 30823.549802                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38774.072199                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28877.687603                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 30823.549802                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    26.500000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        32037                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           32037                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst           22                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           90                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          112                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          230                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          230                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          320                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          342                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           22                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          320                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          342                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          652                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          213                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        20997                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        71558                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        93420                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23227                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        23227                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28424                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28424                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22729                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22729                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34714                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34714                       # number of ReadExReq MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          652                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total       151361                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14604                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14716                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11935                       # number of WriteReq MSHR uncacheable
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-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26539                       # number of overall MSHR uncacheable misses
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    924666076                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    924666076                       # number of HardPFReq MSHR miss cycles
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-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    453146005                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    343401219                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    343401219                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       217500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       217500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1124328801                       # number of ReadExReq MSHR miss cycles
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-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9997244                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2891999                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2275768797                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2888343800                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9997244                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2891999                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2275768797                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total   3813009876                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9435750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2205092749                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2214528499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1754280499                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1754280499                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9435750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3959373248                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3968808998                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.403532                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.080662                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks        36782                       # number of writebacks
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+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          330                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3084                       # number of CleanEvict MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16810000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1287870547                       # number of HardPFReq MSHR miss cycles
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    501412999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348285500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348285500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       339500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       339500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1165172000                       # number of ReadExReq MSHR miss cycles
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+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    905573000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    905573000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1306537498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1306537498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3194500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    905573000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2471709498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3394092498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13615500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3194500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    905573000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2471709498                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1287870547                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4681963045                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9250500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2798164000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2807414500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2338978500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2338978500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9250500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5137142500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5146393000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.024595                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.949080                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.949080                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.958504                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.958504                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.556029                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.556029                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.443241                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.104976                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.443241                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.935580                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.935580                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.955916                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.955916                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.483363                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.483363                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026383                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.358091                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.358091                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.391286                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101089                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.391286                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.124005                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16091.003046                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18882.626836                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39809.965816                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15942.372819                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942.372819                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15108.505390                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.505390                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.126861                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518                       # average SCUpgradeReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32388.339027                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32388.339027                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21414.566367                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22541.587713                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21414.566367                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25191.495009                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150992.382156                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150484.404662                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146986.216925                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146986.216925                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149190.747504                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148917.826648                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1571398                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1216942                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        31019                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11935                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       119832                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        28997                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        76686                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42144                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        86299                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        85106                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66899                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1898456                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       835008                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7108                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        62262                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2802834                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     60750592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25843924                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11084                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       115824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          86721424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     645948                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1991449                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.302505                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.459343                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq         81434                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1353329                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        14413                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       511562                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1270278                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        44724                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        77037                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43004                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        89317                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        97290                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        79982                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1047085                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       561570                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3121460                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1041902                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7336                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        72984                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          4243682                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     67020672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29874703                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       138580                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          97045651                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1176077                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      3823827                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.296126                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.456547                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1389026     69.75%     69.75% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2            602423     30.25%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2691491     70.39%     70.39% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1132336     29.61%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1991449                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     839147473                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     80233998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       3823827                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1513117496                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     87426499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1424533908                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1570862868                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    411735495                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    471839695                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4337999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4412000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     33317735                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     38355467                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31014                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31014                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2099,16 +2158,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180872                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2124,10 +2183,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
@@ -2138,7 +2197,7 @@ system.iobus.reqLayer3.occupancy                12000                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2168,664 +2227,698 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198974708                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187550442                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36789763                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36433                       # number of replacements
-system.iocache.tags.tagsinuse               14.479314                       # Cycle average of tags in use
+system.iocache.tags.replacements                36446                       # number of replacements
+system.iocache.tags.tagsinuse               14.479147                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36462                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270323444000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.479314                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904957                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904957                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270355599000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.479147                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904947                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904947                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
-system.iocache.tags.data_accesses              328203                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          243                       # number of overall misses
-system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31377127                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31377127                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6657460818                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6657460818                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31377127                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31377127                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31377127                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31377127                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
+system.iocache.tags.data_accesses              328320                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide          256                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               256                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          256                       # number of overall misses
+system.iocache.overall_misses::total              256                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     32686877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32686877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4278417565                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4278417565                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32686877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32686877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32686877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32686877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          256                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             256                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          256                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            256                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129123.979424                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129123.979424                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.910391                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.910391                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129123.979424                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129123.979424                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129123.979424                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129123.979424                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22685                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 127683.113281                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 127683.113281                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 127683.113281                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 127683.113281                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 127683.113281                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            21                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3423                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.627228                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     5.250000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18676627                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18676627                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4773786844                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4773786844                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18676627                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18676627                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18676627                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18676627                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          256                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          256                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          256                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19886877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19886877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2467217565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2467217565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19886877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19886877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19886877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19886877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76858.547325                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76858.547325                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.193352                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.193352                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76858.547325                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76858.547325                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76858.547325                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76858.547325                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 77683.113281                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 77683.113281                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   135621                       # number of replacements
-system.l2c.tags.tagsinuse                64040.319526                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     379947                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   200130                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.898501                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   135320                       # number of replacements
+system.l2c.tags.tagsinuse                64080.552826                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     445963                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   199765                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.232438                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12350.088291                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.394364                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030949                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8481.237345                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2821.026897                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35473.229907                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.484833                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2216.311582                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      599.378307                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2022.137051                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.188447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.129413                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.043045                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.541279                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000129                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.033818                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009146                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030855                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.977178                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        29987                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           56                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        34466                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          143                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5502                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24342                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           55                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          307                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3362                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        30784                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.457565                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.525909                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5285534                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5285534                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker          409                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           68                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst              48212                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data              49449                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        47699                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker          127                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           23                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              17668                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data               9341                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         5522                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 178518                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          232415                       # number of Writeback hits
-system.l2c.Writeback_hits::total               232415                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3312                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             786                       # number of UpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::cpu0.data           163                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           161                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               324                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4321                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1657                       # number of ReadExReq hits
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-system.l2c.demand_hits::cpu0.dtb.walker           409                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            68                       # number of demand (read+write) hits
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-system.l2c.ReadReq_misses::cpu1.inst             3329                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu1.data          2936                       # number of UpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::cpu0.data          679                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1284                       # number of SCUpgradeReq misses
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-system.l2c.demand_misses::cpu0.dtb.walker          131                       # number of demand (read+write) misses
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+system.l2c.tags.occ_blocks::cpu0.dtb.walker    69.367527                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.data     2096.784928                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.inst     4024.713832                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1527.951308                       # Average occupied blocks per requestor
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+system.l2c.tags.age_task_id_blocks_1022::4        23534                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
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+system.l2c.ReadSharedReq_hits::cpu1.inst        21738                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::cpu0.l2cache.prefetcher        46675                       # number of demand (read+write) hits
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-system.l2c.Writeback_accesses::total           232415                       # number of Writeback accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::cpu1.data         1445                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2287                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15582                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10006                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25588                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          540                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           69                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           70882                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           74795                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180183                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker          139                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           23                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           20997                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           20952                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11758                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              380338                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          540                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           69                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          70882                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          74795                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180183                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker          139                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           23                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          20997                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          20952                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11758                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             380338                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.319827                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.164896                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.158546                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.146629                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.496778                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.736767                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.788823                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.748651                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.806413                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.888581                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.858330                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.722693                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.834399                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.766375                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.319827                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.281102                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.158546                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.475086                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.514916                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.319827                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.281102                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.158546                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.475086                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.514916                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80586.458844                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 88176.655264                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83348.980174                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 88524.766355                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 99980.057748                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1300.826106                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   991.284060                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1226.369654                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1805.546392                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1146.770249                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1374.640346                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91898.313560                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82183.403042                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 87762.169352                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80586.458844                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 90169.977218                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83348.980174                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83205.895318                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 98756.659338                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80586.458844                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 90169.977218                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 83348.980174                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83205.895318                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 98756.659338                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
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+system.l2c.UpgradeReq_miss_latency::cpu0.data      9401500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      5084500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     14486000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1177000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1665000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2842000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data    989600500                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total   1677205000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10015500                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.data    234711500                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::total  17496763358                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker     10015500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1119629067                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     19173968358                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker     10015500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu1.dtb.walker      3705500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total    19173968358                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       233248                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           233248                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        11780                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5037                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           16817                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1065                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1299                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2364                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data        10593                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25500                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          459                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       175835                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.data        13881                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::total       355698                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          459                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu0.data           71109                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total              381198                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          459                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175835                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total             381198                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.744737                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.812984                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.765178                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.761502                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.937644                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.858291                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.725297                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.794487                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.754039                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.304428                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.151578                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.212648                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.191629                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.492266                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu0.inst       0.304428                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.271850                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.206186                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.031250                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.212648                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.452562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.509777                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.015152                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.304428                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.271850                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.206186                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.031250                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.212648                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.452562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.509777                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1071.640260                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1241.636142                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1125.738265                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1451.294698                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1366.995074                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1400.689995                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91527.978172                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81702.055608                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 87227.220720                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       303000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80207.471853                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87691.337011                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        82500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82372.508942                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88237.406015                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 99925.546597                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 80207.471853                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 89837.204490                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        82500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82372.508942                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83271.578187                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 98669.083694                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 80207.471853                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 89837.204490                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        82500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82372.508942                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83271.578187                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 98669.083694                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                73                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     14.600000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              101997                       # number of writebacks
-system.l2c.writebacks::total                   101997                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks              103312                       # number of writebacks
+system.l2c.writebacks::total                   103312                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          131                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        22668                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         9764                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           12                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         3329                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1605                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         6236                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          176230                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9270                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2936                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12206                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          679                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1284                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1963                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11261                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8349                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19610                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          131                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3718                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3718                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8773                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4095                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12868                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          811                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1218                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2029                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        10812                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8416                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19228                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          116                       # number of ReadSharedReq MSHR misses
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+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       129160                       # number of ReadSharedReq MSHR misses
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+system.l2c.ReadSharedReq_mshr_misses::total       175092                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          116                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        22668                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6236                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           195840                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         9190                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           194320                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        22668                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total          195840                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14601                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38468                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31019                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26536                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69487                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        70000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1542775978                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    738824138                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    235730745                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    121970250                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::total  15440351437                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    165428726                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     52162926                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    217591652                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     12163677                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     22807281                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     34970958                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    895596591                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    581734768                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1477331359                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       870250                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.data    703705018                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::total  16917682796                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1542775978                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1634420729                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       870250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    235730745                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    703705018                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    745216962                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16917682796                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3717048000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6862750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919952251                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5848571001                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2762074500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1533074001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4295148501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6479122500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6862750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3453026252                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10143719502                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.164896                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.146629                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.496772                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.736767                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.788823                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.748651                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.806413                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.888581                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858330                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.722693                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.834399                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.766375                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.281102                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.475086                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.514910                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.281102                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.475086                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.514910                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75668.182917                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70811.278162                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75993.925234                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 87614.772950                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.601510                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.664169                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17826.614124                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17914.104566                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.679907                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.057565                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79530.822396                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69677.179063                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75335.612392                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77737.014459                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70811.278162                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70695.702029                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 86385.226695                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77737.014459                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70695.702029                       # average overall mshr miss latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571                       # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128451.948136                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138468.309778                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average overall mshr uncacheable latency
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     85020001                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25297000                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.data    811556000                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3283407500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2489619500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5994828500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2314728500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::total   4408684500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4583575500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10403513000                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.744737                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.812984                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.765178                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.937644                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.191629                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.492249                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.252723                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.015152                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.304397                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.271850                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.206186                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.031250                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.452562                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.509761                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.252723                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.015152                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.304397                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.271850                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.206186                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.031250                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.452562                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.509761                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20855.807591                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20761.905006                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20825.924852                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20883.477189                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20769.293924                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20814.933465                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81527.978172                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71702.055608                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 77227.220720                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 88670.663637                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 88670.663637                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              214941                       # Transaction distribution
-system.membus.trans_dist::ReadResp             214941                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31019                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31019                       # Transaction distribution
-system.membus.trans_dist::Writeback            138187                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            76766                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40830                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14310                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39945                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19469                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14152                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       662279                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       784385                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 893281                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19271336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19463652                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                24099108                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           124366                       # Total snoops (count)
-system.membus.snoop_fanout::samples            577962                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               38679                       # Transaction distribution
+system.membus.trans_dist::ReadResp             214027                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31171                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31171                       # Transaction distribution
+system.membus.trans_dist::Writeback            139502                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            18408                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            78648                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41625                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15041                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39591                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19084                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        175348                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14764                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       682494                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       805212                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 914134                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19261796                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19455462                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21772582                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           126350                       # Total snoops (count)
+system.membus.snoop_fanout::samples            599467                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  577962    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  599467    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              577962                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91190000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              599467                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            91393000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12300498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12942500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1168075116                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1014707988                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1171902830                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1166663343                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37484237                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64473559                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2858,44 +2951,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             516760                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            516745                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31019                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31019                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           232415                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           80723                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41154                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         121877                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51826                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51826                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1082609                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       339699                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1422308                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34055964                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5608584                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               39664548                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          289563                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           990166                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.036865                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.188429                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              38683                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            520875                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31171                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31171                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           372774                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          100063                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           82453                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41960                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         124413                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51599                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51599                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       482207                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1095171                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       404182                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1499353                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32852839                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6925951                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39778790                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          466118                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1289558                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.161505                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.367996                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 953664     96.31%     96.31% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36502      3.69%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1081288     83.85%     83.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 208270     16.15%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             990166                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          786658690                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1289558                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          856703495                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           342000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           361500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         681591350                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         633166148                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         259907159                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         285761511                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 99269b180..4d6593456 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.852793                       # Number of seconds simulated
-sim_ticks                                2852793222500                       # Number of ticks simulated
-final_tick                               2852793222500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.852648                       # Number of seconds simulated
+sim_ticks                                2852648357500                       # Number of ticks simulated
+final_tick                               2852648357500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 170913                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206647                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4363431399                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 626396                       # Number of bytes of host memory used
-host_seconds                                   653.80                       # Real time elapsed on the host
-sim_insts                                   111742418                       # Number of instructions simulated
-sim_ops                                     135104867                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 166579                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201414                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4236074446                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625784                       # Number of bytes of host memory used
+host_seconds                                   673.42                       # Real time elapsed on the host
+sim_insts                                   112177181                       # Number of instructions simulated
+sim_ops                                     135636113                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         7552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         8192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1671744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9171756                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1670464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9187820                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10852140                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1671744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1671744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7973376                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10867564                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1670464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1670464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7983168                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7990900                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          118                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8000692                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          128                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26121                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143830                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26101                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144081                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170086                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124584                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170327                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124737                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128965                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129118                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2872                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               586003                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3215009                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               585584                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3220804                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3804040                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          586003                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             586003                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2794937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3809640                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          585584                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             585584                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2798511                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2801079                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2794937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2804654                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2798511                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2872                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              586003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3221152                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              585584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3226947                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6605119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170086                       # Number of read requests accepted
-system.physmem.writeReqs                       165189                       # Number of write requests accepted
-system.physmem.readBursts                      170086                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     165189                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10878016                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9060544                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10852140                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10309236                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23589                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4592                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10719                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10428                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10712                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10613                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13554                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10863                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10988                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10936                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10331                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10532                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10066                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9201                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10334                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10898                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9868                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9926                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8834                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8868                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9254                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9172                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8841                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9153                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9171                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9059                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9082                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9087                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8650                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8253                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8834                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9086                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8043                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8184                       # Per bank write bursts
+system.physmem.bw_total::total                6614294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170327                       # Number of read requests accepted
+system.physmem.writeReqs                       129118                       # Number of write requests accepted
+system.physmem.readBursts                      170327                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129118                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10891072                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8012864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10867564                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8000692                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40818                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10912                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10835                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10722                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10734                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13360                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10814                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11148                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10988                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10136                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10280                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10233                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9195                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10314                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10738                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10036                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9728                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8115                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8199                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8378                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8308                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7548                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7862                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8189                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8102                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7754                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7814                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7662                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7060                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7768                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7969                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7379                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7094                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          57                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2852792816500                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2852647955000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169529                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169770                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 160808                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    162438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7239                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       280                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124737                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6778                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       282                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,190 +159,187 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      161                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61793                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      322.665933                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.077551                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     338.586947                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22269     36.04%     36.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14610     23.64%     59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6509     10.53%     70.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3452      5.59%     75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2793      4.52%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1471      2.38%     82.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1217      1.97%     84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1102      1.78%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8370     13.55%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61793                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5884                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.884772                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      583.981749                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5883     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5884                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5884                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.060333                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.369950                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       43.410965                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5554     94.39%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              88      1.50%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              18      0.31%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              15      0.25%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              30      0.51%     96.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             27      0.46%     97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            26      0.44%     97.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             9      0.15%     98.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            10      0.17%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             1      0.02%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            18      0.31%     98.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            12      0.20%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             8      0.14%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             5      0.08%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.03%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.05%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.03%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             6      0.10%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             6      0.10%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.05%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             3      0.05%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            16      0.27%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             3      0.05%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             2      0.03%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             3      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5884                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1705654500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4892573250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849845000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10035.09                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     1946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6808                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6597                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7445                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60792                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      310.959863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.660922                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.542835                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22288     36.66%     36.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14645     24.09%     60.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6538     10.75%     71.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3485      5.73%     77.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2623      4.31%     81.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1593      2.62%     84.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1118      1.84%     86.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1065      1.75%     87.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7437     12.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60792                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6289                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.056766                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      539.634570                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6287     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6289                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6289                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.907934                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.344478                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.522535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5503     87.50%     87.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              53      0.84%     88.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             178      2.83%     91.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              46      0.73%     91.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              61      0.97%     92.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             176      2.80%     95.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              19      0.30%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.10%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              12      0.19%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.16%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.13%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.08%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             165      2.62%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.06%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               5      0.08%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               4      0.06%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.27%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6289                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1698489250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4889233000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    850865000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9980.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28785.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.18                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.61                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28730.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.27                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     140294                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109452                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.30                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8508814.60                       # Average gap between requests
-system.physmem.pageHitRate                      80.16                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  242736480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132445500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 692741400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                468840960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186330281280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83545935120                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638387378750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1909800359490                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.450312                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2725465336224                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95260880000                       # Time in different power states
+system.physmem.avgWrQLen                        24.43                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     140383                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94198                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.49                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9526450.45                       # Average gap between requests
+system.physmem.pageHitRate                      79.41                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  240748200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131360625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 698201400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                419262480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83613121875                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638239679750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1909662992970                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.436876                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2725220726500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95255940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32062608776                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32164219750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  224418600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122450625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 633009000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                448539120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186330281280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82219424850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1639550984250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1909529107725                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.355229                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2727414398224                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95260880000                       # Time in different power states
+system.physmem_1.actEnergy                  218839320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119406375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 629140200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                392040000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82051531065                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1639609496250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1909341071850                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.324025                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2727521283250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95255940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30117847276                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     29871038250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst           157                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              157                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          157                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst          157                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             157                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31001883                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16796453                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2502337                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18460820                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13284720                       # Number of BTB hits
+system.cpu.branchPred.lookups                31035995                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16848460                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2529330                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18616538                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13364370                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.961701                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7904518                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1496209                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             71.787622                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7827743                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1524480                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -373,58 +370,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     66819                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                66819                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43911                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22908                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        66819                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           66819    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        66819                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7827                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11026.574677                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  8748.919938                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  7443.454079                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383         6102     77.96%     77.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767         1719     21.96%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-49151            1      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     66851                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                66851                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44044                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22807                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        66851                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           66851    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        66851                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7848                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11969.673802                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9947.704899                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7432.490287                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383         6134     78.16%     78.16% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         1708     21.76%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7827                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    262515000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       262515000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    262515000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6438     82.25%     82.25% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1389     17.75%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7827                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66819                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total         7848                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    260813000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       260813000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    260813000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6448     82.16%     82.16% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1400     17.84%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7848                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66851                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66819                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7827                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66851                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7848                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7827                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        74646                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7848                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        74699                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24698795                       # DTB read hits
-system.cpu.dtb.read_misses                      59886                       # DTB read misses
-system.cpu.dtb.write_hits                    19408206                       # DTB write hits
-system.cpu.dtb.write_misses                      6933                       # DTB write misses
+system.cpu.dtb.read_hits                     24795366                       # DTB read hits
+system.cpu.dtb.read_misses                      59924                       # DTB read misses
+system.cpu.dtb.write_hits                    19459513                       # DTB write hits
+system.cpu.dtb.write_misses                      6927                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4360                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1246                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1786                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4353                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1315                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1793                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       745                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24758681                       # DTB read accesses
-system.cpu.dtb.write_accesses                19415139                       # DTB write accesses
+system.cpu.dtb.perms_faults                       738                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24855290                       # DTB read accesses
+system.cpu.dtb.write_accesses                19466440                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44107001                       # DTB hits
-system.cpu.dtb.misses                           66819                       # DTB misses
-system.cpu.dtb.accesses                      44173820                       # DTB accesses
+system.cpu.dtb.hits                          44254879                       # DTB hits
+system.cpu.dtb.misses                           66851                       # DTB misses
+system.cpu.dtb.accesses                      44321730                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -454,37 +449,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                      5459                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5459                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5138                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5459                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5459    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5459                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3190                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11236.050157                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  8968.317634                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7059.322929                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1291     40.47%     40.47% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383         1179     36.96%     77.43% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          719     22.54%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                      5476                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5476                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5156                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5476                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5476    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5476                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3185                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12111.930926                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10073.036735                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7077.069157                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1309     41.10%     41.10% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1163     36.51%     77.61% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          712     22.35%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3190                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    262109500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       262109500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    262109500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2880     90.28%     90.28% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           310      9.72%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3190                       # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total         3185                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    260408500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       260408500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    260408500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2875     90.27%     90.27% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.73%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3185                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5459                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5459                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5476                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5476                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3190                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3190                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         8649                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57544146                       # ITB inst hits
-system.cpu.itb.inst_misses                       5459                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3185                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3185                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8661                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57644793                       # ITB inst hits
+system.cpu.itb.inst_misses                       5476                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -493,274 +488,274 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2978                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2975                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8374                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8375                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57549605                       # ITB inst accesses
-system.cpu.itb.hits                          57544146                       # DTB hits
-system.cpu.itb.misses                            5459                       # DTB misses
-system.cpu.itb.accesses                      57549605                       # DTB accesses
-system.cpu.numCycles                        315425036                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57650269                       # ITB inst accesses
+system.cpu.itb.hits                          57644793                       # DTB hits
+system.cpu.itb.misses                            5476                       # DTB misses
+system.cpu.itb.accesses                      57650269                       # DTB accesses
+system.cpu.numCycles                        315472495                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   111742418                       # Number of instructions committed
-system.cpu.committedOps                     135104867                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7746377                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5390221882                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.822787                       # CPI: cycles per instruction
-system.cpu.ipc                               0.354260                       # IPC: instructions per cycle
+system.cpu.committedInsts                   112177181                       # Number of instructions committed
+system.cpu.committedOps                     135636113                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7815514                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5389884731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.812270                       # CPI: cycles per instruction
+system.cpu.ipc                               0.355585                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
-system.cpu.tickCycles                       227203186                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        88221850                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            843958                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.947848                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42509637                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            844470                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.338836                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         313221250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.947848                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999898                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999898                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
+system.cpu.tickCycles                       227521960                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        87950535                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            843739                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.948229                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42652951                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            844251                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.521647                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         310642500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.948229                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999899                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999899                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         175807461                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        175807461                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23001062                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23001062                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18245677                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18245677                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356392                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356392                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443406                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443406                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460170                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460170                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41246739                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41246739                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41603131                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41603131                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       493519                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        493519                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       547788                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       547788                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       170140                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       170140                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22585                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22585                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176384491                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176384491                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23097762                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23097762                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18292469                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18292469                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356103                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356103                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443541                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460142                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460142                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41390231                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41390231                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41746334                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41746334                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       493938                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        493938                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       548534                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       548534                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       170153                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       170153                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22409                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22409                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1041307                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1041307                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1211447                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1211447                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   7303521091                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7303521091                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  23397429282                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  23397429282                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    285183750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    285183750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  30700950373                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30700950373                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  30700950373                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  30700950373                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23494581                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23494581                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18793465                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18793465                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526532                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526532                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465991                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465991                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460172                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460172                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42288046                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42288046                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42814578                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42814578                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021006                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.021006                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029148                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029148                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323133                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.323133                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048467                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048467                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      1042472                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1042472                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1212625                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1212625                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7285426000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7285426000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  23290524980                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  23290524980                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    282897500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    282897500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30575950980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30575950980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30575950980                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30575950980                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23591700                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23591700                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18841003                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18841003                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       526256                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       526256                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460144                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460144                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42432703                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42432703                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42958959                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42958959                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020937                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.020937                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029114                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029114                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323327                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.323327                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048093                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048093                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024624                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024624                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028295                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028295                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14798.865071                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14798.865071                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42712.562674                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42712.562674                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12627.130839                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12627.130839                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29483.092280                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29483.092280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25342.380123                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25342.380123                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          238                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024568                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024568                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028228                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028228                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14749.677085                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14749.677085                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42459.583143                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42459.583143                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12624.280423                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12624.280423                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29330.237148                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29330.237148                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25214.679707                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25214.679707                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          276                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.900000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.545455                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       699616                       # number of writebacks
-system.cpu.dcache.writebacks::total            699616                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75147                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        75147                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249007                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249007                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14321                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14321                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       324154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       324154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       324154                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       324154                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418372                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       418372                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298781                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298781                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121907                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121907                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8264                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8264                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       699258                       # number of writebacks
+system.cpu.dcache.writebacks::total            699258                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75585                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        75585                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249712                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       249712                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14175                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14175                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       325297                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       325297                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       325297                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       325297                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418353                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       418353                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298822                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298822                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121703                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121703                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8234                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8234                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       717153                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       717153                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       839060                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       839060                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       717175                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       717175                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total       838878                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5719215890                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5719215890                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12311488911                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12311488911                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1563028750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1563028750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    105928000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    105928000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       164000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       164000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18030704801                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18030704801                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19593733551                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  19593733551                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5833996750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5833996750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4510200000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4510200000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10344196750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10344196750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015898                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015898                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231528                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231528                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017734                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017734                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5919321500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5919321500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12456778000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12456778000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1615525000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1615525000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109204500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109204500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18376099500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18376099500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19991624500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  19991624500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5909109000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5909109000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4568792500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4568792500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10477901500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10477901500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017733                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017733                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015860                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015860                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231262                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231262                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017671                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017671                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016959                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016959                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019598                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019598                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.168869                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.168869                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41205.728982                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41205.728982                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12821.484820                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12821.484820                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12818.005808                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.005808                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25142.061458                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25142.061458                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23352.005281                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23352.005281                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187419.582048                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187419.582048                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163513.758474                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163513.758474                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176188.393146                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176188.393146                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016901                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016901                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019527                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019527                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14149.107333                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14149.107333                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41686.281465                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41686.281465                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13274.323558                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13274.323558                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13262.630556                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13262.630556                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25622.894691                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25622.894691                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23831.384897                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23831.384897                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189832.594449                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189832.594449                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165637.983541                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165637.983541                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.730442                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.730442                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2897206                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.401811                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54637656                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2897718                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.855408                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       15497791250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.401811                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998832                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998832                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           2894405                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.404377                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54741020                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2894917                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.909357                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       15461690500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.404377                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998837                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998837                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60433115                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60433115                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54637656                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54637656                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54637656                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54637656                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54637656                       # number of overall hits
-system.cpu.icache.overall_hits::total        54637656                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2897730                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2897730                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2897730                       # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::cpu.inst      2897730                       # number of overall misses
-system.cpu.icache.overall_misses::total       2897730                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  39295051229                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  39295051229                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  39295051229                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  39295051229                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  39295051229                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  39295051229                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57535386                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57535386                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57535386                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57535386                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57535386                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57535386                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050364                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050364                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050364                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050364                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050364                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050364                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13560.632367                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13560.632367                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13560.632367                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13560.632367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13560.632367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13560.632367                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60530877                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60530877                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54741020                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54741020                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::cpu.inst      2894929                       # number of overall misses
+system.cpu.icache.overall_misses::total       2894929                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39235778500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39235778500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39235778500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39235778500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39235778500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39235778500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57635949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57635949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57635949                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57635949                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57635949                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57635949                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050228                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050228                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050228                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050228                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050228                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050228                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.278336                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13553.278336                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13553.278336                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13553.278336                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -769,200 +764,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897730                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2897730                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2897730                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2897730                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2897730                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2897730                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3172                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3172                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3172                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3172                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  34939012271                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  34939012271                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  34939012271                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  34939012271                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  34939012271                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  34939012271                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    247386750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    247386750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    247386750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    247386750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050364                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050364                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050364                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050364                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050364                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050364                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.373279                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.373279                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.373279                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.373279                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.373279                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.373279                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894929                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_uncacheable::total         3191                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050228                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average ReadReq mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average ReadReq mshr uncacheable latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96812                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65065.452586                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4048611                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162072                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            24.980324                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            97027                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65057.378732                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7025854                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162288                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            43.292505                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47495.130648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    59.738238                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009476                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12201.333788                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5309.240435                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.724718                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000912                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 47465.165488                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.060465                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009465                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12271.489149                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5249.654166                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.724261                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.186178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.081013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992820                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65214                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           46                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2294                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6948                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55853                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000702                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995087                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         36624702                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        36624702                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        71053                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4456                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        3484432                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       699616                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       699616                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           54                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           54                       # number of UpgradeReq hits
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.Writeback_accesses::total       699616                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       371000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1831389500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11369865500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13212712500                       # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_accesses::total        75463                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       699258                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       295959                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       295959                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        71171                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        71171                       # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::total      3817828                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001658                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000449                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.007930                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026139                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.010630                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.980898                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.980898                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_miss_rate::total     0.001723                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.981998                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981998                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.443227                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.443227                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001658                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000449                       # miss rate for demand accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172310                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044165                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001658                       # miss rate for overall accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.044165                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        85125                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        89875                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80184.505418                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83985.214116                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 81656.229132                       # average ReadReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   393.604400                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77642.190940                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77642.190940                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        85125                       # average overall miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78267.186757                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78533.419117                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        85125                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78267.186757                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78533.419117                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79816.495969                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83141.208251                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       185500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 78258.136642                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78004.016877                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78258.136642                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -971,176 +978,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88394                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88394                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           20                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          140                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          160                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          118                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        88547                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88547                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           24                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           24                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        22959                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total       131177                       # number of ReadExReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        22959                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        22959                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3172                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34300                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3172                       # number of overall MSHR uncacheable misses
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 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61883                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8565250                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1016371500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2579203000                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       137000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       137000                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1554112000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9559719319                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11122550819                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8565250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       154250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1554112000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9559719319                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11122550819                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191729750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5397684500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5589414250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4151492500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4151492500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191729750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9549177000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9740906750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001658                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000449                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.007923                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025883                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010584                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.980898                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.980898                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61902                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       351000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     10157500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     57758000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     57758000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8869857000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8869857000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1601051500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1601051500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1033348500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1033348500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       351000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1601051500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9903205500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11514414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       351000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1601051500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9903205500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11514414500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    199170000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519970000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5719140000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4251529500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4251529500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    199170000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771499500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9970669500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001723                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.981998                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981998                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.443227                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443227                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001658                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000449                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007923                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172144                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044123                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001658                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000449                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007923                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172144                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044123                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67690.753082                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71585.540217                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69190.197709                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17770.383339                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17770.383339                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65128.397654                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65128.397654                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67690.753082                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.032289                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66027.228911                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67690.753082                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.032289                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66027.228911                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173402.868800                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162956.683673                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150509.099808                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150509.099808                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162647.153004                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157408.444161                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444293                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007918                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025737                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025737                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044216                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78134.615385                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20761.322789                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20761.322789                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67447.280774                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67447.280774                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69850.857292                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73229.997874                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73229.997874                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177331.341557                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166646.464058                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154135.862669                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154135.862669                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.879512                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.847436                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3581126                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3581032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         134609                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3577964                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       699616                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36257                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       824000                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2989342                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2833                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2829                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295959                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295959                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5801775                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2511831                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15055                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160898                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8489559                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185655872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99015325                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       284684                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          284973713                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       61355                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4643370                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.029465                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.169105                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2835                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295994                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295994                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894929                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       548519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8639925                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2647968                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15065                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160688                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11463646                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185478080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98978525                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17732                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       284120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          284758457                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194907                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      7812293                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.034587                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.182731                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4506555     97.05%     97.05% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             136815      2.95%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            7542089     96.54%     96.54% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             270204      3.46%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4643370                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3016847250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       211500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        7812293                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4534239000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4356806979                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4347433988                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1344182949                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1312866777                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10597250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10632499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      89732000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      89658000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1231,23 +1249,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198883474                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187463964                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36810507                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.031423                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.030996                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270485733000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.031423                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064464                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064464                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270425383000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.030996                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064437                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064437                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1255,49 +1273,49 @@ system.iocache.tags.tag_accesses               328122                       # Nu
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29239875                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29239875                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6650280092                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6650280092                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29239875                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29239875                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29239875                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29239875                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29161877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29161877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4271869087                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4271869087                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29161877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29161877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29161877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29161877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124956.730769                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183587.679218                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183587.679218                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124956.730769                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124956.730769                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124956.730769                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124956.730769                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22674                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124623.405983                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117929.248206                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117929.248206                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124623.405983                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124623.405983                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3485                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.506169                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1305,88 +1323,90 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16928877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16928877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4766620104                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4766620104                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16928877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16928877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16928877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16928877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17461877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17461877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460669087                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2460669087                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17461877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17461877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17461877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17461877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131587.348277                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131587.348277                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72345.628205                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72345.628205                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67929.248206                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67929.248206                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               71811                       # Transaction distribution
-system.membus.trans_dist::ReadResp              71811                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34319                       # Transaction distribution
+system.membus.trans_dist::ReadResp              71715                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
-system.membus.trans_dist::Writeback            124584                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4592                       # Transaction distribution
+system.membus.trans_dist::Writeback            124737                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8493                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4594                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129358                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129358                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4596                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129696                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129696                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37396                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446770                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554330                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 663217                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455889                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       563451                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 672351                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16525920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16689629                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21325085                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16551136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16714909                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19032029                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              507                       # Total snoops (count)
-system.membus.snoop_fanout::samples            394211                       # Request fanout histogram
+system.membus.snoop_fanout::samples            403270                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  394211    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  403270    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              394211                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87591000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              403270                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87538000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1723500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1706000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1025789403                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           881842801                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          997949408                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          999291900                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37471493                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64464474                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 2dea4306e..d2ddd8522 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827616                       # Number of seconds simulated
-sim_ticks                                2827616186000                       # Number of ticks simulated
-final_tick                               2827616186000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827546                       # Number of seconds simulated
+sim_ticks                                2827546300000                       # Number of ticks simulated
+final_tick                               2827546300000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70271                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85238                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1756065639                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 621588                       # Number of bytes of host memory used
-host_seconds                                  1610.20                       # Real time elapsed on the host
-sim_insts                                   113151083                       # Number of instructions simulated
-sim_ops                                     137250963                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  69908                       # Simulator instruction rate (inst/s)
+host_op_rate                                    84797                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1747497470                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 626724                       # Number of bytes of host memory used
+host_seconds                                  1618.05                       # Real time elapsed on the host
+sim_insts                                   113115023                       # Number of instructions simulated
+sim_ops                                     137206411                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1325344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9769960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1322768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9763816                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11098056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1325344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1325344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8387584                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11089336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1322768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1322768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8388544                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8405108                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8406068                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             153176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22916                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             153080                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                176173                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131056                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                176039                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131071                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135437                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               135452                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            475                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3455193                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               467815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3453106                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3924881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2966309                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6197                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2972507                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2966309                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3921894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          467815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             467815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2966722                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6198                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2972920                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2966722                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           475                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3461391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              467815                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3459303                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6897387                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        176174                       # Number of read requests accepted
-system.physmem.writeReqs                       171661                       # Number of write requests accepted
-system.physmem.readBursts                      176174                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     171661                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11266304                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8832                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9457344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11098120                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10723444                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      138                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23861                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4579                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11334                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10890                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10732                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10393                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14045                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11531                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11498                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11674                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10645                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10993                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10307                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9597                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9956                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10908                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10689                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10844                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9257                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9346                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9336                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8962                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9705                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9746                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9125                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9630                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9307                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9634                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8942                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8449                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8881                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9361                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9018                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9072                       # Per bank write bursts
+system.physmem.bw_total::total                6894813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        176040                       # Number of read requests accepted
+system.physmem.writeReqs                       135452                       # Number of write requests accepted
+system.physmem.readBursts                      176040                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     135452                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11255936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10624                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8418624                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11089400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8406068                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      166                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3886                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40804                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11283                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10909                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10879                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10544                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14049                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11359                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11255                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11497                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10572                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11295                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10218                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9589                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9979                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10701                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10842                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10903                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8346                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8306                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8514                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8219                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8602                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8561                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8053                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8529                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8073                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8804                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7852                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7407                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7747                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8181                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8268                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8079                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          58                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827615975000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827546089000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    2994                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    2997                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  172624                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  172487                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 167280                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    154910                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     18105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       821                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131071                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    154804                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17996                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       828                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,161 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1002                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       87                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66219                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      312.955255                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.034234                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.173316                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24625     37.19%     37.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15873     23.97%     61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6865     10.37%     71.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3626      5.48%     77.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2732      4.13%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1677      2.53%     83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1136      1.72%     85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1168      1.76%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8517     12.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66219                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6252                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.154671                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      564.033809                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6251     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6252                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.635797                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.335011                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       41.227878                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5914     94.59%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              86      1.38%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              17      0.27%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              16      0.26%     96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              17      0.27%     96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             30      0.48%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            32      0.51%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            14      0.22%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            17      0.27%     98.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             6      0.10%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            22      0.35%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            18      0.29%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             7      0.11%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.02%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.02%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             6      0.10%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             4      0.06%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.06%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.05%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             5      0.08%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            16      0.26%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             2      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.05%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             3      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::752-767             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6252                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2104913750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5405588750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    880180000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11957.29                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65199                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      301.760702                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.342640                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.505125                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24507     37.59%     37.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15999     24.54%     62.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6852     10.51%     72.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3716      5.70%     78.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2634      4.04%     82.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1687      2.59%     84.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1128      1.73%     86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1089      1.67%     88.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7587     11.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65199                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6653                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.433789                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      560.061521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6652     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6653                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6653                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.771682                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.345316                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.497785                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5824     87.54%     87.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              71      1.07%     88.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             181      2.72%     91.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              53      0.80%     92.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              64      0.96%     93.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             178      2.68%     95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              29      0.44%     96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.09%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.14%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               9      0.14%     96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             170      2.56%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.06%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.09%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.12%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.17%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6653                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2123501000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5421138500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    879370000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12073.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30707.29                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30823.99                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145058                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    112529                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.14                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8129187.62                       # Average gap between requests
-system.physmem.pageHitRate                      79.54                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  260517600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  142147500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 718356600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                486693360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184686106800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            81488169855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1625088668250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1892870659965                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.422846                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2703351122494                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94420300000                       # Time in different power states
+system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144861                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97354                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9077427.64                       # Average gap between requests
+system.physmem.pageHitRate                      78.78                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  255989160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139676625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 715845000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                435002400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184681529760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            81048006450                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625432730750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892708780145                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.382186                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2703925000250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94417960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     29844456256                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29202842250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  240098040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  131005875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654716400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                470862720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184686106800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80123990850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1626285316500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1892592097185                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.324331                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2705354976994                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94420300000                       # Time in different power states
+system.physmem_1.actEnergy                  236915280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  129269250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 655964400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                417383280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184681529760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80055144540                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626303662250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892479868760                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.301228                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705388162750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94417960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27840895506                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27740163750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -333,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46937284                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24041936                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233234                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29553356                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21362007                       # Number of BTB hits
+system.cpu.branchPred.lookups                46902830                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24030897                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232795                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29532360                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21346058                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.282847                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11754741                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33891                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.280231                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11742213                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33846                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -372,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks              9923                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9923                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9923                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9923    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9923                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walksPending::samples    230116500                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::0    230116500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::total    230116500                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6339     81.70%     81.70% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M         1420     18.30%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7759                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9923                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walks              9925                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9925                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9925                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9925    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9925                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples    227240000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0    227240000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total    227240000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6352     81.85%     81.85% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1409     18.15%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7761                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9925                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9923                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7759                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9925                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7761                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7759                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17682                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7761                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17686                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24588859                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8478                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19638229                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1445                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24580805                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8471                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19633932                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1454                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
 system.cpu.checker.dtb.flush_entries             4321                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1767                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1778                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24597337                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19639674                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24589276                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19635386                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44227088                       # DTB hits
-system.cpu.checker.dtb.misses                    9923                       # DTB misses
-system.cpu.checker.dtb.accesses              44237011                       # DTB accesses
+system.cpu.checker.dtb.hits                  44214737                       # DTB hits
+system.cpu.checker.dtb.misses                    9925                       # DTB misses
+system.cpu.checker.dtb.accesses              44224662                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -445,9 +440,9 @@ system.cpu.checker.itb.walker.walksShort         4826                       # Ta
 system.cpu.checker.itb.walker.walkWaitTime::samples         4826                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.itb.walker.walkWaitTime::0         4826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.checker.itb.walker.walkWaitTime::total         4826                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walksPending::samples    229704000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::0    229704000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::total    229704000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::samples    226829000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0    226829000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total    226829000                       # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walkPageSizes::4K         2798     88.24%     88.24% # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkPageSizes::1M          373     11.76%    100.00% # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkPageSizes::total         3171                       # Table walker page sizes translated
@@ -458,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3171                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3171                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin::total         7997                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115853330                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115815180                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4826                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -475,11 +470,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115858156                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115853330                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115820006                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115815180                       # DTB hits
 system.cpu.checker.itb.misses                    4826                       # DTB misses
-system.cpu.checker.itb.accesses             115858156                       # DTB accesses
-system.cpu.checker.numCycles                139105254                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115820006                       # DTB accesses
+system.cpu.checker.numCycles                139058612                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -511,84 +506,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     72371                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72371                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29709                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22637                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        20025                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52346                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   408.397967                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2384.163324                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        50769     96.99%     96.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          522      1.00%     97.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          392      0.75%     98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          322      0.62%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479          112      0.21%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          191      0.36%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767            8      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     72877                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72877                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29786                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22407                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        20684                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52193                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   427.193302                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2519.151181                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50372     96.51%     96.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          577      1.11%     97.62% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          541      1.04%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          349      0.67%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479           64      0.12%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          245      0.47%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671           20      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767            5      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::40960-45055            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52346                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9112.637070                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  7625.312992                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383        13355     74.20%     74.20% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767         4455     24.75%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-49151          181      1.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::49152-65535            5      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52193                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        18420                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9894.996282                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7919.116299                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383        13659     74.15%     74.15% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         4520     24.54%     98.69% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-49151          229      1.24%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::49152-65535            5      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 117490693224                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.629020                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.491115                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  117435257724     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37744500      0.03%     99.98% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7698500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6179000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1033000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       848500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1404000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       520500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 117490693224                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6498     81.61%     81.61% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1464     18.39%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7962                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72371                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total        18420                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 117420807224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.629573                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.491742                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  117361135224     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      40228000      0.03%     99.98% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8514000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6836000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1132500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       742000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       806000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 117420807224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6507     81.76%     81.76% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1452     18.24%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7959                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72877                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72371                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7962                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72877                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7959                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7962                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        80333                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7959                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80836                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25461869                       # DTB read hits
-system.cpu.dtb.read_misses                      62291                       # DTB read misses
-system.cpu.dtb.write_hits                    19915387                       # DTB write hits
-system.cpu.dtb.write_misses                     10080                       # DTB write misses
+system.cpu.dtb.read_hits                     25454298                       # DTB read hits
+system.cpu.dtb.read_misses                      62609                       # DTB read misses
+system.cpu.dtb.write_hits                    19910353                       # DTB write hits
+system.cpu.dtb.write_misses                     10268                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4354                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       348                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2290                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       354                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2301                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1335                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25524160                       # DTB read accesses
-system.cpu.dtb.write_accesses                19925467                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1336                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25516907                       # DTB read accesses
+system.cpu.dtb.write_accesses                19920621                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45377256                       # DTB hits
-system.cpu.dtb.misses                           72371                       # DTB misses
-system.cpu.dtb.accesses                      45449627                       # DTB accesses
+system.cpu.dtb.hits                          45364651                       # DTB hits
+system.cpu.dtb.misses                           72877                       # DTB misses
+system.cpu.dtb.accesses                      45437528                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -618,56 +615,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11974                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11974                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3948                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7776                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore          250                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11724                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   570.794951                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2803.545728                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-8191        11373     97.01%     97.01% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-16383          269      2.29%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-24575           71      0.61%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     11947                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11947                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3916                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7772                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          259                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11688                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   646.175565                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3062.873414                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        11278     96.49%     96.49% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          250      2.14%     98.63% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575          145      1.24%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767           11      0.09%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::40960-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::73728-81919            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11724                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12176.865046                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9546.126127                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7774.383636                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1294     36.16%     36.16% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383         1330     37.16%     73.32% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          901     25.17%     98.49% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::24576-32767           22      0.61%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-40959           25      0.70%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::40960-49151            5      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11688                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3588                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 13165.830546                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7878.482425                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1266     35.28%     35.28% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1353     37.71%     72.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          898     25.03%     98.02% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           28      0.78%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959           19      0.53%     99.33% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::40960-49151           22      0.61%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::81920-90111            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23001352712                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.973391                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.161136                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       612637000      2.66%      2.66% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     22388223712     97.33%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2          416000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           45500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4           30500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23001352712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         3588                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  22931465712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.972560                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.163591                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       629948000      2.75%      2.75% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     22300919212     97.25%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          517500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           46500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           34500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  22931465712                       # Table walker pending requests distribution
 system.cpu.itb.walker.walkPageSizes::4K          3007     90.33%     90.33% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::1M           322      9.67%    100.00% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::total         3329                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11974                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11974                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11947                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11947                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3329                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15303                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66270436                       # ITB inst hits
-system.cpu.itb.inst_misses                      11974                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin::total        15276                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66251443                       # ITB inst hits
+system.cpu.itb.inst_misses                      11947                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -676,98 +673,98 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3094                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2189                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2204                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66282410                       # ITB inst accesses
-system.cpu.itb.hits                          66270436                       # DTB hits
-system.cpu.itb.misses                           11974                       # DTB misses
-system.cpu.itb.accesses                      66282410                       # DTB accesses
-system.cpu.numCycles                        263104506                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66263390                       # ITB inst accesses
+system.cpu.itb.hits                          66251443                       # DTB hits
+system.cpu.itb.misses                           11947                       # DTB misses
+system.cpu.itb.accesses                      66263390                       # DTB accesses
+system.cpu.numCycles                        263015768                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104871759                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184678718                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46937284                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33116748                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     147875517                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6159108                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     184684                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 7836                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        337023                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       520063                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          109                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66270632                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1094853                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5249                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          256876545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.877001                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.234757                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104824855                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184645834                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46902830                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33088271                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     147851260                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6154028                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     194015                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8214                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        337761                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       519343                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66251613                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1117287                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5276                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          256812577                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.876982                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.234768                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                157598366     61.35%     61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29238251     11.38%     72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14077167      5.48%     78.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55962761     21.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                157563978     61.35%     61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29227624     11.38%     72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14070468      5.48%     78.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55950507     21.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            256876545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.178398                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.701922                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78017085                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             107782223                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64633482                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3841952                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2601803                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422699                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486058                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157446500                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3690202                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2601803                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83861883                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10277178                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74822964                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62634848                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              22677869                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146804130                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                949467                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                441862                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  64017                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  17858                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               19908152                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150492299                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678751292                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164435882                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10966                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141814735                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8677561                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2844686                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2648369                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13872312                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26410080                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21300681                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1687720                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2166938                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143540852                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2119167                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143328298                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            272168                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8409052                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14689564                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125312                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     256876545                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.557966                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.879925                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            256812577                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.178327                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.702033                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77991094                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             107772330                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64608850                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3840943                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2599360                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422500                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485951                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157387425                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3689294                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2599360                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83831420                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10325294                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74929297                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62613486                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              22513720                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146758942                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                947731                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                441861                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  64728                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18116                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               19773665                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150448126                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678536041                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164391886                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10952                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141768145                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8679978                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2842610                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2646257                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13861181                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26401367                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21296245                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1688204                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2197018                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143495141                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2119201                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143282260                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            272024                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8407927                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14689646                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125355                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     256812577                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.557925                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.879880                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           168573864     65.62%     65.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45206232     17.60%     83.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31980064     12.45%     95.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10303635      4.01%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              812717      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           168546355     65.63%     65.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45160300     17.58%     83.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32009606     12.46%     95.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10282549      4.00%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813734      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -775,44 +772,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       256876545                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       256812577                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7356620     32.59%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     33      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5633879     24.95%     57.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9585743     42.46%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7349115     32.77%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     31      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5633990     25.12%     57.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9444813     42.11%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96002656     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114517      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95970305     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114498      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -836,101 +833,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8586      0.01%     67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8584      0.01%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26193106     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21007096     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26184358     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21002178     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143328298                       # Type of FU issued
-system.cpu.iq.rate                           0.544758                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22576275                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157514                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          566346237                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154074171                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140211060                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35347                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13216                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              143282260                       # Type of FU issued
+system.cpu.iq.rate                           0.544767                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22427949                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156530                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          566041717                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         154027392                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140167901                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35353                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13184                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11430                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165879208                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23028                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323617                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165684822                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23050                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323667                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1493976                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1493736                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          505                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18357                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       705133                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18344                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       705002                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87833                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6849                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87759                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6780                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2601803                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  997477                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                311742                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145861072                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2599360                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  993976                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                306451                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145815403                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26410080                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21300681                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1095001                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17866                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                276819                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18357                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317506                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471434                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788940                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142382517                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25789725                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            873528                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26401367                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21296245                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1095018                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17939                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                271517                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18344                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317394                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471153                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               788547                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142337327                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25781702                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            872174                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        201053                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46667574                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26530134                       # Number of branches executed
-system.cpu.iew.exec_stores                   20877849                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.541163                       # Inst execution rate
-system.cpu.iew.wb_sent                      141996041                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140222490                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63271750                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95823649                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        201061                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46654499                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26517785                       # Number of branches executed
+system.cpu.iew.exec_stores                   20872797                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.541174                       # Inst execution rate
+system.cpu.iew.wb_sent                      141950761                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140179331                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63256602                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95788019                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.532954                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660294                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.532969                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660381                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7612502                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1993855                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755483                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    253938585                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.541099                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.141491                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7614067                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1993846                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755141                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    253876624                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.541055                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.141749                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    180469459     71.07%     71.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43296577     17.05%     88.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15470824      6.09%     94.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4378580      1.72%     95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6397908      2.52%     98.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1648304      0.65%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       799189      0.31%     99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       418335      0.16%     99.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1059409      0.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    180454723     71.08%     71.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43255238     17.04%     88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15471181      6.09%     94.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4380130      1.73%     95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6364867      2.51%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1673276      0.66%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       800938      0.32%     99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       418318      0.16%     99.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1057953      0.42%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    253938585                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113305988                       # Number of instructions committed
-system.cpu.commit.committedOps              137405868                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    253876624                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113269928                       # Number of instructions committed
+system.cpu.commit.committedOps              137361316                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45511652                       # Number of memory references committed
-system.cpu.commit.loads                      24916104                       # Number of loads committed
-system.cpu.commit.membars                      814017                       # Number of memory barriers committed
-system.cpu.commit.branches                   26045610                       # Number of branches committed
+system.cpu.commit.refs                       45498874                       # Number of memory references committed
+system.cpu.commit.loads                      24907631                       # Number of loads committed
+system.cpu.commit.membars                      814016                       # Number of memory barriers committed
+system.cpu.commit.branches                   26032948                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120229462                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4892502                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120189151                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4888294                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91772138     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          113493      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91740391     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          113468      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -954,489 +951,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8585      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8583      0.01%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24916104     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20595548     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24907631     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20591243     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137405868                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1059409                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    375672050                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292972268                       # The number of ROB writes
-system.cpu.timesIdled                          891577                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6227961                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5392127867                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113151083                       # Number of Instructions Simulated
-system.cpu.committedOps                     137250963                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.325250                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.325250                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.430061                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.430061                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155826636                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88633022                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9606                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137361316                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1057953                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    375595727                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292884314                       # The number of ROB writes
+system.cpu.timesIdled                          891951                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6203191                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5392076833                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113115023                       # Number of Instructions Simulated
+system.cpu.committedOps                     137206411                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.325206                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.325206                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.430069                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.430069                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155781292                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88602574                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9590                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502981881                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53178096                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               334359649                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1519760                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            839617                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.954240                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40126369                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            840129                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.762152                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         270754250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.954240                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999911                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
+system.cpu.cc_regfile_reads                 502823667                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53168068                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               334407132                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1519751                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            839265                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.954798                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40095385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839777                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.745276                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         267431500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.954798                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999912                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999912                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179354797                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179354797                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23316087                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23316087                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15561026                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15561026                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345829                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345829                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441066                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441066                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       459481                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       459481                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38877113                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38877113                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39222942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39222942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       705718                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        705718                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3595150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3595150                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177438                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177438                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26862                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26862                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179307579                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179307579                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23304230                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23304230                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15542006                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15542006                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345703                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345703                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441081                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441081                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       459484                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       459484                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38846236                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38846236                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39191939                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39191939                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       710133                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        710133                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3609878                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3609878                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177558                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177558                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26867                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26867                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4300868                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4300868                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4478306                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4478306                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10273111663                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10273111663                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149502808344                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    365521996                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    365521996                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4320011                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4320011                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4497569                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4497569                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  10292232000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  10292232000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148465108677                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    365302500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    365302500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       209000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       209000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 159775920007                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 159775920007                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 159775920007                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 159775920007                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24021805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24021805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19156176                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19156176                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523267                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523267                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467928                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       467928                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       459486                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       459486                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43177981                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43177981                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43701248                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43701248                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029378                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029378                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.187676                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.187676                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339096                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339096                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057406                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057406                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 158757340677                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 158757340677                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 158757340677                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 158757340677                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24014363                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24014363                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19151884                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19151884                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523261                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523261                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467948                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       467948                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       459489                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       459489                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43166247                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43166247                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43689508                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43689508                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188487                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188487                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339330                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339330                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057414                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057414                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099608                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099608                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102475                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102475                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100078                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100078                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102944                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102944                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        41800                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        41800                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37149.691645                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35677.758511                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       582483                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36749.290841                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35298.478062                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       590707                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7397                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7439                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.745843                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.406775                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       696320                       # number of writebacks
-system.cpu.dcache.writebacks::total            696320                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291077                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       291077                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3294875                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3294875                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18482                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18482                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3585952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3585952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3585952                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3585952                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414641                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414641                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300275                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300275                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119609                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119609                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8380                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8380                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       696043                       # number of writebacks
+system.cpu.dcache.writebacks::total            696043                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295841                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295841                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3309634                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3309634                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18475                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18475                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3605475                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3605475                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3605475                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3605475                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414292                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414292                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300244                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300244                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119628                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119628                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8392                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8392                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       714916                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       714916                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       834525                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       834525                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714536                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714536                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       834164                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       834164                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5660697158                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5660697158                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13235281165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13235281165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1562991253                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1562991253                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    123125251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    123125251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       201500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       201500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18895978323                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18895978323                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20458969576                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  20458969576                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5831942750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5831942750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4511868951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4511868951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10343811701                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10343811701                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017261                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017261                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015675                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015675                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228581                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228581                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017909                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017909                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5857375000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5857375000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13373750471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13373750471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1627994000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1627994000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    128038500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    128038500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       204000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       204000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19231125471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  19231125471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20859119471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20859119471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5908113500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5908113500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4570874950                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4570874950                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10478988450                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10478988450                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017252                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017252                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015677                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015677                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228620                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228620                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017934                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017934                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016557                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016557                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019096                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019096                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        40300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        40300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016553                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016553                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019093                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019093                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        40800                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        40800                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1892540                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.345997                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64285030                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1893052                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.958407                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       13579028250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.345997                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998723                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998723                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1891955                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.348314                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64263909                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1892467                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.957744                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13555622500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.348314                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998727                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998727                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68160699                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68160699                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64285030                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64285030                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64285030                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64285030                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64285030                       # number of overall hits
-system.cpu.icache.overall_hits::total        64285030                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1982600                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1982600                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1982600                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1982600                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1982600                       # number of overall misses
-system.cpu.icache.overall_misses::total       1982600                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26922947970                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26922947970                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26922947970                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26922947970                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26922947970                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26922947970                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66267630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66267630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66267630                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66267630                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66267630                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66267630                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029918                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029918                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029918                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029918                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029918                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029918                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13579.616650                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13579.616650                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2392                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68141093                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68141093                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64263909                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64263909                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::cpu.inst     64263909                       # number of overall hits
+system.cpu.icache.overall_hits::total        64263909                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1984699                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1984699                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1984699                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1984699                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1984699                       # number of overall misses
+system.cpu.icache.overall_misses::total       1984699                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26888996997                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26888996997                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26888996997                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26888996997                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total  26888996997                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66248608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66248608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66248608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66248608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66248608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66248608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029958                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029958                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029958                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029958                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029958                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029958                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13548.148609                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13548.148609                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2508                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               125                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               127                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.136000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.748031                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        89529                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        89529                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        89529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        89529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        89529                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        89529                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1893071                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1893071                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1893071                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1893071                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1893071                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1893071                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3002                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3002                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3002                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3002                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  23219754000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  23219754000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  23219754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  23219754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  23219754000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  23219754000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    225366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    225366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    225366000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    225366000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028567                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028567                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        92212                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        92212                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        92212                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        92212                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        92212                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        92212                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1892487                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1892487                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1892487                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1892487                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1892487                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1892487                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3005                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3005                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3005                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3005                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24145787497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  24145787497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24145787497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  24145787497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24145787497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  24145787497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    225776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    225776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    225776500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    225776500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028566                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028566                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028566                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           103160                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65071.102218                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3020124                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           168359                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            17.938596                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           103023                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65070.034194                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5007824                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           168222                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            29.769138                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.936082                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.797931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5716.232619                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.751546                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000182                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    12.985449                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.797952                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5712.105601                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.749720                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000198                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.153913                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.087223                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992906                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.155769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.087160                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992890                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2920                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6837                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55246                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         28477722                       # Number of tag accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000375                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000375                       # miss rate for demand accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   350.973907                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1445,176 +1454,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        94866                       # number of writebacks
-system.cpu.l2cache.writebacks::total            94866                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          134                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        94881                       # number of writebacks
+system.cpu.l2cache.writebacks::total            94881                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           22                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           22                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          111                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          111                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          134                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          111                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          133                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          134                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          111                       # number of overall MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19963                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        14214                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        34205                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2720                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2720                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total           28                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2721                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       140540                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       140540                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       140423                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       140423                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19922                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19922                       # number of ReadCleanReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19963                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19963                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total       174745                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3002                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34129                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3002                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3005                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61713                       # number of overall MSHR uncacheable misses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     48397220                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5395669750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5577501750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4151610000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4151610000                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9547279750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9729111750                       # number of overall MSHR uncacheable cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1634500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519024000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5707237500                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771104000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9959317500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026201                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013659                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986938                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986938                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000408                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986942                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986942                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.472180                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.472180                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.471836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.471836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010527                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026255                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026255                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.184198                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.062368                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.184161                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062341                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.184198                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.062368                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.184161                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062341                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2564424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2564404                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128192                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2563081                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       696320                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36268                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       827115                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1997055                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297641                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3792109                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2499777                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32094                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       131034                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6455014                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121202208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98530845                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224204                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          220007633                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       62589                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3624998                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.036134                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.186622                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2762                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297610                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297610                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1892487                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5643819                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2634611                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32016                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8441090                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121164944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98490717                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219930061                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      201613                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5797948                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.046562                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.210699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3494014     96.39%     96.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             130984      3.61%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5527984     95.34%     95.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             269964      4.66%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3624998                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2504368734                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5797948                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3520857499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       322500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2847443747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2842352755                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1338896897                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1306164667                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19507738                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19466986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75011458                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74632435                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1705,23 +1725,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198816983                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187477456                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36845510                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                1.000480                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000222                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         252520633000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.000480                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062530                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062530                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         252500924000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000222                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062514                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062514                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1729,49 +1749,49 @@ system.iocache.tags.tag_accesses               328113                       # Nu
 system.iocache.tags.data_accesses              328113                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          233                       # number of overall misses
 system.iocache.overall_misses::total              233                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28780877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28780877                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6657450596                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6657450596                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28780877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28780877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28780877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28780877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28674877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28674877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4272498579                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4272498579                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28674877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28674877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28674877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28674877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123523.077253                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123523.077253                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123523.077253                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123523.077253                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123523.077253                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22928                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123068.141631                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123068.141631                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123068.141631                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123068.141631                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123068.141631                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.562106                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1779,88 +1799,90 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16449877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16449877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4773782616                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4773782616                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16449877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16449877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16449877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16449877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17024877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17024877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2461298579                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2461298579                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17024877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17024877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17024877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17024877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70600.330472                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70600.330472                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 73068.141631                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 73068.141631                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               68567                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68566                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68549                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::Writeback            131056                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4579                       # Transaction distribution
+system.membus.trans_dist::Writeback            131071                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8154                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4580                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4581                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138681                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138681                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4582                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138564                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138564                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34418                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       465382                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       572946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108886                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108886                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 681832                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       473273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       580837                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 689735                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17186044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17349437                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21984893                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17178284                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17341677                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19658797                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              497                       # Total snoops (count)
-system.membus.snoop_fanout::samples            406751                       # Request fanout histogram
+system.membus.snoop_fanout::samples            414951                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  406751    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  414951    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              406751                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83856500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              414951                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83605000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1725500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1746000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1057992643                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           911806448                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1020413671                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1019741659                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37506490                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64533936                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 22d20f171..51ea3fd8c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.625378                       # Number of seconds simulated
-sim_ticks                                2625378187500                       # Number of ticks simulated
-final_tick                               2625378187500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.625395                       # Number of seconds simulated
+sim_ticks                                2625394935000                       # Number of ticks simulated
+final_tick                               2625394935000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105357                       # Simulator instruction rate (inst/s)
-host_op_rate                                   127837                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2300779000                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 602544                       # Number of bytes of host memory used
-host_seconds                                  1141.08                       # Real time elapsed on the host
-sim_insts                                   120220550                       # Number of instructions simulated
-sim_ops                                     145872273                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  95356                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115687                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2080724894                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 655064                       # Number of bytes of host memory used
+host_seconds                                  1261.77                       # Real time elapsed on the host
+sim_insts                                   120317196                       # Number of instructions simulated
+sim_ops                                     145970023                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         1728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1156128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1193576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8234944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           336832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           657616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       605504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1152320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1224232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8325184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           318816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           736276                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       690624                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12188376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1156128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       336832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1492960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8634432                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12451228                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1152320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       318816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1471136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9003520                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8651996                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           27                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             20310                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19170                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       128671                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5329                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10295                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         9461                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           9021084                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           25                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             20252                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             19649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       130081                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5049                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11525                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        10791                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                193295                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          134913                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                197406                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          140680                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               139304                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           658                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              440366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              454630                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3136670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              128298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              250484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       230635                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               145071                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           171                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              438913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              466304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3171022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              121435                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              280444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       263055                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4642522                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         440366                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         128298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             568665                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3288834                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4742611                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         438913                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         121435                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             560348                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3429396                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6675                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3295524                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3288834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             440366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             461305                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3136670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             128298                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             250500                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       230635                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3436086                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3429396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             438913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             472979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3171022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          244                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             121435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             280459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       263055                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7938046                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        193296                       # Number of read requests accepted
-system.physmem.writeReqs                       175528                       # Number of write requests accepted
-system.physmem.readBursts                      193296                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     175528                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12362624                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9724800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12188440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10970332                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23562                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          14506                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12287                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11514                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12472                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12180                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14590                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12444                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12518                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12466                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11679                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12089                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11915                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11053                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11299                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11450                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11880                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11330                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9713                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9189                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10054                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9647                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9435                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9608                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10036                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9866                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9192                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9471                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9539                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9209                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9294                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9108                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9699                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8890                       # Per bank write bursts
+system.physmem.bw_total::total                8178698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197407                       # Number of read requests accepted
+system.physmem.writeReqs                       145071                       # Number of write requests accepted
+system.physmem.readBursts                      197407                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     145071                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12624448                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9033728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12451292                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9021084                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          50333                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12702                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12398                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12869                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12803                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14881                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12147                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12755                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12276                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11968                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12044                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11861                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11195                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11579                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12354                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11791                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11634                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9169                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9145                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9512                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9193                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8772                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8759                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9221                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8821                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8638                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8679                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8601                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8338                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8547                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8875                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8631                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8251                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          46                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2625377925000                       # Total gap between requests
+system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2625394672500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     550                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    3082                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  189636                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  193742                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 171137                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     58646                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     70721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     16311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7467                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6266                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5177                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4683                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      309                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 140680                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     60453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     70781                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     16881                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12152                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8838                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7520                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6581                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4952                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1308                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      972                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      775                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      324                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      266                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,158 +188,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    11356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2519                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1075                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        87477                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      252.493341                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     140.519371                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     314.341475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45925     52.50%     52.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16983     19.41%     71.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5819      6.65%     78.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3357      3.84%     82.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2775      3.17%     85.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1460      1.67%     87.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          948      1.08%     88.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          995      1.14%     89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9215     10.53%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          87477                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6395                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.205629                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      580.308341                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6393     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6395                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6395                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.760751                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.753987                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       37.694415                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            6028     94.26%     94.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              95      1.49%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              28      0.44%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              10      0.16%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              24      0.38%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             40      0.63%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            30      0.47%     97.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            13      0.20%     98.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            18      0.28%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             5      0.08%     98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            23      0.36%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            21      0.33%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             7      0.11%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             3      0.05%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.03%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             5      0.08%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.05%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.03%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             3      0.05%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             7      0.11%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             6      0.09%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            11      0.17%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             2      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6395                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6824061250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10445923750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    965830000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35327.45                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    10182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9787                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9902                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    11207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7930                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        90794                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      238.541225                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     134.856216                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     301.373578                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          48956     53.92%     53.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17750     19.55%     73.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6013      6.62%     80.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3452      3.80%     83.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2808      3.09%     86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1564      1.72%     88.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          893      0.98%     89.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          995      1.10%     90.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8363      9.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          90794                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7077                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.872686                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      551.008017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7075     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7077                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7077                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.945175                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.553311                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.579174                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5904     83.43%     83.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             368      5.20%     88.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             217      3.07%     91.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              59      0.83%     92.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              82      1.16%     93.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             159      2.25%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.35%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.17%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              13      0.18%     96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.16%     96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              10      0.14%     96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.08%     97.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             165      2.33%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.08%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               6      0.08%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.04%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.14%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             5      0.07%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7077                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6986626052                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10685194802                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    986285000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       35418.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54077.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.70                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.64                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  54168.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.44                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.74                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.24                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     161531                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96107                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.62                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  63.24                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7118240.48                       # Average gap between requests
-system.physmem.pageHitRate                      74.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  340124400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  185583750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 783673800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                502511040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           171476769360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            74898468540                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1509525073500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1757712204390                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.508799                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2511124862587                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     87667060000                       # Time in different power states
+system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     164764                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82850                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                      7665878.31                       # Average gap between requests
+system.physmem.pageHitRate                      73.17                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  357081480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  194836125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 802081800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                470396160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           171477786480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            75099546585                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1509358032750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1757759761380                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.522942                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2510844795677                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     87667580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     26583898663                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     26879018073                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  321201720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  175258875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 723013200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                482124960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           171476769360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74441693340                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1509925753500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1757545814955                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.445422                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2511799542258                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     87667060000                       # Time in different power states
+system.physmem_1.actEnergy                  329321160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179689125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 736515000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                444268800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           171477786480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            74435410800                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1509940608000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1757543599365                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.440607                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2511823665901                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     87667580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     25911565742                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     25903669599                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
@@ -365,15 +366,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               22612465                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14651481                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           907853                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            13732961                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               10133003                       # Number of BTB hits
+system.cpu0.branchPred.lookups               51763361                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         23412597                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           921572                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            31250401                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               23297364                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.786003                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3723828                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29274                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            74.550608                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15315613                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             29376                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -404,80 +405,80 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    61748                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               61748                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        23984                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18764                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        19000                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        42748                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   436.289417                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  2694.039371                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        41732     97.62%     97.62% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          726      1.70%     99.32% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          177      0.41%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767           77      0.18%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           11      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           19      0.04%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        42748                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        15024                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean  8664.869276                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  7136.607726                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7119.581025                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383        14229     94.71%     94.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          745      4.96%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           26      0.17%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455           16      0.11%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        15024                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  87051634064                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.443285                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.503059                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  87007241564     99.95%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     33256500      0.04%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5      5843000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      2996500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9       874000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11       581000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       581000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15       249500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  87051634064                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5088     77.48%     77.48% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1479     22.52%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6567                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        61748                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    63347                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               63347                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        24259                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18763                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        20325                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        43022                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   472.792990                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  2838.942862                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        41882     97.35%     97.35% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          877      2.04%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          115      0.27%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          113      0.26%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959            6      0.01%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           23      0.05%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        43022                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        16160                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean  9833.168317                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  8304.443400                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6846.428458                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383        15169     93.87%     93.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          911      5.64%     99.50% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151           54      0.33%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            3      0.02%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687           20      0.12%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        16160                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  95658285656                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.461466                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.505385                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  95607533656     99.95%     99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     37952000      0.04%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      6012000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      3722000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      1321500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11       760000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       604000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15       360500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17        20000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  95658285656                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5176     77.00%     77.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1546     23.00%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6722                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        63347                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        61748                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6567                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        63347                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6722                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6567                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        68315                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6722                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        70069                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    16748968                       # DTB read hits
-system.cpu0.dtb.read_misses                     52995                       # DTB read misses
-system.cpu0.dtb.write_hits                   13907664                       # DTB write hits
-system.cpu0.dtb.write_misses                     8753                       # DTB write misses
+system.cpu0.dtb.read_hits                    22737235                       # DTB read hits
+system.cpu0.dtb.read_misses                     54172                       # DTB read misses
+system.cpu0.dtb.write_hits                   16921500                       # DTB write hits
+system.cpu0.dtb.write_misses                     9175                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3489                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                       88                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2047                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3524                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      141                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1882                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      843                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16801963                       # DTB read accesses
-system.cpu0.dtb.write_accesses               13916417                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      854                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                22791407                       # DTB read accesses
+system.cpu0.dtb.write_accesses               16930675                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         30656632                       # DTB hits
-system.cpu0.dtb.misses                          61748                       # DTB misses
-system.cpu0.dtb.accesses                     30718380                       # DTB accesses
+system.cpu0.dtb.hits                         39658735                       # DTB hits
+system.cpu0.dtb.misses                          63347                       # DTB misses
+system.cpu0.dtb.accesses                     39722082                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,56 +508,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     9874                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                9874                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3715                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6056                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          103                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         9771                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   366.390339                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  1951.164851                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9421     96.42%     96.42% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          224      2.29%     98.71% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287           80      0.82%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           17      0.17%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479           13      0.13%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575            5      0.05%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            6      0.06%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         9771                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2691                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean  9965.812709                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  8554.132900                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5681.325139                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191         1024     38.05%     38.05% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1554     57.75%     95.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575           43      1.60%     97.40% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           63      2.34%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959            4      0.15%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.07%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2691                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  18106130328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.976227                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.152552                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      430953000      2.38%      2.38% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    17674714828     97.62%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         401500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          61000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  18106130328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2271     87.75%     87.75% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          317     12.25%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    10275                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               10275                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4076                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6085                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          114                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10161                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   480.267690                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2390.213266                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9738     95.84%     95.84% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          133      1.31%     97.15% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          215      2.12%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           37      0.36%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479            9      0.09%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           15      0.15%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767            3      0.03%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            4      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::45056-49151            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10161                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2702                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6204.580963                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          871     32.24%     32.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1681     62.21%     94.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575           53      1.96%     96.41% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           85      3.15%     99.56% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            7      0.26%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2702                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  22643799124                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.979659                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.141451                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      461404000      2.04%      2.04% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    22181693124     97.96%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         593000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         109000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  22643799124                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2268     87.64%     87.64% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          320     12.36%    100.00% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         9874                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         9874                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10275                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10275                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2588                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        12462                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    35678798                       # ITB inst hits
-system.cpu0.itb.inst_misses                      9874                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin::total        12863                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    70928349                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10275                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -565,1020 +572,1041 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2368                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2365                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1932                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1936                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                35688672                       # ITB inst accesses
-system.cpu0.itb.hits                         35678798                       # DTB hits
-system.cpu0.itb.misses                           9874                       # DTB misses
-system.cpu0.itb.accesses                     35688672                       # DTB accesses
-system.cpu0.numCycles                       121733824                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                70938624                       # ITB inst accesses
+system.cpu0.itb.hits                         70928349                       # DTB hits
+system.cpu0.itb.misses                          10275                       # DTB misses
+system.cpu0.itb.accesses                     70938624                       # DTB accesses
+system.cpu0.numCycles                       192976868                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          17621783                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     106366119                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   22612465                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          13856831                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     98711813                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2650530                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    130938                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               54154                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       345087                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       416739                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        73296                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 35679429                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               256075                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   4180                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         118679075                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.081251                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.263308                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          19363908                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     190332929                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   51763361                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          38612977                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    166709106                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5608958                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    145099                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               54692                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       348676                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       420281                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles        85262                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 70928958                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               257958                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   4691                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         189931503                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.225932                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.310916                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                59721044     50.32%     50.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                20146281     16.98%     67.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 8259650      6.96%     74.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                30552100     25.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                88125904     46.40%     46.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                29232702     15.39%     61.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14108338      7.43%     69.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                58464559     30.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           118679075                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.185753                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.873760                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                18470879                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             55646585                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 38814384                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4744194                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1003033                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             2910392                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               326287                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             104430369                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3709386                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1003033                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                23916141                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               11897059                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      33727750                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 37986661                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10148431                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              99624170                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts               979348                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1380369                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                148421                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 51935                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6127142                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          103189966                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            455330287                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       114159594                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9381                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             92428419                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                10761544                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1188796                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1051388                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 11830283                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            17680232                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           15386939                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1636462                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2175060                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  96814528                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1636038                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 95024919                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           451413                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        8911325                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     20849804                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        116309                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    118679075                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.800688                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.033122                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           189931503                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.268236                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.986299                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                24608865                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            101406874                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 56677604                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4757932                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2480228                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             2944179                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               328448                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             148845488                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3759445                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2480228                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                33020653                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               11928133                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      79389996                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 52895431                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10217062                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             132354164                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1007004                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1382043                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                149840                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 52195                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               6188026                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          135879963                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            611395498                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       146969281                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             9373                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            124973310                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                10906650                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2656416                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2518561                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 22027855                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            23660512                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           18424443                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1639164                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2432445                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 129487187                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1661777                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                127665829                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           454854                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10484678                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     21309646                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        116701                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    189931503                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.672168                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.963951                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           65546472     55.23%     55.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           22156727     18.67%     73.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           21116341     17.79%     91.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            8802658      7.42%     99.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1056849      0.89%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 28      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          116041258     61.10%     61.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           32572628     17.15%     78.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           29941917     15.76%     94.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           10293469      5.42%     99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1082195      0.57%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 36      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      118679075                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      189931503                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                8808229     40.49%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   130      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5336848     24.53%     65.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              7610455     34.98%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               10298963     43.90%     43.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   129      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5415712     23.09%     66.99% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              7742693     33.01%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2272      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             62565826     65.84%     65.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               87588      0.09%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          7159      0.01%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     65.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            17417081     18.33%     84.27% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           14944992     15.73%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             86175456     67.50%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              106512      0.08%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          7179      0.01%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            23410232     18.34%     85.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           17964178     14.07%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              95024919                       # Type of FU issued
-system.cpu0.iq.rate                          0.780596                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   21755662                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228947                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         330903688                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        107369307                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     93061278                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              32300                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11278                       # Number of floating instruction queue writes
+system.cpu0.iq.FU_type_0::total             127665829                       # Type of FU issued
+system.cpu0.iq.rate                          0.661560                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   23457497                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.183741                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         469142790                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        141641253                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    124187141                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              32722                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             11272                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses         9724                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             116757282                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  21027                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          347087                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.int_alu_accesses             151099696                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  21358                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          349091                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1857425                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2513                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        18755                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       953252                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1883461                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2555                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18950                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       972383                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       101364                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       327888                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       113459                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       340118                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1003033                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1539075                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               172884                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           98621711                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2480228                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1536268                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               176000                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          131320075                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             17680232                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            15386939                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            849096                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 24467                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               126834                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         18755                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        265533                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       373430                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              638963                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             94008948                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             16992930                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           954343                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             23660512                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            18424443                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            851631                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 24928                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               129599                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18950                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        275041                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       375413                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              650454                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            126634007                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             22982824                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           968597                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       171145                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    31760151                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                15805524                       # Number of branches executed
-system.cpu0.iew.exec_stores                  14767221                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.772250                       # Inst execution rate
-system.cpu0.iew.wb_sent                      93501427                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     93071002                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 48393961                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 79995949                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       171111                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    40767921                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                24572908                       # Number of branches executed
+system.cpu0.iew.exec_stores                  17785097                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.656213                       # Inst execution rate
+system.cpu0.iew.wb_sent                     126104266                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    124196865                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 63208416                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                102222094                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.764545                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.604955                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.643584                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.618344                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        7948634                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1519729                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           585621                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    117035605                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.766100                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.480781                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        9488534                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1545076                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           597321                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    186809549                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.646573                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.344397                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     75174289     64.23%     64.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     23319780     19.93%     84.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      7849886      6.71%     90.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3044520      2.60%     93.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      3180912      2.72%     96.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      1406827      1.20%     97.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1102407      0.94%     98.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       520278      0.44%     98.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1436706      1.23%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    128903317     69.00%     69.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     31993486     17.13%     86.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12242174      6.55%     92.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3077822      1.65%     94.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4650551      2.49%     96.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2601023      1.39%     98.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1367878      0.73%     98.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       526295      0.28%     99.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1447003      0.77%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    117035605                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            74499569                       # Number of instructions committed
-system.cpu0.commit.committedOps              89660931                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    186809549                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            99693903                       # Number of instructions committed
+system.cpu0.commit.committedOps             120785976                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      30256494                       # Number of memory references committed
-system.cpu0.commit.loads                     15822807                       # Number of loads committed
-system.cpu0.commit.membars                     627513                       # Number of memory barriers committed
-system.cpu0.commit.branches                  15208996                       # Number of branches committed
+system.cpu0.commit.refs                      39229111                       # Number of memory references committed
+system.cpu0.commit.loads                     21777051                       # Number of loads committed
+system.cpu0.commit.membars                     629182                       # Number of memory barriers committed
+system.cpu0.commit.branches                  23976855                       # Number of branches committed
 system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 77458658                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             1847857                       # Number of function calls committed.
+system.cpu0.commit.int_insts                105625598                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4749745                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        59311896     66.15%     66.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          85382      0.10%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         7159      0.01%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       15822807     17.65%     83.90% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      14433687     16.10%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        81445291     67.43%     67.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         104395      0.09%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         7179      0.01%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       21777051     18.03%     85.55% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      17452060     14.45%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         89660931                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1436706                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   209187674                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  196861250                       # The number of ROB writes
-system.cpu0.timesIdled                         121559                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3054749                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5129022957                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   74377875                       # Number of Instructions Simulated
-system.cpu0.committedOps                     89539237                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.636694                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.636694                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.610988                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.610988                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               104549028                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               56469550                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8161                       # number of floating regfile reads
+system.cpu0.commit.op_class_0::total        120785976                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1447003                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   292572702                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  263669539                       # The number of ROB writes
+system.cpu0.timesIdled                         123127                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3045365                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5057813082                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   99572209                       # Number of Instructions Simulated
+system.cpu0.committedOps                    120664282                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.938060                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.938060                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.515980                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.515980                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               137228019                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               78727155                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     8192                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                331224109                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                38421528                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              166953922                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1191250                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           674914                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          486.328727                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           27281228                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           675426                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            40.391143                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        277646000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   486.328727                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949861                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.949861                       # Average percentage of cache occupancy
+system.cpu0.cc_regfile_reads                446969794                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                47254034                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              263157526                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1194331                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           673421                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          483.801587                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           36230548                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           673933                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            53.759866                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        274448500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.801587                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.944925                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.944925                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         60112887                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        60112887                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     14700771                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       14700771                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     11392924                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      11392924                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       295732                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       295732                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       354072                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       354072                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       350987                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       350987                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     26093695                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        26093695                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     26389427                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       26389427                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       607182                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       607182                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1803068                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1803068                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141599                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       141599                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24346                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        24346                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21181                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21181                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2410250                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2410250                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2551849                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2551849                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8154354688                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8154354688                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  26135736531                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  26135736531                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    384171142                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    384171142                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    484170513                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    484170513                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       824000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       824000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  34290091219                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  34290091219                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  34290091219                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  34290091219                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15307953                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     15307953                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13195992                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13195992                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       437331                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       437331                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       378418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       372168                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       372168                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     28503945                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     28503945                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     28941276                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     28941276                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039664                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.039664                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136638                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.136638                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323780                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323780                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064336                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064336                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056912                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056912                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084558                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084558                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088173                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.088173                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         78023145                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        78023145                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     20647656                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       20647656                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     14394101                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      14394101                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       296444                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       296444                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       354739                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       354739                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       351671                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       351671                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     35041757                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        35041757                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     35338201                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       35338201                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       609728                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       609728                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1806132                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1806132                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141710                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       141710                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24359                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        24359                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21165                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        21165                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2415860                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2415860                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2557570                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2557570                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8120126000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   8120126000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  26313440366                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  26313440366                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    385463000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    385463000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    480627500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    480627500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       430000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       430000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  34433566366                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  34433566366                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  34433566366                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  34433566366                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     21257384                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     21257384                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     16200233                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     16200233                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438154                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       438154                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379098                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       379098                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       372836                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       372836                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     37457617                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     37457617                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     37895771                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     37895771                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028683                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.028683                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.111488                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.111488                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323425                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323425                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064255                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064255                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056768                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056768                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.064496                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.064496                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067490                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.067490                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          781                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      3670700                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               43                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         191761                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.162791                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    19.142057                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          747                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      3913122                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               47                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         192454                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.893617                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    20.332765                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       492000                       # number of writebacks
-system.cpu0.dcache.writebacks::total           492000                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       239081                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       239081                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1490741                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1490741                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18153                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18153                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1729822                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1729822                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1729822                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1729822                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       368101                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       368101                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312327                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312327                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        98325                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        98325                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6193                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6193                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21181                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21181                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       680428                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       680428                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       778753                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       778753                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17965                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17965                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16714                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16714                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34679                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34679                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4128121038                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4128121038                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5207818329                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5207818329                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1570971031                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1570971031                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     91940502                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     91940502                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    451443987                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    451443987                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       794000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       794000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9335939367                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9335939367                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10906910398                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10906910398                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3693380750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3693380750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2688166013                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2688166013                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6381546763                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6381546763                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023668                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023668                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224830                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224830                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016366                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016366                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056912                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056912                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023871                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023871                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026908                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026908                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       491417                       # number of writebacks
+system.cpu0.dcache.writebacks::total           491417                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       243049                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       243049                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1494093                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1494093                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18165                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18165                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1737142                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1737142                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1737142                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1737142                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       366679                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       366679                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312039                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       312039                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        98387                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        98387                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6194                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6194                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21165                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        21165                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       678718                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       678718                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       777105                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       777105                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29394                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29394                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26127                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26127                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55521                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55521                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4291687500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4291687500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5394914387                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5394914387                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1614083000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1614083000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96183500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96183500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459474500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459474500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       418000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       418000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9686601887                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9686601887                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11300684887                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11300684887                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5681056500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5681056500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4312326500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4312326500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9993383000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9993383000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017249                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017249                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019261                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019261                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224549                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224549                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016339                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016339                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056768                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056768                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018120                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018120                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020506                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020506                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1200530                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.748320                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           34431245                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1201042                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            28.667811                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6414143250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.748320                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999508                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999508                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1208444                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.748718                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           69666115                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1208956                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            57.625021                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6421480000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.748718                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999509                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999509                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          148                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          147                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         72552920                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        72552920                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34431245                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34431245                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34431245                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34431245                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34431245                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34431245                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1244682                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1244682                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1244682                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1244682                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1244682                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1244682                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12221339030                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12221339030                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12221339030                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12221339030                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12221339030                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12221339030                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     35675927                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     35675927                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     35675927                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     35675927                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     35675927                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     35675927                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034889                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.034889                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034889                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.034889                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034889                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.034889                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9818.844516                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9818.844516                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9818.844516                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9818.844516                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9818.844516                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9818.844516                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1349229                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          432                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           105227                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.822080                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    39.272727                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        143059850                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       143059850                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     69666115                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       69666115                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     69666115                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        69666115                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     69666115                       # number of overall hits
+system.cpu0.icache.overall_hits::total       69666115                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1259322                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1259322                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1259322                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1259322                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1259322                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1259322                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12306647041                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  12306647041                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  12306647041                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  12306647041                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  12306647041                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  12306647041                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     70925437                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     70925437                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     70925437                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     70925437                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     70925437                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     70925437                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.017756                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.017756                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.017756                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.017756                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.017756                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.017756                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9772.438694                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9772.438694                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9772.438694                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9772.438694                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9772.438694                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9772.438694                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1459740                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          453                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           110714                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.184782                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    45.300000                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43614                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43614                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        43614                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43614                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        43614                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43614                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1201068                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1201068                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1201068                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1201068                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1201068                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1201068                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3002                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3002                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3002                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3002                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10504795288                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10504795288                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10504795288                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10504795288                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10504795288                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10504795288                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    265434748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    265434748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    265434748                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    265434748                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033666                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033666                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033666                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.033666                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033666                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.033666                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8746.211945                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8746.211945                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8746.211945                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8746.211945                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8746.211945                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8746.211945                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        50344                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        50344                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        50344                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        50344                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        50344                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        50344                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1208978                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1208978                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1208978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1208978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1208978                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1208978                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11179466333                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11179466333                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11179466333                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11179466333                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11179466333                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11179466333                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    265874998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    265874998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    265874998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    265874998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017046                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017046                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017046                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9247.038683                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9247.038683                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9247.038683                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1764126                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1768652                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         4013                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1763942                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1769107                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         4567                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       220332                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          264213                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16022.712569                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2093032                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          280442                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.463333                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       220637                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          266650                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16052.098762                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3449668                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          282876                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           12.194983                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  9357.549400                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.830885                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.990255                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3887.194071                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1642.708300                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1121.439658                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.571139                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000783                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000060                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.237255                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.100263                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068447                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.977949                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1027                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15194                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          304                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          426                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          258                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          450                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4677                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7327                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2684                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062683                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927368                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        41624222                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       41624222                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        49855                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        11685                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1152127                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       374018                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1587685                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       491993                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       491993                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28477                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28477                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1602                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1602                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       210193                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       210193                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        49855                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        11685                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1152127                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       584211                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1797878                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        49855                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        11685                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1152127                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       584211                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1797878                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          397                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          143                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        48926                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        98504                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       147970                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            2                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27483                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27483                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19577                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19577                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        46426                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        46426                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          397                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          143                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        48926                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       144930                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       194396                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          397                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          143                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        48926                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       144930                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       194396                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     10907493                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3478500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2401346947                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2853426397                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   5269159337                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    505786782                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    505786782                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    394596383                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    394596383                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       773499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       773499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2617489063                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2617489063                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     10907493                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3478500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2401346947                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5470915460                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   7886648400                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     10907493                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3478500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2401346947                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5470915460                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   7886648400                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        50252                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        11828                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1201053                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       472522                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      1735655                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       491995                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       491995                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55960                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55960                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21179                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        21179                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       256619                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       256619                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        50252                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        11828                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1201053                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       729141                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1992274                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        50252                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        11828                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1201053                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       729141                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1992274                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007900                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.012090                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040736                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.208464                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.085253                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000004                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000004                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.491119                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.491119                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.924359                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.924359                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks  9287.877050                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    13.757624                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.215297                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4106.053527                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1602.376504                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1041.818760                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.566887                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000840                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000013                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.250614                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.097801                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.063588                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.979742                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1056                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15158                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           44                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          321                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          415                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          276                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4651                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7186                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2852                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.064453                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000732                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.925171                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        63497786                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       63497786                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        50315                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12479                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         62794                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       491416                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       491416                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28453                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28453                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1608                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1608                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       210730                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       210730                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1158323                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1158323                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       372689                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.489587                       # miss rate for UpgradeReq accesses
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-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.180914                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.180914                       # miss rate for ReadExReq accesses
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-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.012090                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040736                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.198768                       # miss rate for demand accesses
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-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.198768                       # miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559                       # average ReadReq miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112                       # average SCUpgradeReq miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          227                       # number of cycles access was blocked
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+system.cpu0.l2cache.blocked_cycles::no_mshrs          236                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               7                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    32.428571                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    29.500000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       192333                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          192333                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       193260                       # number of writebacks
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-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5918                       # number of ReadExReq MSHR hits
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 system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
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-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6652                       # number of demand (read+write) MSHR hits
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-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27483                       # number of UpgradeReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17965                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        20967                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16714                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16714                       # number of WriteReq MSHR uncacheable
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-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15030655008                       # number of HardPFReq MSHR miss cycles
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-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    535907154                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    292472580                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    292472580                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       643499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       643499                       # number of SCUpgradeFailReq MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      8304499                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  20890949936                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    241524750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3549350250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3790875000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2559965955                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6109316205                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6350840955                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007880                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012005                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.040711                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.206911                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.084812                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000004                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000004                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6767                       # number of overall MSHR hits
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+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    299483497                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       327000                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2120543999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2120543999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2210587998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2210587998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      8479500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2120543999                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3858788498                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  21219940139                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    243342000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5445807000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5689149000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4113464958                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4113464958                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    243342000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9559271958                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9802613958                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009324                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.491119                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.491119                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.924359                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.924359                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.489587                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.489587                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.924022                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.924022                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.157853                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.157853                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007880                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.012005                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040711                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.189645                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.094220                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007880                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.012005                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040711                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.189645                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.155023                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.155023                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041863                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.207494                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.207494                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.188995                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.094366                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.188995                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.210579                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.210631                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       327000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       327000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1907833                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1820754                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31055                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16714                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       491995                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       299768                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36263                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        92116                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43624                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114864                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           34                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       284068                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       270286                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2408123                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2274201                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        27655                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       111764                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4821743                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     76915296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82255660                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        47312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       201008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         159419276                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     687931                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3186793                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.203876                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.402878                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        116134                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1839025                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31035                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        26127                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       864426                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1492254                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       304971                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        91775                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43512                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114568                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       284553                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       270414                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1208978                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       592867                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3608808                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2486821                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        28899                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       112519                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6237047                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     77421632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82196692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50612                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       202936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         159871872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1179844                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      5097277                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.224281                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.417108                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2537081     79.61%     79.61% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2            649712     20.39%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           3954053     77.57%     77.57% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1143224     22.43%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3186793                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1807599924                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       5097277                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2520550941                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    112679999                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    112317000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1808718407                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1816757420                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1166698241                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1173564387                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     15837483                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     16253983                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     61547958                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     61816936                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               35319894                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         12619407                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           374072                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            19615876                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               15617711                       # Number of BTB hits
+system.cpu1.branchPred.lookups                6152669                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3868120                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           360109                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             3337115                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                2452438                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            79.617709                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               12648833                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             10709                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.489766                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                1042883                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             10537                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1608,89 +1636,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    24259                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               24259                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        11332                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6025                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         6902                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        17357                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   400.040330                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  2564.899375                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        16829     96.96%     96.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          181      1.04%     98.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          173      1.00%     99.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           71      0.41%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           28      0.16%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575            5      0.03%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671           45      0.26%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767            6      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863           14      0.08%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    24322                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               24322                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        11233                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5990                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         7099                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        17223                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   438.425361                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  2740.461547                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        16689     96.90%     96.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          124      0.72%     97.62% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          219      1.27%     98.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           86      0.50%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           20      0.12%     99.51% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           13      0.08%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671           39      0.23%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           13      0.08%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863           16      0.09%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        17357                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5295                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean  9383.568650                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  7860.112601                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8293.617199                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767         5259     99.32%     99.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535           29      0.55%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303            3      0.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607            3      0.06%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5295                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  69596834880                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.389063                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.490087                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    42554298056     61.14%     61.14% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    27024786824     38.83%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       11219000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        3252000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4         913000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         701500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6         719000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         299000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8          99500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9         182000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         50000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         63500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12        106500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13         34000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14         15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15         96000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  69596834880                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1939     74.63%     74.63% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          659     25.37%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2598                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        24259                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        17223                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5609                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  8674.966878                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6379.427582                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         2437     43.45%     43.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2571     45.84%     89.29% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          453      8.08%     97.36% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          115      2.05%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959            3      0.05%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           25      0.45%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303            4      0.07%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         5609                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  69613371380                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.373428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.487046                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    43658416792     62.72%     62.72% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    25935559588     37.26%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       12091000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        3523500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4        1046500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         593000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         908500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         323500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8         151000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9         143500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         80500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         88500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12        153000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         38000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14         28000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        226500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  69613371380                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1968     73.85%     73.85% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          697     26.15%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2665                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        24322                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        24259                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2598                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        24322                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2665                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2598                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        26857                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2665                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        26987                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    11166498                       # DTB read hits
-system.cpu1.dtb.read_misses                     21069                       # DTB read misses
-system.cpu1.dtb.write_hits                    7306223                       # DTB write hits
-system.cpu1.dtb.write_misses                     3190                       # DTB write misses
+system.cpu1.dtb.read_hits                     5224196                       # DTB read hits
+system.cpu1.dtb.read_misses                     21002                       # DTB read misses
+system.cpu1.dtb.write_hits                    4300766                       # DTB write hits
+system.cpu1.dtb.write_misses                     3320                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2022                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       70                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   623                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2043                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       67                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   616                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      374                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                11187567                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7309413                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      364                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 5245198                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4304086                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         18472721                       # DTB hits
-system.cpu1.dtb.misses                          24259                       # DTB misses
-system.cpu1.dtb.accesses                     18496980                       # DTB accesses
+system.cpu1.dtb.hits                          9524962                       # DTB hits
+system.cpu1.dtb.misses                          24322                       # DTB misses
+system.cpu1.dtb.accesses                      9549284                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1720,63 +1750,58 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     6817                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6817                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4075                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2679                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore           63                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6754                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   138.510512                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  1194.021921                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-2047         6631     98.18%     98.18% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::2048-4095           35      0.52%     98.70% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-6143           28      0.41%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::6144-8191           28      0.41%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-10239           11      0.16%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::10240-12287            8      0.12%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-14335            4      0.06%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::14336-16383            2      0.03%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-22527            2      0.03%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::22528-24575            2      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-26623            2      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::26624-28671            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6754                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1229                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean  9949.958503                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  8666.714001                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5833.930601                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095          208     16.92%     16.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          175     14.24%     31.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          520     42.31%     73.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          258     20.99%     94.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           10      0.81%     95.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            3      0.24%     95.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           30      2.44%     97.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           16      1.30%     99.27% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            2      0.16%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.41%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.08%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1229                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  18026373328                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.989122                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.103762                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0      196149764      1.09%      1.09% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    17830158064     98.91%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2          65500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  18026373328                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          995     85.33%     85.33% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          171     14.67%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1166                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     6842                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                6842                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4094                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2680                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore           68                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         6774                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   241.142604                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1918.263476                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         6651     98.18%     98.18% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           49      0.72%     98.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           35      0.52%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383           15      0.22%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            5      0.07%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575           10      0.15%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            5      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-32767            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-53247            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         6774                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1233                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9875.363796                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6280.061079                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          357     28.95%     28.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383          797     64.64%     93.59% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575           18      1.46%     95.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           48      3.89%     98.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959            5      0.41%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            7      0.57%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1233                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  18042065828                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.988332                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.107619                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      210878764      1.17%      1.17% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    17830879064     98.83%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         267500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3          19000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          21500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  18042065828                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          995     85.41%     85.41% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          170     14.59%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1165                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6817                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6817                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6842                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6842                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1166                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1166                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         7983                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    45723303                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6817                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1165                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1165                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         8007                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    10488200                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6842                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1785,1005 +1810,1037 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1199                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1196                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      537                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      530                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                45730120                       # ITB inst accesses
-system.cpu1.itb.hits                         45723303                       # DTB hits
-system.cpu1.itb.misses                           6817                       # DTB misses
-system.cpu1.itb.accesses                     45730120                       # DTB accesses
-system.cpu1.numCycles                       113567718                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                10495042                       # ITB inst accesses
+system.cpu1.itb.hits                         10488200                       # DTB hits
+system.cpu1.itb.misses                           6842                       # DTB misses
+system.cpu1.itb.accesses                     10495042                       # DTB accesses
+system.cpu1.numCycles                        43023242                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          11092326                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     115445294                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   35319894                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          28266544                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     98824380                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3951464                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     84431                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               39920                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       219438                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       325443                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        27387                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 45722696                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               133886                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2307                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         112589057                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.268755                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.334526                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           9545006                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      31536140                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    6152669                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           3495321                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     31308638                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 988880                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     91081                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               40105                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       214294                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       338691                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        30719                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 10487595                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               131638                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2429                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          42062974                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.911933                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.224898                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                52059388     46.24%     46.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                15346880     13.63%     59.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 8047278      7.15%     67.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                37135511     32.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                24350235     57.89%     57.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 6287044     14.95%     72.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2205515      5.24%     78.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 9220180     21.92%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           112589057                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.311003                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.016533                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                14201102                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             65884249                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 29361473                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1323272                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1818961                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              906595                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               159892                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              74422628                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1448245                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1818961                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                18946447                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2582249                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      60294532                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 25904145                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              3042723                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              61245605                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               312742                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               326990                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 51393                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 18938                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1837973                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           61569183                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            287884146                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        65513638                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1660                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             58022651                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 3546532                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1914472                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1838523                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 13613893                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            11512865                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            7756589                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           697877                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          945772                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  60208856                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             646860                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 59677362                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           148586                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        4522679                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      7282133                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         53722                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    112589057                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.530046                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.866401                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            42062974                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.143008                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.733002                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 8267663                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             20626897                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 11490517                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1337775                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                340122                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              874675                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               157334                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              30100708                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1379443                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                340122                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                10041900                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2603998                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      14921640                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 11019721                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              3135593                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              28621166                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               281517                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               330506                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 50454                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 20125                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1923436                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           29030542                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            132294985                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        32813170                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             1657                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             25609862                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 3420680                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            453393                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        375590                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  3438293                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             5562789                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            4719499                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           701110                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          705314                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  27634808                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             626900                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 27144127                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           143701                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2955966                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      6891737                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         53840                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     42062974                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.645321                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.965357                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           76211299     67.69%     67.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           17665370     15.69%     83.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           14473056     12.85%     96.23% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3891466      3.46%     99.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             347848      0.31%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                 18      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           26343154     62.63%     62.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            7337268     17.44%     80.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            5660550     13.46%     93.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            2402263      5.71%     99.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             319725      0.76%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                 14      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      112589057                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       42062974                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3478019     44.85%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   614      0.01%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1940620     25.03%     69.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              2334930     30.11%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1996325     32.40%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   609      0.01%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     32.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1885144     30.59%     63.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              2280359     37.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               67      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             40635841     68.09%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               52797      0.09%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4119      0.01%     68.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            11419177     19.13%     87.32% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7565361     12.68%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             17084879     62.94%     62.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               34880      0.13%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4083      0.02%     63.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     63.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     63.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             5473288     20.16%     83.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            4546930     16.75%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              59677362                       # Type of FU issued
-system.cpu1.iq.rate                          0.525478                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7754183                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.129935                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         239840869                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         65386915                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     57545759                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               5681                       # Number of floating instruction queue reads
+system.cpu1.iq.FU_type_0::total              27144127                       # Type of FU issued
+system.cpu1.iq.rate                          0.630918                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    6162437                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.227027                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         102651570                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         31226183                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     26510239                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               5796                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              67427880                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   3598                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          109848                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.int_alu_accesses              33302783                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   3714                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          106694                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       624171                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          851                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10604                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       419293                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       599497                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          782                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        10594                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       400513                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        57328                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        95447                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        46755                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        99859                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1818961                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 659321                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               119824                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           60910908                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                340122                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 663664                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               112730                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           28316728                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             11512865                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             7756589                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            325462                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 12815                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                97459                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10604                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         81282                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       152799                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              234081                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             59327650                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             11286961                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           325473                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              5562789                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             4719499                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            329074                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 12650                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                90576                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         10594                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         71921                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       150578                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              222499                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             26808358                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              5342958                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           311471                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        55192                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    18774109                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                12866831                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7487148                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.522399                       # Inst execution rate
-system.cpu1.iew.wb_sent                      59146208                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     57547543                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 28211344                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 43350974                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        55020                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     9813397                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 4108906                       # Number of branches executed
+system.cpu1.iew.exec_stores                   4470439                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.623113                       # Inst execution rate
+system.cpu1.iew.wb_sent                      26632744                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     26512023                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 13415515                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 21195279                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.506724                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.650766                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.616226                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.632948                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        4198450                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         593138                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           217301                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    110549070                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.509875                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.177384                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        2659330                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         573060                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           205791                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     41503303                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.610529                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.356545                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     82464476     74.60%     74.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     15679600     14.18%     88.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6499039      5.88%     94.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       896756      0.81%     95.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      2234307      2.02%     97.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      1661965      1.50%     98.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       498497      0.45%     99.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       155172      0.14%     99.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       459258      0.42%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     29410485     70.86%     70.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      7042051     16.97%     87.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2116509      5.10%     92.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       864843      2.08%     95.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       769424      1.85%     96.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       435639      1.05%     97.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       276731      0.67%     98.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       147889      0.36%     98.94% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       439732      1.06%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    110549070                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            45875888                       # Number of instructions committed
-system.cpu1.commit.committedOps              56366249                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     41503303                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            20778200                       # Number of instructions committed
+system.cpu1.commit.committedOps              25338954                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      18225990                       # Number of memory references committed
-system.cpu1.commit.loads                     10888694                       # Number of loads committed
-system.cpu1.commit.membars                     231720                       # Number of memory barriers committed
-system.cpu1.commit.branches                  12659864                       # Number of branches committed
+system.cpu1.commit.refs                       9282278                       # Number of memory references committed
+system.cpu1.commit.loads                      4963292                       # Number of loads committed
+system.cpu1.commit.membars                     229830                       # Number of memory barriers committed
+system.cpu1.commit.branches                   3902679                       # Number of branches committed
 system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 50354679                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             3453612                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 22267919                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              549742                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        38084418     67.57%     67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          51722      0.09%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4119      0.01%     67.67% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.67% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.67% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.67% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       10888694     19.32%     86.98% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       7337296     13.02%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        16018762     63.22%     63.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          33831      0.13%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     63.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4083      0.02%     63.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     63.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        4963292     19.59%     82.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       4318986     17.04%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         56366249                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               459258                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   150434096                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  123166009                       # The number of ROB writes
-system.cpu1.timesIdled                          67345                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         978661                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5136638072                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   45842675                       # Number of Instructions Simulated
-system.cpu1.committedOps                     56333036                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.477336                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.477336                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.403659                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.403659                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                62490093                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               39068646                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1381                       # number of floating regfile reads
+system.cpu1.commit.op_class_0::total         25338954                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               439732                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    67911551                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   56552827                       # The number of ROB writes
+system.cpu1.timesIdled                          67532                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         960268                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5207215501                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   20744987                       # Number of Instructions Simulated
+system.cpu1.committedOps                     25305741                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.073910                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.073910                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.482181                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.482181                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                29917814                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               16874088                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     1382                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                211116899                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                18233735                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              156287903                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                421035                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           227457                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          483.345523                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           17322126                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           227768                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            76.051623                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      89024511500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   483.345523                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.944034                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.944034                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu1.cc_regfile_reads                 95785070                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 9455596                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               60806398                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                422782                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           228231                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          478.409113                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            8403253                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           228545                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            36.768483                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     103444079500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   478.409113                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.934393                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.934393                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           29                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         36423981                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        36423981                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     10467087                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       10467087                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      6561195                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       6561195                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65021                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        65021                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88659                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88659                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80691                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80691                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     17028282                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        17028282                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     17093303                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       17093303                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       254533                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       254533                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       479063                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       479063                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35844                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        35844                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        19098                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        19098                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23509                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23509                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       733596                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        733596                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       769440                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       769440                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3958996431                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3958996431                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10579018157                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  10579018157                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    370185734                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    370185734                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    549251321                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    549251321                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       798500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       798500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  14538014588                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  14538014588                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  14538014588                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  14538014588                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     10721620                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     10721620                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7040258                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7040258                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       100865                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       100865                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       107757                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       107757                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       104200                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       104200                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     17761878                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     17761878                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     17862743                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     17862743                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023740                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023740                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.068046                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.068046                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.355366                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.355366                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.177232                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.177232                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225614                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225614                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.041302                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.041302                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043075                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043075                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.613281                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         18586968                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        18586968                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      4548259                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        4548259                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3563356                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3563356                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        63759                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        63759                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87271                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        87271                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79516                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        79516                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      8111615                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         8111615                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      8175374                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        8175374                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       254647                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       254647                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       480567                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       480567                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35928                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        35928                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        19211                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        19211                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23462                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23462                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       735214                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        735214                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       771142                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       771142                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4017153000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   4017153000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11025282924                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11025282924                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    376163500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    376163500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    545526500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    545526500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       528500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       528500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15042435924                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15042435924                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15042435924                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15042435924                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      4802906                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      4802906                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4043923                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4043923                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        99687                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        99687                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106482                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       106482                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102978                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       102978                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      8846829                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      8846829                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      8946516                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      8946516                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.053019                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.053019                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.118837                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.118837                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.360408                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.360408                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.180415                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.180415                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227835                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227835                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083105                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.083105                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.086195                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.086195                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          393                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1480475                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               42                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          48784                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.357143                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    30.347552                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          359                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1638919                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               40                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          49248                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.975000                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    33.278895                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       138868                       # number of writebacks
-system.cpu1.dcache.writebacks::total           138868                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        91268                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        91268                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       375164                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       375164                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13545                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13545                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       466432                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       466432                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       466432                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       466432                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       163265                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       163265                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103899                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       103899                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        32275                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        32275                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5553                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5553                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23509                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23509                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       267164                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       267164                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       299439                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       299439                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17059                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17059                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31400                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31400                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2133861458                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2133861458                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2484196176                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2484196176                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    503074190                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    503074190                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     95947255                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     95947255                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    512832179                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    512832179                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       777500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       777500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4618057634                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4618057634                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5121131824                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5121131824                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2900210250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2900210250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2419067503                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2419067503                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5319277753                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5319277753                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015228                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.015228                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014758                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014758                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.319982                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.319982                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225614                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225614                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.015041                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.015041                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016763                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.016763                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       137260                       # number of writebacks
+system.cpu1.dcache.writebacks::total           137260                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        91413                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        91413                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       375801                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       375801                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13808                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13808                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       467214                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       467214                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       467214                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       467214                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       163234                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       163234                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       104766                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       104766                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        32551                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        32551                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5403                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5403                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23462                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23462                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       268000                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       268000                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       300551                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       300551                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5603                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5603                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4908                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4908                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10511                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10511                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2247760000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2247760000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2639771935                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2639771935                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    542309000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    542309000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    101732500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    101732500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    522075500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    522075500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       517500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       517500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4887531935                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4887531935                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5429840935                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5429840935                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    989470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    989470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    857954500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    857954500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1847424500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1847424500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033987                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033987                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025907                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025907                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.326532                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.326532                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050741                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050741                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227835                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227835                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030293                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030293                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033594                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033594                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           671809                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.529348                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           45027049                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           672321                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            66.972546                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      78856865000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.529348                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973690                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973690                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           661426                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.525577                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            9800007                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           661938                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            14.805023                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      78861824000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.525577                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973683                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973683                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         92117192                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        92117192                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     45027049                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       45027049                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     45027049                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        45027049                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     45027049                       # number of overall hits
-system.cpu1.icache.overall_hits::total       45027049                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       695384                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       695384                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       695384                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        695384                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       695384                       # number of overall misses
-system.cpu1.icache.overall_misses::total       695384                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6371214084                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6371214084                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6371214084                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6371214084                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6371214084                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6371214084                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     45722433                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     45722433                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     45722433                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     45722433                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     45722433                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     45722433                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.015209                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.015209                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.015209                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.015209                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.015209                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.015209                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9162.152255                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9162.152255                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9162.152255                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9162.152255                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9162.152255                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9162.152255                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       596666                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            49414                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses         21636569                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        21636569                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      9800007                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        9800007                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      9800007                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         9800007                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      9800007                       # number of overall hits
+system.cpu1.icache.overall_hits::total        9800007                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       687303                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       687303                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       687303                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        687303                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       687303                       # number of overall misses
+system.cpu1.icache.overall_misses::total       687303                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6263235013                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6263235013                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6263235013                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6263235013                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6263235013                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6263235013                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     10487310                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     10487310                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     10487310                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     10487310                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     10487310                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     10487310                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.065537                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.065537                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.065537                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.065537                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.065537                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.065537                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9112.771242                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9112.771242                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9112.771242                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9112.771242                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9112.771242                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9112.771242                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       638996                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          564                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            53890                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.074837                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           27                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.857413                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          564                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        23058                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        23058                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        23058                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        23058                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        23058                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        23058                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       672326                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       672326                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       672326                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       672326                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       672326                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       672326                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          100                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total          100                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          100                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total          100                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5482686465                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5482686465                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5482686465                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5482686465                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5482686465                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5482686465                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8677000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8677000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8677000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8677000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014705                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014705                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014705                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014705                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014705                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014705                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8154.803570                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8154.803570                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8154.803570                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8154.803570                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8154.803570                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8154.803570                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        86770                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        86770                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        86770                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        86770                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        25354                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        25354                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        25354                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        25354                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        25354                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        25354                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       661949                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       661949                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       661949                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       661949                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       661949                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       661949                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5721508360                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5721508360                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5721508360                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5721508360                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5721508360                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5721508360                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8594000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8594000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8594000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8594000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.063119                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.063119                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.063119                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8643.427757                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8643.427757                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8643.427757                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       264317                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       265106                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          699                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       269622                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       270613                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          884                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        68110                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           61852                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15537.791452                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            937119                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           76426                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           12.261783                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        67787                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           66660                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15577.889137                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1655246                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           81265                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           20.368498                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6612.049075                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    15.719968                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.202712                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4939.798550                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2550.027939                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1417.993208                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.403567                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000959                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000134                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.301501                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.155641                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.086547                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.948352                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1249                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           36                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13289                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          878                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          355                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          462                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8497                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4330                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.076233                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002197                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.811096                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        18910778                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       18910778                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        19107                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7219                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       650283                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       128648                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        805257                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       138868                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       138868                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1925                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1925                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1050                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total         1050                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38271                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        38271                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        19107                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7219                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       650283                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       166919                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         843528                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        19107                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7219                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       650283                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       166919                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        843528                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          427                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          276                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst        22038                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        72420                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        95161                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29112                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29112                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22458                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22458                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks  6747.638156                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    12.637913                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.167789                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4673.355619                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2625.058292                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1517.031368                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.411843                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000771                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000132                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.285239                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.160221                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.092592                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.950799                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1291                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13290                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          868                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          406                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          470                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8605                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4215                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078796                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001465                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.811157                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        30536660                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       30536660                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        19077                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7323                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         26400                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       137259                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       137259                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2433                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2433                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1103                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total         1103                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38090                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        38090                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       639615                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       639615                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       127678                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       127678                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        19077                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7323                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       639615                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       165768                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         831783                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        19077                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7323                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       639615                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       165768                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        831783                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          431                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          286                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          717                       # number of ReadReq misses
+system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29127                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29127                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22358                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22358                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        35228                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        35228                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          427                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          276                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        22038                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       107648                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       130389                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          427                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          276                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        22038                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       107648                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       130389                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9785994                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5538750                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    913296236                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1683125409                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   2611746389                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    548231087                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    548231087                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449027944                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449027944                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       763500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       763500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1429440182                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1429440182                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9785994                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5538750                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    913296236                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3112565591                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4041186571                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9785994                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5538750                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    913296236                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3112565591                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4041186571                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        19534                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7495                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       672321                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data       201068                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       900418                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       138868                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       138868                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31037                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31037                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23508                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23508                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadExReq_misses::total        35752                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        22316                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        22316                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73485                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        73485                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          431                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          286                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::cpu1.data       109237                       # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          431                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          286                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        22316                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       109237                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       132270                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9445500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5864000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     15309500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    555921000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    555921000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449033000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449033000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       501000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       501000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1528833498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1528833498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    894673000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    894673000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1746677998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1746677998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9445500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5864000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    894673000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3275511496                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4185493996                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9445500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5864000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    894673000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3275511496                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4185493996                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        19508                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7609                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        27117                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       137260                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       137260                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31560                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        31560                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23461                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23461                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73499                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        73499                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        19534                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7495                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       672321                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       274567                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       973917                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        19534                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7495                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       672321                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       274567                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       973917                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021859                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.036825                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.032779                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.360177                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.105685                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.937977                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.937977                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.955334                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.955334                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73842                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        73842                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       661931                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       661931                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       201163                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       201163                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        19508                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7609                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       661931                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       275005                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       964053                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        19508                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7609                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       661931                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       275005                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       964053                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.026441                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000007                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000007                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.922909                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.922909                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.952986                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.952986                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.479299                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.479299                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021859                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.036825                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.032779                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.392065                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.133881                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021859                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.036825                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.032779                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.392065                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.133881                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       763500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       763500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           61                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.484169                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.484169                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.033713                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.033713                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.365301                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.365301                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.033713                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.397218                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.137202                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.033713                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.397218                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.137202                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       501000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       501000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          124                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    12.200000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    24.800000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        35144                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           35144                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.writebacks::writebacks        39050                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           39050                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           13                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst           16                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          141                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          171                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          736                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          736                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total           13                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          854                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          854                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           14                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          144                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          144                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           13                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           16                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          877                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          907                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           14                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          998                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1025                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           13                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           16                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          877                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          907                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          426                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          263                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        22022                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72279                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        94990                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        36425                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        36425                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29112                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29112                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22458                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22458                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           14                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          998                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1025                       # number of overall MSHR hits
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+system.cpu1.l2cache.ReadReq_mshr_misses::total          704                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3034                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         3034                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        37433                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        37433                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29127                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22358                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22358                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34492                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34492                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          426                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          263                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        22022                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       106771                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       129482                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          426                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          263                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        22022                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       106771                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total       165907                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          100                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17059                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17159                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          100                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31400                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31500                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6994000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3664750                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    767719764                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1208019590                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1986398104                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1404338548                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1404338548                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    484116716                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    484116716                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    336604833                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    336604833                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       672500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       672500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1121552915                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1121552915                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6994000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3664750                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    767719764                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2329572505                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3107951019                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6994000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3664750                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    767719764                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2329572505                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1404338548                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4512289567                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7885000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2763450750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2771335750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2311397498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2311397498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7885000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5074848248                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5082733248                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021808                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035090                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.032755                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.359475                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.105495                       # mshr miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        22302                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73341                       # number of ReadSharedReq MSHR misses
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+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         4908                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         4908                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10511                       # number of overall MSHR uncacheable misses
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+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of ReadReq MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10923000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1619868588                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1619868588                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    495927500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    495927500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    345361500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    345361500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       435000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       435000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1215520500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1215520500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    760109500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    760109500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1300287998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1300287998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4063500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    760109500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2515808498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3286840998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4063500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    760109500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2515808498                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1619868588                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4906709586                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7829000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    944359000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    952188000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    821025498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    821025498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7829000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1765384498                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1773213498                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025962                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000007                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000007                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.937977                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.937977                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.955334                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.955334                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.922909                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.922909                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.952986                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.952986                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.469285                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.469285                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021808                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.035090                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.032755                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.388870                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132950                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021808                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.035090                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.032755                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.388870                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.472604                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.472604                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033692                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.364585                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.364585                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.393589                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136139                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.393589                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.170350                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       672500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       672500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        78850                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        78850                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.174968                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       435000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       435000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1277963                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       964810                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        31055                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14341                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       138868                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        45574                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36263                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        76215                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43067                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89621                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           21                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           34                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        96319                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        79290                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1344847                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       942237                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        16928                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        42916                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2346928                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     43030144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29597157                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29980                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        78136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          72735417                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     628857                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1745350                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.328609                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.469708                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq         70770                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       942311                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        31035                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         4908                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       510267                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict       868505                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        48336                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        75730                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43006                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        89941                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        96740                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        79738                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       661949                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       536905                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1973224                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       988189                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17063                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        42721                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3021197                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     42365216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29405313                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        30436                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        78032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          71878997                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1156869                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2994555                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.368102                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.482289                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1171812     67.14%     67.14% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2            573538     32.86%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1892252     63.19%     63.19% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1102303     36.81%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1745350                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     748369465                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       2994555                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1102178989                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     88425999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     87567999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1009581341                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    993110829                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    468876167                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    449674318                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      9538553                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      9464978                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     23419937                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     23224976                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31011                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31011                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              23197                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59421                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -2874,23 +2931,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198987475                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187554438                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84715000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36777012                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.446991                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.446879                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         254817991000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.446991                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.902937                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.902937                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         254837974000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.446879                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.902930                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.902930                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2898,49 +2955,49 @@ system.iocache.tags.tag_accesses               328284                       # Nu
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32304877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32304877                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6652654586                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6652654586                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32304877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32304877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32304877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32304877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32277877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32277877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4275018561                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4275018561                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32277877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32277877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32277877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32277877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
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-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
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 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
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 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128193.956349                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128193.956349                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128193.956349                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128193.956349                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128193.956349                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22817                       # number of cycles access was blocked
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+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3477                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.562266                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2948,619 +3005,625 @@ system.iocache.writebacks::writebacks           36206                       # nu
 system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
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-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
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 system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19198877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19198877                       # number of ReadReq MSHR miss cycles
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78086.813492                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   130801                       # number of replacements
-system.l2c.tags.tagsinuse                64048.619051                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     351623                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   195125                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.802040                       # Average number of references to valid blocks.
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-system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.525676                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     2.048604                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5727.667382                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1961.871644                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.787095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.903255                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3571.469043                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1470.884658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3857.457480                       # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::total               227479                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data             820                       # number of UpgradeReq hits
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-system.l2c.demand_misses::cpu0.inst             17327                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             18842                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       128828                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           11                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5250                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10314                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         9461                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                190066                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           27                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            17327                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            18842                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       128828                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           11                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5250                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10314                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         9461                       # number of overall misses
-system.l2c.overall_misses::total               190066                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2599500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       443500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   1426835542                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    735252946                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  14338160773                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1206000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker        97250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    448103000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    186224591                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   1256067564                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    18394990666                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      7116778                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      2985907                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     10102685                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1350463                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1030967                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2381430                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1037256751                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    678589231                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1715845982                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      2599500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       443500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1426835542                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1772509697                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14338160773                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      1206000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        97250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    448103000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    864813822                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1256067564                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20110836648                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      2599500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       443500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1426835542                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1772509697                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14338160773                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      1206000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        97250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    448103000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    864813822                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1256067564                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20110836648                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker          196                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker           73                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst          48896                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data          53421                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       172025                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker           79                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker           34                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst          22022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          13143                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        16712                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             326601                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       227479                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           227479                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        11030                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4690                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           15720                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1175                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1266                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2441                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        14596                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10372                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            24968                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          196                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           73                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           48896                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           68017                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       172025                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           79                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           34                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           22022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           23515                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        16712                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              351569                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          196                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           73                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          48896                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          68017                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       172025                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           79                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           34                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          22022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          23515                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        16712                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             351569                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.137755                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.068493                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.354364                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.151963                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.139241                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.029412                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.238398                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.162672                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.524083                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.766546                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.825160                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.784033                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.782979                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.922591                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.855387                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.734722                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.788276                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.756969                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.137755                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.068493                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.354364                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.277019                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.139241                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.029412                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.238398                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.438614                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.540622                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.137755                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.068493                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.354364                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.277019                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.139241                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.029412                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.238398                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.438614                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.540622                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        88700                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        97250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 107468.718472                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   841.724187                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   771.552196                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   819.690467                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1467.894565                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   882.677226                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1140.531609                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90785.501693                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        88700                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        97250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 105809.753707                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        88700                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        97250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 105809.753707                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               234                       # number of cycles access was blocked
+system.l2c.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5063                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        28206                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.466110                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000412                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.514771                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5562101                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5562101                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          232311                       # number of Writeback hits
+system.l2c.Writeback_hits::total               232311                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            2454                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             792                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3246                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           247                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            65                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               312                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             3756                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1862                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5618                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          184                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           89                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        33340                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        45362                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        43171                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           54                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           50                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        17322                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        11995                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         7539                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           159106                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           184                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            89                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               33340                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               49118                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        43171                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker            54                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            50                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               17322                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               13857                       # number of demand (read+write) hits
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+system.l2c.UpgradeReq_misses::cpu1.data          3781                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12011                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          840                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total            1988                       # number of SCUpgradeReq misses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data      4088000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     11724500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1275500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       739500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2015000                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2203000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::total  18692667834                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      2203000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.dtb.walker       855000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::total     20537290834                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      2203000                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total    20537290834                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       232311                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           232311                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        10684                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4573                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::cpu0.data         1087                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::total          2300                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15025                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.demand_accesses::total              358911                       # number of demand (read+write) accesses
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+system.l2c.overall_accesses::total             358911                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.770311                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.826810                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.787245                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.772769                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.946414                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.864348                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.750017                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.829487                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.783465                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.341159                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.151049                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.222915                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171502                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.522155                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.341159                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.282509                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.222915                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.454406                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.541045                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.341159                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.282509                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.222915                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.454406                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.541045                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   927.885784                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1081.195451                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   976.146865                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1518.452381                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   644.163763                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1013.581489                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 90747.429527                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        88120                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        85500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        82750                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        88120                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        85500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        82750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 105760.379603                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        88120                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        85500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        82750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 105760.379603                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              1319                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       21                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           117                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     62.809524                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               98707                       # number of writebacks
-system.l2c.writebacks::total                    98707                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                17                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           27                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            5                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        17319                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         8118                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       128828                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           11                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5241                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         2138                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         9461                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          171149                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8455                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3870                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12325                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          920                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1168                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2088                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        10724                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8176                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         18900                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           27                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17319                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        18842                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128828                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           11                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5241                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10314                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         9461                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           190049                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           27                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            5                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        17319                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        18842                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       128828                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           11                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5241                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10314                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         9461                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          190049                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3002                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17965                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          100                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17055                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38122                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16714                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14341                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31055                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3002                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34679                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          100                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31396                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69177                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2258000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       380000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1209530708                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    633945550                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12753851063                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1069000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        84250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    381902000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    159442409                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1140236224                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  16282699204                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    150732427                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     68800353                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    219532780                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16443920                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     20736167                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     37180087                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    905183749                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    576557769                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1481741518                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2258000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       380000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1209530708                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1539129299                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12753851063                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1069000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        84250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    381902000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    736000178                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1140236224                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  17764440722                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2258000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       380000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1209530708                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1539129299                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12753851063                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1069000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        84250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    381902000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    736000178                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1140236224                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  17764440722                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    181479250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3198370250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5885000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2430251250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5815985750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2250411545                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2045879002                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4296290547                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    181479250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5448781795                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5885000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4476130252                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10112276297                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.137755                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.068493                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.354201                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.151963                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.139241                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.029412                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.237989                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.162672                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.524031                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.766546                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.825160                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.784033                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.782979                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.922591                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.855387                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.734722                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.788276                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.756969                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.137755                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.068493                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.354201                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.277019                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.139241                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.029412                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.237989                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.438614                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.540574                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.137755                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.068493                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.354201                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.277019                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748891                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.139241                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.029412                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.237989                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.438614                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.566120                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.540574                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        76000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        84250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        76000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        84250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 93472.950250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        76000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        84250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 93472.950250                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        58850                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst        58850                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115                       # average overall mshr uncacheable latency
+system.l2c.writebacks::writebacks              104474                       # number of writebacks
+system.l2c.writebacks::total                   104474                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           10                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
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+system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
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+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3781                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12011                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          840                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1148                       # number of SCUpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     78410000                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    189269500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4916712000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5992000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    843515500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    737586502                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8585972542                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1581102002                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10362336044                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.770311                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.826810                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.787245                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.772769                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.946414                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.864348                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.750017                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.829487                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.783465                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.151049                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171502                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.522110                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.282509                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.454406                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.541003                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.282509                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.454406                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.541003                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 95764.025369                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 95764.025369                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              209523                       # Transaction distribution
-system.membus.trans_dist::ReadResp             209522                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31055                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31055                       # Transaction distribution
-system.membus.trans_dist::Writeback            134913                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78034                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41651                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14508                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             38508                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18805                       # Transaction distribution
+system.membus.trans_dist::ReadReq               38100                       # Transaction distribution
+system.membus.trans_dist::ReadResp             212196                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31035                       # Transaction distribution
+system.membus.trans_dist::Writeback            140680                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16716                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            77066                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41581                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14111                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40212                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            20215                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174097                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14300                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       648289                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       770541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108921                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108921                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 879462                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14206                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       677829                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       799987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108934                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108934                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 908921                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162793                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18522228                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18713941                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4636480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4636480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23350421                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           125464                       # Total snoops (count)
-system.membus.snoop_fanout::samples            569969                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28412                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19154168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19345693                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21663837                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           125106                       # Total snoops (count)
+system.membus.snoop_fanout::samples            595969                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  569969    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  595969    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              569969                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81685500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              595969                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81639500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               28500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12047488                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11797490                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1135057072                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1030129184                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1127535962                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1147298884                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37496988                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64422049                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -3593,48 +3656,50 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             490298                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            490282                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31055                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31055                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           227479                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36263                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           81334                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         42004                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         123338                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           34                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           34                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50269                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50269                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side       990291                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       371073                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1361364                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     30980096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6355093                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               37335189                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          292587                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           958737                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.038087                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.191405                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              38103                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            495292                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31035                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31035                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           373006                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           88968                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           80200                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41893                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         122093                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       457205                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1082088                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       352339                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1434427                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31351112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6763093                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               38114205                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          462700                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1239270                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.168619                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.374415                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 922222     96.19%     96.19% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36515      3.81%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1030306     83.14%     83.14% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 208964     16.86%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             958737                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          763418418                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1239270                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          822017005                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           355500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         618495385                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         615196241                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         276060555                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         261600624                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2070                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    2069                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2756                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 9df34f531..a1c5aab40 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827616                       # Number of seconds simulated
-sim_ticks                                2827616186000                       # Number of ticks simulated
-final_tick                               2827616186000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827546                       # Number of seconds simulated
+sim_ticks                                2827546300000                       # Number of ticks simulated
+final_tick                               2827546300000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97479                       # Simulator instruction rate (inst/s)
-host_op_rate                                   118241                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2435971946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 621864                       # Number of bytes of host memory used
-host_seconds                                  1160.78                       # Real time elapsed on the host
-sim_insts                                   113151083                       # Number of instructions simulated
-sim_ops                                     137250963                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  98439                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119404                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2460684463                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625192                       # Number of bytes of host memory used
+host_seconds                                  1149.09                       # Real time elapsed on the host
+sim_insts                                   113115023                       # Number of instructions simulated
+sim_ops                                     137206411                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1325344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9769960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1322768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9763816                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11098056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1325344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1325344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8387584                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11089336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1322768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1322768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8388544                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8405108                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8406068                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             153176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22916                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             153080                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                176173                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131056                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                176039                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131071                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135437                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               135452                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            475                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3455193                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               467815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3453106                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3924881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2966309                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6197                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2972507                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2966309                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3921894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          467815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             467815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2966722                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6198                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2972920                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2966722                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           475                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3461391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              467815                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3459303                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6897387                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        176174                       # Number of read requests accepted
-system.physmem.writeReqs                       171661                       # Number of write requests accepted
-system.physmem.readBursts                      176174                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     171661                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11266304                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8832                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9457344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11098120                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10723444                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      138                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23861                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4579                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11334                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10890                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10732                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10393                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14045                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11531                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11498                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11674                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10645                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10993                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10307                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9597                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9956                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10908                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10689                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10844                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9257                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9346                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9336                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8962                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9705                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9746                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9125                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9630                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9307                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9634                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8942                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8449                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8881                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9361                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9018                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9072                       # Per bank write bursts
+system.physmem.bw_total::total                6894813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        176040                       # Number of read requests accepted
+system.physmem.writeReqs                       135452                       # Number of write requests accepted
+system.physmem.readBursts                      176040                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     135452                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11255936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10624                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8418624                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11089400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8406068                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      166                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3886                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40804                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11283                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10909                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10879                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10544                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14049                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11359                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11255                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11497                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10572                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11295                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10218                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9589                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9979                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10701                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10842                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10903                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8346                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8306                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8514                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8219                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8602                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8561                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8053                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8529                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8073                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8804                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7852                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7407                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7747                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8181                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8268                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8079                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          58                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827615975000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827546089000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    2994                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    2997                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  172624                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  172487                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 167280                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    154910                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     18105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       821                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131071                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    154804                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17996                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       828                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,161 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1002                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       87                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66219                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      312.955255                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.034234                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.173316                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24625     37.19%     37.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15873     23.97%     61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6865     10.37%     71.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3626      5.48%     77.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2732      4.13%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1677      2.53%     83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1136      1.72%     85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1168      1.76%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8517     12.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66219                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6252                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.154671                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      564.033809                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6251     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6252                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.635797                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.335011                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       41.227878                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5914     94.59%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              86      1.38%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              17      0.27%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              16      0.26%     96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              17      0.27%     96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             30      0.48%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            32      0.51%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            14      0.22%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            17      0.27%     98.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             6      0.10%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            22      0.35%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            18      0.29%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             7      0.11%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.02%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.02%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             6      0.10%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             4      0.06%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.06%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.05%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             5      0.08%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            16      0.26%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             2      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.05%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             3      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::752-767             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6252                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2104913750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5405588750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    880180000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11957.29                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65199                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      301.760702                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.342640                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.505125                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24507     37.59%     37.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15999     24.54%     62.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6852     10.51%     72.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3716      5.70%     78.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2634      4.04%     82.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1687      2.59%     84.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1128      1.73%     86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1089      1.67%     88.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7587     11.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65199                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6653                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.433789                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      560.061521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6652     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6653                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6653                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.771682                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.345316                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.497785                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5824     87.54%     87.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              71      1.07%     88.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             181      2.72%     91.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              53      0.80%     92.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              64      0.96%     93.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             178      2.68%     95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              29      0.44%     96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.09%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.14%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               9      0.14%     96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             170      2.56%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.06%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.09%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.12%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.17%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6653                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2123501000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5421138500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    879370000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12073.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30707.29                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30823.99                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145058                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    112529                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.14                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8129187.62                       # Average gap between requests
-system.physmem.pageHitRate                      79.54                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  260517600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  142147500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 718356600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                486693360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184686106800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            81488169855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1625088668250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1892870659965                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.422846                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2703351122494                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94420300000                       # Time in different power states
+system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144861                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97354                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9077427.64                       # Average gap between requests
+system.physmem.pageHitRate                      78.78                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  255989160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139676625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 715845000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                435002400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184681529760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            81048006450                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625432730750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892708780145                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.382186                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2703925000250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94417960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     29844456256                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29202842250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  240098040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  131005875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654716400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                470862720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184686106800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80123990850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1626285316500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1892592097185                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.324331                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2705354976994                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94420300000                       # Time in different power states
+system.physmem_1.actEnergy                  236915280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  129269250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 655964400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                417383280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184681529760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80055144540                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626303662250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892479868760                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.301228                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705388162750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94417960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27840895506                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27740163750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -333,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46937284                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24041936                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233234                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29553356                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21362007                       # Number of BTB hits
+system.cpu.branchPred.lookups                46902830                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24030897                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232795                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29532360                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21346058                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.282847                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11754741                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33891                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.280231                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11742213                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33846                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -372,84 +367,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     72371                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72371                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29709                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22637                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        20025                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52346                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   408.397967                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2384.163324                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        50769     96.99%     96.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          522      1.00%     97.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          392      0.75%     98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          322      0.62%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479          112      0.21%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          191      0.36%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767            8      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     72877                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72877                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29786                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22407                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        20684                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52193                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   427.193302                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2519.151181                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50372     96.51%     96.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          577      1.11%     97.62% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          541      1.04%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          349      0.67%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479           64      0.12%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          245      0.47%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671           20      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767            5      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::40960-45055            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52346                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9112.637070                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  7625.312992                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383        13355     74.20%     74.20% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767         4455     24.75%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-49151          181      1.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::49152-65535            5      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52193                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        18420                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9894.996282                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7919.116299                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383        13659     74.15%     74.15% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         4520     24.54%     98.69% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-49151          229      1.24%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::49152-65535            5      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 117490693224                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.629020                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.491115                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  117435257724     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37744500      0.03%     99.98% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7698500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6179000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1033000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       848500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1404000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       520500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 117490693224                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6498     81.61%     81.61% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1464     18.39%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7962                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72371                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total        18420                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 117420807224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.629573                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.491742                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  117361135224     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      40228000      0.03%     99.98% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8514000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6836000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1132500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       742000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       806000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 117420807224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6507     81.76%     81.76% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1452     18.24%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7959                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72877                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72371                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7962                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72877                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7959                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7962                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        80333                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7959                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80836                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25461869                       # DTB read hits
-system.cpu.dtb.read_misses                      62291                       # DTB read misses
-system.cpu.dtb.write_hits                    19915387                       # DTB write hits
-system.cpu.dtb.write_misses                     10080                       # DTB write misses
+system.cpu.dtb.read_hits                     25454298                       # DTB read hits
+system.cpu.dtb.read_misses                      62609                       # DTB read misses
+system.cpu.dtb.write_hits                    19910353                       # DTB write hits
+system.cpu.dtb.write_misses                     10268                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4354                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       348                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2290                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       354                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2301                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1335                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25524160                       # DTB read accesses
-system.cpu.dtb.write_accesses                19925467                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1336                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25516907                       # DTB read accesses
+system.cpu.dtb.write_accesses                19920621                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45377256                       # DTB hits
-system.cpu.dtb.misses                           72371                       # DTB misses
-system.cpu.dtb.accesses                      45449627                       # DTB accesses
+system.cpu.dtb.hits                          45364651                       # DTB hits
+system.cpu.dtb.misses                           72877                       # DTB misses
+system.cpu.dtb.accesses                      45437528                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -479,56 +476,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11974                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11974                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3948                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7776                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore          250                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11724                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   570.794951                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2803.545728                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-8191        11373     97.01%     97.01% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-16383          269      2.29%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-24575           71      0.61%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     11947                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11947                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3916                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7772                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          259                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11688                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   646.175565                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3062.873414                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        11278     96.49%     96.49% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          250      2.14%     98.63% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575          145      1.24%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767           11      0.09%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::40960-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::73728-81919            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11724                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12176.865046                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9546.126127                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7774.383636                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1294     36.16%     36.16% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383         1330     37.16%     73.32% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          901     25.17%     98.49% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::24576-32767           22      0.61%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-40959           25      0.70%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::40960-49151            5      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11688                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3588                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 13165.830546                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7878.482425                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1266     35.28%     35.28% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1353     37.71%     72.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          898     25.03%     98.02% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           28      0.78%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959           19      0.53%     99.33% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::40960-49151           22      0.61%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::81920-90111            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23001352712                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.973391                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.161136                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       612637000      2.66%      2.66% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     22388223712     97.33%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2          416000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           45500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4           30500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23001352712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         3588                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  22931465712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.972560                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.163591                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       629948000      2.75%      2.75% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     22300919212     97.25%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          517500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           46500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           34500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  22931465712                       # Table walker pending requests distribution
 system.cpu.itb.walker.walkPageSizes::4K          3007     90.33%     90.33% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::1M           322      9.67%    100.00% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::total         3329                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11974                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11974                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11947                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11947                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3329                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15303                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66270436                       # ITB inst hits
-system.cpu.itb.inst_misses                      11974                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin::total        15276                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66251443                       # ITB inst hits
+system.cpu.itb.inst_misses                      11947                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -537,98 +534,98 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3094                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2189                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2204                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66282410                       # ITB inst accesses
-system.cpu.itb.hits                          66270436                       # DTB hits
-system.cpu.itb.misses                           11974                       # DTB misses
-system.cpu.itb.accesses                      66282410                       # DTB accesses
-system.cpu.numCycles                        263104506                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66263390                       # ITB inst accesses
+system.cpu.itb.hits                          66251443                       # DTB hits
+system.cpu.itb.misses                           11947                       # DTB misses
+system.cpu.itb.accesses                      66263390                       # DTB accesses
+system.cpu.numCycles                        263015768                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104871759                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184678718                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46937284                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33116748                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     147875517                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6159108                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     184684                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 7836                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        337023                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       520063                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          109                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66270632                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1094853                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5249                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          256876545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.877001                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.234757                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104824855                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184645834                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46902830                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33088271                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     147851260                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6154028                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     194015                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8214                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        337761                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       519343                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66251613                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1117287                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5276                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          256812577                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.876982                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.234768                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                157598366     61.35%     61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29238251     11.38%     72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14077167      5.48%     78.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55962761     21.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                157563978     61.35%     61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29227624     11.38%     72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14070468      5.48%     78.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55950507     21.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            256876545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.178398                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.701922                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78017085                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             107782223                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64633482                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3841952                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2601803                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422699                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486058                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157446500                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3690202                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2601803                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83861883                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10277178                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74822964                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62634848                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              22677869                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146804130                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                949467                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                441862                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  64017                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  17858                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               19908152                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150492299                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678751292                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164435882                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10966                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141814735                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8677561                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2844686                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2648369                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13872312                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26410080                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21300681                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1687720                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2166938                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143540852                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2119167                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143328298                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            272168                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8409052                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14689564                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125312                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     256876545                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.557966                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.879925                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            256812577                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.178327                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.702033                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77991094                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             107772330                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64608850                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3840943                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2599360                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422500                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485951                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157387425                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3689294                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2599360                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83831420                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10325294                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74929297                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62613486                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              22513720                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146758942                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                947731                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                441861                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  64728                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18116                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               19773665                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150448126                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678536041                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164391886                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10952                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141768145                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8679978                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2842610                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2646257                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13861181                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26401367                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21296245                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1688204                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2197018                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143495141                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2119201                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143282260                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            272024                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8407927                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14689646                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125355                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     256812577                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.557925                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.879880                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           168573864     65.62%     65.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45206232     17.60%     83.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31980064     12.45%     95.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10303635      4.01%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              812717      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           168546355     65.63%     65.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45160300     17.58%     83.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32009606     12.46%     95.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10282549      4.00%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813734      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -636,44 +633,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       256876545                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       256812577                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7356620     32.59%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     33      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5633879     24.95%     57.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9585743     42.46%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7349115     32.77%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     31      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5633990     25.12%     57.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9444813     42.11%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96002656     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114517      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95970305     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114498      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -697,101 +694,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8586      0.01%     67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8584      0.01%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26193106     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21007096     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26184358     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21002178     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143328298                       # Type of FU issued
-system.cpu.iq.rate                           0.544758                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22576275                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157514                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          566346237                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154074171                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140211060                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35347                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13216                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              143282260                       # Type of FU issued
+system.cpu.iq.rate                           0.544767                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22427949                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156530                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          566041717                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         154027392                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140167901                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35353                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13184                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11430                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165879208                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23028                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323617                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165684822                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23050                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323667                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1493976                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1493736                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          505                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18357                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       705133                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18344                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       705002                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87833                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6849                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87759                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6780                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2601803                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  997477                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                311742                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145861072                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2599360                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  993976                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                306451                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145815403                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26410080                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21300681                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1095001                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17866                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                276819                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18357                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317506                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471434                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788940                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142382517                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25789725                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            873528                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26401367                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21296245                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1095018                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17939                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                271517                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18344                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317394                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471153                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               788547                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142337327                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25781702                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            872174                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        201053                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46667574                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26530134                       # Number of branches executed
-system.cpu.iew.exec_stores                   20877849                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.541163                       # Inst execution rate
-system.cpu.iew.wb_sent                      141996041                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140222490                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63271750                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95823649                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        201061                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46654499                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26517785                       # Number of branches executed
+system.cpu.iew.exec_stores                   20872797                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.541174                       # Inst execution rate
+system.cpu.iew.wb_sent                      141950761                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140179331                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63256602                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95788019                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.532954                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660294                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.532969                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660381                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7612502                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1993855                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755483                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    253938585                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.541099                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.141491                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7614067                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1993846                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755141                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    253876624                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.541055                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.141749                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    180469459     71.07%     71.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43296577     17.05%     88.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15470824      6.09%     94.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4378580      1.72%     95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6397908      2.52%     98.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1648304      0.65%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       799189      0.31%     99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       418335      0.16%     99.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1059409      0.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    180454723     71.08%     71.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43255238     17.04%     88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15471181      6.09%     94.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4380130      1.73%     95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6364867      2.51%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1673276      0.66%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       800938      0.32%     99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       418318      0.16%     99.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1057953      0.42%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    253938585                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113305988                       # Number of instructions committed
-system.cpu.commit.committedOps              137405868                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    253876624                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113269928                       # Number of instructions committed
+system.cpu.commit.committedOps              137361316                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45511652                       # Number of memory references committed
-system.cpu.commit.loads                      24916104                       # Number of loads committed
-system.cpu.commit.membars                      814017                       # Number of memory barriers committed
-system.cpu.commit.branches                   26045610                       # Number of branches committed
+system.cpu.commit.refs                       45498874                       # Number of memory references committed
+system.cpu.commit.loads                      24907631                       # Number of loads committed
+system.cpu.commit.membars                      814016                       # Number of memory barriers committed
+system.cpu.commit.branches                   26032948                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120229462                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4892502                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120189151                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4888294                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91772138     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          113493      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91740391     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          113468      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -815,489 +812,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8585      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8583      0.01%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24916104     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20595548     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24907631     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20591243     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137405868                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1059409                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    375672050                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292972268                       # The number of ROB writes
-system.cpu.timesIdled                          891577                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6227961                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5392127867                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113151083                       # Number of Instructions Simulated
-system.cpu.committedOps                     137250963                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.325250                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.325250                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.430061                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.430061                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155826636                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88633021                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9606                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137361316                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1057953                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    375595727                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292884314                       # The number of ROB writes
+system.cpu.timesIdled                          891951                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6203191                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5392076833                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113115023                       # Number of Instructions Simulated
+system.cpu.committedOps                     137206411                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.325206                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.325206                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.430069                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.430069                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155781292                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88602572                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9590                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502981878                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53178096                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               334359649                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1519760                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            839617                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.954240                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40126369                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            840129                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.762152                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         270754250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.954240                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999911                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
+system.cpu.cc_regfile_reads                 502823661                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53168068                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               334407132                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1519751                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            839265                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.954798                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40095385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839777                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.745276                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         267431500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.954798                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999912                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999912                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179354797                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179354797                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23316087                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23316087                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15561026                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15561026                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345829                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345829                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441066                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441066                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       459481                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       459481                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38877113                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38877113                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39222942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39222942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       705718                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        705718                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3595150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3595150                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177438                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177438                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26862                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26862                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179307579                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179307579                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23304230                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23304230                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15542006                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15542006                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345703                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345703                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441081                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441081                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       459484                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       459484                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38846236                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38846236                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39191939                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39191939                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       710133                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        710133                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3609878                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3609878                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177558                       # number of SoftPFReq misses
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+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26867                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26867                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4300868                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4300868                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4478306                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4478306                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10273111663                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10273111663                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149502808344                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    365521996                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    365521996                       # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_misses::total        4320011                       # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total       4497569                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  10292232000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  10292232000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148465108677                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    365302500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    365302500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       209000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       209000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 159775920007                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 159775920007                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 159775920007                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 159775920007                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24021805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24021805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19156176                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19156176                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523267                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523267                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467928                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       467928                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       459486                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       459486                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43177981                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43177981                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43701248                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43701248                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029378                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029378                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.187676                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.187676                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339096                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339096                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057406                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057406                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 158757340677                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 158757340677                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 158757340677                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 158757340677                       # number of overall miss cycles
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029571                       # miss rate for ReadReq accesses
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+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339330                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339330                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057414                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057414                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099608                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099608                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102475                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102475                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640                       # average LoadLockedReq miss latency
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 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        41800                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        41800                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37149.691645                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35677.758511                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       582483                       # number of cycles access was blocked
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+system.cpu.dcache.demand_avg_miss_latency::total 36749.290841                       # average overall miss latency
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+system.cpu.dcache.overall_avg_miss_latency::total 35298.478062                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       590707                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7397                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7439                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.745843                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.406775                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       696320                       # number of writebacks
-system.cpu.dcache.writebacks::total            696320                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291077                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       291077                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3294875                       # number of WriteReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18482                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3585952                       # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total      3585952                       # number of overall MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8380                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8380                       # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8392                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total       834525                       # number of overall MSHR misses
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 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5660697158                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5660697158                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13235281165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13235281165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1562991253                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1562991253                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    123125251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    123125251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       201500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       201500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18895978323                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18895978323                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20458969576                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  20458969576                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5831942750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5831942750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4511868951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4511868951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10343811701                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10343811701                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017261                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017261                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015675                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015675                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228581                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228581                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017909                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017909                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5857375000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5857375000                       # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1627994000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1627994000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    128038500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    128038500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       204000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       204000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19231125471                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total  20859119471                       # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5908113500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4570874950                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10478988450                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10478988450                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017252                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017252                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015677                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015677                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228620                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228620                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017934                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017934                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016557                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016557                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019096                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019096                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        40300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        40300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016553                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016553                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019093                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019093                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        40800                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        40800                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1892540                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.345997                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64285030                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1893052                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.958407                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       13579028250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.345997                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998723                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998723                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1891955                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.348314                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64263909                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1892467                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.957744                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13555622500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.348314                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998727                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998727                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68160699                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68160699                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64285030                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64285030                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64285030                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64285030                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64285030                       # number of overall hits
-system.cpu.icache.overall_hits::total        64285030                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1982600                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1982600                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1982600                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1982600                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1982600                       # number of overall misses
-system.cpu.icache.overall_misses::total       1982600                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26922947970                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26922947970                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26922947970                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26922947970                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26922947970                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26922947970                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66267630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66267630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66267630                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::cpu.inst     66267630                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66267630                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029918                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029918                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029918                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029918                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029918                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029918                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13579.616650                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13579.616650                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2392                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68141093                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68141093                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64263909                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64263909                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        64263909                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1984699                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total       1984699                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26888996997                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26888996997                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26888996997                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total  26888996997                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66248608                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     66248608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66248608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66248608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029958                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029958                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029958                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029958                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029958                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029958                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13548.148609                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13548.148609                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2508                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               125                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               127                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.136000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.748031                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        89529                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        89529                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        89529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        89529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        89529                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        89529                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1893071                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1893071                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1893071                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1893071                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1893071                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1893071                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3002                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3002                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3002                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3002                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  23219754000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  23219754000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  23219754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  23219754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  23219754000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  23219754000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    225366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    225366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    225366000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    225366000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028567                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028567                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028567                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        92212                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        92212                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        92212                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::total      1892487                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1892487                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total      1892487                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3005                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3005                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3005                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3005                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24145787497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  24145787497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24145787497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  24145787497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24145787497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  24145787497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    225776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    225776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    225776500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    225776500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028566                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028566                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028566                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028566                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           103160                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65071.102218                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3020124                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           168359                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            17.938596                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           103023                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65070.034194                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5007824                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           168222                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            29.769138                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.936082                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.797931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5716.232619                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.751546                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000182                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    12.985449                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.797952                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5712.105601                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.749720                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000198                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.153913                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.087223                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992906                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.155769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.087160                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992890                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2920                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6837                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55246                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         28477722                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        28477722                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        56030                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12587                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1873051                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       528182                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2469850                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       696320                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       696320                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2916                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6860                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55225                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000259                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994598                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         44376961                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        44376961                       # Number of data accesses
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+system.cpu.l2cache.ReadReq_hits::total          68572                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       696043                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       696043                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           36                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           36                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.overall_hits::cpu.data       685283                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2626951                       # number of overall hits
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 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::cpu.inst        19985                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total        34339                       # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total         2720                       # number of UpgradeReq misses
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       966469                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       966469                       # number of UpgradeReq miss cycles
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-system.cpu.l2cache.Writeback_accesses::total       696320                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       542189                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       542189                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        56044                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        12556                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1892453                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       839799                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2800852                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        56044                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        12556                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1892453                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       839799                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2800852                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000375                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000556                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010557                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026407                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.013713                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986938                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986938                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000558                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000408                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986942                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986942                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.472180                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.472180                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.471836                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.471836                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010539                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010539                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026459                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026459                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000375                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000556                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010557                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.184332                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.062416                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000558                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010539                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.184293                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.062389                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000375                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000556                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010557                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.184332                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.062416                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   355.319485                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   355.319485                       # average UpgradeReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000558                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010539                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::total     0.062389                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   350.973907                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   350.973907                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1306,176 +1315,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        94866                       # number of writebacks
-system.cpu.l2cache.writebacks::total            94866                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          134                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        94881                       # number of writebacks
+system.cpu.l2cache.writebacks::total            94881                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           22                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           22                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          111                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          111                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          134                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          111                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          133                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          134                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          111                       # number of overall MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19963                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        14214                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2720                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2720                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total           28                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       140540                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       140540                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       140423                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       140423                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14235                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3002                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34129                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3002                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3005                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61713                       # number of overall MSHR uncacheable misses
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10859200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12283992500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1634500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       509500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1422648500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10859200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12283992500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    188213500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519024000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5707237500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4252080000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4252080000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    188213500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771104000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9959317500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026201                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013659                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986938                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986938                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000408                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986942                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986942                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.472180                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.472180                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.471836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.471836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010527                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026255                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026255                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.184198                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.062368                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.184161                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062341                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000375                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010545                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.184198                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.062368                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       100250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000558                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010527                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.184161                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062341                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2564424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2564404                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128192                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2563081                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       696320                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36268                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       827115                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1997055                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297641                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3792109                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2499777                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32094                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       131034                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6455014                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121202208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98530845                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224204                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          220007633                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       62589                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3624998                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.036134                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.186622                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2762                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297610                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297610                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1892487                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5643819                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2634611                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32016                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8441090                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121164944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98490717                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219930061                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      201613                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5797948                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.046562                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.210699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3494014     96.39%     96.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             130984      3.61%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5527984     95.34%     95.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             269964      4.66%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3624998                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2504368734                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5797948                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3520857499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       322500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2847443747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2842352755                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1338896897                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1306164667                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19507738                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19466986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75011458                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74632435                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1566,23 +1586,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198816983                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187477456                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36845510                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                1.000480                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000222                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         252520633000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.000480                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062530                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062530                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         252500924000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000222                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062514                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062514                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1590,49 +1610,49 @@ system.iocache.tags.tag_accesses               328113                       # Nu
 system.iocache.tags.data_accesses              328113                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          233                       # number of overall misses
 system.iocache.overall_misses::total              233                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28780877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28780877                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6657450596                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6657450596                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28780877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28780877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28780877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28780877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28674877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28674877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4272498579                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4272498579                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28674877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28674877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28674877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28674877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123523.077253                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123523.077253                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123523.077253                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123523.077253                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123523.077253                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22928                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123068.141631                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123068.141631                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123068.141631                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123068.141631                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123068.141631                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.562106                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1640,88 +1660,90 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16449877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16449877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4773782616                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4773782616                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16449877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16449877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16449877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16449877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17024877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17024877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2461298579                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2461298579                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17024877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17024877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17024877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17024877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70600.330472                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70600.330472                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 73068.141631                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 73068.141631                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               68567                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68566                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68549                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::Writeback            131056                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4579                       # Transaction distribution
+system.membus.trans_dist::Writeback            131071                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8154                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4580                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4581                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138681                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138681                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4582                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138564                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138564                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34418                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       465382                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       572946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108886                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108886                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 681832                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       473273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       580837                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 689735                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17186044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17349437                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21984893                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17178284                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17341677                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19658797                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              497                       # Total snoops (count)
-system.membus.snoop_fanout::samples            406751                       # Request fanout histogram
+system.membus.snoop_fanout::samples            414951                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  406751    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  414951    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              406751                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83856500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              414951                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83605000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1725500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1746000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1057992643                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           911806448                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1020413671                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1019741659                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37506490                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64533936                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 3492b3590..22877557e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,154 +1,154 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.817778                       # Number of seconds simulated
-sim_ticks                                2817777605000                       # Number of ticks simulated
-final_tick                               2817777605000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.817750                       # Number of seconds simulated
+sim_ticks                                2817750443000                       # Number of ticks simulated
+final_tick                               2817750443000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 298084                       # Simulator instruction rate (inst/s)
-host_op_rate                                   361954                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6653597695                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 624156                       # Number of bytes of host memory used
-host_seconds                                   423.50                       # Real time elapsed on the host
-sim_insts                                   126237777                       # Number of instructions simulated
-sim_ops                                     153286368                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 301376                       # Simulator instruction rate (inst/s)
+host_op_rate                                   365951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6727532391                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 628096                       # Number of bytes of host memory used
+host_seconds                                   418.84                       # Real time elapsed on the host
+sim_insts                                   126227981                       # Number of instructions simulated
+sim_ops                                     153274395                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           655396                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4517280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           653732                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4510496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           125824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1063044                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         5888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           519744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          4071296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           124544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1058884                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         5696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           520896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          4080320                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10959816                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       655396                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       125824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       519744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1300964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8260864                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10955912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       653732                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       124544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       520896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1299172                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8264128                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8278388                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8281652                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             18694                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             71101                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             18668                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             70995                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1966                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           92                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              8121                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             63614                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16546                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           89                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              8139                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             63755                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180220                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          129076                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                180159                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          129127                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133457                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               133508                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            91                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              232593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1603136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              232005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1600744                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               44654                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              377263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          2090                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              184452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1444861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               44200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              375791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker          2021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              184862                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1448077                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3889525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         232593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          44654                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         184452                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             461699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2931695                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3888177                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         232005                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          44200                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         184862                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             461067                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2932881                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6216                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2937914                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2931695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2939101                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2932881                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           91                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             232593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1609352                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             232005                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1606960                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              44654                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             377266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         2090                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             184452                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1444861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              44200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             375793                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker         2021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             184862                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1448077                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6827439                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         90406                       # Number of read requests accepted
-system.physmem.writeReqs                        90720                       # Number of write requests accepted
-system.physmem.readBursts                       90406                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      90720                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5783616                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      2368                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4983552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5785924                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5805960                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       37                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   12831                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2411                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5941                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5711                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5475                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5399                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5366                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5838                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6281                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6483                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6268                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6346                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5330                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5015                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5399                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5276                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               4950                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5291                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4893                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4429                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4791                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4794                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4700                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5367                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5289                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5346                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5326                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5240                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4672                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4285                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5029                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5084                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4218                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4405                       # Per bank write bursts
+system.physmem.bw_total::total                6827277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         90477                       # Number of read requests accepted
+system.physmem.writeReqs                        65811                       # Number of write requests accepted
+system.physmem.readBursts                       90477                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      65811                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5784832                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4210432                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5790468                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4211784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          23137                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5834                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5704                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5463                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5405                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5372                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5837                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6284                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6486                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6223                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6339                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5440                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5142                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5381                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5279                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               4952                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5247                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4133                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                3840                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4117                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4118                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3952                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4415                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4512                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4650                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4383                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4609                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3956                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3578                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4192                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4199                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3505                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3629                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          38                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2816211460500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2816184296500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       1                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   90405                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   90476                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  90718                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     59525                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     27440                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2853                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       545                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  65809                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     59474                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     27494                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2874                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       538                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -175,7 +175,7 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        58                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        54                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        52                       # What write queue length does an incoming req see
@@ -185,164 +185,165 @@ system.physmem.wrQLenPdf::6                        51                       # Wh
 system.physmem.wrQLenPdf::7                        51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     3919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     3652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     3489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      105                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        33321                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      323.130758                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.789706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     346.993140                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12624     37.89%     37.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7779     23.35%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3018      9.06%     70.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1714      5.14%     75.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1413      4.24%     79.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          752      2.26%     81.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          537      1.61%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          554      1.66%     85.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4930     14.80%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          33321                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2995                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.170618                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      514.809638                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           2993     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     3853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4093                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        32481                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.722545                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.643491                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.464678                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12661     38.98%     38.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7717     23.76%     62.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2982      9.18%     71.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1687      5.19%     77.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1406      4.33%     81.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          745      2.29%     83.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          513      1.58%     85.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          495      1.52%     86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4275     13.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          32481                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3213                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.128852                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      487.877717                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3211     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2995                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2995                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.999332                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.796866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       47.448084                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               17      0.57%      0.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            2784     92.95%     93.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              41      1.37%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              11      0.37%     95.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               6      0.20%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              14      0.47%     95.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             11      0.37%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            12      0.40%     96.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             7      0.23%     96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            11      0.37%     97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             7      0.23%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            15      0.50%     98.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            14      0.47%     98.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             4      0.13%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             1      0.03%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.07%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             4      0.13%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.10%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             3      0.10%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             6      0.20%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             1      0.03%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             6      0.20%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             5      0.17%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.07%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.07%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.10%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2995                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1193098984                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2887517734                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    451845000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13202.53                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::26624-27647            1      0.03%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            3213                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3213                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.475568                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.644293                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.368139                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 6      0.19%      0.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 1      0.03%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.03%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               2      0.06%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            2703     84.13%     84.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              65      2.02%     86.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             109      3.39%     89.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              35      1.09%     90.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              33      1.03%     91.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             100      3.11%     95.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               9      0.28%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.09%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               4      0.12%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.25%     95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.06%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.03%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             103      3.21%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.06%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.09%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               4      0.12%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.03%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.06%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.03%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.03%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.22%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3213                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1180806250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2875581250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    451940000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13063.75                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31952.53                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31813.75                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.05                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.77                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.49                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.05                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.06                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.49                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         4.64                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      74590                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     60325                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.45                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15548355.62                       # Average gap between requests
-system.physmem.pageHitRate                      80.18                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  130667040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   71094375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 362653200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                256666320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           178852415040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            68967490005                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1611945575250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1860586561230                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.497599                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2632498894488                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     91437840000                       # Time in different power states
+system.physmem.avgWrQLen                         6.07                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      74627                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49067                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.56                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18019197.23                       # Average gap between requests
+system.physmem.pageHitRate                      79.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  128285640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   69757875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 361803000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                218615760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           178850889360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            68913339435                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1610809853250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1859352544320                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.527151                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2632589257000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91437060000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     14475823012                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     14382937750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  121239720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   65934000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 342209400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                247918320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           178852415040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            68215091715                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1611413256750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1859258064945                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.496864                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2633620948492                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     91437840000                       # Time in different power states
+system.physmem_1.actEnergy                  117270720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   63772500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 343207800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                207690480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           178850889360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68192676180                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1609047407250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1856822914290                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.575499                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2633644277500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91437060000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     13360607258                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     13328364750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -392,48 +393,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     5755                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                5755                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         5755                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           5755    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         5755                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 166069431868                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.475663                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walks                     5725                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                5725                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         5725                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           5725    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         5725                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 166068997868                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.475665                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::stdev     0.499407                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0    87076283368     52.43%     52.43% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    78993148500     47.57%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 166069431868                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3189     67.65%     67.65% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1525     32.35%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4714                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5755                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walksPending::0    87075845118     52.43%     52.43% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    78993152750     47.57%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 166068997868                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3165     67.41%     67.41% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1530     32.59%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4695                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5725                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5755                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4714                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5725                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4695                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4714                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        10469                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4695                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        10420                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14452204                       # DTB read hits
-system.cpu0.dtb.read_misses                      4833                       # DTB read misses
-system.cpu0.dtb.write_hits                   11089888                       # DTB write hits
-system.cpu0.dtb.write_misses                      922                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         189                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14454415                       # DTB read hits
+system.cpu0.dtb.read_misses                      4808                       # DTB read misses
+system.cpu0.dtb.write_hits                   11087884                       # DTB write hits
+system.cpu0.dtb.write_misses                      917                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         190                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3319                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3341                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   937                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   964                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14457037                       # DTB read accesses
-system.cpu0.dtb.write_accesses               11090810                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      218                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14459223                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11088801                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         25542092                       # DTB hits
-system.cpu0.dtb.misses                           5755                       # DTB misses
-system.cpu0.dtb.accesses                     25547847                       # DTB accesses
+system.cpu0.dtb.hits                         25542299                       # DTB hits
+system.cpu0.dtb.misses                           5725                       # DTB misses
+system.cpu0.dtb.accesses                     25548024                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -463,35 +464,35 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     2817                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2817                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2817                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2817    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2817                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 166069431868                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.475664                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walks                     2784                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2784                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2784                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2784    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2784                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 166068997868                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.475665                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::stdev     0.499407                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    87076165368     52.43%     52.43% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    78993266500     47.57%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 166069431868                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1542     75.55%     75.55% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          499     24.45%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2041                       # Table walker page sizes translated
+system.cpu0.itb.walker.walksPending::0    87075735118     52.43%     52.43% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    78993262750     47.57%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 166068997868                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1521     75.19%     75.19% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          502     24.81%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2023                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2817                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2817                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2784                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2784                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2041                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2041                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4858                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    67891248                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2817                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2023                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2023                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4807                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    67912569                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2784                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         189                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         190                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
 system.cpu0.itb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
@@ -501,504 +502,504 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                67894065                       # ITB inst accesses
-system.cpu0.itb.hits                         67891248                       # DTB hits
-system.cpu0.itb.misses                           2817                       # DTB misses
-system.cpu0.itb.accesses                     67894065                       # DTB accesses
-system.cpu0.numCycles                        82517225                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                67915353                       # ITB inst accesses
+system.cpu0.itb.hits                         67912569                       # DTB hits
+system.cpu0.itb.misses                           2784                       # DTB misses
+system.cpu0.itb.accesses                     67915353                       # DTB accesses
+system.cpu0.numCycles                        82537208                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   66111161                       # Number of instructions committed
-system.cpu0.committedOps                     80627134                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             70885778                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5615                       # Number of float alu accesses
-system.cpu0.num_func_calls                    7285085                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      8754092                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    70885778                       # number of integer instructions
-system.cpu0.num_fp_insts                         5615                       # number of float instructions
-system.cpu0.num_int_register_reads          131498293                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          49310474                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4327                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1292                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           245812611                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           29370316                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     26208491                       # number of memory refs
-system.cpu0.num_load_insts                   14628012                       # Number of load instructions
-system.cpu0.num_store_insts                  11580479                       # Number of store instructions
-system.cpu0.num_idle_cycles              77919171.769514                       # Number of idle cycles
-system.cpu0.num_busy_cycles              4598053.230486                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055722                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944278                       # Percentage of idle cycles
-system.cpu0.Branches                         16437108                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2194      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 55772206     67.98%     67.98% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58001      0.07%     68.05% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4497      0.01%     68.06% # Class of executed instruction
+system.cpu0.committedInsts                   66134007                       # Number of instructions committed
+system.cpu0.committedOps                     80648826                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             70905199                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5550                       # Number of float alu accesses
+system.cpu0.num_func_calls                    7283350                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      8754499                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    70905199                       # number of integer instructions
+system.cpu0.num_fp_insts                         5550                       # number of float instructions
+system.cpu0.num_int_register_reads          131519590                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          49325288                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4326                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1228                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           245878640                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           29383702                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     26210186                       # number of memory refs
+system.cpu0.num_load_insts                   14630349                       # Number of load instructions
+system.cpu0.num_store_insts                  11579837                       # Number of store instructions
+system.cpu0.num_idle_cycles              77938505.493998                       # Number of idle cycles
+system.cpu0.num_busy_cycles              4598702.506002                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055717                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944283                       # Percentage of idle cycles
+system.cpu0.Branches                         16436363                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2195      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 55791644     67.98%     67.99% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58049      0.07%     68.06% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4498      0.01%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::MemRead                14628012     17.83%     85.89% # Class of executed instruction
-system.cpu0.op_class::MemWrite               11580479     14.11%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                14630349     17.83%     85.89% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11579837     14.11%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  82045389                       # Class of executed instruction
+system.cpu0.op_class::total                  82066572                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3057                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           831864                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997018                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           47054976                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           832376                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            56.530914                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    3052                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           831549                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997019                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           47051301                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           832061                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            56.547899                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.861119                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.669659                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.466239                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.948947                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032558                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018489                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.952083                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.619501                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.425436                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949125                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032460                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018409                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        198551178                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       198551178                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     13770345                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      4433242                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      8498402                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       26701989                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     10695058                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3174725                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      5187481                       # number of WriteReq hits
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-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       188196                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        61394                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       132351                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       381941                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       234602                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        80377                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       136196                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       451175                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236074                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        82808                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       140857                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459739                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     24465403                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      7607967                       # number of demand (read+write) hits
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-system.cpu0.dcache.demand_hits::total        45759253                       # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total       46141194                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       187937                       # number of ReadReq misses
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-system.cpu0.dcache.ReadReq_misses::total       565886                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       147418                       # number of WriteReq misses
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-system.cpu0.dcache.WriteReq_misses::total      1652946                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54526                       # number of SoftPFReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total       141253                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4541                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3227                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         9714                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17482                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        198549695                       # Number of tag accesses
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 system.cpu0.dcache.StoreCondReq_misses::cpu2.data           16                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013464                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013243                       # miss rate for ReadReq accesses
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-system.cpu0.dcache.ReadReq_miss_rate::total     0.020753                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013596                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.010912                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.220863                       # miss rate for WriteReq accesses
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-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224644                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.249829                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.333687                       # miss rate for SoftPFReq accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018989                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.038599                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066575                       # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.WriteReq_accesses::total     20709472                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       242861                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        82020                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       198450                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       523331                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        83719                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       145748                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       468715                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236175                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        82928                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       140708                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459811                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     24800650                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      7711554                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data     15465341                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     47977545                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     25043511                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      7793574                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data     15663791                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     48500876                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013448                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013211                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.036478                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020849                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013584                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.010914                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.221016                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.079843                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.225372                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.249927                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.333681                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.270292                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018955                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.038462                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066677                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.037279                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000013                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000114                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000041                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013522                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012272                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115604                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.046247                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015568                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014769                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.118368                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048660                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15373.575448                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15303.005439                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10228.127886                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41417.356478                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48299.782617                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43846.327264                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.627208                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13300.493926                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9898.838691                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 20844.062500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17552.894737                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25024.134823                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 42426.035968                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 35272.416137                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20573.900322                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40910.302594                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33161.333445                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       378962                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        29004                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            19067                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            710                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    19.875282                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    40.850704                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013508                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012254                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115906                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.046314                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015562                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014755                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.118665                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048730                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.564117                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15226.744530                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10207.758216                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40799.877357                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 47823.346008                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43415.340512                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.354037                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13269.499897                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9884.249986                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19593.750000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        16500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24770.748897                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41979.972577                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34919.110070                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20355.232265                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40484.403913                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 32829.222610                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       384529                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        27036                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            18388                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            711                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.911953                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    38.025316                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       690587                       # number of writebacks
-system.cpu0.dcache.writebacks::total           690587                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           87                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       157237                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       157324                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1353907                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1353907                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1937                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6801                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8738                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data           87                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      1511144                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1511231                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data           87                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      1511144                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1511231                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        59411                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       161214                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       220625                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35026                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       116595                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       151621                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20077                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        44216                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        64293                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1290                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         2913                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4203                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       690633                       # number of writebacks
+system.cpu0.dcache.writebacks::total           690633                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           93                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       159890                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       159983                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1354576                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1354576                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1940                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6930                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8870                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data           93                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      1514466                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1514559                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data           93                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      1514466                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1514559                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        59345                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       161443                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       220788                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35061                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       116611                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       151672                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20123                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43935                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        64058                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1280                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         2788                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4068                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           16                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        94437                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       277809                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       372246                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       114514                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       322025                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       436539                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5880                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         8599                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14479                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4601                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6739                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        11340                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        10481                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        15338                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        25819                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    823130250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2155055358                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2978185608                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1391922672                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5640631884                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7032554556                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    264066008                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    576983002                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    841049010                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19999250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     37322251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57321501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       309495                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       309495                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2215052922                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7795687242                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10010740164                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2479118930                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8372670244                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10851789174                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1043159500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1692820000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2735979500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    803109000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1311241000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2114350000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1846268500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3004061000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4850329500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013224                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018285                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008091                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.010912                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017512                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007321                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.245320                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.222603                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.122886                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.015430                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019964                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.008968                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        94406                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       278054                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       372460                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       114529                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       321989                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       436518                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5882                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         8601                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14483                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4590                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6802                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        11392                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        10472                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        15403                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        25875                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    849299000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2242226500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3091525500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1395423500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5679297435                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7074720935                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    276712000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    590115500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    866827500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     20457500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     37492500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57950000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       297500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       297500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2244722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7921523935                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10166246435                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2521434500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8511639435                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11033073935                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1056963000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1715153500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2772116500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    811573000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1342286000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2153859000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1868536000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3057439500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4925975500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013191                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018327                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008097                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.010914                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017518                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007324                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.245343                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.221391                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.122404                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.015289                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019129                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.008679                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000114                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012261                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017952                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.007759                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014711                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020546                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.009001                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012242                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017979                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.007763                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014695                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020556                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.009000                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39799.877357                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1799096                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.534039                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          100909280                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1799607                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            56.072954                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10982089250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   477.173904                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    21.006307                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    13.353828                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.931980                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.041028                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.026082                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999090                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1799604                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.542681                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          100855692                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1800115                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            56.027360                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10987259500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.414957                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    20.920922                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    12.206802                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934404                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.040861                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.023841                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999107                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          154                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          157                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        104560332                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       104560332                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     67029897                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     21781554                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     12097829                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      100909280                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     67029897                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     21781554                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     12097829                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       100909280                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     67029897                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     21781554                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     12097829                       # number of overall hits
-system.cpu0.icache.overall_hits::total      100909280                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       863392                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       250227                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       737787                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1851406                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       863392                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       250227                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       737787                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1851406                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       863392                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       250227                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       737787                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1851406                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   3390224750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  10026619709                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13416844459                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   3390224750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  10026619709                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13416844459                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   3390224750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  10026619709                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13416844459                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     67893289                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     22031781                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     12835616                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    102760686                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     67893289                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     22031781                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     12835616                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    102760686                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     67893289                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     22031781                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     12835616                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    102760686                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012717                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011358                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.057480                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.018017                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012717                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011358                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.057480                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.018017                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012717                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011358                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.057480                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.018017                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.596874                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13590.127922                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7246.840757                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.596874                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13590.127922                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7246.840757                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.596874                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13590.127922                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7246.840757                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7212                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        104509492                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       104509492                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     67050712                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     21807219                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     11997761                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      100855692                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     67050712                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     21807219                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     11997761                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       100855692                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     67050712                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     21807219                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     11997761                       # number of overall hits
+system.cpu0.icache.overall_hits::total      100855692                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       863880                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       249894                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       739869                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1853643                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       863880                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       249894                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       739869                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1853643                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       863880                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       249894                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       739869                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1853643                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   3388286000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  10019746984                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13408032984                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   3388286000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst  10019746984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13408032984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   3388286000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst  10019746984                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13408032984                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     67914592                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     22057113                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     12737630                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    102709335                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     67914592                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     22057113                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     12737630                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    102709335                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     67914592                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     22057113                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     12737630                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    102709335                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012720                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011329                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.058085                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.018047                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012720                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011329                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.058085                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.018047                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012720                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011329                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.058085                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.018047                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13558.892971                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13542.596033                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7233.341579                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13558.892971                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13542.596033                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7233.341579                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13558.892971                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13542.596033                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7233.341579                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         7691                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              416                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              418                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.336538                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.399522                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        51759                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        51759                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        51759                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        51759                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        51759                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        51759                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       250227                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       686028                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       936255                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       250227                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       686028                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       936255                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       250227                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       686028                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       936255                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   3014176750                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8498569729                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11512746479                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   3014176750                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8498569729                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11512746479                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   3014176750                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8498569729                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11512746479                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011358                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.053447                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009111                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011358                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.053447                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009111                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011358                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.053447                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009111                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.769441                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12388.079975                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12296.592786                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.769441                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        53485                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        53485                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        53485                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        53485                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        53485                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        53485                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       249894                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       686384                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       936278                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       249894                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       686384                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       936278                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       249894                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       686384                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       936278                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   3138392000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8843257984                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11981649984                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   3138392000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8843257984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11981649984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   3138392000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8843257984                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11981649984                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009116                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009116                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009116                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12797.107252                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12797.107252                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12797.107252                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1029,56 +1030,56 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     1874                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                1874                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          637                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1237                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         1874                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           1874    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         1874                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1601                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6448.828751                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191          390     24.36%     24.36% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383          856     53.47%     77.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          354     22.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     1911                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                1911                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          628                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1283                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         1911                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           1911    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         1911                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1624                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6539.405372                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191          417     25.68%     25.68% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383          849     52.28%     77.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          357     21.98%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::81920-90111            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1601                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1000015500                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1000015500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1000015500                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K          972     60.71%     60.71% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          629     39.29%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1601                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1874                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         1624                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1004     61.82%     61.82% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          620     38.18%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1624                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1911                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1874                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1601                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1911                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1624                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1601                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         3475                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1624                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3535                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4664064                       # DTB read hits
-system.cpu1.dtb.read_misses                      1628                       # DTB read misses
-system.cpu1.dtb.write_hits                    3297220                       # DTB write hits
-system.cpu1.dtb.write_misses                      246                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         168                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     112                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                     4670594                       # DTB read hits
+system.cpu1.dtb.read_misses                      1655                       # DTB read misses
+system.cpu1.dtb.write_hits                    3300164                       # DTB write hits
+system.cpu1.dtb.write_misses                      256                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         167                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     123                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1307                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   257                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       60                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4665692                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3297466                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       65                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 4672249                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3300420                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7961284                       # DTB hits
-system.cpu1.dtb.misses                           1874                       # DTB misses
-system.cpu1.dtb.accesses                      7963158                       # DTB accesses
+system.cpu1.dtb.hits                          7970758                       # DTB hits
+system.cpu1.dtb.misses                           1911                       # DTB misses
+system.cpu1.dtb.accesses                      7972669                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1108,128 +1109,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                      876                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                 876                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          230                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2          646                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples          876                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0            876    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total          876                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          692                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6272.001420                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::2048-4095          140     20.23%     20.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          230     33.24%     53.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335          143     20.66%     74.13% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-22527          156     22.54%     96.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575           23      3.32%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          692                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                      935                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                 935                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          229                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          706                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples          935                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0            935    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total          935                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          723                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6487.735992                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          166     22.96%     22.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          228     31.54%     54.50% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335          139     19.23%     73.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383            7      0.97%     74.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          183     25.31%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          723                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          462     66.76%     66.76% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          230     33.24%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          692                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          494     68.33%     68.33% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          229     31.67%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          723                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          876                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total          876                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          935                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total          935                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          692                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          692                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         1568                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    22031781                       # ITB inst hits
-system.cpu1.itb.inst_misses                       876                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          723                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          723                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1658                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    22057113                       # ITB inst hits
+system.cpu1.itb.inst_misses                       935                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         168                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     112                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         167                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     123                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     752                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     783                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                22032657                       # ITB inst accesses
-system.cpu1.itb.hits                         22031781                       # DTB hits
-system.cpu1.itb.misses                            876                       # DTB misses
-system.cpu1.itb.accesses                     22032657                       # DTB accesses
-system.cpu1.numCycles                       158012603                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                22058048                       # ITB inst accesses
+system.cpu1.itb.hits                         22057113                       # DTB hits
+system.cpu1.itb.misses                            935                       # DTB misses
+system.cpu1.itb.accesses                     22058048                       # DTB accesses
+system.cpu1.numCycles                       158011873                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   21317281                       # Number of instructions committed
-system.cpu1.committedOps                     25549926                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22701009                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1608                       # Number of float alu accesses
-system.cpu1.num_func_calls                    2410952                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2737582                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22701009                       # number of integer instructions
-system.cpu1.num_fp_insts                         1608                       # number of float instructions
-system.cpu1.num_int_register_reads           41843043                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15920660                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1288                       # number of times the floating registers were read
+system.cpu1.committedInsts                   21342205                       # Number of instructions committed
+system.cpu1.committedOps                     25582989                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             22730381                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1657                       # Number of float alu accesses
+system.cpu1.num_func_calls                    2417962                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2740367                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    22730381                       # number of integer instructions
+system.cpu1.num_fp_insts                         1657                       # number of float instructions
+system.cpu1.num_int_register_reads           41903720                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          15946634                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1337                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                320                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            92840963                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            9448697                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      8172131                       # number of memory refs
-system.cpu1.num_load_insts                    4710232                       # Number of load instructions
-system.cpu1.num_store_insts                   3461899                       # Number of store instructions
-system.cpu1.num_idle_cycles              151539718.287508                       # Number of idle cycles
-system.cpu1.num_busy_cycles              6472884.712492                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.040964                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.959036                       # Percentage of idle cycles
-system.cpu1.Branches                          5298424                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   41      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 18071289     68.81%     68.81% # Class of executed instruction
-system.cpu1.op_class::IntMult                   19339      0.07%     68.88% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1186      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.88% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4710232     17.93%     86.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3461899     13.18%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            92962985                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            9452948                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      8180627                       # number of memory refs
+system.cpu1.num_load_insts                    4716601                       # Number of load instructions
+system.cpu1.num_store_insts                   3464026                       # Number of store instructions
+system.cpu1.num_idle_cycles              151538894.643419                       # Number of idle cycles
+system.cpu1.num_busy_cycles              6472978.356581                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.040965                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.959035                       # Percentage of idle cycles
+system.cpu1.Branches                          5307887                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   38      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 18096671     68.81%     68.81% # Class of executed instruction
+system.cpu1.op_class::IntMult                   19327      0.07%     68.89% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1187      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.89% # Class of executed instruction
+system.cpu1.op_class::MemRead                 4716601     17.94%     86.83% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3464026     13.17%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  26263986                       # Class of executed instruction
+system.cpu1.op_class::total                  26297850                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               17390044                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9451928                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           400737                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            10830418                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                8125283                       # Number of BTB hits
+system.cpu2.branchPred.lookups               17205761                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          9385761                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           401350                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            10751395                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                8022189                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            75.022802                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4068079                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21097                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            74.615331                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4025562                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             21207                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1259,88 +1260,89 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    43271                       # Table walker walks requested
-system.cpu2.dtb.walker.walksShort               43271                       # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1        13795                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2        11030                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksSquashedBefore        18446                       # Table walks squashed before starting
-system.cpu2.dtb.walker.walkWaitTime::samples        24825                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::mean   526.888218                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::stdev  3382.784717                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0-16383        24602     99.10%     99.10% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::16384-32767          180      0.73%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::32768-49151           23      0.09%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::49152-65535           14      0.06%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::65536-81919            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walks                    43873                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               43873                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1        13923                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2        10993                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksSquashedBefore        18957                       # Table walks squashed before starting
+system.cpu2.dtb.walker.walkWaitTime::samples        24916                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::mean   571.078825                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::stdev  3693.718026                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0-16383        24688     99.08%     99.08% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::16384-32767          176      0.71%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::32768-49151           30      0.12%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::49152-65535            9      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::65536-81919            9      0.04%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu2.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::98304-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu2.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        24825                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples         9018                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev  7598.717395                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-8191         2712     30.07%     30.07% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::8192-16383         3866     42.87%     72.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::16384-24575         2205     24.45%     97.39% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::24576-32767          103      1.14%     98.54% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-40959           58      0.64%     99.18% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::40960-49151           71      0.79%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkWaitTime::total        24916                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         9164                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  7680.126787                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191         2739     29.89%     29.89% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383         3883     42.37%     72.26% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575         2316     25.27%     97.53% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::24576-32767           72      0.79%     98.32% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-40959           91      0.99%     99.31% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::40960-49151           60      0.65%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walkCompletionTime::81920-90111            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total         9018                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples  60407494468                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::mean     0.614556                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::stdev     0.505382                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0-1  60349981968     99.90%     99.90% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::2-3     42488500      0.07%     99.98% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::4-5      7802000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::6-7      2924500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::8-9      1368500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::10-11       844500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::12-13       331000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::14-15      1040000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::16-17       124500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::18-19       121000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::20-21       186000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::22-23        81500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::24-25       109000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::26-27        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkCompletionTime::total         9164                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples  60380803468                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::mean     0.564289                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::stdev     0.516018                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0-1  60322207968     99.90%     99.90% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::2-3     41747500      0.07%     99.97% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::4-5      8670500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::6-7      3297500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::8-9      1514000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::10-11       972000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::12-13       454500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::14-15      1161000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::16-17       173500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::18-19       164000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::20-21       123500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::22-23        89000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::24-25       134500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::26-27        15500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::28-29         5500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::30-31        75000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total  60407494468                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K         2796     73.35%     73.35% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M         1016     26.65%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total         3812                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        43271                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walksPending::30-31        73000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total  60380803468                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K         2766     73.10%     73.10% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M         1018     26.90%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         3784                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        43873                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        43271                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         3812                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        43873                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         3784                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         3812                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total        47083                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         3784                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        47657                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     9630626                       # DTB read hits
-system.cpu2.dtb.read_misses                     37535                       # DTB read misses
-system.cpu2.dtb.write_hits                    7130235                       # DTB write hits
-system.cpu2.dtb.write_misses                     5736                       # DTB write misses
+system.cpu2.dtb.read_hits                     9620013                       # DTB read hits
+system.cpu2.dtb.read_misses                     37991                       # DTB read misses
+system.cpu2.dtb.write_hits                    7129568                       # DTB write hits
+system.cpu2.dtb.write_misses                     5882                       # DTB write misses
 system.cpu2.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     360                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva                     348                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2330                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      520                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   952                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    2312                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      478                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   974                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      414                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 9668161                       # DTB read accesses
-system.cpu2.dtb.write_accesses                7135971                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      415                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 9658004                       # DTB read accesses
+system.cpu2.dtb.write_accesses                7135450                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         16760861                       # DTB hits
-system.cpu2.dtb.misses                          43271                       # DTB misses
-system.cpu2.dtb.accesses                     16804132                       # DTB accesses
+system.cpu2.dtb.hits                         16749581                       # DTB hits
+system.cpu2.dtb.misses                          43873                       # DTB misses
+system.cpu2.dtb.accesses                     16793454                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1370,395 +1372,392 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                     6235                       # Table walker walks requested
-system.cpu2.itb.walker.walksShort                6235                       # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1         2044                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2         4088                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksSquashedBefore          103                       # Table walks squashed before starting
-system.cpu2.itb.walker.walkWaitTime::samples         6132                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::mean  1114.562948                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::stdev  4869.153513                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0-8191         5831     95.09%     95.09% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::8192-16383          152      2.48%     97.57% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::16384-24575           99      1.61%     99.18% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::24576-32767           29      0.47%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::32768-40959            9      0.15%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::40960-49151            4      0.07%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::49152-57343            3      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::57344-65535            1      0.02%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::65536-73727            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::106496-114687            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total         6132                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples         1857                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev  8040.211817                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-4095          547     29.46%     29.46% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-8191           43      2.32%     31.77% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::8192-12287          410     22.08%     53.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-16383          373     20.09%     73.94% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::16384-20479            9      0.48%     74.42% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::20480-24575          413     22.24%     96.66% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-28671           14      0.75%     97.42% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::28672-32767           13      0.70%     98.12% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-36863           11      0.59%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::36864-40959            8      0.43%     99.14% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::40960-45055           10      0.54%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::45056-49151            1      0.05%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::49152-53247            1      0.05%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::53248-57343            2      0.11%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::57344-61439            1      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::61440-65535            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total         1857                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples  13162833212                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::mean     0.828087                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::stdev     0.377922                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0     2265327000     17.21%     17.21% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::1    10895443212     82.77%     99.98% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::2        1802500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::3         162000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::4          51500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::5          47000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total  13162833212                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K         1358     77.42%     77.42% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M          396     22.58%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total         1754                       # Table walker page sizes translated
+system.cpu2.itb.walker.walks                     5947                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                5947                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1         1786                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         4054                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksSquashedBefore          107                       # Table walks squashed before starting
+system.cpu2.itb.walker.walkWaitTime::samples         5840                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::mean  1732.534247                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::stdev  7455.028366                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0-8191         5455     93.41%     93.41% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::8192-16383          164      2.81%     96.22% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::16384-24575          114      1.95%     98.17% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::24576-32767           45      0.77%     98.94% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::32768-40959           19      0.33%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::40960-49151            8      0.14%     99.40% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::49152-57343           13      0.22%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::57344-65535            3      0.05%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::65536-73727            6      0.10%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::73728-81919            3      0.05%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::81920-90111            5      0.09%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::98304-106495            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::106496-114687            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::122880-131071            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         5840                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples         1844                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  8164.078124                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-8191          568     30.80%     30.80% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::8192-16383          796     43.17%     73.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::16384-24575          418     22.67%     96.64% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-32767           27      1.46%     98.10% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-40959           12      0.65%     98.75% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::40960-49151           15      0.81%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::49152-57343            4      0.22%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::57344-65535            3      0.16%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-73727            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total         1844                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples  13135820712                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::mean     0.816052                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::stdev     0.388899                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0     2421306500     18.43%     18.43% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::1    10711149212     81.54%     99.97% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::2        2311000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::3         636500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::4         285000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::5          97500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::6          35000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total  13135820712                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K         1342     77.26%     77.26% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          395     22.74%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total         1737                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         6235                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total         6235                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         5947                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         5947                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst         1754                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total         1754                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total         7989                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    12837123                       # ITB inst hits
-system.cpu2.itb.inst_misses                      6235                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst         1737                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total         1737                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         7684                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    12739134                       # ITB inst hits
+system.cpu2.itb.inst_misses                      5947                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     360                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva                     348                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1683                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                    1664                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1125                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1123                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                12843358                       # ITB inst accesses
-system.cpu2.itb.hits                         12837123                       # DTB hits
-system.cpu2.itb.misses                           6235                       # DTB misses
-system.cpu2.itb.accesses                     12843358                       # DTB accesses
-system.cpu2.numCycles                        69616646                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                12745081                       # ITB inst accesses
+system.cpu2.itb.hits                         12739134                       # DTB hits
+system.cpu2.itb.misses                           5947                       # DTB misses
+system.cpu2.itb.accesses                     12745081                       # DTB accesses
+system.cpu2.numCycles                        69598203                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          26594039                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      69071466                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   17390044                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          12193362                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     39655163                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                2070826                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     93322                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                 918                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              302                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       323029                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       106475                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          727                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 12835626                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               269064                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2716                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          67809362                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.223662                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.348600                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          26515709                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      68908003                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   17205761                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          12047751                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     39848524                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                2067901                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     93242                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                1673                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              258                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       197550                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       103741                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          733                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 12737635                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               269288                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2836                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          67795354                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.222311                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.353518                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                49260090     72.64%     72.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                 2390617      3.53%     76.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                 1561768      2.30%     78.47% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4865604      7.18%     85.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                 1097205      1.62%     87.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  701816      1.03%     88.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 3870082      5.71%     94.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  751059      1.11%     95.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 3311121      4.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                49366248     72.82%     72.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                 2347568      3.46%     76.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                 1568593      2.31%     78.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4737747      6.99%     85.58% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                 1131198      1.67%     87.25% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  711180      1.05%     88.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 3791892      5.59%     93.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  790451      1.17%     95.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 3350477      4.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            67809362                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.249797                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.992169                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                18546973                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             36871218                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 10413141                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1051163                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                926599                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved             1313756                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred               110434                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              59271705                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               356279                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                926599                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                19159512                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                3828211                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      27033628                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 10840093                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              6021054                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              56800254                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 1622                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                892733                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                160451                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4475802                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           58727822                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            260839504                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        63695069                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             4195                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             48596346                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10131460                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            953771                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        889969                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  6004915                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            10275852                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            7909386                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          1396867                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores         1932490                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  54546075                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             673336                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 51866821                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            68048                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8110099                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     18430167                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         68913                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     67809362                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.764892                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.469149                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            67795354                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.247216                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.990083                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                18554298                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             36869392                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 10385190                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1060917                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                925294                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved             1315001                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred               110273                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              59218991                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               355421                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                925294                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                19165450                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                3849841                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      27045066                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 10823220                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5986178                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              56757014                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 1753                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                886942                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                164990                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4446768                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           58681863                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            260617277                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        63638433                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             4180                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             48518636                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10163211                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            951510                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        887874                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  5959133                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            10269621                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            7907555                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          1397245                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores         1927093                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  54497262                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             673331                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 51805193                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            68913                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8128009                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     18480591                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         69367                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     67795354                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.764141                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.469300                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           47470041     70.01%     70.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6738750      9.94%     79.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            5086869      7.50%     87.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4143776      6.11%     93.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1653610      2.44%     95.99% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1071590      1.58%     97.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            1124885      1.66%     99.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             357423      0.53%     99.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             162418      0.24%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           47462334     70.01%     70.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            6771907      9.99%     80.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            5071293      7.48%     87.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4140398      6.11%     93.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1621050      2.39%     95.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1073842      1.58%     97.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            1127363      1.66%     99.22% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             365418      0.54%     99.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             161749      0.24%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       67809362                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       67795354                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  76711      9.73%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     2      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                365050     46.29%     56.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               346827     43.98%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  78874      9.93%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                365128     45.98%     55.91% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               350163     44.09%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass              102      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             34390478     66.31%     66.31% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               39542      0.08%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   1      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  1      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc          2888      0.01%     66.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     66.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             9917724     19.12%     85.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            7516080     14.49%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass              104      0.00%      0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             34340504     66.29%     66.29% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               39551      0.08%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   1      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  1      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc          2876      0.01%     66.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             9906412     19.12%     85.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            7515741     14.51%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              51866821                       # Type of FU issued
-system.cpu2.iq.rate                          0.745035                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     788590                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.015204                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         172390251                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         63361989                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     50322136                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               9391                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              4966                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         4144                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              52650258                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   5051                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          268895                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              51805193                       # Type of FU issued
+system.cpu2.iq.rate                          0.744347                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     794166                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.015330                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         172259378                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         63331070                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     50263649                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               9441                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              4992                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         4167                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              52594172                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   5083                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          269403                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1610409                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1859                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation        38198                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       800698                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1615728                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1799                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation        38192                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       801002                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       130635                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        68542                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       130832                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        65205                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                926599                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3277236                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               403345                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           55328961                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            92252                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             10275852                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             7909386                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            360332                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 33301                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               361214                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents         38198                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        183568                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       164696                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              348264                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             51429187                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              9738477                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           394455                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                925294                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3298023                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               403705                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           55280627                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            94381                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             10269621                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             7907555                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            360066                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 33263                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               361678                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents         38192                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        184473                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       164818                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              349291                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             51367571                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              9727601                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           393852                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                       109550                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    17180160                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 9476518                       # Number of branches executed
-system.cpu2.iew.exec_stores                   7441683                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.738748                       # Inst execution rate
-system.cpu2.iew.wb_sent                      51031347                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     50326280                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 26469079                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 46041332                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                       110034                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    17167980                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 9465672                       # Number of branches executed
+system.cpu2.iew.exec_stores                   7440379                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.738059                       # Inst execution rate
+system.cpu2.iew.wb_sent                      50970582                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     50267816                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 26418019                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 45975704                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.722906                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.574898                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.722257                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.574608                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        8143906                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         604423                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           291897                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     66086949                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.713825                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.622364                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8162826                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         603964                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           292667                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     66072678                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.712969                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.621762                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     48131767     72.83%     72.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      7989880     12.09%     84.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      3968576      6.01%     90.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      1690353      2.56%     93.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       906489      1.37%     94.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       608385      0.92%     95.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      1262051      1.91%     97.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       299318      0.45%     98.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1230130      1.86%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     48122515     72.83%     72.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      8016673     12.13%     84.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      3951454      5.98%     90.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      1700222      2.57%     93.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       874557      1.32%     94.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       615125      0.93%     95.77% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      1261958      1.91%     97.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       299480      0.45%     98.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1230694      1.86%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     66086949                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            38874571                       # Number of instructions committed
-system.cpu2.commit.committedOps              47174544                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     66072678                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            38816949                       # Number of instructions committed
+system.cpu2.commit.committedOps              47107760                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                      15774131                       # Number of memory references committed
-system.cpu2.commit.loads                      8665443                       # Number of loads committed
-system.cpu2.commit.membars                     227144                       # Number of memory barriers committed
-system.cpu2.commit.branches                   8900555                       # Number of branches committed
-system.cpu2.commit.fp_insts                      4112                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 41283041                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             1636102                       # Number of function calls committed.
+system.cpu2.commit.refs                      15760446                       # Number of memory references committed
+system.cpu2.commit.loads                      8653893                       # Number of loads committed
+system.cpu2.commit.membars                     226862                       # Number of memory barriers committed
+system.cpu2.commit.branches                   8887739                       # Number of branches committed
+system.cpu2.commit.fp_insts                      4128                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 41222164                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             1631970                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        31359241     66.47%     66.47% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          38284      0.08%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc         2888      0.01%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        8665443     18.37%     84.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       7108688     15.07%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        31306209     66.46%     66.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          38229      0.08%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc         2876      0.01%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        8653893     18.37%     84.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       7106553     15.09%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         47174544                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1230130                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   112818862                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  112362949                       # The number of ROB writes
-system.cpu2.timesIdled                         279332                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1807284                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  5249914577                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   38809335                       # Number of Instructions Simulated
-system.cpu2.committedOps                     47109308                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.793812                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.793812                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.557472                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.557472                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                56301107                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               31916155                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    15723                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   13758                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                181999487                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                19225356                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               94261250                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                485009                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                30180                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30180                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59003                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22779                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54126                       # Packet count per connected master and slave (bytes)
+system.cpu2.commit.op_class_0::total         47107760                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1230694                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   112781874                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  112267275                       # The number of ROB writes
+system.cpu2.timesIdled                         279594                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1802849                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  5249879064                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   38751769                       # Number of Instructions Simulated
+system.cpu2.committedOps                     47042580                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.796001                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.796001                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.556793                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.556793                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                56233169                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               31866388                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    15654                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   13819                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                181781148                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                19208893                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               94223470                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                484431                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59005                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59005                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54134                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -1779,11 +1778,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       105414                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       105422                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178366                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67843                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67851                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -1804,11 +1803,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       159071                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       159079                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480319                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             18225000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2480327                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             18337000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1830,29 +1829,29 @@ system.iobus.reqLayer19.occupancy                2000                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             2714000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             2698000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy                1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            15729000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            15728000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               25000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           124959118                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           107120699                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            39808000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            39854000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            23061006                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            20948000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse                0.992064                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.991924                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         244950709509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.992064                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062004                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062004                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         244949964009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.991924                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.061995                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.061995                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1860,377 +1859,389 @@ system.iocache.tags.tag_accesses               328284                       # Nu
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     14858930                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     14858930                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   4185043182                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   4185043182                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     14858930                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     14858930                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     14858930                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     14858930                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     14446931                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     14446931                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   2442151768                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2442151768                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     14446931                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     14446931                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     14446931                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     14446931                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 58964.007937                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 58964.007937                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 58964.007937                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 58964.007937                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 58964.007937                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         14316                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 57329.091270                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 57329.091270                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 67418.058966                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 67418.058966                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 57329.091270                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 57329.091270                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 57329.091270                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 57329.091270                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 2165                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.612471                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          125                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          125                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        22752                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        22752                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          125                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          125                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          125                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          125                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide      8240930                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      8240930                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   3001927194                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   3001927194                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide      8240930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      8240930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide      8240930                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      8240930                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.496032                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.628092                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.628092                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.496032                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.496032                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 65927.440000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 65927.440000                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131941.244462                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131941.244462                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 65927.440000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 65927.440000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 65927.440000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 65927.440000                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::realview.ide          122                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          122                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        20704                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        20704                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          122                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          122                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          122                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          122                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide      8346931                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      8346931                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1406951768                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1406951768                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide      8346931                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      8346931                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide      8346931                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      8346931                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.484127                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.571555                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.571555                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.484127                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.484127                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68417.467213                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68417.467213                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67955.552937                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67955.552937                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68417.467213                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68417.467213                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68417.467213                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68417.467213                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   100862                       # number of replacements
-system.l2c.tags.tagsinuse                65121.580421                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2889469                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166056                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    17.400570                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   100800                       # number of replacements
+system.l2c.tags.tagsinuse                65125.449839                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4808585                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   165996                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    28.968078                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49829.873035                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939329                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   49726.772555                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939327                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5354.052994                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2949.398573                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5415.190350                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2959.237721                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1018.817810                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      810.859726                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    62.513746                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     3585.332677                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1507.823205                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.760344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu1.inst     1018.129085                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      815.178543                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    59.704078                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     3616.145822                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     1512.183033                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.758770                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000030                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081696                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.045004                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.082629                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.045154                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.015546                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.012373                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000954                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.054708                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.023008                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993676                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65144                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           50                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu1.inst       0.015535                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.012439                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000911                       # Average percentage of cache occupancy
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 system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::4        53568                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000763                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994019                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27412273                       # Number of tag accesses
-system.l2c.tags.data_accesses                27412273                       # Number of data accesses
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-system.l2c.ReadReq_accesses::total            2378491                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       690587                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           690587                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1352                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          303                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         1107                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2762                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu1.inst    159178000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1323080500                       # number of overall miss cycles
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 system.l2c.SCUpgradeReq_accesses::cpu0.data            3                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu2.data           16                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.dtb.walker         4629                       # number of demand (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007857                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030540                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu2.inst      0.011854                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::total          0.014271                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992604                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.986799                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.970190                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.982983                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.002222                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992481                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988439                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.968721                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.982628                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.375000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.473684                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.440595                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.418051                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.519364                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.468659                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000864                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000414                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.011208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.181833                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000583                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007857                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.147038                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu2.inst       0.011854                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.199095                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.064604                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000864                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000414                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.011208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.181833                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000583                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007857                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.147038                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003404                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.011854                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.199095                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.064604                       # miss rate for overall accesses
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+system.l2c.SCUpgradeReq_miss_rate::total     0.421053                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.440002                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.416535                       # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.468569                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.011172                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007787                       # miss rate for ReadCleanReq accesses
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+system.l2c.ReadCleanReq_miss_rate::total     0.010969                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028995                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.030713                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021527                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.026353                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000871                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::total          0.064579                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79977.492370                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 82685.957844                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85760.869565                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83981.521338                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 87068.460339                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 42505.641881                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   312.698997                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   261.630354                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   137.932965                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 10583.166667                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  7055.444444                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78211.488771                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81648.045295                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 43447.402493                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88966.292135                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 84215.789474                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   270.467836                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   322.412156                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   159.116022                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        25400                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        15875                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77426.486860                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81198.719015                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 43237.391824                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81797.533402                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83497.054130                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 42515.625000                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82053.830645                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 42150.782412                       # average ReadSharedReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 79977.492370                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 78861.463169                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu2.data 82025.363284                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 79977.492370                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 78861.463169                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85760.869565                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83981.521338                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 82025.363284                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 43262.408643                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 81797.533402                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu2.inst 83497.054130                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81631.450202                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 43088.592170                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2239,210 +2250,221 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               92886                       # number of writebacks
-system.l2c.writebacks::total                    92886                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data            44                       # number of ReadReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu2.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.writebacks::writebacks               92937                       # number of writebacks
+system.l2c.writebacks::total                    92937                       # number of writebacks
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            5                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu2.data             44                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 51                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             7                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::cpu2.data            44                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                51                       # number of overall MSHR hits
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1966                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu2.data         1074                       # number of UpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000583                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021331                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.007187                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.970190                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.497104                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000583                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007857                       # mshr miss rate for overall accesses
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161549.228429                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181573.304645                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173448.897707                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162589.876920                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 182294.203938                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 174295.402610                       # average overall mshr uncacheable latency
+system.l2c.overall_mshr_misses::cpu1.inst         1946                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        16940                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           89                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         8142                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        64547                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           91665                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5882                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         8601                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        14483                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4590                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         6802                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        11392                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10472                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data        15403                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        25875                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total      7100500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7101000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     21856500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     28957500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data       108000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       108000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    974987000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4279755000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5254742000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    139718000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    598575000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    738293000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    178693500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    344725500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    523419000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    139718000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1153680500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    598575000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   4624480500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6523554500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    139718000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1153680500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    598575000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   4624480500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6523554500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    983438000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1607640500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2591078500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    758788000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1264062500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2022850500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1742226000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2871703000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4613929000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.988439                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.968721                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.504886                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.312500                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.263158                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.416535                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.520289                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.251776                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005604                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.030713                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021316                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012907                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.146714                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.199410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034269                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.146714                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.199410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034269                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 78894.444444                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.157895                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20756.410256                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.064516                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        21600                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        21600                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67426.486860                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71198.719015                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70467.238836                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73185.269627                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72053.830645                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77693.373901                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75671.389331                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68103.925620                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71645.165538                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 71167.343043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68103.925620                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71645.165538                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 71167.343043                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167194.491670                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186913.207767                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 178904.819443                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165313.289760                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185836.886210                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177567.635183                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166369.938885                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186437.901707                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 178316.096618                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74250                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74249                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27555                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27555                       # Transaction distribution
-system.membus.trans_dist::Writeback            129076                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4552                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              9                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4561                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137020                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137020                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105414                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               40110                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74274                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27559                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27559                       # Transaction distribution
+system.membus.trans_dist::Writeback            129127                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7993                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4555                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4563                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            136939                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           136939                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34165                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105422                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       471581                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       578995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109017                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109017                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 688012                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159071                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2000                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       479379                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       586811                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 695961                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159079                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16928828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17091899                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4642624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4642624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21734523                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              283                       # Total snoops (count)
-system.membus.snoop_fanout::samples            408724                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16928316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17091415                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2324480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2324480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19415895                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              278                       # Total snoops (count)
+system.membus.snoop_fanout::samples            416813                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  408724    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  416813    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              408724                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            45631500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              416813                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            45715500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              463000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              475000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           565034415                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           457691597                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          525270598                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          520011564                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           23441994                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           36772084                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2475,50 +2497,53 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2441800                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2441792                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             27555                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            27555                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           690587                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        22777                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2762                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             105713                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2441896                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             27559                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            27559                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           756453                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1923004                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2763                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq            19                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2781                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296286                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296286                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3617238                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2478347                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        29055                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87637                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6212277                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115207096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97661699                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        48712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       154828                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              213072335                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           51752                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3495385                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.029269                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.168561                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp           2782                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296176                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296176                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1800158                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       536033                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        20704                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5399808                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2615033                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28551                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87799                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8131191                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115239416                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97644319                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        47800                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       155188                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              213086723                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          121684                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5505945                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.031256                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.174010                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3393077     97.07%     97.07% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 102308      2.93%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5333849     96.87%     96.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 172096      3.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3495385                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1275217471                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           177000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5505945                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1781656500                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           172500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1406471499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1404823682                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         694961258                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         679741283                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11749485                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11544481                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          39124219                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          39263676                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 30daa6157..a839f8e59 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.804323                       # Number of seconds simulated
-sim_ticks                                2804323403500                       # Number of ticks simulated
-final_tick                               2804323403500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.804297                       # Number of seconds simulated
+sim_ticks                                2804296829000                       # Number of ticks simulated
+final_tick                               2804296829000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 112232                       # Simulator instruction rate (inst/s)
-host_op_rate                                   136221                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2690265937                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 630508                       # Number of bytes of host memory used
-host_seconds                                  1042.40                       # Real time elapsed on the host
-sim_insts                                   116990114                       # Number of instructions simulated
-sim_ops                                     141995948                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 111214                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134984                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2666624096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631592                       # Number of bytes of host memory used
+host_seconds                                  1051.63                       # Real time elapsed on the host
+sim_insts                                   116955586                       # Number of instructions simulated
+sim_ops                                     141953418                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         4352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         4480                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           690752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4989088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           687552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4838856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           694336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4949664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           683520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4874120                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11215656                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       690752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       687552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1378304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8426048                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11211752                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       694336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       683520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1377856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8431616                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8443572                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           68                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8449140                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           70                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             78473                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           63                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10743                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             75609                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10849                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             77857                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           72                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10680                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             76160                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175765                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131657                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175704                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131744                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136038                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1552                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136125                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1598                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              246317                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1779070                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              245176                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1725499                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              247597                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1765029                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              243740                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1738090                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3999416                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         246317                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         245176                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             491493                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3004663                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3998062                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         247597                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         243740                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             491337                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3006677                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3010912                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3004663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3012926                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3006677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1598                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             246317                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1785316                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             245176                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1725501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             247597                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1771275                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1643                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             243740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1738093                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7010328                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175766                       # Number of read requests accepted
-system.physmem.writeReqs                       172232                       # Number of write requests accepted
-system.physmem.readBursts                      175766                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     172232                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11239872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9513088                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11215720                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10759988                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23563                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4633                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11568                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11615                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11475                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10984                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11566                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11265                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12051                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11828                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10136                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10546                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10466                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9460                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10169                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11261                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10850                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10383                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9594                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9874                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9855                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9284                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9607                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9407                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10082                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9751                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8758                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9037                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8724                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8208                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8857                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9711                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9203                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8690                       # Per bank write bursts
+system.physmem.bw_total::total                7010988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175705                       # Number of read requests accepted
+system.physmem.writeReqs                       136125                       # Number of write requests accepted
+system.physmem.readBursts                      175705                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136125                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11235200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9920                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8462208                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11211816                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8449140                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      155                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40824                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11564                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11591                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11445                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11009                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11560                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11263                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12057                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11817                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10124                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10528                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10442                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9442                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10178                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11257                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10875                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10398                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8593                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8838                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8913                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8377                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8541                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8325                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9064                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8810                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7663                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7908                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7816                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7099                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7741                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8641                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8211                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7682                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2804323239500                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2804296665000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  175210                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  175149                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 167851                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    103659                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61692                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8548                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1701                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131744                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    103856                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61431                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1726                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -161,201 +161,210 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       84                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1608                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::17                     3817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5886                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                     6715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6937                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24                     6678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9641                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31                     7571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      112                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      314.556969                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.654540                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.497717                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24476     37.10%     37.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15740     23.86%     60.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6623     10.04%     71.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3719      5.64%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2901      4.40%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1575      2.39%     83.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1142      1.73%     85.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1107      1.68%     86.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8692     13.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65975                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6306                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.843324                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      438.660877                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6303     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-6143            1      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6306                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6306                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.571519                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.321112                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       39.451011                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               32      0.51%      0.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5917     93.83%     94.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              88      1.40%     95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              21      0.33%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              16      0.25%     96.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              33      0.52%     96.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             35      0.56%     97.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            27      0.43%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            13      0.21%     98.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            17      0.27%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             5      0.08%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            20      0.32%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            18      0.29%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             8      0.13%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             5      0.08%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.03%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.03%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             9      0.14%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.06%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             6      0.10%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             4      0.06%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            11      0.17%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             4      0.06%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             6      0.10%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-623             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6306                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2686692750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5979624000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    878115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15298.07                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::6                        89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        87                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples        65040                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.849692                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.291679                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.303136                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24533     37.72%     37.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15784     24.27%     61.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6682     10.27%     72.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3695      5.68%     77.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2905      4.47%     82.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1458      2.24%     84.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1174      1.81%     86.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1054      1.62%     88.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7755     11.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65040                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6683                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.267993                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      478.078944                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6681     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6683                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6683                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.784827                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.157430                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.794900                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                18      0.27%      0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.09%      0.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                6      0.09%      0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              12      0.18%      0.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5769     86.32%     86.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             120      1.80%     88.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             172      2.57%     91.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              80      1.20%     92.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              71      1.06%     93.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             155      2.32%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              21      0.31%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              14      0.21%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              11      0.16%     96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.09%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.03%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             156      2.33%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.06%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               5      0.07%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.04%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.06%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.04%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.21%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6683                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2675585250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5967147750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    877750000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15241.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34048.07                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  33991.16                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.01                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.39                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.02                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.84                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.09                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145297                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    112992                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.73                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.00                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8058446.43                       # Average gap between requests
-system.physmem.pageHitRate                      79.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  264138840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  144123375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 720337800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                501901920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           183164495280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            78122450385                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1614063177750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1876980625350                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.317704                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2685041541216                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     93642380000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.63                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        10.95                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145103                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97628                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.66                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.83                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8993030.39                       # Average gap between requests
+system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  260993880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  142407375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 719979000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                450107280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           183162969600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            78025608810                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1614134111250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1876896177195                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.293165                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2685155496500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     93641600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     25639471784                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     25499722000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  234632160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  128023500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 649513800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                461298240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           183164495280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            76868306460                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1615163304000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1876669573440                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.206785                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2686874826210                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     93642380000                       # Time in different power states
+system.physmem_1.actEnergy                  230708520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  125882625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 649303200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                406691280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           183162969600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            76764954915                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1615239948000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1876580458140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.180581                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2687003305500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     93641600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23802212540                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23651154500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          640                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           10                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             10                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          228                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              228                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          228                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          228                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          228                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             228                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst          251                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              251                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          251                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          251                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          251                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             251                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26894349                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13975311                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           545296                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            16832825                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12628735                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26812041                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13971263                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           545954                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            16789639                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12578074                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            75.024454                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6673545                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29900                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            74.915691                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6641912                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             29629                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -386,84 +395,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    59638                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               59638                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19278                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14808                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        25552                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        34086                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   541.028575                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3545.315816                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        33770     99.07%     99.07% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          252      0.74%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           35      0.10%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           20      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    60251                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               60251                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19166                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14911                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        26174                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        34077                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   605.672448                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3875.346595                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        33739     99.01%     99.01% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          267      0.78%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           41      0.12%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           11      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::131072-147455            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        34086                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        11896                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11442.270763                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9167.474880                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7450.500727                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-8191         3982     33.47%     33.47% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5461     45.91%     79.38% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2160     18.16%     97.54% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::24576-32767          140      1.18%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-40959           47      0.40%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::40960-49151           93      0.78%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-57343            3      0.03%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::57344-65535            3      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-73727            4      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-90111            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::90112-98303            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total        34077                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12355                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12355.685957                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10118.887695                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7958.316755                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-8191         4001     32.38%     32.38% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5682     45.99%     78.37% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2378     19.25%     97.62% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::24576-32767           80      0.65%     98.27% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-40959           88      0.71%     98.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::40960-49151          103      0.83%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-57343            4      0.03%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::73728-81919            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-90111            7      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::90112-98303            8      0.06%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::106496-114687            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        11896                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  76466975540                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.696036                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.478552                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3  76445440540     99.97%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7     15483000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11      3531500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15      1916000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19       394500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23       120500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27        34000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31        54000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35         1500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  76466975540                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3544     69.19%     69.19% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1578     30.81%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5122                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        59638                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        12355                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  80764749336                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.624014                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.503698                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  80684502836     99.90%     99.90% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     56898500      0.07%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     12104000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      4341500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2388000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1576500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       755000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      1408500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       265500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       266500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        51500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        38500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25        30000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        29500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29        26000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31        67000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  80764749336                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3631     69.79%     69.79% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1572     30.21%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5203                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        60251                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        59638                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5122                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        60251                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5203                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5122                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        64760                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5203                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        65454                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    13978309                       # DTB read hits
-system.cpu0.dtb.read_misses                     51149                       # DTB read misses
-system.cpu0.dtb.write_hits                   10338750                       # DTB write hits
-system.cpu0.dtb.write_misses                     8489                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14022096                       # DTB read hits
+system.cpu0.dtb.read_misses                     51656                       # DTB read misses
+system.cpu0.dtb.write_hits                   10360983                       # DTB write hits
+system.cpu0.dtb.write_misses                     8595                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     463                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3463                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      922                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1428                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3475                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      881                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1392                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      586                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14029458                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10347239                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      599                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14073752                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10369578                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24317059                       # DTB hits
-system.cpu0.dtb.misses                          59638                       # DTB misses
-system.cpu0.dtb.accesses                     24376697                       # DTB accesses
+system.cpu0.dtb.hits                         24383079                       # DTB hits
+system.cpu0.dtb.misses                          60251                       # DTB misses
+system.cpu0.dtb.accesses                     24443330                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -493,806 +511,806 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     8503                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                8503                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3306                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5069                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          128                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         8375                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1173.014925                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  5467.905811                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         7973     95.20%     95.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          197      2.35%     97.55% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575          109      1.30%     98.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           49      0.59%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           12      0.14%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151           14      0.17%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343            5      0.06%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            7      0.08%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            2      0.02%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            4      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::90112-98303            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                     8217                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                8217                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2960                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5117                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          140                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         8077                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1443.543395                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  6102.235478                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         7600     94.09%     94.09% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          232      2.87%     96.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          133      1.65%     98.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           50      0.62%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           22      0.27%     99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151           13      0.16%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            2      0.02%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            8      0.10%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.05%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         8375                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2444                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12500.308511                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9992.698413                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7939.202624                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          801     32.77%     32.77% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383          949     38.83%     71.60% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          632     25.86%     97.46% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           25      1.02%     98.49% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           24      0.98%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            9      0.37%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343            2      0.08%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkWaitTime::total         8077                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2488                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13472.467846                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11168.518762                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7984.929111                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          793     31.87%     31.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383          981     39.43%     71.30% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          648     26.05%     97.35% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           24      0.96%     98.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           15      0.60%     98.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151           24      0.96%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::65536-73727            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2444                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  29185295284                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.914937                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.279656                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     2486739500      8.52%      8.52% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    26695454284     91.47%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2358500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         523000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         145500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          74500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  29185295284                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1760     75.99%     75.99% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          556     24.01%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2316                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2488                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  37746197376                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.883119                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.321811                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     4416616428     11.70%     11.70% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    33326087448     88.29%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2489000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         727000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         244500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          33000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  37746197376                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1794     76.41%     76.41% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          554     23.59%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2348                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8503                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8503                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8217                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8217                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2316                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2316                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        10819                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20234859                       # ITB inst hits
-system.cpu0.itb.inst_misses                      8503                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2348                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2348                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        10565                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20173848                       # ITB inst hits
+system.cpu0.itb.inst_misses                      8217                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     463                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2268                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2291                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1416                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1412                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20243362                       # ITB inst accesses
-system.cpu0.itb.hits                         20234859                       # DTB hits
-system.cpu0.itb.misses                           8503                       # DTB misses
-system.cpu0.itb.accesses                     20243362                       # DTB accesses
-system.cpu0.numCycles                       106376136                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20182065                       # ITB inst accesses
+system.cpu0.itb.hits                         20173848                       # DTB hits
+system.cpu0.itb.misses                           8217                       # DTB misses
+system.cpu0.itb.accesses                     20182065                       # DTB accesses
+system.cpu0.numCycles                       106431987                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39965142                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     103919162                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26894349                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19302280                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     61475471                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3204102                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    133084                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                4359                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              386                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       482542                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       142714                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          389                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20233629                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               371892                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3629                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         103806101                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.204244                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.303663                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39926124                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     104046311                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26812041                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19219986                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     61721491                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3201846                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    134355                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4118                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              472                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       336728                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       143479                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          355                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20172603                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               372165                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3674                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         103868008                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.205189                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.307808                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                75119256     72.36%     72.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3853264      3.71%     76.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2394905      2.31%     78.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 8055629      7.76%     86.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1633408      1.57%     87.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1025690      0.99%     88.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6108914      5.88%     94.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1037923      1.00%     95.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4577112      4.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                75224337     72.42%     72.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3826153      3.68%     76.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2403715      2.31%     78.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 7967440      7.67%     86.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1659017      1.60%     87.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1036461      1.00%     88.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6057785      5.83%     94.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1065173      1.03%     95.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4627927      4.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           103806101                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.252823                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.976903                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                27584011                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             57734540                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15584006                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1449686                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1453608                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1869283                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               150514                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              86108463                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               484067                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1453608                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                28423517                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6508141                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      43695790                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16185317                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7539460                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              82326363                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 3052                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1072870                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                278724                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               5472953                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           84763927                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            379438570                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        91864230                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6406                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             71037693                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                13726234                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1533064                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1439152                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8446360                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14835811                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11457004                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1997727                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2772041                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  79153572                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1058697                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 75784801                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            96696                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       11308863                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     24599963                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        115562                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    103806101                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.730061                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.422275                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           103868008                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.251917                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.977585                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                27603064                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             57749227                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15599106                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1464170                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1452197                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1874763                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               150759                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86325331                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               486551                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1452197                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                28440398                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6572412                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      43697521                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16217184                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7488032                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82550644                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 3098                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1081958                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                289974                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               5413982                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           85027824                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            380373358                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        92135642                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6326                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             71200016                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                13827808                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1531327                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1437175                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8438984                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14879838                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11477452                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1996170                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2776563                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79349721                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1058033                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 75951748                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            96660                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11354988                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     24738171                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        114625                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    103868008                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.731233                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.423636                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           73542195     70.85%     70.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10050115      9.68%     80.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7748986      7.46%     87.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6432670      6.20%     94.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2352911      2.27%     96.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1476701      1.42%     97.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1498599      1.44%     99.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             479431      0.46%     99.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             224493      0.22%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           73542868     70.80%     70.80% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10072511      9.70%     80.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7759579      7.47%     87.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6464332      6.22%     94.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2333365      2.25%     96.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1472075      1.42%     97.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1515581      1.46%     99.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             481814      0.46%     99.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             225883      0.22%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      103806101                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      103868008                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  98458      8.93%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                516893     46.87%     55.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               487368     44.20%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 101947      9.17%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     2      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                527360     47.45%     56.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               481989     43.37%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2186      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             50425393     66.54%     66.54% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57237      0.08%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4320      0.01%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14387296     18.98%     85.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10908366     14.39%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2185      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             50526992     66.53%     66.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57691      0.08%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4308      0.01%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14430381     19.00%     85.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           10930190     14.39%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              75784801                       # Type of FU issued
-system.cpu0.iq.rate                          0.712423                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1102720                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.014551                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         256560915                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91566516                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     73457837                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              14204                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              7630                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         6340                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              76877738                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   7597                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          359549                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              75951748                       # Type of FU issued
+system.cpu0.iq.rate                          0.713618                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1111298                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014632                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         256965506                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91807957                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     73625831                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              13956                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              7486                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         6230                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77053395                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7466                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          363562                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2204717                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2719                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        54058                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1152347                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2216786                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2550                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53728                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1148638                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       205467                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked        94593                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       206531                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked        94919                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1453608                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5664191                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               635354                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80356167                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           128884                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14835811                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11457004                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            551529                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 43992                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               579512                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         54058                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        250397                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       220538                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              470935                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             75169409                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14142783                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           555867                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1452197                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5712747                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               651844                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80559572                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           134213                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14879838                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11477452                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            551306                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 44233                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               595893                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53728                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        250776                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       220293                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              471069                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             75340518                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14186156                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           551092                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       143898                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    24942986                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14187310                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10800203                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.706638                       # Inst execution rate
-system.cpu0.iew.wb_sent                      74627910                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     73464177                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38231116                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 66477839                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       151818                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25009470                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14210768                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10823314                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.707875                       # Inst execution rate
+system.cpu0.iew.wb_sent                      74794094                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     73632061                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38328256                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 66642343                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.690608                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575096                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.691823                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575134                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       11279021                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         943135                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           396816                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    101272480                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.681216                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.570732                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       11328784                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         943408                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           397191                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    101330688                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.682350                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.572509                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     74367990     73.43%     73.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12119249     11.97%     85.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6128079      6.05%     91.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2581969      2.55%     94.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1298466      1.28%     95.28% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       821679      0.81%     96.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1839446      1.82%     97.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       396658      0.39%     98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1718944      1.70%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     74383354     73.41%     73.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12129402     11.97%     85.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6135914      6.06%     91.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2613445      2.58%     94.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1268685      1.25%     95.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       826588      0.82%     96.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1844857      1.82%     97.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       402953      0.40%     98.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1725490      1.70%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    101272480                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            56718354                       # Number of instructions committed
-system.cpu0.commit.committedOps              68988407                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    101330688                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            56867581                       # Number of instructions committed
+system.cpu0.commit.committedOps              69142978                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      22935751                       # Number of memory references committed
-system.cpu0.commit.loads                     12631094                       # Number of loads committed
-system.cpu0.commit.membars                     378784                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13402892                       # Number of branches committed
-system.cpu0.commit.fp_insts                      6286                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 60396974                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2623511                       # Number of function calls committed.
+system.cpu0.commit.refs                      22991866                       # Number of memory references committed
+system.cpu0.commit.loads                     12663052                       # Number of loads committed
+system.cpu0.commit.membars                     379145                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13422378                       # Number of branches committed
+system.cpu0.commit.fp_insts                      6158                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 60521589                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2622248                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        45992810     66.67%     66.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55529      0.08%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4317      0.01%     66.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        46090829     66.66%     66.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55975      0.08%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4308      0.01%     66.75% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.75% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.75% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12631094     18.31%     85.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10304657     14.94%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12663052     18.31%     85.06% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10328814     14.94%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         68988407                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1718944                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   167372763                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  163072923                       # The number of ROB writes
-system.cpu0.timesIdled                         393865                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        2570035                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2956119679                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   56633353                       # Number of Instructions Simulated
-system.cpu0.committedOps                     68903406                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.878330                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.878330                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.532388                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.532388                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                81817364                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               46775146                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16878                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13235                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                265909763                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27649979                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              144518865                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                724107                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           853909                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.982202                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42514992                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           854421                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.758833                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        105520250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.898512                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.083689                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.361130                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.638835                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         69142978                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1725490                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   167648310                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  163485257                       # The number of ROB writes
+system.cpu0.timesIdled                         393439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2563979                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2956083785                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   56777369                       # Number of Instructions Simulated
+system.cpu0.committedOps                     69052766                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.874549                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.874549                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.533462                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.533462                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                82027611                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               46869593                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16807                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13164                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                266520742                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27747679                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              144321385                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                724502                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           852950                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.982213                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42504025                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           853462                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.801895                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        105251500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   187.204537                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   324.777676                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.365634                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.634331                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189859724                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189859724                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12422539                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12908546                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25331085                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7676552                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8235772                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15912324                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178433                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183837                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       362270                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209755                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237006                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446761                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216045                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243370                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459415                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20099091                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21144318                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41243409                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20277524                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21328155                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41605679                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       408353                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       423480                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       831833                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1950457                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1746190                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3696647                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        84124                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        98955                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       183079                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13813                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14039                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27852                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           21                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses        189817658                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189817658                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12454816                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12866965                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25321781                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7691483                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total      15910168                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178893                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183845                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       362738                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209855                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236893                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446748                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216102                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243311                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459413                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20146299                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     21085650                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41231949                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20325192                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     21269495                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41594687                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       412638                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       834054                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1958462                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1736177                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3694639                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        85616                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        97979                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       183595                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13773                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14074                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27847                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           27                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data           34                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           55                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2358810                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2169670                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4528480                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2442934                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2268625                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4711559                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6108609853                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6466487368                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  12575097221                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85969014596                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  79541032692                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 165510047288                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    182474999                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    208223500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    390698499                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       466006                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       533501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       999507                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  92077624449                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  86007520060                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 178085144509                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  92077624449                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  86007520060                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 178085144509                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12830892                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13332026                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26162918                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9627009                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9981962                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19608971                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       262557                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       282792                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       545349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223568                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251045                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474613                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216066                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243404                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459470                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22457901                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23313988                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45771889                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22720458                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23596780                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46317238                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031826                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031764                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031794                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202603                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174935                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188518                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.320403                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.349921                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335710                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061784                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055922                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058684                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000097                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::total           61                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2371100                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      2157593                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4528693                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2456716                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2255572                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4712288                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6076761000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6454165500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  12530926500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  84857330299                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  79343865125                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 164201195424                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    181836500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    208543500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    390380000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       611500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       544500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      1156000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  90934091299                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  85798030625                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 176732121924                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  90934091299                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  85798030625                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 176732121924                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12867454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13288381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26155835                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9649945                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9954862                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19604807                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       264509                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       281824                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       546333                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223628                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474595                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216129                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243345                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459474                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22517399                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23243243                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45760642                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22781908                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23525067                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46306975                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032068                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031713                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031888                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202951                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174405                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188456                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323679                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.347660                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336050                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061589                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056079                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058675                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000125                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000140                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000120                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105033                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093063                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.098936                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107521                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096141                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.101724                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14959.140383                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15269.876660                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15117.333913                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44076.344465                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45551.190129                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44773.019249                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13210.381452                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14831.790014                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14027.664046                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22190.761905                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15691.205882                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18172.854545                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39035.625781                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39640.830200                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39325.589273                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37691.408957                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37911.739516                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37797.498558                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1124276                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       180492                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            53485                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2944                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.020398                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    61.308424                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000133                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105301                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.092827                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.098965                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107836                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.095880                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.101762                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14726.615096                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.425850                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.118942                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43328.555928                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45700.331893                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44443.095908                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13202.388732                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14817.642461                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14018.745287                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22648.148148                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16014.705882                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18950.819672                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38351.014845                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39765.623371                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39024.972972                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37014.490604                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38038.258422                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37504.524750                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1148125                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       185430                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            52981                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2987                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.670505                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    62.079009                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       704443                       # number of writebacks
-system.cpu0.dcache.writebacks::total           704443                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       195410                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       211050                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       406460                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1794100                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1602957                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3397057                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9538                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8888                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18426                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1989510                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1814007                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3803517                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1989510                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1814007                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3803517                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       212943                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212430                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       425373                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156357                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143233                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299590                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58111                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64761                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122872                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4275                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5151                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9426                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           21                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       703579                       # number of writebacks
+system.cpu0.dcache.writebacks::total           703579                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       198603                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       210557                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       409160                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1801482                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1593619                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3395101                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9550                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9160                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18710                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2000085                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1804176                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3804261                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2000085                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1804176                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3804261                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       214035                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       210859                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       424894                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156980                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       142558                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299538                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58648                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64092                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       122740                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4223                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4914                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9137                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           27                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           34                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           55                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       369300                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       355663                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       724963                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       427411                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       420424                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       847835                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16558                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14569                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           61                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       371015                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       353417                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       724432                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       429663                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       417509                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       847172                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16542                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14585                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16166                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11418                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16149                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11435                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32724                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        25987                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32691                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26020                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2911652660                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2946522646                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5858175306                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7110951020                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6670158760                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13781109780                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    777722500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    894500250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1672222750                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     53569251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82009500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    135578751                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       434494                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       482499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       916993                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10022603680                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9616681406                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  19639285086                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10800326180                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10511181656                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  21311507836                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3107181500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2733353000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5840534500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2374455377                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2136736500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4511191877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5481636877                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4870089500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10351726377                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016596                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015934                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016259                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016241                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014349                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.221327                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.229006                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225309                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019122                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020518                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019860                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000097                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3018980500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3044091500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6063072000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7145217382                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6750047429                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13895264811                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    806467500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    918616000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1725083500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     54857500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82625000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137482500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       584500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       510500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1095000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10164197882                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9794138929                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  19958336811                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10970665382                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10712754929                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  21683420311                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3143585500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2772334000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5915919500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2404168377                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2168590500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4572758877                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5547753877                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4940924500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10488678377                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016634                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015868                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016267                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014320                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.221724                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.227419                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224662                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018884                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019580                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019252                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000125                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000140                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000120                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016444                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015255                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015839                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018812                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017817                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018305                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13673.389874                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13870.558047                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13771.855068                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45478.942548                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46568.589361                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45999.899129                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13383.395571                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13812.329180                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13609.469611                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12530.818947                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15921.083285                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14383.487269                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20690.190476                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14191.147059                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16672.600000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27139.462984                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27038.745683                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 187654.396666                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187614.318073                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187635.637871                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 146879.585364                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187137.545980                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163543.789044                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167511.211252                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187404.837034                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176316.642145                       # average overall mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000133                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016477                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015205                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015831                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018860                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017747                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018295                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14105.078609                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14436.621154                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14269.610774                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45516.737049                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47349.481818                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46388.988412                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13750.980426                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14332.771641                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14054.778393                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12990.172863                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16814.204314                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15046.787786                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21648.148148                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15014.705882                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17950.819672                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27395.652149                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27712.698962                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27550.324683                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25533.186199                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25658.740121                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25595.062527                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190036.603796                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190081.179294                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.490282                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148874.133197                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189644.993441                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.771353                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169702.789055                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189889.488855                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.288498                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1944350                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.567211                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39122099                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1944862                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.115617                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9678062250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   228.929190                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   282.638021                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.447127                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.552027                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999155                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1944870                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.570452                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           39033281                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1945382                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.064584                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9679828500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   227.356025                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   284.214426                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.444055                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.555106                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999161                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          145                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43155983                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43155983                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19191895                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19930204                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39122099                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19191895                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19930204                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39122099                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19191895                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19930204                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39122099                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1041065                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1047869                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2088934                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1041065                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1047869                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2088934                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1041065                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1047869                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2088934                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14016266373                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14162867905                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  28179134278                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14016266373                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  14162867905                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  28179134278                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14016266373                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  14162867905                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  28179134278                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20232960                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20978073                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41211033                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20232960                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20978073                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41211033                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20232960                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20978073                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41211033                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051454                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.049951                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050689                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051454                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.049951                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050689                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051454                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.049951                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050689                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.876417                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.719770                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.876417                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13489.719770                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.876417                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13489.719770                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        10636                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         43073652                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        43073652                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19127800                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19905481                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       39033281                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19127800                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19905481                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        39033281                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19127800                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19905481                       # number of overall hits
+system.cpu0.icache.overall_hits::total       39033281                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1044128                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1050765                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2094893                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1044128                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1050765                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2094893                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1044128                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1050765                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2094893                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14016783986                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14160518990                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  28177302976                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14016783986                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  14160518990                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  28177302976                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14016783986                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  14160518990                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  28177302976                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20171928                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20956246                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41128174                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20171928                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20956246                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     41128174                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20171928                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20956246                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     41128174                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051761                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050141                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050936                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051761                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050141                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050936                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051761                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050141                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050936                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13424.392398                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.390049                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13450.473593                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13424.392398                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.390049                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13450.473593                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13424.392398                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.390049                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13450.473593                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        10866                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              597                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              629                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.815745                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.275040                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71345                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        72638                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       143983                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        71345                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        72638                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       143983                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        71345                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        72638                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       143983                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       969720                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       975231                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1944951                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       969720                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       975231                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1944951                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       969720                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       975231                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1944951                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          666                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total          666                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          666                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total          666                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11896534814                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12012713558                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  23909248372                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11896534814                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12012713558                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  23909248372                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11896534814                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12012713558                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  23909248372                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     52863250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     52863250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     52863250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total     52863250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047195                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047195                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047195                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.813480                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.982380                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.813480                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.982380                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.813480                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.982380                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79374.249249                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79374.249249                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        74230                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        75184                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       149414                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        74230                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        75184                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       149414                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        74230                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        75184                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       149414                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       969898                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       975581                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1945479                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       969898                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       975581                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1945479                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       969898                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       975581                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1945479                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          670                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total          670                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          670                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total          670                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12381694490                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12496898492                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  24878592982                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12381694490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12496898492                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  24878592982                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12381694490                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12496898492                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  24878592982                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     52946500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     52946500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     52946500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total     52946500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047303                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047303                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047303                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12787.901068                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12787.901068                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12787.901068                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27831531                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14488346                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           557776                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17618092                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               13095982                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27779338                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14456404                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           556707                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17586832                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               13077233                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            74.332578                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6872630                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             30030                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            74.358094                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6867114                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29983                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1322,88 +1340,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    58148                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               58148                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20423                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13441                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        24284                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        33864                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   507.057642                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3287.460249                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        33558     99.10%     99.10% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          245      0.72%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           40      0.12%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    59343                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               59343                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20532                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13405                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25406                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        33937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   563.264284                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3642.212390                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        33612     99.04%     99.04% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          250      0.74%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           49      0.14%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           14      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919            8      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        33864                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        11833                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12004.944308                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9742.881321                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7470.572043                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         3519     29.74%     29.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5647     47.72%     77.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2322     19.62%     97.08% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          174      1.47%     98.55% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959           60      0.51%     99.06% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151          104      0.88%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535            3      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        11833                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  89903617428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.686126                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.480378                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  89833985928     99.92%     99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     50516000      0.06%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5      9974500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      3130500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      1885500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1212500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       715000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      1356000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       345000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       227000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21        44000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23        32500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25        52500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        22500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29        23000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31        95000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  89903617428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3585     68.60%     68.60% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1641     31.40%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5226                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58148                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        33937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        12361                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12657.592428                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10412.763280                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7705.801044                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         3725     30.14%     30.14% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5842     47.26%     77.40% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2426     19.63%     97.02% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          136      1.10%     98.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959          110      0.89%     99.01% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151          110      0.89%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::73728-81919            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        12361                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  85582012132                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.698276                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.478879                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  85506656132     99.91%     99.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     54226500      0.06%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     10815500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      3396500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2104000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1227000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       804500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      1696500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       468000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       271500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21       107000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        23500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25       101500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29        14000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31        85500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  85582012132                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3538     68.22%     68.22% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1648     31.78%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5186                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59343                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58148                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5226                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59343                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5186                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5226                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        63374                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5186                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        64529                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14522717                       # DTB read hits
-system.cpu1.dtb.read_misses                     49745                       # DTB read misses
-system.cpu1.dtb.write_hits                   10695995                       # DTB write hits
-system.cpu1.dtb.write_misses                     8403                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         177                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14473413                       # DTB read hits
+system.cpu1.dtb.read_misses                     50516                       # DTB read misses
+system.cpu1.dtb.write_hits                   10662986                       # DTB write hits
+system.cpu1.dtb.write_misses                     8827                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     454                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3436                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      922                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1213                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3428                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      911                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1182                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      578                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14572462                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10704398                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      534                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14523929                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10671813                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         25218712                       # DTB hits
-system.cpu1.dtb.misses                          58148                       # DTB misses
-system.cpu1.dtb.accesses                     25276860                       # DTB accesses
+system.cpu1.dtb.hits                         25136399                       # DTB hits
+system.cpu1.dtb.misses                          59343                       # DTB misses
+system.cpu1.dtb.accesses                     25195742                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1433,387 +1453,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     7828                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                7828                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2631                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         5055                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          142                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         7686                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1468.839448                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6467.961047                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         7241     94.21%     94.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          210      2.73%     96.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575          113      1.47%     98.41% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           52      0.68%     99.09% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           17      0.22%     99.31% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           18      0.23%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343            9      0.12%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535           10      0.13%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            7      0.09%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::73728-81919            6      0.08%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         7686                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2491                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12581.694099                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10170.903635                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7854.515527                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          763     30.63%     30.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1045     41.95%     72.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          622     24.97%     97.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           29      1.16%     98.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           22      0.88%     99.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            6      0.24%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2491                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  25478819488                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.779989                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.414945                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     5610872428     22.02%     22.02% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    19864341560     77.96%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2357000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         850000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         398500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  25478819488                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1770     75.35%     75.35% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          579     24.65%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2349                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     8383                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                8383                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         3253                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4959                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          171                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         8212                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1247.503653                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  5444.991786                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         7787     94.82%     94.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          188      2.29%     97.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575          140      1.70%     98.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           47      0.57%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           15      0.18%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           15      0.18%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343            8      0.10%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.07%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            4      0.05%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         8212                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2522                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13607.454401                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11346.951670                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7824.124854                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095           43      1.70%      1.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          713     28.27%     29.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          591     23.43%     53.41% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          450     17.84%     71.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           33      1.31%     72.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575          613     24.31%     96.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           21      0.83%     97.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           20      0.79%     98.49% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863           10      0.40%     98.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.12%     99.01% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055           20      0.79%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151            3      0.12%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::53248-57343            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2522                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  25452156488                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.888283                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.315639                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     2847537836     11.19%     11.19% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    22601300152     88.80%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2634500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         584500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          99500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  25452156488                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1775     75.50%     75.50% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          576     24.50%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2351                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7828                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7828                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8383                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8383                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2349                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2349                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10177                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20979938                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7828                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2351                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2351                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10734                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20958158                       # ITB inst hits
+system.cpu1.itb.inst_misses                      8383                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         177                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     454                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2294                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2298                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1372                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1383                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20987766                       # ITB inst accesses
-system.cpu1.itb.hits                         20979938                       # DTB hits
-system.cpu1.itb.misses                           7828                       # DTB misses
-system.cpu1.itb.accesses                     20987766                       # DTB accesses
-system.cpu1.numCycles                       108755615                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20966541                       # ITB inst accesses
+system.cpu1.itb.hits                         20958158                       # DTB hits
+system.cpu1.itb.misses                           8383                       # DTB misses
+system.cpu1.itb.accesses                     20966541                       # DTB accesses
+system.cpu1.numCycles                       108767456                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          40802320                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     108613899                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27831531                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19968612                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     63156510                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3276855                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    120748                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                7463                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              413                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       335058                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       133595                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          290                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20978077                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               379105                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3473                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         106194788                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.229505                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.326126                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          40797494                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     108309619                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27779338                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19944347                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     62902331                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3273623                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    135203                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                7501                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              353                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       608716                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       138611                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          328                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20956250                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               381072                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3851                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         106227312                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.226074                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.322776                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                76382363     71.93%     71.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3967856      3.74%     75.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2509209      2.36%     78.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8248224      7.77%     85.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1616537      1.52%     87.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1210559      1.14%     88.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6288171      5.92%     94.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1186864      1.12%     95.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4785005      4.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                76467157     71.98%     71.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3961882      3.73%     75.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2508117      2.36%     78.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8239256      7.76%     85.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1628076      1.53%     87.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1204845      1.13%     88.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6274984      5.91%     94.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1183680      1.11%     95.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4759315      4.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           106194788                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.255909                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.998697                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                27865394                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             59086633                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 16014101                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1741536                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1486862                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             2014125                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               153633                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              90617334                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               499096                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1486862                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                28829421                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                4993628                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46364703                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16784538                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              7735362                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              86665296                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 1758                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1681489                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                204965                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               5046479                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           89687558                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            399294691                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        96716693                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5355                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             75738735                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13948807                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1608168                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1506785                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10100252                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15391291                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11882778                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2188376                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2888870                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  83375619                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1158159                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 79910899                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            92494                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11441232                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25615832                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        107265                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    106194788                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.752494                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.434563                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           106227312                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.255401                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.995791                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                27883552                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             59140248                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15967546                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1750379                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1485269                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             2004727                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               153597                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              90349816                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               499958                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1485269                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                28837036                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                5092551                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46434989                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16757814                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              7619325                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              86416848                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 2460                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1673796                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                189232                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               4958723                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           89422811                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            398213792                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        96413461                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5558                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             75531757                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13891038                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1607608                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1506576                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 10031791                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15342800                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11846385                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2170677                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2932432                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  83143036                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1157387                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 79677045                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            92227                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       11399767                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     25586754                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        106787                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    106227312                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.750062                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.431163                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           74167073     69.84%     69.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10703729     10.08%     79.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8178605      7.70%     87.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6800959      6.40%     94.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2513016      2.37%     96.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1570037      1.48%     97.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1528184      1.44%     99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             489750      0.46%     99.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             243435      0.23%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           74225476     69.87%     69.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10735161     10.11%     79.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8165707      7.69%     87.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6810651      6.41%     94.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2489155      2.34%     96.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1551071      1.46%     97.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1525154      1.44%     99.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             483878      0.46%     99.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             241059      0.23%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      106194788                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      106227312                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 110018      9.66%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                521312     45.77%     55.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               507746     44.58%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 112109      9.87%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                520489     45.82%     55.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               503315     44.31%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass              151      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             53586361     67.06%     67.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59349      0.07%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              2      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4262      0.01%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14931900     18.69%     85.82% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11328871     14.18%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass              152      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             53438266     67.07%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               58943      0.07%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              2      0.00%     67.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4274      0.01%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14882536     18.68%     85.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11292868     14.17%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              79910899                       # Type of FU issued
-system.cpu1.iq.rate                          0.734775                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1139082                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014254                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         267236203                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         96019084                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     77543645                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11959                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6290                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5191                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              81043377                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6453                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          351971                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              79677045                       # Type of FU issued
+system.cpu1.iq.rate                          0.732545                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1135919                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014257                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         266797245                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         95743822                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     77316154                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              12303                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6570                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5329                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              80806190                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6622                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          349291                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2202451                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2360                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        51509                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1138977                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2194104                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2343                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        51353                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1130901                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       192557                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       108870                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       191600                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       108001                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1486862                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4086013                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               663456                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           84657415                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           129656                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15391291                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11882778                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            585252                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 42277                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               608480                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         51509                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        260306                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       223242                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              483548                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             79294806                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14687602                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           558095                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1485269                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                4109384                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               740435                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           84415132                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           132598                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15342800                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11846385                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            585452                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 40704                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               687401                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         51353                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        260476                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       222264                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              482740                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             79065408                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14638962                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           552436                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       123637                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25906137                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14775343                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11218535                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.729110                       # Inst execution rate
-system.cpu1.iew.wb_sent                      78721983                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     77548836                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 40818570                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 71550295                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       114709                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25822462                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14738058                       # Number of branches executed
+system.cpu1.iew.exec_stores                  11183500                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.726922                       # Inst execution rate
+system.cpu1.iew.wb_sent                      78493230                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     77321483                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 40676282                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 71272745                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.713056                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.570488                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.710888                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.570713                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       11482053                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls        1050894                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           406174                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    103612507                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.706116                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.593552                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       11437303                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls        1050600                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           405128                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    103651619                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.703948                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.590010                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     75208979     72.59%     72.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12628786     12.19%     84.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6551089      6.32%     91.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2721278      2.63%     93.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1429301      1.38%     95.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       940289      0.91%     96.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1888025      1.82%     97.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       437231      0.42%     98.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1807529      1.74%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     75257268     72.61%     72.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12658548     12.21%     84.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6546278      6.32%     91.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2731593      2.64%     93.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1415647      1.37%     95.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       932934      0.90%     96.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1873819      1.81%     97.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       434966      0.42%     98.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1800566      1.74%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    103612507                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            60426665                       # Number of instructions committed
-system.cpu1.commit.committedOps              73162446                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    103651619                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            60242910                       # Number of instructions committed
+system.cpu1.commit.committedOps              72965345                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23932641                       # Number of memory references committed
-system.cpu1.commit.loads                     13188840                       # Number of loads committed
-system.cpu1.commit.membars                     435550                       # Number of memory barriers committed
-system.cpu1.commit.branches                  14000562                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5142                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 64124542                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2721670                       # Number of function calls committed.
+system.cpu1.commit.refs                      23864180                       # Number of memory references committed
+system.cpu1.commit.loads                     13148696                       # Number of loads committed
+system.cpu1.commit.membars                     435175                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13969261                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5270                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 63961435                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2719031                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        49168040     67.20%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57503      0.08%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4262      0.01%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        49039858     67.21%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57036      0.08%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.29% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4271      0.01%     67.29% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.29% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.29% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13188840     18.03%     85.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10743801     14.68%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13148696     18.02%     85.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10715484     14.69%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         73162446                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1807529                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   173729017                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  171875858                       # The number of ROB writes
-system.cpu1.timesIdled                         390006                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2560827                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2437360736                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   60356761                       # Number of Instructions Simulated
-system.cpu1.committedOps                     73092542                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.801880                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.801880                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.554976                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.554976                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                86251314                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               49415173                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    15994                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13022                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                279979126                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29562027                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              148792397                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                795609                       # number of misc regfile writes
+system.cpu1.commit.op_class_0::total         72965345                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1800566                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   173538824                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  171385524                       # The number of ROB writes
+system.cpu1.timesIdled                         389774                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2540144                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2437281840                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   60178217                       # Number of Instructions Simulated
+system.cpu1.committedOps                     72900652                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.807422                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.807422                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.553274                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.553274                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                85982923                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               49280931                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    16090                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13091                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                279167136                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29456801                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              148724045                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                795207                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1904,356 +1926,368 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198975032                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187534443                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36852019                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                0.981278                       # Cycle average of tags in use
-system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         234149213000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.981278                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.061330                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.061330                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36410                       # number of replacements
+system.iocache.tags.tagsinuse                0.981092                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     29                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000796                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         234155624000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.981092                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.061318                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.061318                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
-system.iocache.tags.data_accesses              328227                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide           29                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total           29                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328228                       # Number of tag accesses
+system.iocache.tags.data_accesses              328228                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide           28                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total            28                       # number of WriteLineReq hits
 system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36195                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36195                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36196                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36196                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     30962377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     30962377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6648903636                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6648903636                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     30962377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     30962377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     30962377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     30962377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     30881877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30881877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4272011566                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4272011566                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30881877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30881877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30881877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30881877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.999199                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999227                       # miss rate for WriteLineReq accesses
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 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124346.895582                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124346.895582                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183696.743639                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183696.743639                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124346.895582                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124346.895582                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124346.895582                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124346.895582                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22802                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124023.602410                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124023.602410                       # average ReadReq miss latency
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+system.iocache.WriteLineReq_avg_miss_latency::total 118024.410598                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124023.602410                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124023.602410                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124023.602410                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124023.602410                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3472                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.567396                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36160                       # number of writebacks
-system.iocache.writebacks::total                36160                       # number of writebacks
+system.iocache.writebacks::writebacks           36161                       # number of writebacks
+system.iocache.writebacks::total                36161                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36195                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36195                       # number of WriteInvalidateReq MSHR misses
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+system.iocache.WriteLineReq_mshr_misses::total        36196                       # number of WriteLineReq MSHR misses
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 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17850377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17850377                       # number of ReadReq MSHR miss cycles
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-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4766725674                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17850377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17850377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17850377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17850377                       # number of overall MSHR miss cycles
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+system.iocache.WriteLineReq_mshr_miss_latency::total   2462211566                       # number of WriteLineReq MSHR miss cycles
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-system.iocache.overall_avg_mshr_miss_latency::total 71688.261044                       # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 74023.602410                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104656                       # number of replacements
-system.l2c.tags.tagsinuse                65129.158587                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3113742                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169901                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    18.326802                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104591                       # number of replacements
+system.l2c.tags.tagsinuse                65128.853062                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5158175                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169835                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    30.371684                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48669.329761                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    43.033999                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   48560.603393                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    44.868379                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000245                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4678.591805                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2387.812073                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    44.916630                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5867.753400                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3437.720673                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.742635                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000657                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     4741.126354                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2359.678514                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    45.227842                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5921.248068                       # Average occupied blocks per requestor
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-system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          366                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::3         9051                       # Occupied blocks per task id
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-system.l2c.ReadReq_hits::cpu0.data             268247                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        36362                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.data             274193                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2555184                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          704443                       # number of Writeback hits
-system.l2c.Writeback_hits::total               704443                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              48                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              39                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  87                       # number of UpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::cpu1.data            32                       # number of SCUpgradeReq hits
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-system.l2c.overall_hits::cpu0.data             351100                       # number of overall hits
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-system.l2c.overall_hits::cpu1.data             347502                       # number of overall hits
-system.l2c.overall_hits::total                2711346                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           68                       # number of ReadReq misses
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+system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          365                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3250                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         9056                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52484                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_percent::1024     0.994415                       # Percentage of cache occupancy per task id
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+system.l2c.tags.data_accesses                45590460                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        36255                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         7974                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        36433                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         8351                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  89013                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          703579                       # number of Writeback hits
+system.l2c.Writeback_hits::total               703579                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              56                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              38                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  94                       # number of UpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::cpu1.data            29                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                48                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_hits::cpu1.data            72292                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               156179                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        959569                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        964750                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1924319                       # number of ReadCleanReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.970455                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.969160                       # miss rate for UpgradeReq accesses
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-system.l2c.overall_miss_rate::total          0.061236                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87084.558824                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        68750                       # average ReadReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2262,240 +2296,251 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.460440                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.488289                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.473698                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010730                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.024465                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.029613                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027052                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001927                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000125                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.181238                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001972                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.183486                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.061169                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001927                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000125                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.181238                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001972                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.183486                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.061169                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 74776.223776                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20791.298436                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20745.245642                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.032931                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 33062.500000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        21000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28423.076923                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73402.215517                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73016.156154                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73212.760281                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72351.578594                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76518.083850                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78415.409678                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77562.047673                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73671.573507                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73595.211596                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 73483.090475                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73671.573507                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73595.211596                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 73483.090475                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177536.392214                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177581.110730                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.520772                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137239.209858                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178144.468736                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.563225                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157630.020495                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177828.689470                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.475607                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               68118                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68117                       # Transaction distribution
+system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68122                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::Writeback            131657                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36194                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36194                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              9                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4635                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138750                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138750                       # Transaction distribution
+system.membus.trans_dist::Writeback            131744                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9021                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4618                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             13                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4631                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138685                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138685                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36326                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36195                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36195                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465313                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       572881                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 681695                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       474277                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       581847                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 690677                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17344028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17507933                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4631616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22139549                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17345628                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17509597                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2315264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19824861                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              523                       # Total snoops (count)
-system.membus.snoop_fanout::samples            406994                       # Request fanout histogram
+system.membus.snoop_fanout::samples            416234                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  406994    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  416234    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              406994                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95655500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              416234                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95824000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               16812                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1658000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1684000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1067096296                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           923050293                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1022750121                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1019598366                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37540981                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64439557                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2528,50 +2573,53 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2657014                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2656928                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             154492                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2656868                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           704443                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2822                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            55                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2876                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296803                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296803                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3891000                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2536661                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42360                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169075                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6639096                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124504512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99962077                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        64700                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       291504                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224822793                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           70210                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3724954                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.042649                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.202064                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback           835335                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2054815                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2828                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            61                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2888                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296748                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296748                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1945479                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       556983                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        36195                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5795514                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2675972                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42691                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169160                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8683337                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124535936                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99845469                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        65304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       291320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              224738029                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          211435                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5959204                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.050368                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.218703                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3566090     95.74%     95.74% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 158864      4.26%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5659051     94.96%     94.96% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 300153      5.04%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3724954                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2562504434                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5959204                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3608244499                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           246000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2923288858                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2920237464                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1353663761                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1326853963                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          26203715                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          26388950                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          96601513                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          96751648                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3039                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 99e4aebe7..d3ad4a453 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.477179                       # Number of seconds simulated
-sim_ticks                                47477179149500                       # Number of ticks simulated
-final_tick                               47477179149500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.482330                       # Number of seconds simulated
+sim_ticks                                47482329862000                       # Number of ticks simulated
+final_tick                               47482329862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 181000                       # Simulator instruction rate (inst/s)
-host_op_rate                                   212908                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9614368962                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 772236                       # Number of bytes of host memory used
-host_seconds                                  4938.15                       # Real time elapsed on the host
-sim_insts                                   893806699                       # Number of instructions simulated
-sim_ops                                    1051369194                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 176341                       # Simulator instruction rate (inst/s)
+host_op_rate                                   207374                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9393535208                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769764                       # Number of bytes of host memory used
+host_seconds                                  5054.79                       # Real time elapsed on the host
+sim_insts                                   891365561                       # Number of instructions simulated
+sim_ops                                    1048233259                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       125376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       108736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7965248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         14333320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     15086080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       149568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       136256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3627008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         11510096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14847104                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        436288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68325080                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7965248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3627008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11592256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     80335616                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       124416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       101184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          8041216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         40378184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     15310528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       143616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       132928                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3236032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         17140560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     13345792                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        446144                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             98400600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      8041216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3236032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11277248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78262528                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          80356200                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1959                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            124457                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            223971                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       235720                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2337                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2129                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56672                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            179858                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       231986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6817                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1067605                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1255244                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78283112                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1944                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1581                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            125644                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            630922                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       239227                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2244                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2077                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             50563                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            267834                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       208528                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6971                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1537535                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1222852                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1257818                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2641                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              167770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              301899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       317754                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               76395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              242434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       312721                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9189                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1439114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         167770                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          76395                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             244165                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1692089                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1225426                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2131                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              169352                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              850383                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       322447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3025                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2800                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               68152                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              360988                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       281069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2072363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         169352                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          68152                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             237504                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1648245                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1692523                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1692089                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2290                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             167770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             302333                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       317754                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              76395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             242434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       312721                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3131637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1067605                       # Number of read requests accepted
-system.physmem.writeReqs                      1929186                       # Number of write requests accepted
-system.physmem.readBursts                     1067605                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1929186                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 68309056                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     17664                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 120257344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  68325080                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              123323752                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      276                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   50133                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         117648                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               62386                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               65796                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               60427                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               63507                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               66319                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               73621                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               69221                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               63591                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               61143                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              115825                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              59973                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              66407                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              58867                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              61123                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              58743                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              60380                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              115877                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              122877                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              115996                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              119851                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              119313                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              126432                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              119028                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              120185                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              118113                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              119452                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             113141                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             117109                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             112676                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             113553                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             112771                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             112647                       # Per bank write bursts
+system.physmem.bw_write::total                1648679                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1648245                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2131                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             169352                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             850817                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       322447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2800                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              68152                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             360988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       281069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3721041                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1537535                       # Number of read requests accepted
+system.physmem.writeReqs                      1225426                       # Number of write requests accepted
+system.physmem.readBursts                     1537535                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1225426                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 98362112                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     40128                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78282112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  98400600                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78283112                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      627                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         220170                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               94941                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               98803                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               90365                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              103122                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               90513                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              102407                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               86370                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               97727                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               90531                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              141203                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              86748                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              95428                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              92596                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              93840                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              85305                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              87009                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               77173                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               80360                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               74652                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               83758                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75004                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               81344                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               71841                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               79366                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               74851                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               75375                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              73319                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              78054                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              76445                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              77751                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              70793                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              73072                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         226                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47477177227000                       # Total gap between requests
+system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47482327991500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1067575                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1537505                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1926612                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    704225                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    128672                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     50762                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     38076                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     32557                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     29624                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     27261                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     24554                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     21025                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      5650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      763                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      566                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      265                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      210                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       70                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1222852                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    944383                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    373776                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::6                     25089                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     22356                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     19759                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4466                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1975                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1145                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,153 +188,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::17                    93465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   105702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   113971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   112162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   108444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   104050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   100974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    97727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    97663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   116214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   104741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   100206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   114790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   102548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    96204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    91928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     7498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     6040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     6647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     7551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     7971                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::39                     6845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     7426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     5746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     5672                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49                     2570                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52                      919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1025                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57                      623                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63                      704                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1080190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      174.567156                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     106.861850                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     244.135229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         694007     64.25%     64.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       206792     19.14%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        51978      4.81%     88.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24974      2.31%     90.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18580      1.72%     92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11712      1.08%     93.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8387      0.78%     94.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7821      0.72%     94.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        55939      5.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1080190                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         83578                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.770071                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      136.461901                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          83575    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           83578                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         83578                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.482244                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.955849                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.755182                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-31            75860     90.77%     90.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-63            5202      6.22%     96.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95            1276      1.53%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127            755      0.90%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159           241      0.29%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191           100      0.12%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223            48      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255             8      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287             9      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-319            10      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-351            17      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383            25      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-447             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-575             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-671             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-703             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::992-1023            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1056-1087            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           83578                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40962619238                       # Total ticks spent queuing
-system.physmem.totMemAccLat               60975037988                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5336645000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       38378.62                       # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::1024-1151        44462      4.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         940608                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         69828                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.009810                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-4095          69825    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           69828                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         69828                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.516727                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.040521                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::16-19           66194     94.80%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1213      1.74%     96.53% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::52-55              28      0.04%     98.98% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::64-67             437      0.63%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              36      0.05%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              59      0.08%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              38      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              18      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.93% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::128-131            30      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.01%     99.99% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::172-175             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           69828                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    47438420321                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76255445321                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7684540000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       30866.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  57128.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.53                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.60                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  49616.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.07                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.07                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.65                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.20                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     799066                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1067089                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.87                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  56.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15842672.12                       # Average gap between requests
-system.physmem.pageHitRate                      63.34                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4225820760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2305755375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4093954800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6217942320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3100978164960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1196990920755                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27436312080750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31751124639720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.766110                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45642284556030                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1585367160000                       # Time in different power states
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.49                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1237162                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    582295                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.50                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.61                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17185305.18                       # Average gap between requests
+system.physmem.pageHitRate                      65.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3664415160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1999432875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5961079800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4040267040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3101314831680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1200459376170                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27436362274500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31753801677225                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.749891                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45642197013620                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1585539280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    249523460470                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    254592941380                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3940415640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2150028375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4231125600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5958113760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3100978164960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1192295919105                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27440430503250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31749984270690                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.742090                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45649112064952                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1585367160000                       # Time in different power states
+system.physmem_1.actEnergy                 3446581320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1880575125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6026748000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3885796800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3101314831680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1189099091205                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27446327436750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31751981060880                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.711548                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45658799171891                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1585539280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    242698243548                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    237989586859                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -368,15 +379,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              146228375                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        102974776                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6711039                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           109409110                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               78811291                       # Number of BTB hits
+system.cpu0.branchPred.lookups              132987745                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         94268605                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6098049                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           100013530                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               72636793                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.033573                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17518133                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1190785                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.626967                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15695407                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1093856                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -407,62 +418,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   302414                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               302414                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9161                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        80364                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       302414                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         302414    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       302414                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        89525                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        88579     98.94%     98.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          783      0.87%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           49      0.05%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           43      0.05%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           44      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        89525                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    788586204                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      788586204    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    788586204                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        80364     89.77%     89.77% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         9161     10.23%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        89525                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       302414                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   275636                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               275636                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8285                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76005                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       275636                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         275636    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       275636                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        84290                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        79742     94.60%     94.60% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3631      4.31%     98.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          417      0.49%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          355      0.42%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           30      0.04%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           13      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           32      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143            8      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           18      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679           24      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447           12      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        84290                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    669754704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      669754704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    669754704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        76005     90.17%     90.17% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         8285      9.83%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        84290                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       275636                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       302414                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        89525                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       275636                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        84290                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        89525                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       391939                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        84290                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       359926                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    94852147                       # DTB read hits
-system.cpu0.dtb.read_misses                    252189                       # DTB read misses
-system.cpu0.dtb.write_hits                   83443537                       # DTB write hits
-system.cpu0.dtb.write_misses                    50225                       # DTB write misses
+system.cpu0.dtb.read_hits                    84907220                       # DTB read hits
+system.cpu0.dtb.read_misses                    227423                       # DTB read misses
+system.cpu0.dtb.write_hits                   75575788                       # DTB write hits
+system.cpu0.dtb.write_misses                    48213                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   36113                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     2068                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9574                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   35105                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1851                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8962                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10663                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                95104336                       # DTB read accesses
-system.cpu0.dtb.write_accesses               83493762                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10953                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                85134643                       # DTB read accesses
+system.cpu0.dtb.write_accesses               75624001                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        178295684                       # DTB hits
-system.cpu0.dtb.misses                         302414                       # DTB misses
-system.cpu0.dtb.accesses                    178598098                       # DTB accesses
+system.cpu0.dtb.hits                        160483008                       # DTB hits
+system.cpu0.dtb.misses                         275636                       # DTB misses
+system.cpu0.dtb.accesses                    160758644                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -492,187 +507,193 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    66598                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                66598                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          516                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        54284                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        66598                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          66598    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        66598                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        54800                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        53728     98.04%     98.04% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          946      1.73%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607           48      0.09%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           54      0.10%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        54800                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    787865704                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      787865704    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    787865704                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        54284     99.06%     99.06% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          516      0.94%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        54800                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    64906                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                64906                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          453                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52493                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        64906                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          64906    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        64906                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52946                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        48035     90.72%     90.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         3919      7.40%     98.13% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          305      0.58%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          573      1.08%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           22      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           23      0.04%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           32      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143           10      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911           11      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52946                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    669040204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      669040204    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    669040204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        52493     99.14%     99.14% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          453      0.86%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52946                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        66598                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        66598                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        64906                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        64906                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        54800                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        54800                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       121398                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   261387859                       # ITB inst hits
-system.cpu0.itb.inst_misses                     66598                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52946                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52946                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       117852                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   238223958                       # ITB inst hits
+system.cpu0.itb.inst_misses                     64906                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   25865                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24846                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   223375                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   205008                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               261454457                       # ITB inst accesses
-system.cpu0.itb.hits                        261387859                       # DTB hits
-system.cpu0.itb.misses                          66598                       # DTB misses
-system.cpu0.itb.accesses                    261454457                       # DTB accesses
-system.cpu0.numCycles                      1029830596                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               238288864                       # ITB inst accesses
+system.cpu0.itb.hits                        238223958                       # DTB hits
+system.cpu0.itb.misses                          64906                       # DTB misses
+system.cpu0.itb.accesses                    238288864                       # DTB accesses
+system.cpu0.numCycles                       971262699                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  487755400                       # Number of instructions committed
-system.cpu0.committedOps                    573075495                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     47715438                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4391                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93925247519                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.111367                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.473627                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  437915417                       # Number of instructions committed
+system.cpu0.committedOps                    515248827                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     45685554                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4508                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93994129820                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.217923                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.450872                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13314                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      777849504                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      251981092                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5902107                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          475.000126                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          169363182                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5902609                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.692936                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       5093256500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.000126                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.927735                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.927735                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          502                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          153                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.980469                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        359562725                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       359562725                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     86974547                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       86974547                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     77401946                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      77401946                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       298185                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       298185                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       275916                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       275916                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1961524                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1961524                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1923644                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1923644                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    164376493                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       164376493                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    164674678                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      164674678                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3650210                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3650210                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2435892                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2435892                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670224                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       670224                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       817849                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       817849                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       165967                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       165967                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       202383                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       202383                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      6086102                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6086102                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6756326                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6756326                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  55969500387                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  55969500387                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  47032436273                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  47032436273                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  33507618312                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  33507618312                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2441854002                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2441854002                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4283229947                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4283229947                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1855000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1855000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 103001936660                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 103001936660                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     90624757                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     90624757                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     79837838                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     79837838                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       968409                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       968409                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1093765                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1093765                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2127491                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2127491                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2126027                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2126027                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    170462595                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    170462595                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    171431004                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    171431004                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040278                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.040278                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030510                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.030510                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.692088                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.692088                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.747737                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.747737                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078011                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078011                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095193                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095193                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.035703                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.035703                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.039411                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.039411                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903                       # average StoreCondReq miss latency
+system.cpu0.kern.inst.quiesce                   13434                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      710739035                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      260523664                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5570429                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          501.849943                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          152007137                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5570934                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.285754                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       4974167000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.849943                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.980176                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.980176                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          505                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.986328                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        323765599                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       323765599                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77611950                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       77611950                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69963904                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69963904                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       263445                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       263445                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       169638                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       169638                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1758419                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1758419                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1721710                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1721710                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147575854                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       147575854                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147839299                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      147839299                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3380647                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3380647                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2384184                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2384184                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670394                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       670394                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       781336                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       781336                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       154783                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       154783                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189820                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       189820                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5764831                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5764831                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6435225                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6435225                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  51653726500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  51653726500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  46144722000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  46144722000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  52344211500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  52344211500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2307846500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2307846500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3989603000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3989603000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3214000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3214000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  97798448500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  97798448500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  97798448500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  97798448500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     80992597                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     80992597                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     72348088                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     72348088                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       933839                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       933839                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       950974                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       950974                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1913202                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1913202                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1911530                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1911530                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    153340685                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    153340685                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    154274524                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    154274524                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041740                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.041740                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032954                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.032954                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.717890                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.717890                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.821617                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.821617                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.080903                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.080903                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099303                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099303                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037595                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.037595                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041713                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.041713                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -681,161 +702,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3966592                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3966592                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       443574                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       443574                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1010368                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1010368                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data          102                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total          102                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43626                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43626                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           27                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           27                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1453942                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1453942                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1453942                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1453942                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3206636                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3206636                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1425524                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1425524                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       664815                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       664815                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       817747                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       817747                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122341                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       122341                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       202356                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       202356                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4632160                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4632160                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5296975                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5296975                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31604                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30977                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62581                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42580313466                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42580313466                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25667045166                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  25667045166                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14837829930                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14837829930                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  32271814438                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  32271814438                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1568491891                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1568491891                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3969414040                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3969414040                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1696000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1696000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  68247358632                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  68247358632                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  83085188562                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  83085188562                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5612600750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5612600750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5285393252                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5285393252                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10897994002                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10897994002                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035384                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035384                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017855                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017855                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.686502                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.686502                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.747644                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.747644                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057505                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057505                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095180                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095180                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027174                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027174                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030899                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.030899                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3773399                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3773399                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       430069                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       430069                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       999795                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       999795                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data          103                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total          103                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40774                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40774                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           43                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           43                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1429864                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1429864                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1429864                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1429864                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2950578                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2950578                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1384389                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1384389                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       664773                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       664773                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       781233                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       781233                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       114009                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       114009                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189777                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       189777                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4334967                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4334967                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4999740                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4999740                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32882                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32882                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        32815                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        32815                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        65697                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        65697                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40501320500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40501320500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25594559000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  25594559000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15267286500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15267286500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  51557242500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51557242500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1530630500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1530630500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3798446000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3798446000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2841500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2841500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  66095879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  66095879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  81363166000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  81363166000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5911844500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5911844500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5682739500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5682739500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11594584000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11594584000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036430                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036430                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019135                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019135                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.711871                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.711871                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.821508                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.821508                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059591                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059591                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099280                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099280                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032408                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032408                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         10289736                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.930282                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          250868144                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         10290248                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.379213                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      24018555250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.930282                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999864                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          9510825                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.926606                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          228501569                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9511337                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            24.024127                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      29799763000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926606                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999857                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          266                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          431                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        532607059                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       532607059                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    250868144                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      250868144                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    250868144                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       250868144                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    250868144                       # number of overall hits
-system.cpu0.icache.overall_hits::total      250868144                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst     10290257                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     10290257                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst     10290257                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      10290257                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst     10290257                       # number of overall misses
-system.cpu0.icache.overall_misses::total     10290257                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101454150461                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 101454150461                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 101454150461                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 101454150461                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 101454150461                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    261158401                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    261158401                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    261158401                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    261158401                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    261158401                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    261158401                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039402                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.039402                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039402                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.039402                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039402                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.039402                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9859.243599                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9859.243599                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9859.243599                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9859.243599                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9859.243599                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9859.243599                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        485537176                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       485537176                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    228501569                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      228501569                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    228501569                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       228501569                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    228501569                       # number of overall hits
+system.cpu0.icache.overall_hits::total      228501569                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9511346                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9511346                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9511346                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9511346                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9511346                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9511346                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  94734195000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  94734195000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  94734195000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  94734195000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  94734195000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  94734195000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    238012915                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    238012915                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    238012915                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    238012915                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    238012915                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    238012915                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039961                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.039961                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039961                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.039961                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039961                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.039961                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9960.124992                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9960.124992                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9960.124992                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9960.124992                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9960.124992                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9960.124992                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -844,462 +865,490 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10290257                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10290257                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst     10290257                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10290257                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst     10290257                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10290257                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        52307                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        52307                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  91134485035                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  91134485035                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  91134485035                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  91134485035                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  91134485035                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  91134485035                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4833897250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   4833897250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039402                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.039402                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.039402                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8856.385709                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8856.385709                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8856.385709                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9511346                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9511346                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9511346                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9511346                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9511346                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9511346                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total        52292                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total        52292                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  89978522000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  89978522000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  89978522000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  89978522000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  89978522000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  89978522000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4777780500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   4777780500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039961                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.039961                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.039961                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9460.124992                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9460.124992                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9460.124992                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8031555                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8035489                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         3395                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7512189                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7515615                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2942                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1023103                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2858654                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16072.506631                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          16359356                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2874620                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.690963                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      5820437500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7531.283903                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    82.699151                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.479413                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4176.151665                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3206.986567                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   995.905932                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.459673                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005048                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004851                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.254892                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.195739                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.060785                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.980988                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1379                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14509                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          349                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          790                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          240                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           24                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage       975521                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2798117                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16231.650842                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          26314432                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2814109                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            9.350893                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     27335773000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6405.405319                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    66.558250                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    59.359829                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5460.175756                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3311.396146                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   928.755541                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.390955                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004062                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003623                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.333263                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.202112                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056687                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.990701                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1465                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14441                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          296                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          685                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          484                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           25                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           40                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          671                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4595                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6778                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2297                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.084167                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004761                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.885559                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       347615506                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      347615506                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       522089                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       157285                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      9486915                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data      2945564                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total      13111853                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3966591                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3966591                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       220070                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total       220070                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       104135                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       104135                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36121                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36121                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       927424                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       927424                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       522089                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       157285                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      9486915                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3872988                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       14039277                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       522089                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       157285                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      9486915                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3872988                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      14039277                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12017                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8240                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       803341                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data      1047943                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total      1871541                       # number of ReadReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       596217                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::total       596217                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       136954                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       136954                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       166233                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       166233                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       268888                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       268888                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12017                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8240                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       803341                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1316831                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2140429                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12017                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8240                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       803341                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1316831                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2140429                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    431373212                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    321871478                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  24275854446                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  35706676401                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  60735775537                       # number of ReadReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    217330162                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    217330162                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2999502703                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2999502703                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3447611393                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3447611393                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1659499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1659499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13657276886                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  13657276886                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    431373212                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    321871478                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  24275854446                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  49363953287                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  74393052423                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    431373212                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    321871478                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  24275854446                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  49363953287                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  74393052423                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       534106                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       165525                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst     10290256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3993507                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total     14983394                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3966591                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3966591                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       816287                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::total       816287                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       241089                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       241089                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       202354                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       202354                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1196312                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1196312                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       534106                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       165525                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst     10290256                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5189819                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     16179706                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       534106                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       165525                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst     10290256                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5189819                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     16179706                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.078068                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.262412                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.124908                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.730401                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.730401                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.568064                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.568064                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.821496                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.821496                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          821                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4037                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5036                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4531                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089417                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.881409                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       507029075                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      507029075                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       480958                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       155860                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        636818                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3773399                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3773399                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       109301                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       109301                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        35296                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        35296                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       877723                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       877723                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8733791                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      8733791                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2708727                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2708727                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       190451                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       190451                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       480958                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       155860                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      8733791                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3586450                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       12957059                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       480958                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       155860                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      8733791                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3586450                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      12957059                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12195                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8813                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        21008                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       130468                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       130468                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154478                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       154478                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       278567                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       278567                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       777554                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       777554                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1020411                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1020411                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       589182                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       589182                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12195                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8813                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       777554                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1298978                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2097540                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12195                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8813                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       777554                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1298978                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2097540                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    429581500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    328472000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    758053500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2811659500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2811659500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3201796000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3201796000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2748498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2748498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13465224999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  13465224999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  23641079500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  23641079500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33953780489                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33953780489                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  49014503000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  49014503000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    429581500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    328472000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  23641079500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  47419005488                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  71818138488                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    429581500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    328472000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  23641079500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  47419005488                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  71818138488                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       493153                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       164673                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       657826                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3773399                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3773399                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       239769                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       239769                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       189774                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       189774                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1156290                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1156290                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9511345                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      9511345                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3729138                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3729138                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       779633                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       779633                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       493153                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       164673                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      9511345                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      4885428                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     15054599                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       493153                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       164673                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      9511345                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4885428                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     15054599                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.031935                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.544140                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.544140                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.814010                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.814010                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.224764                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.224764                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.078068                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253734                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.132291                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.078068                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253734                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.132291                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30218.617556                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34073.109321                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32452.281589                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   364.515205                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   364.515205                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21901.534114                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21901.534114                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20739.632883                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20739.632883                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 829749.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 829749.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50791.693516                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50791.693516                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30218.617556                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37486.931343                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 34756.141139                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30218.617556                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37486.931343                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 34756.141139                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          127                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240914                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240914                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.081750                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.081750                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.273632                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.273632                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.755717                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.755717                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.081750                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.265888                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.139329                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.081750                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.265888                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.139329                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36084.039414                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21550.567955                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21550.567955                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20726.550059                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20726.550059                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       916166                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       916166                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48337.473567                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48337.473567                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30404.421429                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30404.421429                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33274.612376                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33274.612376                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 83190.767878                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 83190.767878                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30404.421429                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36504.856501                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 34239.222369                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30404.421429                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36504.856501                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 34239.222369                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          127                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1439553                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1439553                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks      1441697                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1441697                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           11                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         1023                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         1037                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           27                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           27                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8712                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         8712                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total         8436                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            8                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          865                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          865                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           68                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total           68                       # number of InvalidateReq MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           11                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9735                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         9749                       # number of demand (read+write) MSHR hits
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 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           11                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9735                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         9749                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12017                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8237                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       803330                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data      1046920                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total      1870504                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       757617                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       757617                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       596190                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       596190                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       136954                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       136954                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       166233                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       166233                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       260176                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       260176                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12017                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1307096                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2130680                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1307096                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      2888297                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        83911                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30977                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       114888                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    267790036                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  19027435054                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  28762264327                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  48410165203                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  36487468285                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  36487468285                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  26018290315                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  26018290315                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2786437286                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2786437286                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2450969244                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2450969244                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1425499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1425499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10771329997                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10771329997                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    267790036                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19027435054                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  39533594324                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  59181495200                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  95668963485                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5359743750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9750814500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5053047499                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5053047499                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10412791249                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14803861999                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.262156                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.124838                       # mshr miss rate for ReadReq accesses
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+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       114790                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total       114790                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       731294                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       731294                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       130468                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       130468                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       154478                       # number of SCUpgradeReq MSHR misses
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       270131                       # number of ReadExReq MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       777546                       # number of ReadCleanReq MSHR misses
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+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       589114                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       589114                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12195                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        32815                       # number of WriteReq MSHR uncacheable
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  35755952523                       # number of HardPFReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2356042000                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  45478624000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  45478624000                       # number of InvalidateReq MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  38548286488                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  93911678511                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5648614500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10008059000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5436600500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5436600500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11085215000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15444659500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.031931                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.730368                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.730368                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.568064                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.568064                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.821496                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821496                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.544140                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.544140                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.814010                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.814010                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.217482                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.217482                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.251858                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.131688                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.251858                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233619                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233619                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081749                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.273400                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.273400                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.755630                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.755630                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.263984                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.138710                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.263984                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.178514                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.187286                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       794166                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       794166                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      17664917                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     15307376                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38492                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        30977                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3966591                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1103078                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1166462                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       816287                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       481802                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       368927                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       516230                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1338230                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1206066                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     20685127                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17177406                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       364539                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1170846                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         39397918                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    661924032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    645723507                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1324200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4272848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1313244587                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    4794163                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     26128529                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.203121                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.402322                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        870203                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     14200168                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        38095                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        32815                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      7469298                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     14383795                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1113522                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       480939                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348630                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       494804                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           46                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1552927                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1165328                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9511346                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6196752                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       886361                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       779633                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28635865                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18059535                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       358708                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1078688                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         48132796                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    612072768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    561022439                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1317384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3945224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1178357815                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   11561310                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     42854991                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.281176                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.449573                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          20821287     79.69%     79.69% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           5307242     20.31%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          30805196     71.88%     71.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          12049795     28.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      26128529                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   15626998682                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      42854991                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   19582200977                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    207003480                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    188679986                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  15540735463                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14347273859                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8534595583                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7985002182                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    199309237                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    194043982                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    637104704                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    585561447                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              125576312                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90437850                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5588126                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            96414800                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               70448335                       # Number of BTB hits
+system.cpu1.branchPred.lookups              137760504                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         98367064                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6188278                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           103396299                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               75843064                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.067968                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               14240452                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            921306                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.351817                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               15930905                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1003913                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1329,67 +1378,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   267188                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               267188                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10577                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85745                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       267188                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         267188    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       267188                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        96322                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        91721     95.22%     95.22% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         3398      3.53%     98.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          602      0.62%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          416      0.43%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           24      0.02%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           24      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           36      0.04%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           19      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           31      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           34      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        96322                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1244507444                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1244507444    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1244507444                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        85745     89.02%     89.02% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10577     10.98%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        96322                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       267188                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   290439                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               290439                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10797                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        87034                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       290439                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         290439    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       290439                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        97831                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        96557     98.70%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1078      1.10%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           36      0.04%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           66      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           60      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        97831                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1532721648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1532721648    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1532721648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        87034     88.96%     88.96% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        10797     11.04%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        97831                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       290439                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       267188                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        96322                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       290439                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97831                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        96322                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       363510                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97831                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       388270                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    79480191                       # DTB read hits
-system.cpu1.dtb.read_misses                    220503                       # DTB read misses
-system.cpu1.dtb.write_hits                   69950509                       # DTB write hits
-system.cpu1.dtb.write_misses                    46685                       # DTB write misses
+system.cpu1.dtb.read_hits                    89204123                       # DTB read hits
+system.cpu1.dtb.read_misses                    242859                       # DTB read misses
+system.cpu1.dtb.write_hits                   77378465                       # DTB write hits
+system.cpu1.dtb.write_misses                    47580                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   40279                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1007                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  7671                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   40087                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1034                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8257                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    12807                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                79700694                       # DTB read accesses
-system.cpu1.dtb.write_accesses               69997194                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11467                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                89446982                       # DTB read accesses
+system.cpu1.dtb.write_accesses               77426045                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        149430700                       # DTB hits
-system.cpu1.dtb.misses                         267188                       # DTB misses
-system.cpu1.dtb.accesses                    149697888                       # DTB accesses
+system.cpu1.dtb.hits                        166582588                       # DTB hits
+system.cpu1.dtb.misses                         290439                       # DTB misses
+system.cpu1.dtb.accesses                    166873027                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1419,187 +1463,192 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    64917                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                64917                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          645                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55496                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        64917                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          64917    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        64917                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        56141                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        54677     97.39%     97.39% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1297      2.31%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           47      0.08%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           81      0.14%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           18      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        56141                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1243919944                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1243919944    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1243919944                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        55496     98.85%     98.85% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          645      1.15%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        56141                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    66791                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                66791                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          712                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57147                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        66791                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          66791    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        66791                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        57859                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        53326     92.17%     92.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         3146      5.44%     97.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          488      0.84%     98.45% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          735      1.27%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           30      0.05%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           27      0.05%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           52      0.09%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           18      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            8      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            9      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        57859                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1533304148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1533304148    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1533304148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        57147     98.77%     98.77% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          712      1.23%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        57859                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        64917                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        64917                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        66791                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        66791                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        56141                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        56141                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       121058                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   225481249                       # ITB inst hits
-system.cpu1.itb.inst_misses                     64917                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        57859                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        57859                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       124650                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   246625416                       # ITB inst hits
+system.cpu1.itb.inst_misses                     66791                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   28543                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   29073                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202570                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   217204                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               225546166                       # ITB inst accesses
-system.cpu1.itb.hits                        225481249                       # DTB hits
-system.cpu1.itb.misses                          64917                       # DTB misses
-system.cpu1.itb.accesses                    225546166                       # DTB accesses
-system.cpu1.numCycles                       849119079                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               246692207                       # ITB inst accesses
+system.cpu1.itb.hits                        246625416                       # DTB hits
+system.cpu1.itb.misses                          66791                       # DTB misses
+system.cpu1.itb.accesses                    246692207                       # DTB accesses
+system.cpu1.numCycles                       916577474                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  406051299                       # Number of instructions committed
-system.cpu1.committedOps                    478293699                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     46606937                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     5644                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 94106060514                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.091162                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.478203                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  453450144                       # Number of instructions committed
+system.cpu1.committedOps                    532984432                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     47678042                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5221                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 94048897478                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.021341                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.494721                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5757                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      666946808                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      182172271                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5052284                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          457.990994                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          141727438                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5052796                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.049309                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8380007678500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.990994                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.894514                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.894514                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                    5293                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      728135326                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      188442148                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5347951                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          430.817141                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          158458993                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5348463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.627015                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8387659413500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.817141                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841440                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.841440                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        301466109                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       301466109                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     72704936                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       72704936                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     65165576                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      65165576                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       206723                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       206723                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        46881                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total        46881                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1586345                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1586345                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1544117                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1544117                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    137870512                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       137870512                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    138077235                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      138077235                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3207186                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3207186                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2249159                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2249159                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       660232                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       660232                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       426407                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       426407                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       160976                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       160976                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       201965                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       201965                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5456345                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5456345                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6116577                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6116577                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  49733165026                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  49733165026                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  39916128019                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  39916128019                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  12105984043                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  12105984043                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2535632453                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2535632453                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4276755567                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4276755567                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1256500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1256500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  89649293045                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  89649293045                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  89649293045                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  89649293045                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     75912122                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     75912122                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     67414735                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     67414735                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       866955                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       866955                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       473288                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       473288                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1747321                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1747321                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1746082                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1746082                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    143326857                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    143326857                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    144193812                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    144193812                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.042249                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.042249                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.033363                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.033363                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.761553                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.761553                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.900946                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.900946                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092127                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092127                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.115668                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.115668                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038069                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038069                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042419                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.042419                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        335833986                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       335833986                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     81837847                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       81837847                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     72225758                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      72225758                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       239509                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       239509                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       145455                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       145455                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1785819                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1785819                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1759762                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1759762                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    154063605                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       154063605                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    154303114                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      154303114                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3469404                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3469404                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2254005                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2254005                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       641263                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       641263                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       468533                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       468533                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       172541                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       172541                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       196757                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       196757                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5723409                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5723409                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6364672                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6364672                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  51425230000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  51425230000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  38096829500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  38096829500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  16555952500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  16555952500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2623224000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2623224000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4131954500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4131954500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2147500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2147500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  89522059500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  89522059500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  89522059500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  89522059500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     85307251                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     85307251                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     74479763                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     74479763                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       880772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       880772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       613988                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       613988                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1958360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1958360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1956519                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1956519                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    159787014                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    159787014                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    160667786                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    160667786                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040670                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.040670                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030263                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030263                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.728069                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.728069                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.763098                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.763098                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088105                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088105                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100565                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100565                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035819                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.035819                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039614                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.039614                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1608,161 +1657,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3294639                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3294639                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       376716                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       376716                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       934861                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       934861                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           50                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           50                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39920                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39920                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           26                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           26                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1311577                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1311577                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1311577                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1311577                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2830470                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2830470                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1314298                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1314298                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       659943                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       659943                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       426357                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       426357                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       121056                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       121056                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       201939                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       201939                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4144768                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4144768                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4804711                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4804711                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7026                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7026                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14541                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14541                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38398702439                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38398702439                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21764603493                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21764603493                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13372610673                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13372610673                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  11459992206                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  11459992206                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1620200910                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1620200910                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3963729421                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3963729421                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1148000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1148000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  60163305932                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  60163305932                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  73535916605                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  73535916605                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    828088750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    828088750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    987688750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    987688750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1815777500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1815777500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037286                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037286                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019496                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019496                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.761219                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.761219                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.900841                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.900841                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069281                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069281                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.115653                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.115653                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028918                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028918                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033321                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033321                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3440440                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3440440                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       392659                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       392659                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       925831                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       925831                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           46                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           46                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41204                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41204                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           43                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           43                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1318490                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1318490                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1318490                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1318490                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3076745                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3076745                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1328174                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1328174                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       640972                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       640972                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       468487                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       468487                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       131337                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       131337                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       196714                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       196714                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4404919                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4404919                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5045891                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5045891                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5366                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5366                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5280                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5280                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10646                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10646                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41480566500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41480566500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21714665000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21714665000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12811841000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12811841000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  16084660000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  16084660000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1751023000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1751023000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3933903500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3933903500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63195231500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  63195231500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  76007072500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  76007072500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    593786000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    593786000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    651165500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    651165500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1244951500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1244951500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036067                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036067                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017833                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017833                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.727739                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.727739                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.763023                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.763023                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067065                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067065                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100543                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100543                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027567                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027567                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031406                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031406                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          8512500                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.044267                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          216759728                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          8513012                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.462166                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8369990866500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.044267                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990321                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990321                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          9156821                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.982135                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          237244674                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9157333                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.907617                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8375787773000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.982135                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990199                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990199                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          336                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        459058494                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       459058494                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    216759728                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      216759728                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    216759728                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       216759728                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    216759728                       # number of overall hits
-system.cpu1.icache.overall_hits::total      216759728                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      8513013                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      8513013                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      8513013                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       8513013                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      8513013                       # number of overall misses
-system.cpu1.icache.overall_misses::total      8513013                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  85304905568                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  85304905568                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  85304905568                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  85304905568                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  85304905568                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  85304905568                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    225272741                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    225272741                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    225272741                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    225272741                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    225272741                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    225272741                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037790                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037790                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037790                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037790                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037790                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037790                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10020.530401                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10020.530401                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        501961349                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       501961349                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    237244674                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      237244674                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    237244674                       # number of demand (read+write) hits
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+system.cpu1.icache.overall_hits::cpu1.inst    237244674                       # number of overall hits
+system.cpu1.icache.overall_hits::total      237244674                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9157334                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9157334                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9157334                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9157334                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9157334                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9157334                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  90409615500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  90409615500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  90409615500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  90409615500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  90409615500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  90409615500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    246402008                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    246402008                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    246402008                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    246402008                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    246402008                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    246402008                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037164                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.037164                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037164                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.037164                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037164                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.037164                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9872.918854                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9872.918854                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9872.918854                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9872.918854                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9872.918854                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9872.918854                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1771,241 +1820,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8513013                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      8513013                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      8513013                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      8513013                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      8513013                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      8513013                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total           90                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total           90                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  76768195856                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  76768195856                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  76768195856                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  76768195856                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  76768195856                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  76768195856                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8107000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8107000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8107000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8107000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037790                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.037790                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.037790                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9017.746814                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9017.746814                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9017.746814                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9157334                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9157334                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9157334                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9157334                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9157334                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9157334                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  85830949000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  85830949000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  85830949000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  85830949000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  85830949000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  85830949000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8848000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8848000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8848000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8848000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037164                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.037164                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.037164                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9372.918908                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9372.918908                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9372.918908                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7158191                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7159863                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         1351                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7355033                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7356454                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         1193                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       847001                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2383886                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13587.340153                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          13938188                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2400056                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.807443                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10048790087250                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4939.758457                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    75.017087                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    74.049784                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4551.314512                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3187.549823                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   759.650489                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.301499                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004579                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004520                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.277790                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.194553                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.046365                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.829305                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1323                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14780                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           42                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          433                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          562                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1093                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4947                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2638                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5915                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.080750                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004089                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.902100                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       292928618                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      292928618                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       489959                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155192                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      7753793                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2612837                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total      11011781                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3294638                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3294638                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       173190                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       173190                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        70896                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        70896                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35338                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        35338                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       862674                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       862674                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       489959                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155192                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      7753793                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3475511                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       11874455                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       489959                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155192                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      7753793                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3475511                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      11874455                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11727                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8782                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       759220                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data       998421                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1778150                       # number of ReadReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       251764                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       251764                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       136318                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       136318                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       166600                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       166600                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       246181                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       246181                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11727                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8782                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       759220                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1244602                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2024331                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11727                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8782                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       759220                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1244602                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2024331                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    449146209                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    373707270                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  22071218543                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  32673719778                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  55567791800                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    216255594                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    216255594                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2967566092                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2967566092                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3447328545                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3447328545                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1119500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1119500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10839077173                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10839077173                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    449146209                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    373707270                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22071218543                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  43512796951                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  66406868973                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    449146209                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    373707270                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22071218543                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  43512796951                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  66406868973                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       501686                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       163974                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      8513013                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3611258                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total     12789931                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3294638                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3294638                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       424954                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       424954                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207214                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       207214                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       201938                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       201938                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1108855                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1108855                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       501686                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       163974                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      8513013                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4720113                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     13898786                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       501686                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       163974                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      8513013                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4720113                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     13898786                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.089183                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.276475                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.139027                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.592450                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.592450                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.657861                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.657861                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.825006                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.825006                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       921370                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2420449                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13525.501015                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          25921683                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2436577                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           10.638565                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9890893366500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5242.566110                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    80.941753                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    86.247702                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3561.549924                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3753.026790                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   801.168735                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.319981                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004940                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.217380                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.229067                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048899                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.825531                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1192                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14878                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          534                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          335                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           39                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1163                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5423                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4799                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3398                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.072754                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003540                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.908081                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       488189494                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      488189494                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       527706                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       160378                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        688084                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3440434                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3440434                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        69060                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        69060                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        37815                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        37815                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       888572                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       888572                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8367748                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      8367748                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2856681                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2856681                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022220                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050512                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.028964                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
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+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.663629                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.807763                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.222014                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.222014                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.089183                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.263681                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.145648                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.089183                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.263681                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.145648                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29070.912967                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32725.393174                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31250.339848                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   858.961543                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   858.961543                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21769.436846                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21769.436846                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20692.248169                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20692.248169                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1119500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1119500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44028.894078                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44028.894078                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29070.912967                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34961.214068                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32804.353129                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29070.912967                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34961.214068                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32804.353129                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.209825                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.209825                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.086224                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.086224                       # miss rate for ReadCleanReq accesses
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+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.583367                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022220                       # miss rate for demand accesses
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+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21775.546976                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20797.542396                       # average SCUpgradeReq miss latency
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+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 440999.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 440999.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41994.200103                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41994.200103                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28153.127082                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28153.127082                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31809.177113                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31809.177113                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51473.366856                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51473.366856                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37223.315544                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41495.253165                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28153.127082                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33766.175939                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31644.312655                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37223.315544                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41495.253165                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28153.127082                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33766.175939                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31644.312655                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2014,214 +2079,236 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1051021                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1051021                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          699                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          701                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            6                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            6                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         8312                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         8312                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         9011                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         9013                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         9011                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         9013                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11727                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8782                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       759218                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       997722                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total      1777449                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       732693                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       732693                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       251758                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       251758                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       136318                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       136318                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       166600                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       166600                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
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-system.cpu1.l2cache.ReadExReq_mshr_misses::total       237869                       # number of ReadExReq MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1235591                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total      2748011                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7026                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7116                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14541                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14631                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  17115860957                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  26083443690                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  43887496684                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  35590505004                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  35590505004                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   8154289208                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   8154289208                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2662634544                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2662634544                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2448254099                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2448254099                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       937500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       937500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8085398810                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8085398810                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17115860957                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34168842500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  51972895494                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17115860957                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34168842500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  35590505004                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  87563400498                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7349000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    771832750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    779181750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    931317500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    931317500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7349000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1703150250                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1710499250                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.276281                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.138973                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks      1031306                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1031306                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.InvalidateReq_mshr_hits::total           17                       # number of InvalidateReq MSHR hits
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+system.cpu1.l2cache.Writeback_mshr_misses::total            3                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       115811                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total       115811                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       714965                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       158895                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       158895                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       789585                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       789585                       # number of ReadCleanReq MSHR misses
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       272632                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       272632                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2745430                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5366                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5459                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5280                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5280                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10646                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10739                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    677246000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30632454632                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  30632454632                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2763352994                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2763352994                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2438062999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2438062999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1505998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1505998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7634474497                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7634474497                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  17491788500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  17491788500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25566861991                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25566861991                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  12398047000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  12398047000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17491788500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33201336488                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  51370370988                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17491788500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33201336488                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30632454632                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  82002825620                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8104000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    550842500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    558946500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    611561500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    611561500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8104000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1162404000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1170508000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028961                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.592436                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.592436                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.657861                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.657861                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825006                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.825006                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.663629                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.663629                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.807763                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.807763                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.214518                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.214518                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.261771                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.145000                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.261771                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.203570                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.203570                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.086224                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.257602                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257602                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.583331                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.583331                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245384                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136831                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245384                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.197716                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       937500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       937500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.185012                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      15573132                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13012901                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38492                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         7515                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3294638                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1065592                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1119456                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       424954                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       452600                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       368137                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       473527                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           37                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1269149                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1115295                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17026205                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     14595450                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       357835                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1096931                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         33076421                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    544838528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    546511254                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1311792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4013488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1096675062                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5302361                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     23181233                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.250406                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.433247                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        927149                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     13939785                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38095                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5280                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      7136333                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict     14143122                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1073027                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       445884                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       351130                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       465721                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1873672                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1132302                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9157334                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6348630                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       574099                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       467371                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27470555                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17217135                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       368278                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1176846                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         46232814                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    586075264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    544882505                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1351280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4317584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1136626633                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   12009621                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     42070384                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.298426                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.457567                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          17376502     74.96%     74.96% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           5804731     25.04%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          29515487     70.16%     70.16% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          12554897     29.84%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      23181233                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   12806281931                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      42070384                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   18619089977                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    180531485                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    181245984                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  12781520856                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  13738184900                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7568960857                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7905383000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    194234943                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    199375485                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    595690418                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    637173449                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40349                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40349                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136610                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29882                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47640                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136608                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136608                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47696                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2231,18 +2318,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122574                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231264                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231264                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122578                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231202                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231202                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353918                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47660                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353860                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47716                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2252,18 +2339,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155681                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155708                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338824                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338824                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496839                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36172000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496618                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36211000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2283,7 +2370,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2291,778 +2378,754 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607512131                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569805082                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92695000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92701000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148588668                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147898000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              170500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115637                       # number of replacements
-system.iocache.tags.tagsinuse               11.310069                       # Cycle average of tags in use
+system.iocache.tags.replacements               115582                       # number of replacements
+system.iocache.tags.tagsinuse               11.293791                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115653                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115598                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9129457632000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.399895                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.910174                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.462493                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.244386                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706879                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9174209621000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.830929                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.462862                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.239433                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466429                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705862                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041045                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041045                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040766                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040766                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8941                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8873                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8910                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8904                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8944                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8873                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8913                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8904                       # number of overall misses
-system.iocache.overall_misses::total             8944                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5195500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1622865167                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1628060667                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8873                       # number of overall misses
+system.iocache.overall_misses::total             8913                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1631093968                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1636288968                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19842621296                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19842621296                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5564500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1622865167                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1628429667                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5564500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1622865167                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1628429667                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12624582114                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12624582114                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1631093968                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1636657968                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1631093968                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1636657968                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8941                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8873                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8910                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8904                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8944                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8873                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8913                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8904                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8944                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8873                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8913                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182089.326362                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183646.348822                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 182262.485063                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182069.506597                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 182262.485063                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182069.506597                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        110288                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 183826.661558                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183625.936048                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 183826.661558                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183625.936048                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31363                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16227                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3550                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.796574                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.834648                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106703                       # number of writebacks
-system.iocache.writebacks::total               106703                       # number of writebacks
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8904                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8941                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8873                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8910                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8904                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8944                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8873                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8913                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8904                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8944                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3270500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1158690425                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1161960925                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14292687374                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14292687374                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3483500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1158690425                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1162173925                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3483500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1158690425                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1162173925                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8873                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8913                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1187443968                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1190788968                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7288182114                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7288182114                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1187443968                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1191007968                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1187443968                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1191007968                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 129938.945103                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 129938.945103                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133625.936048                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133625.936048                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1500558                       # number of replacements
-system.l2c.tags.tagsinuse                64423.791175                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5010724                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1561220                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.209493                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               8774171000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   18406.054563                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   163.983954                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   204.641755                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4710.197783                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8659.570147                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11639.948556                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   186.392680                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   219.831325                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3870.715230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     6776.772016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9585.683167                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.280854                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002502                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003123                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.071872                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.132135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.177612                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002844                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003354                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.059062                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.103405                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.146266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9890                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50532                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           96                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          403                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9383                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          240                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1652                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5116                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        43541                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.150909                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.771057                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 65146304                       # Number of tag accesses
-system.l2c.tags.data_accesses                65146304                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         6273                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4042                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             730934                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             606426                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       316069                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6330                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         4616                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             702346                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             568034                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       305702                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                3250772                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2490573                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2490573                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       135019                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       128371                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       263390                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           28214                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           29967                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               58181                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6140                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          6184                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12324                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            50287                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53122                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               103409                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6273                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4042                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              730934                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              656713                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       316069                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6330                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4616                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              702346                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              621156                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       305702                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3354181                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6273                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4042                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             730934                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             656713                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       316069                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6330                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4616                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             702346                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             621156                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       305702                       # number of overall hits
-system.l2c.overall_hits::total                3354181                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1959                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1699                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            72396                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           144803                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       235787                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2337                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2129                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            56871                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           125845                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       232153                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               875979                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       452629                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       114950                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       567579                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         49085                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         42979                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             92064                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9286                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         8933                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18219                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          81593                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          56532                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             138125                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1959                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1699                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             72396                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            226396                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       235787                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2337                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2129                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             56871                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            182377                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       232153                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1014104                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1959                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1699                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            72396                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           226396                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       235787                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2337                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2129                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            56871                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           182377                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       232153                       # number of overall misses
-system.l2c.overall_misses::total              1014104                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    183693028                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    155473534                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   6124405792                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  13529784764                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    209221515                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    197082496                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   4800216916                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  11513015623                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    98828755334                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     50831909                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     41081201                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total     91913110                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    314052545                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    253554995                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    567607540                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     59571609                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     53385310                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    112956919                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7326457212                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4778922810                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12105380022                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    183693028                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    155473534                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6124405792                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  20856241976                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    209221515                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    197082496                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4800216916                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  16291938433                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    110934135356                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    183693028                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    155473534                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6124405792                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  20856241976                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    209221515                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    197082496                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4800216916                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  16291938433                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   110934135356                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         8232                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         5741                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         803330                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         751229                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       551856                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         8667                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6745                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         759217                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         693879                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       537855                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            4126751                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2490573                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2490573                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       587648                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       243321                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       830969                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        77299                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        72946                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          150245                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15426                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        15117                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30543                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       131880                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       109654                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           241534                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8232                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5741                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          803330                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          883109                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       551856                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8667                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6745                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          759217                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          803533                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       537855                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4368285                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8232                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5741                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         803330                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         883109                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       551856                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8667                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6745                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         759217                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         803533                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       537855                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4368285                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.090120                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.192755                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.074907                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.181364                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.212268                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.770238                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.472421                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.683033                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.635002                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.589189                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.612759                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.601971                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590924                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.596503                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.618691                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.515549                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.571866                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.090120                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.256362                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.074907                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.226969                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.232152                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.090120                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.256362                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.074907                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.226969                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.232152                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84595.914028                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 93435.804258                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84405.354504                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 91485.681775                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 112820.918463                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   112.303695                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   357.383219                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   161.938884                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6398.136804                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5899.508946                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6165.358229                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6415.206655                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5976.190529                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6199.951644                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89792.717660                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84534.826470                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 87640.760340                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 84595.914028                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 92122.837753                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84405.354504                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 89331.102239                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 109391.280733                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 84595.914028                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 92122.837753                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84405.354504                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 89331.102239                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 109391.280733                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              1791                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1460315                       # number of replacements
+system.l2c.tags.tagsinuse                63815.106569                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6243583                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1520944                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.105071                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   17020.262251                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   105.114677                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   114.825043                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4617.432955                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6910.402402                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  7514.168760                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   272.316465                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   336.862323                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3976.770964                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9922.626808                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.259709                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001604                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001752                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.070456                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.105444                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.114657                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004155                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.005140                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.060681                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.151407                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.198735                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.973741                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9634                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          233                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50762                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          214                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          450                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8970                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          232                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2000                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4985                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        43502                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.147003                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003555                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.774567                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 74931302                       # Number of tag accesses
+system.l2c.tags.data_accesses                74931302                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2473005                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2473005                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           29717                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           30251                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               59968                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          5861                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          6611                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             12472                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           174264                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           168948                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               343212                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6955                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5054                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       704009                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       596815                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       296922                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6236                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4142                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       738933                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       577563                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       321187                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3257816                       # number of ReadSharedReq hits
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.595769                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.593842                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.598727                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590625                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.594472                       # miss rate for SCUpgradeReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6235.157564                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6139.657158                       # average UpgradeReq miss latency
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+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5711.889285                       # average SCUpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 92003.086666                       # average ReadExReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 107524.824092                       # average ReadSharedReq miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92715.686275                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 83411.391544                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 93193.137323                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89963.235294                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88832.450650                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82904.740282                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 87115.935018                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 100716.248695                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               107                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       28                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     63.964286                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     35.666667                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1148541                       # number of writebacks
-system.l2c.writebacks::total                  1148541                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst           220                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            34                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst           280                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            31                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               565                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            220                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            280                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             31                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                565                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           220                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           280                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            31                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               565                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1959                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1699                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        72176                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       144769                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2337                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2129                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        56591                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       125814                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          875414                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       452629                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       114950                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total       567579                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        49085                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        42979                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        92064                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9286                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8933                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18219                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        81593                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        56532                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        138125                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1959                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1699                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        72176                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       226362                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2337                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2129                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        56591                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       182346                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1013539                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1959                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1699                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        72176                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       226362                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2337                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2129                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        56591                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       182346                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1013539                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7024                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        91025                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38492                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14539                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       129517                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   5203434958                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11714509236                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   4069447334                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data   9933395627                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  87929902680                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  15184820591                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   3681276299                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total  18866096890                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    873684340                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    765163234                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1638847574                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    165173761                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    159092905                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    324266666                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6306752788                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4071633688                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  10378386476                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   5203434958                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  18021262024                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   4069447334                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  14005029315                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  98308289156                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   5203434958                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  18021262024                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   4069447334                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  14005029315                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  98308289156                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4742528250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5282500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    634028250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8569851750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4479331501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    791938501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5271270002                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9221859751                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5282500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1425966751                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13841121752                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.192710                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.181320                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.212132                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.770238                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.472421                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.683033                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.635002                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.589189                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.612759                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.601971                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590924                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.596503                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.618691                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.515549                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.571866                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.256324                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.226930                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.232022                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.256324                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.226930                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.232022                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085                       # average ReadReq mshr miss latency
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+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.203848                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.218452                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.238282                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.094352                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.451557                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.264623                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.333977                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.063950                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.266924                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.292149                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.218452                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.238282                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.094352                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.451557                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.264623                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.333977                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.063950                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.266924                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.292149                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 90723.447575                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 90723.447575                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              975380                       # Transaction distribution
-system.membus.trans_dist::ReadResp             975380                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38492                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38492                       # Transaction distribution
-system.membus.trans_dist::Writeback           1255244                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       671368                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       671368                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           435292                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         320448                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          117663                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            151367                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133687                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122574                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               90631                       # Transaction distribution
+system.membus.trans_dist::ReadResp             933772                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38095                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38095                       # Transaction distribution
+system.membus.trans_dist::Writeback           1222852                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           259291                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           429274                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         300804                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          113465                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            664837                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           644660                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        843141                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122578                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26446                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5296349                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5445421                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5781341                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155681                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24884                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5299387                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5446901                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5789694                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155708                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177552960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    177762857                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14095872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14095872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191858729                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           658635                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3847839                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49768                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    169409152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    169615952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7274560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7274560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               176890512                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           639479                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3957833                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3847839    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3957833    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3847839                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109654500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3957833                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109447997                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               33484                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21898998                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            20601500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         11397821385                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8645644788                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6506682845                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8381282870                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          152058832                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229327995                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3106,45 +3169,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            5105910                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5098639                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38492                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38492                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2490573                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       937823                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       830969                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          486096                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        332772                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         818868                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302211                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302211                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8322623                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6766752                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15089375                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    277489443                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    218349254                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              495838697                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1695482                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9694113                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.011945                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.108639                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              90633                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           5042509                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38095                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38095                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3695900                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1651242                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          481742                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        313276                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         795018                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          104                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1145784                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1145784                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4959107                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8783138                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7404481                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16187619                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    270950615                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    216626041                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              487576656                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3318184                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         13892424                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.121763                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.327012                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9578315     98.81%     98.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115798      1.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               12200843     87.82%     87.82% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1691581     12.18%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9694113                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8435746901                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           13892424                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8859040198                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2506500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2520000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4797228870                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5187778836                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4287100444                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4493465928                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 505d3c407..df26aa07d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.610037                       # Number of seconds simulated
-sim_ticks                                51610036853000                       # Number of ticks simulated
-final_tick                               51610036853000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.694137                       # Number of seconds simulated
+sim_ticks                                51694136923000                       # Number of ticks simulated
+final_tick                               51694136923000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 188716                       # Simulator instruction rate (inst/s)
-host_op_rate                                   221745                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10246213919                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 724572                       # Number of bytes of host memory used
-host_seconds                                  5036.99                       # Real time elapsed on the host
-sim_insts                                   950561948                       # Number of instructions simulated
-sim_ops                                    1116924449                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 185117                       # Simulator instruction rate (inst/s)
+host_op_rate                                   217521                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10090931944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 725160                       # Number of bytes of host memory used
+host_seconds                                  5122.83                       # Real time elapsed on the host
+sim_insts                                   948323287                       # Number of instructions simulated
+sim_ops                                    1114322939                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       410048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       340288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10352448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          67122824                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        411200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78636808                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10352448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10352448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     95202624                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       407232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       344384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10254400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         100902664                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        404352                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            112313032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10254400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10254400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     94405184                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          95223204                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         6407                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5317                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             161757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1048807                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6425                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1228713                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1487541                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          94425764                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5381                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             160225                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1576617                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6318                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1754904                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1475081                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1490114                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           7945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               200590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1300577                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1523673                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          200590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             200590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1844653                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1845052                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1844653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          7945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              200590                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1300976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3368725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1228713                       # Number of read requests accepted
-system.physmem.writeReqs                      2143008                       # Number of write requests accepted
-system.physmem.readBursts                     1228713                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2143008                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 78600192                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37440                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 133928256                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78636808                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              137008420                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      585                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   50360                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          39728                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               75722                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               79954                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               72878                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               71278                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               72651                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               79829                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               73600                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               73320                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               65239                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              127420                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              73665                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              77478                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              72459                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              72712                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              69098                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              70825                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              130775                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              132563                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              131683                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              133448                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              132375                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              136941                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              129100                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              132855                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              124239                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              131924                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             130753                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             132768                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             128150                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             130180                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             126529                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             128346                       # Per bank write bursts
+system.physmem.num_writes::total              1477654                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6662                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               198367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1951917                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7822                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2172645                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          198367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             198367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1826226                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1826624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1826226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6662                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              198367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1952315                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7822                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3999270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1754904                       # Number of read requests accepted
+system.physmem.writeReqs                      1477654                       # Number of write requests accepted
+system.physmem.readBursts                     1754904                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1477654                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                112259136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     54720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  94423744                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 112313032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               94425764                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      855                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2252                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         146151                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              109407                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              112864                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              109220                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              104188                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              106449                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              113846                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              104146                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              106564                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               99467                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              160932                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             104576                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             109948                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             102336                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             105581                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              99543                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             104982                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               93507                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               95050                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               93111                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               91031                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               92702                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               96804                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               89915                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               93502                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               87351                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               94209                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              90719                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              94851                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              89273                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              92330                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              88747                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              92269                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         140                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51610035211500                       # Total gap between requests
+system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51694135218000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1228698                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1754889                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2140435                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1157126                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     64351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       447                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       546                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       776                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       503                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1798                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       70                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1475081                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1420187                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    327570                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       933                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       482                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       515                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       534                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       776                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       878                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -159,168 +159,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    52200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    61876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   103140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   107216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   115340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   154284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   127380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   116704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   115742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   109222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   108713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   142144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   115995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   122630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   110947                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   107019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   104847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     5575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     6143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     7595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     8109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     7187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     6881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     8026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     6843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     6405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     5844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     5760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1002                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      312                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       733749                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      289.646732                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     167.469062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.982397                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         301017     41.02%     41.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       179214     24.42%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        65174      8.88%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36623      4.99%     79.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        25257      3.44%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        17346      2.36%     85.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13099      1.79%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        11628      1.58%     88.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        84391     11.50%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         733749                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        100720                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.193388                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      124.138953                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023         100718    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          100720                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        100720                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.776698                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.274786                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.101890                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31           96977     96.28%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47            2012      2.00%     98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63             404      0.40%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79             303      0.30%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             157      0.16%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            153      0.15%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           320      0.32%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           134      0.13%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            20      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            11      0.01%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            66      0.07%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            35      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            14      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             5      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             7      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             6      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             7      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             8      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            12      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            21      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             5      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             5      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             5      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::912-927             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          100720                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    16983547454                       # Total ticks spent queuing
-system.physmem.totMemAccLat               40010947454                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6140640000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13828.81                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    15753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    18367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    69542                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    87805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    88303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    88136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    87821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    90771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    91285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    93842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    92895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    93403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    89996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    90062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   102154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    88485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    90293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    86850                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       688077                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      300.376987                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.587339                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.638975                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         270609     39.33%     39.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       164654     23.93%     63.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        63521      9.23%     72.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        36566      5.31%     77.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        27027      3.93%     81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        18739      2.72%     84.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14736      2.14%     86.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        13602      1.98%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        78623     11.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         688077                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         86230                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.341007                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      270.950677                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          86227    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           86230                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         86230                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.109718                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.738195                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        5.845815                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           83739     97.11%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             148      0.17%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             433      0.50%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             182      0.21%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             327      0.38%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             491      0.57%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             146      0.17%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              35      0.04%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              38      0.04%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              19      0.02%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              25      0.03%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              26      0.03%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             445      0.52%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              41      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              34      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              31      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            32      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             8      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           86230                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    26659687931                       # Total ticks spent queuing
+system.physmem.totMemAccLat               59548106681                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8770245000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15198.94                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32578.81                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.60                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.65                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  33948.94                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.17                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.17                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     948457                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1638549                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.23                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.30                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15306733.63                       # Average gap between requests
-system.physmem.pageHitRate                      77.90                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2845387440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1552542750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4674001800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6867115200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3370916218800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1311782988195                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29815330787250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34513969041435                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.745387                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49599639397461                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1723372300000                       # Time in different power states
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1434287                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1107055                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.77                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15991711.59                       # Average gap between requests
+system.physmem.pageHitRate                      78.69                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2644873560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1443135375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6760088400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4831630560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1310236671105                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29867151449250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34569477532170                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.731116                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49685803332014                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1726180820000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    287019858539                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    282152299236                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2701755000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1474171875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4905342000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               6693120720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3370916218800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1303897064130                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29822248264500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34512835937025                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.723432                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49611170347429                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1723372300000                       # Time in different power states
+system.physmem_1.actEnergy                 2556988560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1395182250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6921447000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4728773520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1305311169150                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29871472073250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34568795317650                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.717918                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49692977337193                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1726180820000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    275493728071                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    274978307807                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -344,15 +340,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               260902420                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         182959992                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12222887                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            194114900                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               136429435                       # Number of BTB hits
+system.cpu.branchPred.lookups               260235992                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         182594285                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12181539                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            193306639                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136184729                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.282825                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31730781                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2172348                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.450104                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31573215                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2152291                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -383,61 +379,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    588227                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                588227                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22315                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191623                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       588227                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          588227    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       588227                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       213938                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       211313     98.77%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         2233      1.04%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          146      0.07%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          117      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           91      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    586554                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                586554                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22200                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191198                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       586554                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          586554    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       586554                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       213398                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 26171.173113                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 22678.472578                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15672.620914                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       210833     98.80%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2191      1.03%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          145      0.07%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          108      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           74      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           36      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       213938                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    -15748296                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       -15748296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    -15748296                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        191624     89.57%     89.57% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         22315     10.43%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       213939                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       588227                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       213398                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    -58656296                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       -58656296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    -58656296                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        191199     89.60%     89.60% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         22200     10.40%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       213399                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       586554                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       588227                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213939                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       586554                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213399                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213939                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       802166                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213399                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       799953                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183548892                       # DTB read hits
-system.cpu.dtb.read_misses                     485969                       # DTB read misses
-system.cpu.dtb.write_hits                   162881584                       # DTB write hits
-system.cpu.dtb.write_misses                    102258                       # DTB write misses
+system.cpu.dtb.read_hits                    183104972                       # DTB read hits
+system.cpu.dtb.read_misses                     484611                       # DTB read misses
+system.cpu.dtb.write_hits                   162443368                       # DTB write hits
+system.cpu.dtb.write_misses                    101943                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               47246                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    79791                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       811                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15585                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    80156                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       829                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  15457                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23526                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                184034861                       # DTB read accesses
-system.cpu.dtb.write_accesses               162983842                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23578                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                183589583                       # DTB read accesses
+system.cpu.dtb.write_accesses               162545311                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         346430476                       # DTB hits
-system.cpu.dtb.misses                          588227                       # DTB misses
-system.cpu.dtb.accesses                     347018703                       # DTB accesses
+system.cpu.dtb.hits                         345548340                       # DTB hits
+system.cpu.dtb.misses                          586554                       # DTB misses
+system.cpu.dtb.accesses                     346134894                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -467,341 +463,345 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    136538                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                136538                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1085                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       118818                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       136538                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          136538    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       136538                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       119903                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27208.529278                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       116996     97.58%     97.58% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         2625      2.19%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          168      0.14%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           53      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           37      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       119903                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    -16365796                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       -16365796    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    -16365796                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        118818     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1085      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       119903                       # Table walker page sizes translated
+system.cpu.itb.walker.walks                    136663                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                136663                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       119012                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       136663                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          136663    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       136663                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       120092                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28563.884355                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25001.850654                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 17459.523046                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767        59524     49.57%     49.57% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535        57595     47.96%     97.52% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303         1126      0.94%     98.46% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071         1581      1.32%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839           30      0.02%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607          128      0.11%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375           37      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143           22      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911           13      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       120092                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    -59528796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       -59528796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    -59528796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        119012     99.10%     99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1080      0.90%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       120092                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136538                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       136538                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136663                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       136663                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119903                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       119903                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       256441                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    454119408                       # ITB inst hits
-system.cpu.itb.inst_misses                     136538                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       120092                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       120092                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       256755                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    453103030                       # ITB inst hits
+system.cpu.itb.inst_misses                     136663                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               47246                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    57195                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    57609                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369083                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    364302                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                454255946                       # ITB inst accesses
-system.cpu.itb.hits                         454119408                       # DTB hits
-system.cpu.itb.misses                          136538                       # DTB misses
-system.cpu.itb.accesses                     454255946                       # DTB accesses
-system.cpu.numCycles                       2495798541                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                453239693                       # ITB inst accesses
+system.cpu.itb.hits                         453103030                       # DTB hits
+system.cpu.itb.misses                          136663                       # DTB misses
+system.cpu.itb.accesses                     453239693                       # DTB accesses
+system.cpu.numCycles                       2508251480                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   950561948                       # Number of instructions committed
-system.cpu.committedOps                    1116924449                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      97483728                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7747                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100725440428                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.625603                       # CPI: cycles per instruction
-system.cpu.ipc                               0.380865                       # IPC: instructions per cycle
+system.cpu.committedInsts                   948323287                       # Number of instructions committed
+system.cpu.committedOps                    1114322939                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      97332960                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7744                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100881187078                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.644933                       # CPI: cycles per instruction
+system.cpu.ipc                               0.378081                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16607                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1794634441                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       701164100                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          11128908                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.957332                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           330012577                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11129420                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.652271                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4320792250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.957332                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999917                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999917                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16604                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1790178903                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       718072577                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          11134622                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.957818                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           329114421                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11135134                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.556395                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4277412500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.957818                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999918                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999918                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1386837426                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1386837426                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    168701491                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       168701491                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    152033429                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      152033429                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       523995                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        523995                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       336687                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       336687                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4025252                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4025252                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4342024                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4342024                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     320734920                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        320734920                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    321258915                       # number of overall hits
-system.cpu.dcache.overall_hits::total       321258915                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6599201                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6599201                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4320372                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4320372                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1481368                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1481368                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1244671                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1244671                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       318506                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       318506                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10919573                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10919573                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12400941                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12400941                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 107641538217                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 155110738831                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  35571203201                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  35571203201                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4850646421                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4850646421                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 262752277048                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 262752277048                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 262752277048                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 262752277048                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    175300692                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    175300692                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    156353801                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    156353801                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2005363                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2005363                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1581358                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1581358                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4343758                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4343758                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4342025                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4342025                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    331654493                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    331654493                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    333659856                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    333659856                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037645                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037645                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027632                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027632                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738703                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.738703                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.787090                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787090                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073325                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073325                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1383337751                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1383337751                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    168246441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       168246441                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    151606594                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      151606594                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       524249                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        524249                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       336460                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       336460                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4018923                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4018923                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4332342                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4332342                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     319853035                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        319853035                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    320377284                       # number of overall hits
+system.cpu.dcache.overall_hits::total       320377284                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6626426                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6626426                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4317891                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4317891                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1480828                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1480828                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1245336                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1245336                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       315150                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       315150                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     10944317                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10944317                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     12425145                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12425145                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 107226750500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 107226750500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 152543350000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 152543350000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  58512566000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  58512566000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4781324500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4781324500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       115500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       115500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 259770100500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 259770100500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 259770100500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 259770100500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    174872867                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    174872867                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    155924485                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    155924485                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2005077                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2005077                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1581796                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1581796                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4334073                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4334073                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4332344                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4332344                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    330797352                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    330797352                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    332802429                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    332802429                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037893                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037893                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027692                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027692                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738539                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.738539                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787292                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.787292                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072715                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072715                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032925                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032925                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037166                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037166                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24062.504738                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21188.091859                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.033085                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.033085                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037335                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037335                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.686855                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.686855                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35328.207683                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35328.207683                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 46985.364592                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 46985.364592                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15171.583373                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15171.583373                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        57750                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        57750                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23735.615525                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23735.615525                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20906.806359                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20906.806359                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8539693                       # number of writebacks
-system.cpu.dcache.writebacks::total           8539693                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       803144                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       803144                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904565                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1904565                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data          147                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          147                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69655                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69655                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2707709                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2707709                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2707709                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2707709                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5796057                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5796057                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2415807                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2415807                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473891                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1473891                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1244524                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244524                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       248851                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       248851                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8211864                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8211864                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9685755                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9685755                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33705                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33705                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67401                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67401                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  85294782786                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  85294782786                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  79878018296                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  79878018296                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23078167080                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23078167080                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  33700697799                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  33700697799                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3279664007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3279664007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        80500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        80500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 165172801082                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 188250968162                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5750649000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5750649000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5615353750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5615353750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11366002750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11366002750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033064                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033064                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015451                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015451                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734975                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734975                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786997                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786997                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057289                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057289                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks      8552025                       # number of writebacks
+system.cpu.dcache.writebacks::total           8552025                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       818755                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       818755                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904630                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1904630                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          150                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          150                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70014                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70014                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2723385                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2723385                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2723385                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2723385                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5807671                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5807671                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2413261                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2413261                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473332                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1473332                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1245186                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1245186                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       245136                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       245136                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8220932                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8220932                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9694264                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9694264                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  87900213000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  87900213000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80008628500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  80008628500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23654166000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23654166000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  57263274500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  57263274500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3335164500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3335164500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       113500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       113500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167908841500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 167908841500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191563007500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191563007500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830486500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830486500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5692032500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5692032500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11522519000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11522519000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033211                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033211                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015477                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015477                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787198                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787198                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056560                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056560                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024760                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024760                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029029                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029029                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024852                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024852                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029129                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029129                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15135.191542                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15135.191542                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33153.740312                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33153.740312                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16054.878330                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16054.878330                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 45987.727536                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 45987.727536                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13605.363961                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13605.363961                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        56750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        56750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20424.550586                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20424.550586                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19760.448808                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19760.448808                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173016.602867                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173016.602867                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168867.965111                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168867.965111                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170942.037801                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170942.037801                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24596775                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.926998                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           429140951                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24597287                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.446678                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       22329177250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.926998                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999857                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
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+system.cpu.icache.tags.avg_refs             17.507889                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26893649500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.918526                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999841                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
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+system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         478335544                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        478335544                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    429140951                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       429140951                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total        429140951                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    429140951                       # number of overall hits
-system.cpu.icache.overall_hits::total       429140951                       # number of overall hits
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-system.cpu.icache.ReadReq_misses::total      24597297                       # number of ReadReq misses
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-system.cpu.icache.overall_misses::cpu.inst     24597297                       # number of overall misses
-system.cpu.icache.overall_misses::total      24597297                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 327843901768                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 327843901768                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 327843901768                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 327843901768                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 327843901768                       # number of overall miss cycles
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054210                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13328.452381                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13328.452381                       # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 13328.452381                       # average overall miss latency
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13317.498675                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -810,212 +810,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.icache.overall_mshr_uncacheable_latency::total   4024065500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054210                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11826.429614                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11826.429614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11826.429614                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average overall mshr uncacheable latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1624472                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65307.335302                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           40176051                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1687699                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.805223                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6393601000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36145.263997                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   333.648075                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.733439                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8142.717924                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 20262.971868                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.551533                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5584                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54389                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003860                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.960907                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::writebacks      8539693                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8539693                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       698094                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       698094                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10791                       # number of UpgradeReq hits
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-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6407                       # number of ReadReq misses
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-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       546430                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       546430                       # number of WriteInvalidateReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total        38901                       # number of UpgradeReq misses
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-system.cpu.l2cache.UpgradeReq_miss_latency::total    584783300                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.Writeback_accesses::total      8539693                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1244524                       # number of WriteInvalidateReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006494                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.439067                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.439067                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782842                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782842                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.replacements          1604829                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65266.156442                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           67107084                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1667914                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            40.234139                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      24502559000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 35881.888844                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   344.047128                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   429.269400                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          504                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2442                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5503                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54305                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958389                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        585371330                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       585371330                       # Number of data accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018329                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.032755                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87492.618206                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81823.947210                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84865.203507                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 84201.987729                       # average ReadReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data    11.433852                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total    11.433852                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15032.603275                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15032.603275                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82215.692627                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82215.692627                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87492.618206                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81823.947210                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83061.480051                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82989.703972                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87492.618206                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81823.947210                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83061.480051                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82989.703972                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.298531                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.298531                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004413                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004413                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043697                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043697                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.436442                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.436442                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018653                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004413                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.104613                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.032408                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018653                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004413                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average ReadReq miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 86968.239101                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14905.325750                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14905.325750                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        55250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        55250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81684.748649                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81684.748649                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81443.923156                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81443.923156                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84371.790778                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84371.790778                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87882.458584                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87882.458584                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82481.492246                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82481.492246                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1024,185 +1037,200 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1380910                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1380910                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.writebacks::writebacks      1368450                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1368450                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
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+system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
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-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       546430                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       546430                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38901                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        38901                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    479479000                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  18411194701                       # number of WriteInvalidateReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    691147894                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        67500                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5278320250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8387240250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176274500                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10454594750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13563514750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.044582                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013668                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.439067                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.439067                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782842                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782842                       # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  24456668500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  42325300000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  42325300000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    413343500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7712869000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  75049398500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  83666182500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    413343500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7712869000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  75049398500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  83666182500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409182000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8641547500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5303781000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5303781000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10712963000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13945328500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009264                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782948                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782948                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.302097                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.302097                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.106229                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.032755                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.106229                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.032755                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72344.386192                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71676.843540                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33693.601561                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33693.601561                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17766.841315                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17766.841315                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.298531                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.298531                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004413                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043694                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043694                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.436442                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.436442                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.032407                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.032407                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76968.239101                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.283868                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.283868                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71684.748649                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71684.748649                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71444.560747                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74373.452116                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74373.452116                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77882.458584                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77882.458584                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160514.614677                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.121404                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157349.541638                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157349.541638                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158931.890336                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116501.353372                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       33924038                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33915953                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33705                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33705                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8539693                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351286                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        49695                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        49696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2366369                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2366369                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49299178                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31033537                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       698041                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2292039                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          83322795                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1577573568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1259064522                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2320736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7893144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2846851970                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      553019                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     46264787                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.039533                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.194859                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        1796538                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33784448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback     10027137                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     27284097                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        49406                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        49408                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2364132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2364132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24461269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7534742                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1351850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1245186                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73484098                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33638682                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       696808                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2281485                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         110101073                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1568867840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1180529566                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2307872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7834120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2759539398                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2279468                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     74907361                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.047344                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.212374                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           44435816     96.05%     96.05% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1828971      3.95%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           71360927     95.27%     95.27% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            3546434      4.73%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       46264787                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32875768488                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       74907361                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    45104615497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy      1167000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   37011580552                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36773946781                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15738706286                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15533347490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     408640707                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     408345956                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1306185489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1302236467                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1219,11 +1247,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1240,11 +1268,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1273,211 +1301,213 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           606954435                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568973549                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148397760                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115470                       # number of replacements
-system.iocache.tags.tagsinuse               10.439534                       # Cycle average of tags in use
+system.iocache.tags.replacements               115486                       # number of replacements
+system.iocache.tags.tagsinuse               10.447136                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115486                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13142420796000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.524742                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.914791                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.220296                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.432174                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652471                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13147036427000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.519010                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928125                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219938                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433008                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.652946                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039749                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039893                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8824                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8864                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8824                       # number of overall misses
-system.iocache.overall_misses::total             8864                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1602204582                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1607276582                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19806517093                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19806517093                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1602204582                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1607629082                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1602204582                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1607629082                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
+system.iocache.overall_misses::total             8880                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1592056146                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1597125146                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12612249403                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12612249403                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1592056146                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1597476146                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1592056146                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1597476146                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8824                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8864                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8824                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8864                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 181387.719445                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 181573.502040                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 181366.096796                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 181573.502040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 181366.096796                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        109809                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 180096.849095                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 179917.218204                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118242.794223                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118242.794223                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 179895.962387                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 179895.962387                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         29944                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16154                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3370                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.797635                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.885460                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8824                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8864                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8824                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8864                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1142260060                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1145402060                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14259947135                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14259947135                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1142260060                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1145595560                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1142260060                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1145595560                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1150056146                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1153275146                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279049403                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7279049403                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1150056146                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1153476146                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1150056146                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1153476146                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 129241.376354                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 129241.376354                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130096.849095                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 129917.218204                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68242.794223                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68242.794223                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              551255                       # Transaction distribution
-system.membus.trans_dist::ReadResp             551255                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33705                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33705                       # Transaction distribution
-system.membus.trans_dist::Writeback           1487541                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       652894                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       652894                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            39734                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           39735                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            714242                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           714242                       # Transaction distribution
+system.membus.trans_dist::ReadReq               85994                       # Transaction distribution
+system.membus.trans_dist::ReadResp             543407                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
+system.membus.trans_dist::Writeback           1475081                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           242486                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            39492                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           39494                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1248409                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1248409                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        457413                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5003208                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5132856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335248                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335248                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5468104                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5186779                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5316437                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341268                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341268                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5657705                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13824                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    201583148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201753546                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14062080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14062080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               215815626                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3099                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3479513                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199510060                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    199680478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7228736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7228736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               206909214                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3224                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3692024                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3479513    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3692024    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3479513                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102597500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3692024                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           102515000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5574500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5516000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         12409067173                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9935800091                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7217145927                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         9380119144                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151545740                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228946369                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1488,11 +1518,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index c76990264..2b80b1dcb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.320469                       # Number of seconds simulated
-sim_ticks                                51320468905000                       # Number of ticks simulated
-final_tick                               51320468905000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.323721                       # Number of seconds simulated
+sim_ticks                                51323721423000                       # Number of ticks simulated
+final_tick                               51323721423000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81731                       # Simulator instruction rate (inst/s)
-host_op_rate                                    96032                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4902851121                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 723872                       # Number of bytes of host memory used
-host_seconds                                 10467.47                       # Real time elapsed on the host
-sim_insts                                   855512158                       # Number of instructions simulated
-sim_ops                                    1005211605                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  78661                       # Simulator instruction rate (inst/s)
+host_op_rate                                    92428                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4731079623                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 729012                       # Number of bytes of host memory used
+host_seconds                                 10848.21                       # Real time elapsed on the host
+sim_insts                                   853325819                       # Number of instructions simulated
+sim_ops                                    1002674190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       202624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       193280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5755680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          42629000                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        415488                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49196072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5755680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5755680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69369152                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       203200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       189632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5727200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          73778504                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        419776                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             80318312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5727200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5727200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68723904                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69389732                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3020                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105885                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             666091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6492                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                784654                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1083893                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68744484                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3175                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         2963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105440                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1152802                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1270939                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1073811                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1086466                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3948                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               112152                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               830643                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  958605                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          112152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1351686                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1076384                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           3959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           3695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1437513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8179                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1564935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111590                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111590                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1339028                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1352087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1351686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3948                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              112152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              831044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8096                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2310692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        784654                       # Number of read requests accepted
-system.physmem.writeReqs                      1688539                       # Number of write requests accepted
-system.physmem.readBursts                      784654                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1688539                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 50184064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     33792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104909952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  49196072                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              107922404                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      528                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   49293                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          35218                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               46664                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51485                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               48018                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               46409                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               44064                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               51949                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               45895                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               48923                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               45299                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               70789                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              48156                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              46739                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              48771                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              48997                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              45133                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              46835                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               99610                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              104326                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              103481                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              102430                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              101747                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104971                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              100056                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              103888                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               99840                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              106110                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102643                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             100858                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103355                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             103593                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             100350                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             101960                       # Per bank write bursts
+system.physmem.bw_write::total                1339429                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1339028                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          3959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          3695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1437914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8179                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2904365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1270939                       # Number of read requests accepted
+system.physmem.writeReqs                      1076384                       # Number of write requests accepted
+system.physmem.readBursts                     1270939                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1076384                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 81299584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     40512                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68742976                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  80318312                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68744484                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      633                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         142017                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               76590                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               80112                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               82312                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               76894                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               75148                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               84486                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               75307                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               76047                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               76921                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104197                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              75653                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              81028                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              74845                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              77383                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              76622                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              76761                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64108                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67910                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               69982                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               67432                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               65959                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70786                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64733                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               66187                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67287                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               71812                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65064                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              69201                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65082                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              66370                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66024                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              66172                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         560                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51320467654000                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51323720227500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  763369                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1249654                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1685966                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    521104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    214865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29991                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12339                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       553                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       459                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1073811                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    646219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    339232                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    151287                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    128129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       684                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       502                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       533                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       812                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       936                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,160 +159,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    62903                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    63057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    90168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    80361                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    95410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    92759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   101527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    92557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    84728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   110064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    83833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    78687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    89131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    74275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    70833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    66282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     8883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     7376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     8392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     9232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     9334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     8685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     9103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     9266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     8544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     8245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     7856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     7810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     5765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     6644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     5091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     4890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     3916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     3295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     3011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     2474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     3139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     2181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     2765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                     1862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                     4424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                     1539                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       512637                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.540847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     171.812512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.509823                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207576     40.49%     40.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       124268     24.24%     64.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44401      8.66%     73.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23774      4.64%     78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        16232      3.17%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10193      1.99%     83.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8192      1.60%     84.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7548      1.47%     86.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        70453     13.74%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         512637                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         56080                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        13.981651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       75.084718                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           56073     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            5      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           56080                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         56080                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        29.229993                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       22.064414                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       40.823681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-31            46001     82.03%     82.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-63            3837      6.84%     88.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95            4190      7.47%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127            975      1.74%     98.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159           304      0.54%     98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191           127      0.23%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223            99      0.18%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255            80      0.14%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287           114      0.20%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-319           122      0.22%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-351            75      0.13%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383            40      0.07%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415            26      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-447            17      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479            12      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511             8      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543            13      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-575            10      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-607             5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-639             3      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-671             4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-703             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-735             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-767             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-799             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-927             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::992-1023            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1056-1087            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1184-1215            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           56080                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15388206863                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30090569363                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3920630000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19624.66                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    11927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    14439                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34                      572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       481355                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.708207                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.914901                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     339.146013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         186832     38.81%     38.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       113175     23.51%     62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        45398      9.43%     71.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23450      4.87%     76.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18101      3.76%     80.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11671      2.42%     82.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10460      2.17%     84.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8315      1.73%     86.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        63953     13.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         481355                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61522                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.647411                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      265.936082                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          61519    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           61522                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61522                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.458942                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.948779                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.823778                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           58490     95.07%     95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             664      1.08%     96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             448      0.73%     96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             190      0.31%     97.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             308      0.50%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             527      0.86%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             143      0.23%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              33      0.05%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              36      0.06%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              18      0.03%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              32      0.05%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              22      0.04%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             426      0.69%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              45      0.07%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              33      0.05%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              35      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              13      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            31      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61522                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31530968444                       # Total ticks spent queuing
+system.physmem.totMemAccLat               55349205944                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6351530000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       24821.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38374.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.96                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43571.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.56                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     598254                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1312451                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.06                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20750692.59                       # Average gap between requests
-system.physmem.pageHitRate                      78.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1947569400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1062661875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2990566800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5316898320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352003380960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1226375853165                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29716511616000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34306208546520                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.470318                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49436040472112                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713703160000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.31                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1047361                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    815697                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21864788.20                       # Average gap between requests
+system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1828287720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  997577625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4889757600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3480388560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1226219398425                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29718601656750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34308233025720                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.467372                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49439480717043                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713811840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    170725136888                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    170428636707                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1927966320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1051965750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3125569200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5305234320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352003380960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1229368112910                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29713886826750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34306669056210                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.479291                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49431639282027                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713703160000                       # Time in different power states
+system.physmem_1.actEnergy                 1810756080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  988011750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5018598000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3479837760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1228704019020                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29716422156750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34308639338400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.475289                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49435820968594                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713811840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    175126075973                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    174088371406                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -336,15 +340,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               226088242                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         151212051                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12236747                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159576730                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104394184                       # Number of BTB hits
+system.cpu.branchPred.lookups               225557622                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         150824960                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12221670                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159273353                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104130221                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.419428                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31024336                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             344701                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.378307                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30957399                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             344598                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -375,45 +379,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks            200795                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        200795                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       200795                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       200795    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       200795                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walksPending::samples   1638530500                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::0   1638530500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::total   1638530500                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       155523     90.97%     90.97% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        15432      9.03%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       170955                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       200795                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walks            199616                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        199616                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       199616                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       199616    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       199616                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples   1622408500                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0   1622408500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total   1622408500                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K       155025     91.25%     91.25% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        14865      8.75%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       169890                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       199616                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       200795                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       170955                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       199616                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       169890                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       170955                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       371750                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       169890                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       369506                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            160924630                       # DTB read hits
-system.cpu.checker.dtb.read_misses             149513                       # DTB read misses
-system.cpu.checker.dtb.write_hits           145982592                       # DTB write hits
-system.cpu.checker.dtb.write_misses             51282                       # DTB write misses
+system.cpu.checker.dtb.read_hits            160527490                       # DTB read hits
+system.cpu.checker.dtb.read_misses             148526                       # DTB read misses
+system.cpu.checker.dtb.write_hits           145616651                       # DTB write hits
+system.cpu.checker.dtb.write_misses             51090                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid        79718                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid            2054                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            72580                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid        79428                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid            2050                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries            72318                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           7050                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           7517                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             19166                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        161074143                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       146033874                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             19125                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        160676016                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       145667741                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 306907222                       # DTB hits
-system.cpu.checker.dtb.misses                  200795                       # DTB misses
-system.cpu.checker.dtb.accesses             307108017                       # DTB accesses
+system.cpu.checker.dtb.hits                 306144141                       # DTB hits
+system.cpu.checker.dtb.misses                  199616                       # DTB misses
+system.cpu.checker.dtb.accesses             306343757                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -443,46 +447,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.walks            120591                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        120591                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       120591                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       120591    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       120591                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walksPending::samples   1637932000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::0   1637932000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::total   1637932000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       108617     98.83%     98.83% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::2M         1291      1.17%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109908                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walks            120521                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        120521                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       120521                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       120521    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       120521                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples   1621807000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0   1621807000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total   1621807000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K       108578     98.83%     98.83% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M         1286      1.17%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       109864                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       120591                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       120591                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       120521                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       120521                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109908                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109908                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       230499                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            855922330                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             120591                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109864                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109864                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       230385                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            853734937                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             120521                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
 system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid        79718                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid            2054                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            52096                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid        79428                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid            2050                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries            52057                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        856042921                       # ITB inst accesses
-system.cpu.checker.itb.hits                 855922330                       # DTB hits
-system.cpu.checker.itb.misses                  120591                       # DTB misses
-system.cpu.checker.itb.accesses             856042921                       # DTB accesses
-system.cpu.checker.numCycles               1005785493                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        853855458                       # ITB inst accesses
+system.cpu.checker.itb.hits                 853734937                       # DTB hits
+system.cpu.checker.itb.misses                  120521                       # DTB misses
+system.cpu.checker.itb.accesses             853855458                       # DTB accesses
+system.cpu.checker.numCycles               1003246954                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -514,86 +518,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    945525                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                945525                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        17037                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156802                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       426099                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       519426                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  1842.763936                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-32767       513062     98.77%     98.77% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-65535         3320      0.64%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-98303         1249      0.24%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::98304-131071         1137      0.22%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-163839          115      0.02%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::163840-196607          205      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-229375           84      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::229376-262143           60      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-294911           94      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::294912-327679            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-360447           21      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::360448-393215           44      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-425983           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       519426                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       477950                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       472923     98.95%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         4117      0.86%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          574      0.12%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          200      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           75      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    951838                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                951838                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16475                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156308                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435006                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       516832                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  1986.510123                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-32767       508349     98.36%     98.36% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-65535         5443      1.05%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-98303         1244      0.24%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::98304-131071         1085      0.21%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-163839          165      0.03%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::163840-196607          178      0.03%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-229375          121      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::229376-262143           54      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-294911           95      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::294912-327679            7      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-360447            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::360448-393215           38      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-425983           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::425984-458751            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       516832                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       485267                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       475094     97.90%     97.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         9290      1.91%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          546      0.11%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          199      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           82      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           20      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       477950                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 768700308080                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.730043                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.512304                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  766743156580     99.75%     99.75% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1060609500      0.14%     99.88% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     401667500      0.05%     99.94% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     174666000      0.02%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     138312000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    106588500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     24500000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     48487000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2321000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 768700308080                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        156803     90.20%     90.20% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         17037      9.80%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       173840                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       945525                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total       485267                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 776250627376                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.722476                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.519579                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  774163165376     99.73%     99.73% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1120728500      0.14%     99.88% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     435636500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     187638500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     148036000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    113935000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     26323500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     52542500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2621500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 776250627376                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        156309     90.46%     90.46% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16475      9.54%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       172784                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       951838                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       945525                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       173840                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       951838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       172784                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       173840                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1119365                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       172784                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1124622                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    170900022                       # DTB read hits
-system.cpu.dtb.read_misses                     675244                       # DTB read misses
-system.cpu.dtb.write_hits                   148749524                       # DTB write hits
-system.cpu.dtb.write_misses                    270281                       # DTB write misses
+system.cpu.dtb.read_hits                    170417440                       # DTB read hits
+system.cpu.dtb.read_misses                     677013                       # DTB read misses
+system.cpu.dtb.write_hits                   148384109                       # DTB write hits
+system.cpu.dtb.write_misses                    274825                       # DTB write misses
 system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               79718                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    2054                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72825                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       117                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10420                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               79428                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    2050                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72556                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10696                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69816                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171575266                       # DTB read accesses
-system.cpu.dtb.write_accesses               149019805                       # DTB write accesses
+system.cpu.dtb.perms_faults                     70061                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171094453                       # DTB read accesses
+system.cpu.dtb.write_accesses               148658934                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         319649546                       # DTB hits
-system.cpu.dtb.misses                          945525                       # DTB misses
-system.cpu.dtb.accesses                     320595071                       # DTB accesses
+system.cpu.dtb.hits                         318801549                       # DTB hits
+system.cpu.dtb.misses                          951838                       # DTB misses
+system.cpu.dtb.accesses                     319753387                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -623,209 +628,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161869                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161869                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walks                    162167                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                162167                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       122204                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17648                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144221                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1045.076653                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  6935.040907                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143697     99.64%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          129      0.09%     99.73% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303          259      0.18%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           98      0.07%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839           18      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144221                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       141285                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 26183.154631                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       139260     98.57%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         1739      1.23%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          189      0.13%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           61      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           22      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       122178                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17760                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144407                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1087.128740                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  7079.961036                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       143546     99.40%     99.40% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          491      0.34%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          245      0.17%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           86      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           14      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144407                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       141371                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 27408.566821                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       138940     98.28%     98.28% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         2106      1.49%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          209      0.15%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           62      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           27      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       141285                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 652736132088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.935835                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.245289                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     41920855152      6.42%      6.42% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    610778213436     93.57%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        36269000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          794000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4             500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 652736132088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        122204     98.84%     98.84% # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total       141371                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 655988501088                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.936740                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.243710                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     41542191152      6.33%      6.33% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    614402729936     93.66%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        43110500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          467500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 655988501088                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        122178     98.84%     98.84% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123637                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       123611                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161869                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162167                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       162167                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123637                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123637                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       285506                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    359459512                       # ITB inst hits
-system.cpu.itb.inst_misses                     161869                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123611                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       123611                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       285778                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    358625455                       # ITB inst hits
+system.cpu.itb.inst_misses                     162167                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               79718                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    2054                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53398                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               79428                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    2050                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53363                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372095                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372145                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                359621381                       # ITB inst accesses
-system.cpu.itb.hits                         359459512                       # DTB hits
-system.cpu.itb.misses                          161869                       # DTB misses
-system.cpu.itb.accesses                     359621381                       # DTB accesses
-system.cpu.numCycles                       1580751099                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                358787622                       # ITB inst accesses
+system.cpu.itb.hits                         358625455                       # DTB hits
+system.cpu.itb.misses                          162167                       # DTB misses
+system.cpu.itb.accesses                     358787622                       # DTB accesses
+system.cpu.numCycles                       1590418745                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          647898483                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1008720689                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   226088242                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135418520                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     855549558                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26139542                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3573192                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                26865                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9268939                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1033386                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          427                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 359070671                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6123790                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48662                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1530420621                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.772272                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.159981                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          646410999                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1006402404                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225557622                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135087620                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     866562323                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26107474                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3678311                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                25439                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9275413                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1023850                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          676                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 358236204                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6112300                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   49056                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1540030748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.765724                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.157325                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                968902908     63.31%     63.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215807485     14.10%     77.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71036994      4.64%     82.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                274673234     17.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                979927440     63.63%     63.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215057699     13.96%     77.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70955696      4.61%     82.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                274089913     17.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1530420621                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.143026                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.638127                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526178421                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             508648126                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 435713994                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50619608                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9260472                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33861678                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3868815                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1093600087                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29077129                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9260472                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571338545                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                48532565                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      364379914                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 441167933                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              95741192                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1073752213                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6802962                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5086497                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 358848                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 628248                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               43820548                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20190                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1021575372                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1655508848                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1270030956                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1469892                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             955737015                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65838354                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27320538                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23636945                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 103635545                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            174900719                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           152333814                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9971771                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9081144                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1038303468                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27624460                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1054196021                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3299994                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60716319                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33847358                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         315461                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1530420621                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.688828                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.927358                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1540030748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.141823                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.632791                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                525466953                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             519947088                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 434864784                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50506307                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9245616                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33796734                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3867997                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1090931528                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29050280                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9245616                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                570424085                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50840114                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363017689                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 440398811                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             106104433                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1071115355                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6801917                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5040663                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 343395                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 645255                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               54344412                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20434                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1018974666                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1651092433                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1266893179                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1473696                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             953236782                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65737881                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27206823                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23528426                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 103688094                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            174464093                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           151959443                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9931077                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9032567                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1035787653                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27506074                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1051526043                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3293799                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60619533                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33780075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         314140                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1540030748                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.682795                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.925415                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           877745445     57.35%     57.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           337069342     22.02%     79.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           236293073     15.44%     94.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72729594      4.75%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6564084      0.43%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19083      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           888949202     57.72%     57.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           336251490     21.83%     79.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           235798342     15.31%     94.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72468185      4.71%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6544331      0.42%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19198      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1530420621                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1540030748                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58206836     35.09%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99242      0.06%     35.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26725      0.02%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              744      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44573023     26.87%     62.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62969604     37.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58035888     35.01%     35.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  99674      0.06%     35.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26738      0.02%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              574      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44566242     26.88%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63041416     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                57      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             725956407     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2542188      0.24%     69.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                123122      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             724142674     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2543730      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122779      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 376      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -847,102 +852,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         120904      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121012      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            174804143     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150649152     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            174312709     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150282706     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1054196021                       # Type of FU issued
-system.cpu.iq.rate                           0.666896                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   165876174                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157349                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3805514237                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1125839347                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1036122901                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2474593                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             946702                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909865                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1218517790                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1554348                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4347401                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1051526043                       # Type of FU issued
+system.cpu.iq.rate                           0.661163                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   165770532                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157648                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3809671307                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1123107931                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1033541701                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2475857                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             947397                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       910004                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1215741366                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1555198                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4333965                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13878328                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14961                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       143108                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6347044                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13839303                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14833                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143349                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6338712                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2552620                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1870361                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2540349                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1552925                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9260472                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6554396                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3651492                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1066150871                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9245616                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6389360                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5797347                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1063516239                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             174900719                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            152333814                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23208148                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  59700                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3513413                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         143108                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3675827                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5121930                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8797757                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1042985483                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             170888878                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10276947                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             174464093                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            151959443                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23100216                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  59008                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               5663632                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143349                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3667729                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5111764                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8779493                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1040328227                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             170406440                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10257681                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222943                       # number of nop insts executed
-system.cpu.iew.exec_refs                    319634404                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                197926826                       # Number of branches executed
-system.cpu.iew.exec_stores                  148745526                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.659804                       # Inst execution rate
-system.cpu.iew.wb_sent                     1037843882                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1037032766                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 441278048                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 713779914                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        222512                       # number of nop insts executed
+system.cpu.iew.exec_refs                    318786335                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                197400349                       # Number of branches executed
+system.cpu.iew.exec_stores                  148379895                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.654122                       # Inst execution rate
+system.cpu.iew.wb_sent                     1035262700                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1034451705                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 440415620                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 712619707                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.656038                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618227                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.650427                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618023                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51563874                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27308999                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8427448                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1518403714                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.662019                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.290608                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51498978                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27191934                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8413549                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1528028900                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.656188                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.286676                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1001866977     65.98%     65.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    290832617     19.15%     85.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121646355      8.01%     93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36740427      2.42%     95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28447666      1.87%     97.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14105700      0.93%     98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8667985      0.57%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4229973      0.28%     99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11866014      0.78%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1013092181     66.30%     66.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    289858237     18.97%     85.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121052617      7.92%     93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36682667      2.40%     95.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28563883      1.87%     97.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14105791      0.92%     98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8655946      0.57%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4198069      0.27%     99.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11819509      0.77%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1518403714                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            855512158                       # Number of instructions committed
-system.cpu.commit.committedOps             1005211605                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1528028900                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            853325819                       # Number of instructions committed
+system.cpu.commit.committedOps             1002674190                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      307009160                       # Number of memory references committed
-system.cpu.commit.loads                     161022390                       # Number of loads committed
-system.cpu.commit.membars                     6998413                       # Number of memory barriers committed
-system.cpu.commit.branches                  190975004                       # Number of branches committed
-system.cpu.commit.fp_insts                     896164                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 923410198                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25456304                       # Number of function calls committed.
+system.cpu.commit.refs                      306245520                       # Number of memory references committed
+system.cpu.commit.loads                     160624789                       # Number of loads committed
+system.cpu.commit.membars                     6977905                       # Number of memory barriers committed
+system.cpu.commit.branches                  190474151                       # Number of branches committed
+system.cpu.commit.fp_insts                     896785                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 921116747                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25400785                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        695830631     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2161783      0.22%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98401      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        694059947     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2158876      0.22%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98131      0.01%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
@@ -965,522 +970,535 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% #
 system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111588      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111674      0.01%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       161022390     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      145986770     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       160624789     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      145620731     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1005211605                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11866014                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2555711925                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2125474325                       # The number of ROB writes
-system.cpu.timesIdled                         8142220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        50330478                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101060186847                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   855512158                       # Number of Instructions Simulated
-system.cpu.committedOps                    1005211605                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.847725                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.847725                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.541206                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.541206                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1234726115                       # number of integer regfile reads
-system.cpu.int_regfile_writes               737118920                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1461359                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   784484                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 227546613                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                228200703                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2526906641                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27367002                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9794555                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.983548                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           285502634                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9795067                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.147594                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1659133250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.983548                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total        1002674190                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11819509                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2562796067                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2120254358                       # The number of ROB writes
+system.cpu.timesIdled                         8129447                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        50387997                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101057024238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   853325819                       # Number of Instructions Simulated
+system.cpu.committedOps                    1002674190                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.863788                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.863788                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.536542                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.536542                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1231590969                       # number of integer regfile reads
+system.cpu.int_regfile_writes               735370650                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462122                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782688                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 226859046                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                227515194                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2534481060                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27245755                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9758519                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983709                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           284707567                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9759031                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.173754                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1642601500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983709                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          409                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1246939843                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1246939843                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    148420477                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       148420477                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    129257116                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      129257116                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       380071                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        380071                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       323830                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       323830                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3338713                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3338713                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3738459                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3738459                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     277677593                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        277677593                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    278057664                       # number of overall hits
-system.cpu.dcache.overall_hits::total       278057664                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9529450                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9529450                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11422113                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11422113                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1191409                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1191409                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233320                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1233320                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       451226                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       451226                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20951563                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20951563                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22142972                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22142972                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 145395860730                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 336812014094                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  35299806246                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  35299806246                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6459718484                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6459718484                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       237001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       237001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 482207874824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 482207874824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 482207874824                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 482207874824                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    157949927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    157949927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140679229                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140679229                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1571480                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1571480                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557150                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1557150                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3789939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3789939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3738465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3738465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    298629156                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    298629156                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    300200636                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    300200636                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060332                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060332                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081193                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081193                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758145                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.758145                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.792037                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.792037                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119059                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119059                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1243872376                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1243872376                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147964440                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147964440                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128940955                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128940955                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       380183                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        380183                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       324678                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       324678                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3327415                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3327415                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3725844                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3725844                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     276905395                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        276905395                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    277285578                       # number of overall hits
+system.cpu.dcache.overall_hits::total       277285578                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9612542                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9612542                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11385353                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11385353                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1184834                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1184834                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1232047                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1232047                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20997895                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20997895                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22182729                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22182729                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 144669003500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 330867751444                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  63675897168                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  63675897168                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       251000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       251000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 475536754944                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 475536754944                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 475536754944                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 475536754944                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    157576982                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    157576982                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    140326308                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    140326308                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1565017                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1565017                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1556725                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1556725                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3777448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3777448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3725851                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3725851                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    297903290                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    297903290                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    299468307                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    299468307                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061002                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061002                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081135                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.757074                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.757074                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791435                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791435                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119137                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119137                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070159                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070159                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073761                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073761                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23015.365241                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21777.016871                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20545206                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070486                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070486                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074074                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074074                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22646.877458                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21437.252150                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     35158879                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1559097                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1606955                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.177632                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.879193                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7577660                       # number of writebacks
-system.cpu.dcache.writebacks::total           7577660                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4366240                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4366240                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9388231                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9388231                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7155                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7155                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       220115                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       220115                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13754471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13754471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13754471                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13754471                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5163210                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5163210                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2033882                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2033882                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1184642                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1184642                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1226165                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1226165                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       231111                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       231111                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7197092                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7197092                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8381734                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8381734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67343                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67343                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  73626554579                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  73626554579                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  56871439750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  56871439750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  19552019274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  19552019274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  33205804688                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  33205804688                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2956928250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2956928250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       227999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       227999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 130497994329                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 150050013603                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5746385500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5746385500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5629281968                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5629281968                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11375667468                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11375667468                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032689                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032689                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753838                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753838                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787442                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787442                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060980                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060980                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks      7549082                       # number of writebacks
+system.cpu.dcache.writebacks::total           7549082                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4467834                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4467834                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9360902                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9360902                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7079                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7079                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219205                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219205                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13828736                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13828736                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13828736                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13828736                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5144708                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5144708                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2024451                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2024451                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1178103                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1178103                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224968                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1224968                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7169159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7169159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8347262                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8347262                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75818409500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75818409500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  57062160713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  57062160713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20148080000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20148080000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  62191648168                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  62191648168                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       244000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       244000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 132880570213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 153028650213                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5828327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5828327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5707957967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5707957967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11536285467                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11536285467                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032649                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032649                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014427                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014427                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752773                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752773                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786888                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786888                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061107                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061107                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024100                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024100                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027920                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027920                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024065                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024065                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027874                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027874                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15070815                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.953323                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           343233622                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15071327                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.773948                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       14049577000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.953323                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements          15042093                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.944879                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           342405629                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15042605                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.762389                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       17214303500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.944879                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999892                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         374120916                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        374120916                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    343233622                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       343233622                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     343233622                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        343233622                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    343233622                       # number of overall hits
-system.cpu.icache.overall_hits::total       343233622                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15815747                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15815747                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15815747                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15815747                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15815747                       # number of overall misses
-system.cpu.icache.overall_misses::total      15815747                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208885866517                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208885866517                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208885866517                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208885866517                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208885866517                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    359049369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    359049369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    359049369                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    359049369                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    359049369                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    359049369                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044049                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044049                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044049                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044049                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044049                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13207.461305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13207.461305                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        13684                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         373257734                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        373257734                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    342405629                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       342405629                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     342405629                       # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst     15809279                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst     15809279                       # number of overall misses
+system.cpu.icache.overall_misses::total      15809279                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208403044384                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208403044384                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208403044384                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208403044384                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208403044384                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    358214908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    358214908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    358214908                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    358214908                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    358214908                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    358214908                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044134                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044134                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.044134                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.044134                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.044134                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.044134                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13182.324405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13182.324405                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        15030                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1126                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1210                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.152753                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    12.421488                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       744199                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       744199                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       744199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       744199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       744199                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       744199                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15071548                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15071548                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15071548                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15071548                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15071548                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15071548                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766453                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       766453                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       766453                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       766453                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total       766453                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15042826                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     15042826                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     15042826                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     15042826                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     15042826                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     15042826                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 179787086612                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 179787086612                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1585009250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1585009250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1585009250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   1585009250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041976                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041976                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041976                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 186915451392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1594412000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   1594412000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1159288                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65272.997993                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29043191                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1221496                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.776739                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       2756226000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   319.528316                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   474.614102                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7535.726920                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.568752                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004876                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007242                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114986                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300131                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          304                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61904                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          304                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          579                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2674                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5116                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53473                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004639                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.944580                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        272839925                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       272839925                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       805883                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::cpu.inst     14986718                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6321707                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       22418684                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7577660                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7577660                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       730602                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       730602                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9499                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9499                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.ReadExReq_hits::cpu.data      1579833                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3020                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        84629                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total       344501                       # number of ReadReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       495562                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       495562                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34430                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34430                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.replacements          1148683                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65278.817014                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46198537                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1210914                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.151790                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      15659706000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   301.460755                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   460.210435                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7626.713626                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004600                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007022                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116374                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        61851                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          379                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          530                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2690                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5173                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53395                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.005798                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.943771                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.ReadReq_hits::total        1088746                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      7549082                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      7549082                       # number of Writeback hits
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+system.cpu.l2cache.InvalidateReq_hits::total       732370                       # number of InvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::total       413693                       # number of ReadExReq misses
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-system.cpu.l2cache.overall_misses::total       758194                       # number of overall misses
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-system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data      4785347                       # number of WriteInvalidateReq miss cycles
-system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      4785347                       # number of WriteInvalidateReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  59642695593                       # number of overall miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks      7577660                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7577660                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1226164                       # number of WriteInvalidateReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data      8568919                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005615                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.038581                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015134                       # miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.404156                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.404156                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783765                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783765                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::total     0.207518                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.003913                       # miss rate for demand accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287                       # average ReadReq miss latency
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-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     9.656404                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53000                       # average SCUpgradeReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790                       # average ReadExReq miss latency
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+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402131                       # miss rate for InvalidateReq accesses
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1489,182 +1507,196 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       977263                       # number of writebacks
-system.cpu.l2cache.writebacks::total           977263                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2963                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        84184                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       661637                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       751959                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54956                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33682                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67343                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88638                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    225518000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   6085544162                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  19591961036                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  26140194449                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  16855177398                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  16855177398                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    611252927                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    611252927                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       153001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       153001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31729551871                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31729551871                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    225518000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   6085544162                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51321512907                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  57869746320                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    225518000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   6085544162                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51321512907                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  57869746320                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1276231250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5274563500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6550794750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5186666500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5186666500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1276231250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10461230000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11737461250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.038578                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015133                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.404156                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.404156                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783765                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783765                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.207518                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.207518                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077881                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030625                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077881                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030625                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286                       # average overall mshr miss latency
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-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063                       # average overall mshr uncacheable latency
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+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       161500                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   6240732500                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  46277939000                       # number of InvalidateReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407344500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6735569000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5315951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10723295500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12051520000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005596                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038736                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038736                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402131                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402131                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030479                       # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23293786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23285542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7577660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332936                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1226164                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43938                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1993526                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1993526                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30185484                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27390990                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       736951                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1962535                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          60275960                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    964906864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1112084525                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2459168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6472392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2085922949                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      583028                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     34275542                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.049559                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.217032                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        1633565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23227278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8622904                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     17438576                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        44010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        44017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1983984                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1983984                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15042826                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6558947                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1331632                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1224968                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45167572                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29499463                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       732865                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1940611                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77340511                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    963068272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1029563294                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2422088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6336984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2001390638                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1864369                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     52693428                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.056141                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.230194                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           32576878     95.04%     95.04% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1698664      4.96%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           49735173     94.39%     94.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            2958255      5.61%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       34275542                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    25901169608                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       52693428                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    33222815494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       909000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1182000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22654600125                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22592032956                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13659008538                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13487423434                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     430754363                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     430634727                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1154477924                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1148958035                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40283                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40283                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136558                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29894                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1675,17 +1707,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29496                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122652                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230950                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230950                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353682                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1696,17 +1728,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17529                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155805                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492123                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1727,7 +1759,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21908000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -1735,211 +1767,213 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607064814                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568813596                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92761000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148363066                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115456                       # number of replacements
-system.iocache.tags.tagsinuse               10.424607                       # Cycle average of tags in use
+system.iocache.tags.replacements               115455                       # number of replacements
+system.iocache.tags.tagsinuse               10.423947                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115472                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13092103918000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544640                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879967                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221540                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429998                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13095311635000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544418                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879529                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221526                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429971                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651497                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039632                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039632                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039623                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8811                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8848                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8811                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8851                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8810                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8850                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8811                       # number of overall misses
-system.iocache.overall_misses::total             8851                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1609809480                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1614881480                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19830913268                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19830913268                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1609809480                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1615233980                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1609809480                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1615233980                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8810                       # number of overall misses
+system.iocache.overall_misses::total             8850                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1621911166                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1626980166                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12610487430                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12610487430                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1621911166                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1627331166                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1621911166                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1627331166                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8811                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8848                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8811                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8851                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8810                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8850                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8811                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8851                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8810                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8850                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182513.729656                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 182704.514811                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182491.693594                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 182704.514811                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182491.693594                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        110252                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183901.906409                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31681                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16154                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3345                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.825059                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.471151                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8811                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8848                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8811                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8851                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8810                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8850                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8811                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8851                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1150531536                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1153673536                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14284309344                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14284309344                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1150531536                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1153867036                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1150531536                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1153867036                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8810                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1181411166                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1184630166                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1181411166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1184831166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1181411166                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1184831166                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 130365.725455                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 130365.725455                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              408284                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408284                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33682                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33682                       # Transaction distribution
-system.membus.trans_dist::Writeback           1083893                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       602073                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       602073                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35223                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
+system.membus.trans_dist::ReadResp             407867                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
+system.membus.trans_dist::Writeback           1073811                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           187846                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35358                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35226                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            413056                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           413056                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122652                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp           35361                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            899707                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           899707                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        352894                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3600651                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3730211                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4065512                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155805                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3753956                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3883578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4225292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    143052172                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    143222109                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14066304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14066304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               157288413                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3023                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2576774                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    141818700                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    141988686                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7244096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7244096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               149232782                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2955                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2747442                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2576774    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2747442    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2576774                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104078000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2747442                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           104159500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5439500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5443500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9540063820                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7279924206                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4726359104                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6776038462                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151502434                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228860056                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1984,6 +2018,6 @@ system.realview.ethernet.coalescedTotal             0                       # av
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16160                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16150                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 3de7ccdf1..8076f9ab6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,172 +1,172 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.385466                       # Number of seconds simulated
-sim_ticks                                47385466309500                       # Number of ticks simulated
-final_tick                               47385466309500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.309771                       # Number of seconds simulated
+sim_ticks                                47309771277000                       # Number of ticks simulated
+final_tick                               47309771277000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109383                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128637                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5566054279                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 771804                       # Number of bytes of host memory used
-host_seconds                                  8513.30                       # Real time elapsed on the host
-sim_insts                                   931207580                       # Number of instructions simulated
-sim_ops                                    1095127739                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 108265                       # Simulator instruction rate (inst/s)
+host_op_rate                                   127309                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5527040503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 775928                       # Number of bytes of host memory used
+host_seconds                                  8559.69                       # Real time elapsed on the host
+sim_insts                                   926711685                       # Number of instructions simulated
+sim_ops                                    1089722710                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       167872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       148672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4509472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         15471624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     18877376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       171456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       164224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3092064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12069648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     17196544                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        427520                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             72296472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4509472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3092064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7601536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     87689472                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       238272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       235456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4799840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         48757000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     23433152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       111936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        80000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2674208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         14294352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12912064                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        433024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            107969304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4799840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2674208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7474048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     89515968                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          87710056                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2623                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2323                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             86413                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            241757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       294959                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2679                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2566                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             48357                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            188601                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       268696                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6680                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1145654                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1370148                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          89536552                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         3723                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         3679                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             90950                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            761841                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       366143                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1749                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1250                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             41828                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            223362                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       201751                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6766                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1703042                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1398687                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1372722                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               95166                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              326506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       398379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               65253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              254712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       362908                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1525710                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          95166                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          65253                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             160419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1850556                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1401261                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          5036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          4977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              101456                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1030590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       495313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2366                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1691                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              302144                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       272926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9153                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2282178                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         101456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56525                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             157981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1892124                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1850991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1850556                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              95166                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             326940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       398379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3618                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3466                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              65253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             254712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       362908                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9022                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3376701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1145654                       # Number of read requests accepted
-system.physmem.writeReqs                      2060182                       # Number of write requests accepted
-system.physmem.readBursts                     1145654                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2060182                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 73301632                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20224                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 128743424                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  72296472                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              131707496                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      316                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   48535                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         120456                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               65572                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               75328                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               66668                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               73797                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               73498                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               82651                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               70750                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               70075                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               62480                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               88491                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              66146                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              72268                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              67491                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              74959                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              69333                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              65831                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              122352                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              129436                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              124260                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              131298                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              127700                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              133890                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              125807                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              124647                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              116114                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              124444                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             122980                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             126137                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             123363                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             128612                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             126014                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             124562                       # Per bank write bursts
+system.physmem.bw_write::total                1892559                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1892124                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         5036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         4977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             101456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1031025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       495313                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2366                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1691                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             302144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       272926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9153                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4174737                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1703042                       # Number of read requests accepted
+system.physmem.writeReqs                      1401261                       # Number of write requests accepted
+system.physmem.readBursts                     1703042                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1401261                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                108957568                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  89535296                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 107969304                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               89536552                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         222271                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              104244                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              111881                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              106230                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              103315                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              101355                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              106401                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              102755                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              105565                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              101297                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              131029                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             105406                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             116947                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              96908                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             102973                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             100156                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             106000                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               86649                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               91854                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               85255                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               87156                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               84624                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               89053                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               87549                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               90107                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               85432                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               90372                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              86508                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              91779                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              81073                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              87139                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              84132                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              90307                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                       81198                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47385464863500                       # Total gap between requests
+system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47309769886500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1124296                       # Read request sizes (log2)
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 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
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 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
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 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1398687                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::24                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
@@ -188,136 +188,168 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples      1120451                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      180.324302                       # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev     247.440504                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         698811     62.37%     62.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       221320     19.75%     82.12% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::384-511        27543      2.46%     90.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21267      1.90%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12605      1.12%     93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9064      0.81%     93.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8274      0.74%     94.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        59900      5.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1120451                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         73379                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.608158                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       65.872388                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           73373     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           73379                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         73379                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.414056                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.095862                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev      903.451601                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-4095          73376    100.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::98304-102399            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::102400-106495            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192512-196607            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           73379                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    58866128789                       # Total ticks spent queuing
-system.physmem.totMemAccLat               80341216289                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5726690000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       51396.29                       # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::total        1072258                       # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean        21.254829                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::total           80097                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         80097                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::gmean       17.028138                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             7      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           80097                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    88359532056                       # Total ticks spent queuing
+system.physmem.totMemAccLat              120280694556                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8512310000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51901.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  70146.29                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.78                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  70651.03                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.89                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.89                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.33                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     867894                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1168605                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.78                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14781000.92                       # Average gap between requests
-system.physmem.pageHitRate                      64.51                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4336385760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2366083500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4510974000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6605647200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3094987836720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1170067048560                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27404900969250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31687774944990                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.723600                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45590272941113                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582304620000                       # Time in different power states
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1368420                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    660769                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.38                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15240061.90                       # Average gap between requests
+system.physmem.pageHitRate                      65.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4037576760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2203042875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6565556400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4550560560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1167667097760                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27361592107500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31636660066815                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.713051                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45518112024303                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1579777160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    212884395887                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    211880830197                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4134208680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2255768625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4422568800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               6429624480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3094987836720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1167604821270                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27407060817750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31686895646325                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.705044                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45593855726560                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582304620000                       # Time in different power states
+system.physmem_1.actEnergy                 4068693720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2220021375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6713584800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4514888160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1175652112905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27354587708250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31637801134170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.737170                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45506397156129                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1579777160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    209300747940                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    223594850121                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -351,15 +383,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              143219505                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         95215917                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6874228                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           100849572                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               65904871                       # Number of BTB hits
+system.cpu0.branchPred.lookups              148829565                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         98586451                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          7318222                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           104779817                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               69383898                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.349678                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               19505246                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            190029                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            66.218762                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               20536581                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            208145                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -390,88 +422,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   557114                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               557114                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11925                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88835                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       245678                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       311436                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  1783.814331                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       309571     99.40%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1396      0.45%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          332      0.11%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143           57      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           59      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       311436                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       275434                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767       261399     94.90%     94.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535        11343      4.12%     99.02% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303         1146      0.42%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071          802      0.29%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839          102      0.04%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607          163      0.06%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375          287      0.10%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143           70      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911           43      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679           36      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-425983            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::425984-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       275434                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 527372589640                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.581951                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.533395                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 526425698140     99.82%     99.82% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    513345500      0.10%     99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    204440500      0.04%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7     94120000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     67519500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     37561500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     13535000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     16113500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       245000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 527372589640                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        88835     88.16%     88.16% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11925     11.84%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       100760                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       557114                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   633176                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               633176                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        15593                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       103829                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       293482                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       339694                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2057.107279                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 12691.149268                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-32767       334819     98.56%     98.56% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-65535         2369      0.70%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-98303          775      0.23%     99.49% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-131071         1050      0.31%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-163839          325      0.10%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::163840-196607          166      0.05%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-229375           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::229376-262143           24      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-294911           28      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::294912-327679           54      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-360447           18      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::360448-393215           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-491519            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       339694                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       334006                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19047.289570                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15950.264710                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 18217.957975                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       329273     98.58%     98.58% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3345      1.00%     99.58% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          501      0.15%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          607      0.18%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          176      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           53      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           15      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       334006                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 554756829244                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.612373                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.535164                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 553440790244     99.76%     99.76% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    774310500      0.14%     99.90% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    264675000      0.05%     99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    116251500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     83135500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     43553500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     14917000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     18677500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       518500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 554756829244                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K       103830     86.94%     86.94% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        15593     13.06%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       119423                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       633176                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       557114                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       100760                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       633176                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       119423                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       100760                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       657874                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       119423                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       752599                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   103903304                       # DTB read hits
-system.cpu0.dtb.read_misses                    386941                       # DTB read misses
-system.cpu0.dtb.write_hits                   87265042                       # DTB write hits
-system.cpu0.dtb.write_misses                   170173                       # DTB write misses
+system.cpu0.dtb.read_hits                   108615139                       # DTB read hits
+system.cpu0.dtb.read_misses                    465587                       # DTB read misses
+system.cpu0.dtb.write_hits                   88878639                       # DTB write hits
+system.cpu0.dtb.write_misses                   167589                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44809                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1073                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   37535                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      216                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  6819                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   45162                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      301                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7481                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    40407                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               104290245                       # DTB read accesses
-system.cpu0.dtb.write_accesses               87435215                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    44285                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               109080726                       # DTB read accesses
+system.cpu0.dtb.write_accesses               89046228                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        191168346                       # DTB hits
-system.cpu0.dtb.misses                         557114                       # DTB misses
-system.cpu0.dtb.accesses                    191725460                       # DTB accesses
+system.cpu0.dtb.hits                        197493778                       # DTB hits
+system.cpu0.dtb.misses                         633176                       # DTB misses
+system.cpu0.dtb.accesses                    198126954                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -501,1134 +535,1164 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    85759                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                85759                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          908                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        62470                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         9907                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        75852                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1136.575173                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  8938.964276                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        75266     99.23%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          257      0.34%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          133      0.18%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          159      0.21%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839            9      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                    92658                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                92658                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1215                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67279                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        10404                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        82254                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1278.472779                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8944.038924                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        81396     98.96%     98.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          425      0.52%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          229      0.28%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          180      0.22%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        75852                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        73285                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        71796     97.97%     97.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1220      1.66%     99.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          122      0.17%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           69      0.09%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           44      0.06%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           20      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           12      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        73285                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 394225556964                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.858766                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.348387                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    55694159292     14.13%     14.13% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   338516533172     85.87%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       13791500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        1055500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4          17500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 394225556964                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        62470     98.57%     98.57% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          908      1.43%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        63378                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        82254                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        78898                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 24333.924814                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 20592.654972                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 23297.887242                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        76185     96.56%     96.56% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         2219      2.81%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          249      0.32%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143          140      0.18%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           58      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        78898                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 417288840772                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.850626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.356648                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    62357623096     14.94%     14.94% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   354908424176     85.05%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       20580000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1826000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         387500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 417288840772                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        67279     98.23%     98.23% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         1215      1.77%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        68494                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85759                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85759                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        92658                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        92658                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        63378                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        63378                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       149137                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   225166936                       # ITB inst hits
-system.cpu0.itb.inst_misses                     85759                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        68494                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        68494                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       161152                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   234838704                       # ITB inst hits
+system.cpu0.itb.inst_misses                     92658                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44809                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1073                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   26709                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   33056                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   217420                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   232539                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               225252695                       # ITB inst accesses
-system.cpu0.itb.hits                        225166936                       # DTB hits
-system.cpu0.itb.misses                          85759                       # DTB misses
-system.cpu0.itb.accesses                    225252695                       # DTB accesses
-system.cpu0.numCycles                       777590959                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               234931362                       # ITB inst accesses
+system.cpu0.itb.hits                        234838704                       # DTB hits
+system.cpu0.itb.misses                          92658                       # DTB misses
+system.cpu0.itb.accesses                    234931362                       # DTB accesses
+system.cpu0.numCycles                       826354541                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          90148881                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     632830647                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  143219505                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          85410117                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    647310508                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               14846236                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1771940                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              282653                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6199385                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       737729                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       721364                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                224948990                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1718929                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  28705                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         754595578                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.984480                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.221164                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          96417195                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     658349874                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  148829565                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          89920479                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    686511551                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               15731276                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2082372                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              301509                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6642770                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       777478                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       876995                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                234604466                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1859928                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  30773                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         801475508                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.962394                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.215680                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               398817072     52.85%     52.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               138444624     18.35%     71.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                47562041      6.30%     77.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               169771841     22.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               432057914     53.91%     53.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               143320091     17.88%     71.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                50277190      6.27%     78.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               175820313     21.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           754595578                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.184184                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.813835                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               107688832                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            365256192                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                237731032                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             38638584                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5280938                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            20683549                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2184734                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             657953246                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             23988018                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5280938                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               144086550                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               51798126                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     247348242                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                239349699                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             66732023                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             640403541                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6134927                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              9593053                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                279391                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                288384                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              30790790                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           11378                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          609803525                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            987601051                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       757009838                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           819226                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            550929032                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                58874487                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16040201                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14019715                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 78263207                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           104115554                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           90761559                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9526213                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8179417                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 617656959                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16134834                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                622248752                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2762846                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       55648828                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     35830856                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        282296                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    754595578                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.824612                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.071196                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           801475508                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.180104                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.796692                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               115405888                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            393574581                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                246061591                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             40857295                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5576153                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            21574429                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2334934                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             682682220                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             25205347                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5576153                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               153705251                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               60022582                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     253017805                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                248013590                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             81140127                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             664288996                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6473093                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10525488                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                404111                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                973821                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              42702914                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           12474                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          634198397                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups           1026536806                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       783997445                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           728382                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            571881769                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                62316623                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          17028830                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      14786866                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 82376276                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           108687128                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           92520441                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9956675                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8516242                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 640223835                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           17051325                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                645202743                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2940745                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       58459841                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     38213470                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        295844                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    801475508                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.805019                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.062618                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          416444489     55.19%     55.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          139981431     18.55%     73.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          120577545     15.98%     89.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           69261363      9.18%     98.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8325608      1.10%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5142      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          449210773     56.05%     56.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          147559174     18.41%     74.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          124891919     15.58%     90.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           71400363      8.91%     98.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            8407753      1.05%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               5526      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      754595578                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      801475508                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               64632492     45.32%     45.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 49764      0.03%     45.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  24321      0.02%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               8      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.37% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              36912792     25.88%     71.25% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             41006253     28.75%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               66711662     45.46%     45.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 70956      0.05%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  22678      0.02%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              31      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              38740309     26.40%     71.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             41215825     28.08%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            425093937     68.32%     68.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1435088      0.23%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                72707      0.01%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         80017      0.01%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           106973715     17.19%     85.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           88593239     14.24%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            441248281     68.39%     68.39% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1607382      0.25%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                84016      0.01%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                 12      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         46433      0.01%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           111952136     17.35%     86.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           90264483     13.99%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             622248752                       # Type of FU issued
-system.cpu0.iq.rate                          0.800226                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  142625630                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.229210                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2143120412                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        689044772                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    604966692                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1361144                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            552290                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       506244                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             764032585                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 841796                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2890526                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             645202743                       # Type of FU issued
+system.cpu0.iq.rate                          0.780782                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  146761461                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.227466                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2240404538                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        715416173                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    626754280                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1178660                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            474470                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       433754                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             791232333                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 731871                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         3009936                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     12594321                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        16775                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       157768                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6060902                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     13422485                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        18059                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       156652                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      6220264                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2889033                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4437246                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2933130                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      5035754                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5280938                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                6404578                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              3121375                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          633914393                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5576153                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                8424043                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              6068776                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          657405938                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            104115554                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            90761559                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13746258                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 66239                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              2987519                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        157768                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2095186                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2941806                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5036992                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            614307958                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            103896068                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7396426                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            108687128                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            92520441                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          14528017                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 62220                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              5930416                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        156652                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2211475                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3142674                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5354149                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            636790575                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            108609704                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7786358                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       122600                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   191163401                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               115873704                       # Number of branches executed
-system.cpu0.iew.exec_stores                  87267333                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.790014                       # Inst execution rate
-system.cpu0.iew.wb_sent                     606266119                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    605472936                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                293481694                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                481488998                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       130778                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   197486892                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               120113448                       # Number of branches executed
+system.cpu0.iew.exec_stores                  88877188                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.770602                       # Inst execution rate
+system.cpu0.iew.wb_sent                     628006707                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    627188034                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                305309945                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                500537218                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.778652                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609529                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.758982                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609965                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       48614829                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15852538                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4732048                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    745378077                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.775637                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.576449                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       51032011                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       16755481                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          5028737                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    791775198                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.756295                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.558039                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    493396348     66.19%     66.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    129662648     17.40%     83.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     56044004      7.52%     91.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     18992920      2.55%     93.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13761945      1.85%     95.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9179296      1.23%     96.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6220016      0.83%     97.57% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3818014      0.51%     98.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14302886      1.92%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    529474510     66.87%     66.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    135713871     17.14%     84.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     58480062      7.39%     91.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     19506672      2.46%     93.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     13859320      1.75%     95.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      9636766      1.22%     96.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6431343      0.81%     97.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3969096      0.50%     98.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14703558      1.86%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    745378077                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           491403423                       # Number of instructions committed
-system.cpu0.commit.committedOps             578142958                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    791775198                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           510225692                       # Number of instructions committed
+system.cpu0.commit.committedOps             598815315                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     176221889                       # Number of memory references committed
-system.cpu0.commit.loads                     91521232                       # Number of loads committed
-system.cpu0.commit.membars                    3904419                       # Number of memory barriers committed
-system.cpu0.commit.branches                 110044339                       # Number of branches committed
-system.cpu0.commit.fp_insts                    493876                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                530522943                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            14584303                       # Number of function calls committed.
+system.cpu0.commit.refs                     181564818                       # Number of memory references committed
+system.cpu0.commit.loads                     95264643                       # Number of loads committed
+system.cpu0.commit.membars                    4026241                       # Number of memory barriers committed
+system.cpu0.commit.branches                 114090927                       # Number of branches committed
+system.cpu0.commit.fp_insts                    424114                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                549390032                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            15322892                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       400598379     69.29%     69.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1193753      0.21%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           57671      0.01%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        71224      0.01%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       91521232     15.83%     85.35% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      84700657     14.65%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       415791168     69.44%     69.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1352857      0.23%     69.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           66520      0.01%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        39952      0.01%     69.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       95264643     15.91%     85.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      86300175     14.41%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        578142958                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14302886                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1353470869                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1262695982                       # The number of ROB writes
-system.cpu0.timesIdled                        1015060                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       22995381                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93993341722                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  491403423                       # Number of Instructions Simulated
-system.cpu0.committedOps                    578142958                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.582388                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.582388                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.631956                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.631956                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               725839901                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              430463320                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   805500                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  450680                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                133543353                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               134332816                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1348291201                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16059632                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6141043                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          503.422627                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          163818652                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6141554                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            26.673811                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1929842500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.422627                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983247                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.983247                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total        598815315                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14703558                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1422522153                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1309355495                       # The number of ROB writes
+system.cpu0.timesIdled                        1107002                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       24879033                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93793188049                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  510225692                       # Number of Instructions Simulated
+system.cpu0.committedOps                    598815315                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.619586                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.619586                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.617442                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.617442                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               751256572                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              446675945                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   709287                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  346140                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                138932349                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               139558794                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1422736351                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              16846265                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          6557508                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          508.746857                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          168230159                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6558019                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            25.652588                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1887096000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.746857                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993646                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.993646                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          366                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        365108655                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       365108655                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     84789793                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       84789793                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     73815215                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      73815215                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       223529                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       223529                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       254722                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       254722                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1935633                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1935633                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1977053                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1977053                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    158605008                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       158605008                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    158828537                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      158828537                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6791004                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6791004                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7631461                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7631461                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       739012                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       739012                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       806083                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       806083                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       273207                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       273207                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195599                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       195599                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     14422465                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      14422465                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     15161477                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     15161477                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101570086088                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 101570086088                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 139050346077                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 139050346077                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  37625975422                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  37625975422                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3995007021                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3995007021                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4127543324                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4127543324                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2928500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2928500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 240620432165                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 240620432165                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 240620432165                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 240620432165                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     91580797                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     91580797                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     81446676                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     81446676                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       962541                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       962541                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1060805                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1060805                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2208840                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2208840                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2172652                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2172652                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    173027473                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    173027473                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    173990014                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    173990014                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074153                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.074153                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.093699                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.093699                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.767772                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767772                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.759879                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.759879                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.123688                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.123688                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.090028                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.090028                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083354                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.083354                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087140                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.087140                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18220.671779                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 46677.544896                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21102.067618                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        376736198                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       376736198                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     88222232                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       88222232                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     74841943                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      74841943                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       232729                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       232729                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258353                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       258353                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1906592                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1906592                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1977838                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1977838                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    163064175                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       163064175                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    163296904                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      163296904                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      7298679                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7298679                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      8186484                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      8186484                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       785305                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       785305                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       832077                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       832077                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       303324                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       303324                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       192936                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       192936                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     15485163                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      15485163                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     16270468                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     16270468                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111692276000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 111692276000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 148685242611                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 148685242611                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  79029404267                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  79029404267                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4531612500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4531612500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4045324000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4045324000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3600000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3600000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 260377518611                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 260377518611                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 260377518611                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 260377518611                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     95520911                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     95520911                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     83028427                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     83028427                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1018034                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1018034                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1090430                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1090430                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2209916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2209916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2170774                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2170774                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    178549338                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    178549338                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    179567372                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    179567372                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076409                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.076409                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.098599                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.098599                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771394                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.771394                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763072                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763072                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.137256                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.137256                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088879                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088879                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086728                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086728                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.090609                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.090609                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15303.081010                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15303.081010                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18162.283419                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18162.283419                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 94978.474669                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 94978.474669                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14939.841556                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14939.841556                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20967.180827                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20967.180827                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16683.724465                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16683.724465                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15870.513946                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15870.513946                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     10994171                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     20243365                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           733732                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         746062                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.983906                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    27.133623                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16814.645000                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16814.645000                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16003.074934                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16003.074934                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     24592023                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     22766928                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           764014                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         809850                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.187922                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    28.112525                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4196368                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4196368                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3475469                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3475469                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6119501                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6119501                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         4173                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         4173                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141236                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141236                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9594970                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9594970                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9594970                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9594970                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3315535                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3315535                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1511960                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1511960                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       732291                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       732291                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       801910                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       801910                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       131971                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       131971                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195594                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       195594                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4827495                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4827495                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5559786                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5559786                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31767                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31767                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31179                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31179                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62946                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62946                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  45402822425                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45402822425                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  28839272084                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  28839272084                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16627256811                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16627256811                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  36253693272                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  36253693272                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1734403771                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1734403771                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3825076676                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3825076676                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2835500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2835500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  74242094509                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  74242094509                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  90869351320                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  90869351320                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5616435750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5616435750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5304462017                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5304462017                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10920897767                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10920897767                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036203                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036203                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018564                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018564                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.760789                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.760789                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.755945                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.755945                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059747                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059747                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.090025                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.090025                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027900                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027900                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031955                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031955                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13693.965657                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13693.965657                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19074.097254                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19074.097254                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22705.805221                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 45209.179674                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19556.206612                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      4422416                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4422416                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3749707                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3749707                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6590276                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6590276                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4547                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4547                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       153940                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       153940                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data     10339983                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     10339983                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data     10339983                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     10339983                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3548972                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3548972                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1596208                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1596208                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       778051                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       778051                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       827530                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       827530                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       149384                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       149384                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       192928                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       192928                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5145180                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5145180                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5923231                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5923231                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20289                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22269                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        42558                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  52135719000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  52135719000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31476098425                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  31476098425                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17784168000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17784168000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  78021331267                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  78021331267                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   2035314000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2035314000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3852473000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3852473000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3523000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3523000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83611817425                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  83611817425                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 101395985425                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 101395985425                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3695888000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3695888000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3839366000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3839366000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7535254000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7535254000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037154                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037154                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019225                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019225                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.764268                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.764268                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758902                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.758902                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.067597                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.067597                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088875                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088875                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028817                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028817                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032986                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032986                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14690.372029                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14690.372029                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.296248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.296248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.329404                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.329404                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94282.178612                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94282.178612                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13624.712151                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13624.712151                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19968.449370                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19968.449370                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15379.010130                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15379.010130                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16344.037580                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16344.037580                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176800.949098                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176800.949098                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170129.318355                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170129.318355                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173496.294713                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173496.294713                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16250.513573                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16250.513573                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17118.357434                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17118.357434                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182162.156834                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182162.156834                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172408.550002                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172408.550002                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177058.461394                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177058.461394                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6182706                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.960451                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          218406038                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6183218                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.322390                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      14060425250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.960451                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999923                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999923                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          6585231                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.955630                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          227602766                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6585743                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.559922                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      17287340000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955630                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999913                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          310                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        456025787                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       456025787                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    218406038                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      218406038                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    218406038                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       218406038                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    218406038                       # number of overall hits
-system.cpu0.icache.overall_hits::total      218406038                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6515233                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6515233                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6515233                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6515233                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6515233                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6515233                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  69121769887                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  69121769887                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  69121769887                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  69121769887                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  69121769887                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  69121769887                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    224921271                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    224921271                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    224921271                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    224921271                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    224921271                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    224921271                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028967                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028967                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028967                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028967                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028967                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028967                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10609.255246                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10609.255246                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10609.255246                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10609.255246                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10609.255246                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10609.255246                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      9343070                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          429                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           716553                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.038910                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    47.666667                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        475737897                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       475737897                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    227602766                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      227602766                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    227602766                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       227602766                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    227602766                       # number of overall hits
+system.cpu0.icache.overall_hits::total      227602766                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6973294                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6973294                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6973294                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6973294                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6973294                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6973294                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  74030582287                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  74030582287                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  74030582287                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  74030582287                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  74030582287                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  74030582287                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    234576060                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    234576060                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    234576060                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    234576060                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    234576060                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    234576060                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029727                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029727                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029727                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029727                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029727                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029727                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10616.300171                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10616.300171                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10616.300171                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10616.300171                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10890869                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          530                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           815898                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.348322                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           53                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       331988                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       331988                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       331988                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       331988                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       331988                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       331988                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6183245                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6183245                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6183245                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6183245                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6183245                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6183245                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       387516                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       387516                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       387516                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       387516                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       387516                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       387516                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6585778                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6585778                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6585778                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6585778                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6585778                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6585778                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  59487086557                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  59487086557                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  59487086557                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  59487086557                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  59487086557                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  59487086557                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1881164498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1881164498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1881164498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   1881164498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027491                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027491                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027491                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027491                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027491                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027491                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9620.690520                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9620.690520                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9620.690520                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9620.690520                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9620.690520                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9620.690520                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88342.467268                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88342.467268                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  67014306188                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  67014306188                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  67014306188                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  67014306188                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  67014306188                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  67014306188                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1863746498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   1863746498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028075                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028075                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028075                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10175.609653                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7927934                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8230587                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit       262068                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8598962                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8934370                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit       290328                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1052933                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2785828                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16244.844688                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          12810731                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2801890                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            4.572175                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      2265530500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7084.641278                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    80.581753                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    91.908936                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4232.509595                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3861.356831                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   893.846295                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.432412                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004918                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005610                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.258332                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.235679                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054556                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.991507                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1296                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14681                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           27                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          251                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          612                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          406                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           47                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1442                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5343                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4502                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3254                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.079102                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.896057                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       290229122                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      290229122                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       541748                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180817                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      5534153                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data      3094433                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       9351151                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      4196351                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      4196351                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       207942                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total       207942                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       120308                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       120308                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36466                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36466                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       968728                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       968728                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       541748                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180817                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5534153                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4063161                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       10319879                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       541748                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180817                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5534153                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4063161                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      10319879                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12343                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9059                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       649075                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data      1080475                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total      1750952                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks           10                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total           10                       # number of Writeback misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       592445                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::total       592445                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       136302                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       136302                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       159123                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       159123                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       299943                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       299943                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12343                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9059                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       649075                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1380418                       # number of demand (read+write) misses
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-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12343                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9059                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       649075                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1380418                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2050895                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    496433453                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    403677084                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  20306210078                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  39087285353                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  60293605968                       # number of ReadReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    252817543                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    252817543                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2986484321                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2986484321                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3304695138                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3304695138                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2772999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2772999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16034165055                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  16034165055                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    496433453                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    403677084                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20306210078                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  55121450408                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  76327771023                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    496433453                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    403677084                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20306210078                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  55121450408                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  76327771023                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       554091                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       189876                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      6183228                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data      4174908                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total     11102103                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      4196361                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      4196361                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       800387                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::total       800387                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       256610                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       256610                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195589                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       195589                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1268671                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1268671                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       554091                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       189876                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      6183228                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       554091                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       189876                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      6183228                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5443579                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     12370774                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022276                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.047710                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.104973                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.258802                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.157714                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.740198                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.740198                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.531164                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.531164                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.813558                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.813558                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1159342                       # number of prefetches not generated due to page crossing
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+system.cpu0.l2cache.tags.tagsinuse       16246.172494                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          22237347                       # Total number of references to valid blocks.
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+system.cpu0.l2cache.tags.avg_refs            7.301035                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     15974403000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7087.125273                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.689704                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker   100.487660                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4186.697540                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3865.106436                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   931.065881                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.432564                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004620                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14155                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           86                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          252                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          649                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          433                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           77                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          782                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4799                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4726                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3642                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.086670                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.863953                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       448543088                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      448543088                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       611768                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       192592                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        804360                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      4422408                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      4422408                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       116889                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       116889                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        39729                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        39729                       # number of SCUpgradeReq hits
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+system.cpu0.l2cache.ReadExReq_hits::total      1062033                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5870980                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5870980                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3339122                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      3339122                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       194533                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       194533                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       611768                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       192592                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5870980                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      4401155                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       11076495                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       611768                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       192592                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5870980                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      4401155                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      11076495                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        14162                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11237                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        25399                       # number of ReadReq misses
+system.cpu0.l2cache.Writeback_misses::writebacks            6                       # number of Writeback misses
+system.cpu0.l2cache.Writeback_misses::total            6                       # number of Writeback misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       131236                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       131236                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       153191                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       153191                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296814                       # number of ReadExReq misses
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+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       714775                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       714775                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1134930                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1134930                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       631728                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       631728                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        14162                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11237                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       714775                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1431744                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2171918                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        14162                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11237                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       714775                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1431744                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2171918                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    627635500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    557924000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   1185559500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2881179498                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2881179498                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3211389999                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3211389999                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3406498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3406498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  17257972999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  17257972999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22144079998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22144079998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43103483484                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43103483484                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  74596156500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  74596156500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    627635500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    557924000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22144079998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  60361456483                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  83691095981                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    627635500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    557924000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22144079998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  60361456483                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  83691095981                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       625930                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       203829                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       829759                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      4422414                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      4422414                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       248125                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       248125                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       192920                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       192920                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1358847                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1358847                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6585755                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      6585755                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4474052                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4474052                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       826261                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       625930                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       203829                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       625930                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       203829                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      6585755                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5832899                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     13248413                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.030610                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.528911                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.528911                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.794065                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.794065                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.236423                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.236423                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022276                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.047710                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.104973                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253586                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.165786                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022276                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.047710                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.104973                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253586                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.165786                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40219.837398                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44560.887957                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31284.843936                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36176.020133                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34434.756617                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   426.735888                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   426.735888                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21910.788697                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21910.788697                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20768.180200                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20768.180200                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 554599.800000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 554599.800000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53457.373751                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53457.373751                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40219.837398                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44560.887957                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31284.843936                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39930.984968                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37216.810721                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40219.837398                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44560.887957                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31284.843936                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39930.984968                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37216.810721                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           70                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.218431                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.218431                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.108533                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.108533                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253669                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253669                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.764562                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.764562                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.108533                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245460                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.163938                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.108533                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245460                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.163938                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46677.408559                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21954.185574                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21954.185574                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20963.307237                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20963.307237                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 425812.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 425812.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58144.066651                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58144.066651                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30980.490361                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30980.490361                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37978.979747                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37978.979747                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 118082.713605                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 118082.713605                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38533.266901                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38533.266901                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          232                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           35                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    77.333333                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1537125                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1537125                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          146                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           10                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         4037                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         4196                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           18                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           18                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        22490                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        22490                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          146                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           10                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        26527                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        26686                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
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 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
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-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022271                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.046941                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.104972                       # mshr miss rate for ReadReq accesses
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-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.030432                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.740176                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.740176                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.531164                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.531164                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.813558                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.813558                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.528911                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.528911                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794065                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.794065                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.218696                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.218696                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022271                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.046941                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.104972                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248713                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.163628                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022271                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.046941                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.104972                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248713                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.199728                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.199728                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.108533                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252457                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252457                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.764534                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.764534                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.161599                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227508                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226467                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40647.994139                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65257.964947                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.799979                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20803.799979                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15571.195403                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15571.195403                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 368062.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 368062.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46048.485626                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46048.485626                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24980.193654                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31809.070604                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31809.070604                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 112085.930933                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 112085.930933                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31438.523322                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41125.621412                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174158.632757                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125953.995623                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164664.824060                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164664.824060                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169190.879905                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 139454.769890                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      13667246                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11407678                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38779                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        31179                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      4196361                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1120333                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp           10                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1176973                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       800387                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       496358                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       355576                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       523512                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           86                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          143                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1407436                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1277584                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     12409061                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17898439                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414925                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1222034                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         31944459                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    396067296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    675577736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1519008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4432728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1077596768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    4739028                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     22459193                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.235945                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.424588                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq       1048889                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     12194005                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        22269                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      8425423                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     11622390                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1249461                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       495211                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       344893                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       512947                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1710859                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1368930                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6585778                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6660291                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       932989                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       826261                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19798041                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     21027852                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       446745                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1372185                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         42644823                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    421828960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    663719558                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1630632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5007440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1092186590                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   11579815                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     39116658                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.312501                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.463513                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          17160060     76.41%     76.41% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           5299133     23.59%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          26892655     68.75%     68.75% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          12224003     31.25%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      22459193                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   14039414488                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      39116658                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   18374497429                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    204401970                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    206346476                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9316604024                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9904865164                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8912883405                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   9419389746                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    225880552                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    243194937                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    669143268                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    746720066                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              128543512                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         85865577                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6421624                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            90850028                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               59627534                       # Number of BTB hits
+system.cpu1.branchPred.lookups              121710225                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         81714662                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5979961                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            85476181                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               55576245                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.632929                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17292026                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            181846                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            65.019570                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16076930                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            165894                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1658,83 +1722,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   599268                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               599268                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        13824                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        99235                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       280644                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       318624                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  1973.247464                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       316338     99.28%     99.28% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1742      0.55%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          377      0.12%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143           71      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           83      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   527361                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               527361                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10839                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        84415                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       237711                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       289650                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2083.972035                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12311.346834                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       287768     99.35%     99.35% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1260      0.44%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          464      0.16%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143           78      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           55      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           21      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       318624                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       319817                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       316762     99.04%     99.04% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         2191      0.69%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          345      0.11%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          267      0.08%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          157      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           61      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           16      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       319817                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 467242764496                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.609754                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.540089                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 466086530996     99.75%     99.75% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    677505500      0.15%     99.90% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    222526000      0.05%     99.95% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    100711000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     81855500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     40422000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     15395000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     17231500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       579500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 467242764496                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        99236     87.77%     87.77% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        13824     12.23%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       113060                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       599268                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       289650                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       263786                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 17712.334999                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 15356.267972                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 12186.421874                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       262356     99.46%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1127      0.43%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          155      0.06%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           73      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           35      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           26      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       263786                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 425904638364                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.594204                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.544845                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 424921434364     99.77%     99.77% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    524417000      0.12%     99.89% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    206354500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    102255000      0.02%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     73118500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     43959500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     13868000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     18884000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       347500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 425904638364                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        84415     88.62%     88.62% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        10839     11.38%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        95254                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       527361                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       599268                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       113060                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       527361                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        95254                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       113060                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       712328                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        95254                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       622615                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    95146273                       # DTB read hits
-system.cpu1.dtb.read_misses                    436726                       # DTB read misses
-system.cpu1.dtb.write_hits                   76756681                       # DTB write hits
-system.cpu1.dtb.write_misses                   162542                       # DTB write misses
+system.cpu1.dtb.read_hits                    90076123                       # DTB read hits
+system.cpu1.dtb.read_misses                    364024                       # DTB read misses
+system.cpu1.dtb.write_hits                   74326349                       # DTB write hits
+system.cpu1.dtb.write_misses                   163337                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44809                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1073                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   41064                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      604                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6738                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   33241                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      185                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  5418                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    39860                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                95582999                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76919223                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    36861                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                90440147                       # DTB read accesses
+system.cpu1.dtb.write_accesses               74489686                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        171902954                       # DTB hits
-system.cpu1.dtb.misses                         599268                       # DTB misses
-system.cpu1.dtb.accesses                    172502222                       # DTB accesses
+system.cpu1.dtb.hits                        164402472                       # DTB hits
+system.cpu1.dtb.misses                         527361                       # DTB misses
+system.cpu1.dtb.accesses                    164929833                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1764,1128 +1828,1155 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    83675                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                83675                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          922                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        60249                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9641                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        74034                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1137.571926                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  8570.962609                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        73376     99.11%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          334      0.45%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          142      0.19%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          157      0.21%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        74034                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        70812                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        68933     97.35%     97.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1547      2.18%     99.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          153      0.22%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143          111      0.16%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           33      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           27      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    77446                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                77446                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          594                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55102                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore         9325                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        68121                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1127.809339                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8184.124599                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        67907     99.69%     99.69% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071          190      0.28%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        68121                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        65021                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21947.540026                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19801.580238                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14876.528667                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        64283     98.86%     98.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          594      0.91%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607           78      0.12%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           16      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        70812                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 419972060240                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.852209                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.355033                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    62087724216     14.78%     14.78% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   357865938524     85.21%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       17105000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        1290000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4           2500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 419972060240                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        60249     98.49%     98.49% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          922      1.51%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        61171                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        65021                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 387249857200                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.854665                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.352569                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    56297043096     14.54%     14.54% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   330938122104     85.46%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       13360500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        1244000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          37500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          50000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 387249857200                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        55102     98.93%     98.93% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          594      1.07%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        55696                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        83675                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        83675                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77446                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77446                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61171                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61171                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       144846                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   203060553                       # ITB inst hits
-system.cpu1.itb.inst_misses                     83675                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55696                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55696                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       133142                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   191622824                       # ITB inst hits
+system.cpu1.itb.inst_misses                     77446                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44809                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1073                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29792                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   23450                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   217868                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   204512                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               203144228                       # ITB inst accesses
-system.cpu1.itb.hits                        203060553                       # DTB hits
-system.cpu1.itb.misses                          83675                       # DTB misses
-system.cpu1.itb.accesses                    203144228                       # DTB accesses
-system.cpu1.numCycles                       689224896                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               191700270                       # ITB inst accesses
+system.cpu1.itb.hits                        191622824                       # DTB hits
+system.cpu1.itb.misses                          77446                       # DTB misses
+system.cpu1.itb.accesses                    191700270                       # DTB accesses
+system.cpu1.numCycles                       652098782                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          83111859                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     570743281                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  128543512                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          76919560                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    571668142                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13828506                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1777982                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              253475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6260799                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       781198                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       699050                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                202821648                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1630400                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  27635                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         671466758                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.996773                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.223843                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          77581821                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     539946872                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  121710225                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          71653175                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    543040637                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               12931684                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1632229                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              244335                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      5898534                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       685251                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       721414                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                191398691                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1512045                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  26398                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         636270063                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.997205                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.224602                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               351036099     52.28%     52.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               124470987     18.54%     70.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                43050208      6.41%     77.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               152909464     22.77%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               332513921     52.26%     52.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               118489139     18.62%     70.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                39798398      6.25%     77.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               145468605     22.86%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           671466758                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.186504                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.828094                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               100354838                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            318587695                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                211284340                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             36331371                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4908514                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            18177231                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              2045887                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             591006296                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             22089664                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4908514                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               134210773                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               44178364                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     216212349                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                213325919                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             58630839                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             574898328                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5600894                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              8989963                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                383271                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                860464                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              24265786                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           10988                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          548407946                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            889065279                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       679031773                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           678204                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            493384651                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                55023295                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15514043                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13585261                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 73076002                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            95606432                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           79961275                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8917606                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7761424                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 553073173                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15730545                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                557717167                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2597694                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       51818937                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     33853803                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        272876                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    671466758                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.830595                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.066249                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           636270063                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.186644                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.828014                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                93717841                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            303303779                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                200797968                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             33854734                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               4595741                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            17115460                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1907562                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             560589350                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             20699594                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               4595741                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               125431952                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               39494252                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     209485809                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                202527049                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             54735260                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             545352444                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5255771                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              8923159                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                236326                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                251378                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              23064401                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           10277                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          518904030                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            842346329                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       645518990                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           772636                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            467533188                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                51370836                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14457491                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12765800                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 68374020                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            90157460                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           77360116                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8411660                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7288721                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 524903956                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           14739695                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                529653671                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2395600                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       48736249                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     31414673                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        252865                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    636270063                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.832435                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.069985                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          364901654     54.34%     54.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          131371089     19.56%     73.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          106572496     15.87%     89.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           61289322      9.13%     98.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7327865      1.09%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               4332      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          346386206     54.44%     54.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          123009687     19.33%     73.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          101156259     15.90%     89.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           58544050      9.20%     98.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7169989      1.13%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               3872      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      671466758                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      636270063                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               55930906     44.08%     44.08% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 67479      0.05%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   9405      0.01%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              14      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              34760931     27.40%     71.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             36114343     28.46%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               53039712     43.72%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 43863      0.04%     43.76% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  10928      0.01%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              13      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              32632716     26.90%     70.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             35589452     29.34%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               41      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            380161908     68.16%     68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1344725      0.24%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                78828      0.01%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  3      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   5      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         45642      0.01%     68.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            98115732     17.59%     86.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           77970283     13.98%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            360085884     67.99%     67.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1163863      0.22%     68.20% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                64768      0.01%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         79405      0.01%     68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            92781248     17.52%     85.75% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           75478453     14.25%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             557717167                       # Type of FU issued
-system.cpu1.iq.rate                          0.809195                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  126883078                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.227504                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1915274546                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        620324151                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    541832642                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1107318                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            438573                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       407875                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             683910466                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 689738                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2496582                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             529653671                       # Type of FU issued
+system.cpu1.iq.rate                          0.812229                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  121316684                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.229049                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1818002123                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        587994704                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    514426397                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1287564                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            520666                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       480327                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             650175074                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 795279                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2341712                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11949439                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        17528                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       140940                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5567236                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     11071583                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        15258                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       136605                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5366212                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2504839                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      3936319                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2403910                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      3823950                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4908514                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                7583348                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1594599                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          568926208                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               4595741                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5738657                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1529256                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          539757610                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             95606432                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            79961275                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13359998                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 58436                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1466228                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        140940                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1941130                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2763310                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4704440                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            550354066                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             95142052                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6771828                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             90157460                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            77360116                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12526602                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 63879                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1404906                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        136605                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1813433                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2553447                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4366880                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            522753556                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             90069669                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6385743                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       122490                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   171896040                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               103292614                       # Number of branches executed
-system.cpu1.iew.exec_stores                  76753988                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.798512                       # Inst execution rate
-system.cpu1.iew.wb_sent                     542951378                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    542240517                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                263529127                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                431811268                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       113959                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   164397082                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                97927466                       # Number of branches executed
+system.cpu1.iew.exec_stores                  74327413                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.801648                       # Inst execution rate
+system.cpu1.iew.wb_sent                     515591253                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    514906724                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                248837648                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                408235008                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.786740                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610288                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.789615                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.609545                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       45371481                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15457669                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4415885                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    662874998                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.779913                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.574524                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       42654937                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14486830                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4109860                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    628197112                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.781454                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.577369                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    435019222     65.63%     65.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    119535237     18.03%     83.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     49733246      7.50%     91.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     16752738      2.53%     93.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     12005106      1.81%     95.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8186664      1.24%     96.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5495672      0.83%     97.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3379842      0.51%     98.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12767271      1.93%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    412381395     65.65%     65.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    112703002     17.94%     83.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     47448288      7.55%     91.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15899123      2.53%     93.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     11433065      1.82%     95.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      7648889      1.22%     96.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5327937      0.85%     97.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3177183      0.51%     98.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     12178230      1.94%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    662874998                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           439804157                       # Number of instructions committed
-system.cpu1.commit.committedOps             516984781                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    628197112                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           416485993                       # Number of instructions committed
+system.cpu1.commit.committedOps             490907395                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     158051032                       # Number of memory references committed
-system.cpu1.commit.loads                     83656993                       # Number of loads committed
-system.cpu1.commit.membars                    3709079                       # Number of memory barriers committed
-system.cpu1.commit.branches                  98009532                       # Number of branches committed
-system.cpu1.commit.fp_insts                    399401                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                474457036                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12875376                       # Number of function calls committed.
+system.cpu1.commit.refs                     151079780                       # Number of memory references committed
+system.cpu1.commit.loads                     79085876                       # Number of loads committed
+system.cpu1.commit.membars                    3553216                       # Number of memory barriers committed
+system.cpu1.commit.branches                  92889165                       # Number of branches committed
+system.cpu1.commit.fp_insts                    468052                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                450541794                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            11963242                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       357731742     69.20%     69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1099808      0.21%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           62550      0.01%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        39649      0.01%     69.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       83656993     16.18%     85.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      74394039     14.39%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       338771351     69.01%     69.01% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult         933774      0.19%     69.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           51484      0.01%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        70964      0.01%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       79085876     16.11%     85.33% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      71993904     14.67%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        516984781                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12767271                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1208536006                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1133266670                       # The number of ROB writes
-system.cpu1.timesIdled                         962801                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       17758138                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94081707774                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  439804157                       # Number of Instructions Simulated
-system.cpu1.committedOps                    516984781                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.567118                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.567118                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.638114                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.638114                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               649922276                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              385926927                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   666608                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  325148                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                119080359                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               119756232                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1205246137                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15455536                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5466279                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          430.006906                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          146874051                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5466791                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            26.866593                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8478589492000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.006906                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839857                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.839857                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        328243838                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       328243838                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     77663514                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       77663514                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     64795157                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      64795157                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       170774                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       170774                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        62879                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total        62879                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1733317                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1733317                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1753267                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1753267                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    142458671                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       142458671                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    142629445                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      142629445                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6440843                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6440843                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7141641                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7141641                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       671959                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       671959                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       448993                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       448993                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       259783                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       259783                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195367                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       195367                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13582484                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13582484                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     14254443                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     14254443                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  96129677540                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  96129677540                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 127902484654                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 127902484654                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  14399209171                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  14399209171                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3810993278                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3810993278                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4142660469                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4142660469                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3781500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3781500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 224032162194                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 224032162194                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 224032162194                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 224032162194                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     84104357                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     84104357                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     71936798                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     71936798                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       842733                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       842733                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       511872                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       511872                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1993100                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1993100                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1948634                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1948634                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    156041155                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    156041155                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    156883888                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    156883888                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.076582                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.076582                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.099277                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.099277                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.797357                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.797357                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.877159                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.877159                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.130341                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.130341                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100258                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100258                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.087044                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.087044                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.090860                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.090860                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        490907395                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             12178230                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1145716069                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1075160501                       # The number of ROB writes
+system.cpu1.timesIdled                         888623                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       15828719                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 93967443806                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  416485993                       # Number of Instructions Simulated
+system.cpu1.committedOps                    490907395                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.565716                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.565716                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.638685                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.638685                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               618570567                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              365658107                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   762313                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  433520                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                112664520                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               113502103                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1139246007                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14605610                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5006870                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          430.966811                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          140806906                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5007379                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.119882                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8489665359000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.966811                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841732                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.841732                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        313329932                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       313329932                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     73478112                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       73478112                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     62922278                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      62922278                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       161792                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       161792                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        60224                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        60224                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1740937                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1740937                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1748633                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1748633                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    136400390                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       136400390                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    136562182                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      136562182                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      5886586                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      5886586                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      6650181                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      6650181                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       625497                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       625497                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       420972                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       420972                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       235563                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       235563                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       185045                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       185045                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     12536767                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      12536767                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     13162264                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     13162264                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  84434005000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  84434005000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 115550287907                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 115550287907                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14693527706                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  14693527706                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3280765000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   3280765000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3888950500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3888950500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3327000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3327000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 199984292907                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 199984292907                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 199984292907                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 199984292907                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     79364698                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     79364698                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     69572459                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     69572459                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       787289                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       787289                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       481196                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       481196                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1976500                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1976500                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1933678                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1933678                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    148937157                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    148937157                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    149724446                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    149724446                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074171                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.074171                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.095586                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.095586                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.794495                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.794495                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.874845                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.874845                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119182                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119182                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095696                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095696                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084175                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.084175                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087910                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.087910                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14343.459010                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14343.459010                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17375.510216                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17375.510216                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34903.812382                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 34903.812382                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13927.335787                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13927.335787                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21016.241995                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21016.241995                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15716.654954                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      3725007                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     19991584                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           377661                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         721598                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.863362                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    27.704600                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15951.823377                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15951.823377                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.760960                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15193.760960                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      3842918                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     18319630                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           344375                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         666302                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.159109                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    27.494484                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3504875                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3504875                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3270021                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3270021                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5779466                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5779466                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3415                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total         3415                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       132178                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       132178                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9049487                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9049487                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9049487                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9049487                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3170822                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3170822                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1362175                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1362175                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       671771                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       671771                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       445578                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       445578                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127605                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127605                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195366                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       195366                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4532997                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4532997                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5204768                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5204768                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7126                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7126                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7600                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7600                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14726                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14726                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  42364690330                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  42364690330                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24508372089                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24508372089                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14203530799                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14203530799                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  13616215076                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  13616215076                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1679833771                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1679833771                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3840214031                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3840214031                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3660000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3660000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  66873062419                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  66873062419                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  81076593218                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  81076593218                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    831425000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    831425000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    995372500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    995372500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1826797500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1826797500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037701                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037701                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018936                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018936                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.797134                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.797134                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.870487                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.870487                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064023                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064023                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100258                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100258                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029050                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.029050                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033176                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033176                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3252895                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3252895                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3007786                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3007786                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5379273                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5379273                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3474                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3474                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       121870                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       121870                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      8387059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      8387059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      8387059                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      8387059                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2878800                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2878800                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1270908                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1270908                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       625447                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       625447                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       417498                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       417498                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       113693                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       113693                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       185035                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       185035                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4149708                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4149708                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4775155                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4775155                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18068                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        34063                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38840223500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38840223500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22606708667                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22606708667                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13883914500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13883914500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14151578206                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14151578206                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521353000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521353000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3703986500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3703986500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3256000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3256000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  61446932167                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  61446932167                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75330846667                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  75330846667                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2814873000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2814873000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2522981000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2522981000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5337854000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5337854000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036273                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036273                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018267                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018267                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.794431                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.794431                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.867626                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.867626                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.057522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.057522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095691                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095691                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027862                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027862                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031893                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031893                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13491.810303                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13491.810303                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17787.840400                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17787.840400                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22198.386914                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22198.386914                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33896.158080                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 33896.158080                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13381.237191                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.237191                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20017.761505                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20017.761505                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14807.531558                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14807.531558                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15775.581456                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15775.581456                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155793.280939                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 155793.280939                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157735.604877                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157735.604877                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156705.340105                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156705.340105                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5740789                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.866118                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          196754052                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5741301                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            34.269942                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8518317120500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.866118                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980207                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980207                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5324088                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.812989                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          185755475                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5324600                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            34.886278                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8495816906000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.812989                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980103                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.980103                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          334                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          124                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        411371773                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       411371773                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    196754052                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      196754052                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    196754052                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       196754052                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    196754052                       # number of overall hits
-system.cpu1.icache.overall_hits::total      196754052                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6061167                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6061167                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6061167                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6061167                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6061167                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6061167                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  63767181305                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  63767181305                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  63767181305                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  63767181305                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  63767181305                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  63767181305                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    202815219                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    202815219                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    202815219                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    202815219                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    202815219                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    202815219                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029885                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.029885                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029885                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.029885                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029885                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.029885                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10520.611180                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10520.611180                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10520.611180                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10520.611180                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10520.611180                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      8678948                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets           76                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           693947                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              2                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.506644                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           38                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        388109731                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       388109731                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    185755475                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      185755475                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    185755475                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       185755475                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    185755475                       # number of overall hits
+system.cpu1.icache.overall_hits::total      185755475                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5637082                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5637082                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5637082                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5637082                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5637082                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5637082                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  58647080384                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  58647080384                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  58647080384                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  58647080384                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  58647080384                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  58647080384                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    191392557                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    191392557                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    191392557                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    191392557                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    191392557                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    191392557                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029453                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029453                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029453                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029453                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029453                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029453                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10403.801184                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10403.801184                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10403.801184                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10403.801184                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      8439613                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets           34                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           658051                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.825166                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           34                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       319831                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       319831                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       319831                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       319831                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       319831                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       319831                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5741336                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5741336                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5741336                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5741336                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5741336                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5741336                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       312465                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       312465                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       312465                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       312465                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       312465                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       312465                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5324617                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5324617                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5324617                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5324617                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5324617                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5324617                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  54923658725                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  54923658725                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  54923658725                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  54923658725                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  54923658725                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  54923658725                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6151998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6151998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6151998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6151998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028308                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028308                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028308                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.028308                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028308                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.028308                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9566.355065                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9566.355065                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9566.355065                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9566.355065                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9566.355065                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9566.355065                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91820.865672                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  53161463126                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  53161463126                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  53161463126                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  53161463126                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  53161463126                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  53161463126                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6100998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      6100998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027820                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.027820                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.027820                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9984.091462                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91059.671642                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91059.671642                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7332494                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7535643                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit       175627                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6690086                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6848412                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit       136895                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       929621                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2299794                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13092.282613                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          11932680                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2315440                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.153526                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9714628416493                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5051.662856                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    84.315143                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    91.749127                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3269.093236                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3705.071376                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   890.390874                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.308329                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.005146                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005600                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.199530                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.226140                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.054345                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.799090                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1406                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023          105                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14135                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           76                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          267                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          643                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          420                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           73                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          703                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4677                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4917                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3606                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.085815                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006409                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.862732                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       260544625                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      260544625                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       585527                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       176354                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5103092                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2955317                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       8820290                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3504868                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3504868                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       166502                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       166502                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        71993                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        71993                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35298                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        35298                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       907237                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       907237                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       585527                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       176354                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5103092                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3862554                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9727527                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       585527                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       176354                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5103092                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3862554                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9727527                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13010                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9568                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       638215                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data      1012370                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1673163                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            6                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            6                       # number of Writeback misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       277800                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       277800                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       139883                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       139883                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       160055                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       160055                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           13                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total           13                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       249549                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       249549                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        13010                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9568                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       638215                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1261919                       # number of demand (read+write) misses
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-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9568                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       638215                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1261919                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1922712                       # number of overall misses
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-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    430734867                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  18770053212                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  34728720424                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  54442466711                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    206094146                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    206094146                       # number of WriteInvalidateReq miss cycles
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3019471858                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3326642430                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3326642430                       # number of SCUpgradeReq miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3578499                       # number of SCUpgradeFailReq miss cycles
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-system.cpu1.l2cache.ReadExReq_miss_latency::total  12555468370                       # number of ReadExReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.data  47284188794                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    430734867                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18770053212                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  47284188794                       # number of overall miss cycles
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       185922                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3967687                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.Writeback_accesses::writebacks      3504874                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3504874                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       444302                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       444302                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       211876                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       211876                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195353                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021736                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.051462                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.111162                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.255154                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.159448                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.625250                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.625250                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.660212                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.660212                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.819312                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.819312                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       833652                       # number of prefetches not generated due to page crossing
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.194019                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    18.354708                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4841.731410                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3496.437967                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1023.380912                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.227029                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          222                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          606                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          357                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.895020                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.demand_accesses::cpu1.inst      5324606                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4681956                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10705170                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       527131                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       171477                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5324606                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4681956                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10705170                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.026845                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000006                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000006                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.640058                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.640058                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.821698                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.821698                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.215726                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.215726                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021736                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.051462                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.111162                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246253                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.165036                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021736                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.051462                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.111162                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246253                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.165036                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39427.994466                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45018.276233                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29410.235128                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34304.375302                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32538.650873                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   741.879575                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   741.879575                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21585.695603                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21585.695603                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20784.370560                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.370560                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275269.153846                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275269.153846                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50312.637478                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50312.637478                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39427.994466                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45018.276233                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29410.235128                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37470.066458                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34845.538532                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39427.994466                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45018.276233                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29410.235128                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37470.066458                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34845.538532                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           20                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.229036                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.229036                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.109893                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.109893                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267173                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267173                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.553142                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.553142                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109893                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.258473                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.169456                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109893                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.258473                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.169456                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36120.134371                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21604.928464                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21604.928464                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20599.665873                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20599.665873                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 524833.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 524833.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44355.133795                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44355.133795                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28935.276917                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28935.276917                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32348.469818                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32348.469818                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51934.744938                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51934.744938                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32905.724476                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32905.724476                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs     6.666667                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1059677                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1059677                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            6                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          183                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         3574                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total         3763                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            5                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            5                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        19034                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        19034                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            6                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          183                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        22608                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        22797                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            6                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          183                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        22608                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        22797                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        13004                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9385                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       638215                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data      1008796                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total      1669400                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            6                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            6                       # number of Writeback MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       738806                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       738806                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       277795                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       277795                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       139883                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       139883                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       160055                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       160055                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           13                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           13                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       230515                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       230515                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        13004                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9385                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       638215                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1239311                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1899915                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        13004                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9385                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       638215                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1239311                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       738806                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2638721                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks       947503                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          947503                       # number of writebacks
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+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          197                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total        11124                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         2294                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         2294                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data           25                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total           25                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            7                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        13418                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.Writeback_mshr_misses::total           19                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        99449                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total        99449                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       135316                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       135316                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       152038                       # number of SCUpgradeReq MSHR misses
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+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       233519                       # number of ReadExReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       585138                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       963220                       # number of ReadSharedReq MSHR misses
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       230233                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7571                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       585138                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1196739                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2470296                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7126                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7193                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7600                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7600                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18135                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14726                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14793                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    427470062                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    361612807                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  14605198288                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  27880753226                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  43275034383                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  44447581689                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  44447581689                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   9533570164                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   9533570164                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2794262081                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2794262081                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2375248051                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2375248051                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3051999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3051999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8594281659                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8594281659                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    427470062                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    361612807                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14605198288                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  36475034885                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  51869316042                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    427470062                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    361612807                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14605198288                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  36475034885                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  44447581689                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  96316897731                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5626000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    774397000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    780023000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    938365000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    938365000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5626000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1712762000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1718388000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021726                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050478                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.111162                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.254253                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.159090                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        34130                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    557999500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32826022044                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2716564991                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2716564991                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2299520000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2299520000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8060381997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8060381997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13420310000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13420310000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25345446988                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25345446988                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  10575798500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  10575798500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13420310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33405828985                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  47384138485                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13420310000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33405828985                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  80210160529                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2670265000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2675862500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2403001000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2403001000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5073266000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5078863500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026553                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000006                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000006                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.625239                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.625239                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.660212                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.660212                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.819312                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.819312                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.640058                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.640058                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.821698                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821698                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.199272                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.199272                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021726                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050478                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.111162                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.241842                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.163079                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021726                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050478                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.111162                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.241842                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.218622                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.218622                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109893                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.266538                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.266538                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.553082                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.553082                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.168183                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.226495                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22884.448482                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27637.652435                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25922.507717                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60161.370764                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34318.724829                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34318.724829                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19975.708850                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14840.199000                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14840.199000                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 234769.153846                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234769.153846                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37282.960584                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37282.960584                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22884.448482                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29431.704298                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27300.861376                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22884.448482                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36501.357184                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108672.046029                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123469.078947                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123469.078947                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116308.705691                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.230757                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30080.835580                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 49003.644062                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20075.711601                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20075.711601                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15124.639893                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.639893                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 453833.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 453833.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34517.028580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34517.028580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22935.290478                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26313.248259                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26313.248259                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45935.198256                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45935.198256                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26318.278100                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32469.858077                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147789.738765                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147552.384891                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150234.510785                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150234.510785                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 148937.733024                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148809.361266                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      13189135                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10749038                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38779                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         7600                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3504874                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1040151                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           17                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1162830                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       444302                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       468816                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       354419                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       478843                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           75                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          143                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1323230                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1164313                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11482776                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15667685                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       405853                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1309392                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         28865706                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    367444720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    587773064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1487376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4788296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         961493456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5242184                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     21082310                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.277260                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.447646                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        892292                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9878632                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        15995                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      7255897                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      9976246                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       974296                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       447021                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338151                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       459645                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           83                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1866908                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1075363                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5324617                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6289738                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       523001                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       416273                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15972735                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16223776                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       373937                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1157245                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         33727693                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    340775856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    514151471                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1371816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4217048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         860516191                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   12204948                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     33927884                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.375605                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.484279                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          15237020     72.27%     72.27% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           5845290     27.73%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          21184404     62.44%     62.44% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          12743480     37.56%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      21082310                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   12037419620                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      33927884                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   14269396468                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    200301486                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176820981                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8624197196                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7990923619                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8185098674                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7460231410                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    220844820                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    202704009                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    711986885                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    630714293                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136632                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29904                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47732                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40336                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40336                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136670                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136670                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47832                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2895,18 +2986,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122614                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122766                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231166                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231166                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353956                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47752                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354012                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2916,18 +3007,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155873                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338680                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338680                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496894                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36253000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496639                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36328000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2947,7 +3038,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2955,780 +3046,757 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607574888                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569486466                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92713000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92827000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
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+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 135205.087747                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 134998.207083                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1633733                       # number of replacements
-system.l2c.tags.tagsinuse                64442.276820                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4812382                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1694389                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.840187                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               3265660000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   17567.436669                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   345.231271                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   471.940947                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4509.499901                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    13049.127195                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17952.495565                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    52.864907                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    70.453845                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2659.379343                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4127.659130                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3636.188048                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.268058                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.005268                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.007201                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.068810                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.199114                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.273933                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000807                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001075                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040579                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.062983                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.055484                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983311                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10750                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          247                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49659                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1276                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          687                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8787                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          238                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2518                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4806                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41987                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.164032                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003769                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.757736                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 65067124                       # Number of tag accesses
-system.l2c.tags.data_accesses                65067124                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         6771                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4585                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             583685                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             633203                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       298139                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6546                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         4209                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             589652                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             570600                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       281047                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2978437                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2596817                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2596817                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       138250                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       130696                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       268946                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           34228                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           26005                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               60233                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6128                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          6125                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12253                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            55044                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            49984                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               105028                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6771                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4585                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              583685                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              688247                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       298139                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6546                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4209                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              589652                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              620584                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       281047                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3083465                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6771                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4585                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             583685                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             688247                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       298139                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6546                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4209                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             589652                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             620584                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       281047                       # number of overall hits
-system.l2c.overall_hits::total                3083465                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2623                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2323                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            65378                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           160715                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       295001                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2679                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2566                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            48562                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           132475                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       268900                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               981222                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       444602                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       139009                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       583611                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         48239                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         46690                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             94929                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9164                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         9498                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18662                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          83588                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          58117                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             141705                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2623                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2323                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             65378                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            244303                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       295001                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2679                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2566                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             48562                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            190592                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       268900                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1122927                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2623                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2323                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            65378                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           244303                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       295001                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2679                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2566                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            48562                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           190592                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       268900                       # number of overall misses
-system.l2c.overall_misses::total              1122927                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    244393039                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    217850761                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   5706510559                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  16014013375                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  43733676321                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    249111297                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    239093772                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   4255255686                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  13145453309                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  39841128623                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total   123646486742                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     51997674                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     39165941                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total     91163615                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    308199351                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    263365265                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    571564616                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     47104504                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     54418277                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    101522781                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7762052110                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5404141951                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  13166194061                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    244393039                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    217850761                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   5706510559                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  23776065485                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  43733676321                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    249111297                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    239093772                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4255255686                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  18549595260                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  39841128623                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    136812680803                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    244393039                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    217850761                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   5706510559                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  23776065485                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  43733676321                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    249111297                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    239093772                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4255255686                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  18549595260                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  39841128623                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   136812680803                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         9394                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6908                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         649063                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         793918                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.dtb.walker         9225                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6775                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         638214                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         703075                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       549947                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            3959659                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2596817                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2596817                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       582852                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       269705                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       852557                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        82467                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        72695                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          155162                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15292                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        15623                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30915                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       138632                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       108101                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.itb.walker         6908                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          649063                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          932550                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       593140                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9225                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6775                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          638214                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          811176                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       549947                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4206392                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9394                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6908                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         649063                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         932550                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       593140                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9225                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6775                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         638214                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         811176                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       549947                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4206392                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.279221                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.336277                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.100727                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.202433                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.497355                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.290407                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.378745                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.076090                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.188422                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.488956                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.247805                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.762804                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.515411                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.684542                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.584949                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.642273                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.611806                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.599268                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.607950                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.603655                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.602949                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.537618                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.574325                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.279221                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.336277                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.100727                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.261973                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.497355                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.290407                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.378745                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.076090                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.234958                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.488956                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.266957                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.279221                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.336277                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.100727                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.261973                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.497355                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.290407                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.378745                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.076090                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.234958                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.488956                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.266957                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93173.099123                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93779.922944                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87284.875019                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 99642.307034                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 92986.673012                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 93177.619641                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87625.214901                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 99229.690953                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 126012.754241                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   116.953307                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   281.751117                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   156.206129                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6389.007877                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5640.721032                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6020.969525                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5140.168485                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5729.445883                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5440.080431                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92860.842585                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 92987.283428                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 92912.699347                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93173.099123                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93779.922944                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 87284.875019                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 97322.036508                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92986.673012                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93177.619641                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 87625.214901                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 97326.200785                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 121835.774545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93173.099123                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93779.922944                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 87284.875019                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 97322.036508                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92986.673012                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 93177.619641                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 87625.214901                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 97326.200785                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 121835.774545                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             14255                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1677022                       # number of replacements
+system.l2c.tags.tagsinuse                63960.007157                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5998379                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1737036                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.453227                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   15741.839802                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   357.273948                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   484.122298                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4874.372847                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    16502.292162                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20727.343192                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.818696                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     7.376448                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2388.813179                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1821.049873                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1043.704711                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.240201                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.005452                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.007387                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.074377                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.251805                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.316274                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000180                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000113                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.036450                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.027787                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.015926                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.975952                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10260                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          258                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49496                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          879                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          504                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8874                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          254                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2439                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4866                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        41821                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.156555                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003937                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.755249                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 75068652                       # Number of tag accesses
+system.l2c.tags.data_accesses                75068652                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2604285                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2604285                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           28546                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           29320                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               57866                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6394                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          5412                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11806                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           161030                       # number of ReadExReq hits
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+system.l2c.ReadExReq_hits::total               318843                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6923                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4910                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       644950                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       656166                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       305817                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5910                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4051                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       543185                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       555453                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       279182                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3006547                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6923                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4910                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              644950                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              817196                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       305817                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5910                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.inst              543185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              713266                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       279182                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3325390                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         6923                       # number of overall hits
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+system.l2c.overall_hits::cpu0.data             817196                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       305817                       # number of overall hits
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+system.l2c.overall_hits::cpu1.inst             543185                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             713266                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       279182                       # number of overall hits
+system.l2c.overall_hits::total                3325390                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         46522                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         43915                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             90437                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        10622                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         7888                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           18510                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         567822                       # number of ReadExReq misses
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+system.l2c.ReadExReq_misses::total             685630                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3723                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3679                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        69821                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total         997002                       # number of ReadSharedReq misses
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+system.l2c.overall_misses::total              1682632                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    264342500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    275145500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    539488000                       # number of UpgradeReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.data  19146364498                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    166591000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    119960500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3610747500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  10634037494                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 119169156024                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    347505000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    338090000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   6068374002                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  92839998498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    166591000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    119960500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3610747500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  22660430993                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    204889183523                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    347505000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    338090000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   6068374002                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  92839998498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    166591000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    119960500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3610747500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  22660430993                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   204889183523                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2604285                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2604285                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        75068                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        73235                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          148303                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        17016                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        13300                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         30316                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       728852                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       275621                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1004473                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10646                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8589                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       714771                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       853704                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       672173                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7659                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5301                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       585138                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       664603                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       480965                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      4003549                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        10646                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         8589                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          714771                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1582556                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       672173                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         7659                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5301                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          585138                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          940224                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       480965                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             5008022                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        10646                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         8589                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         714771                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1582556                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       672173                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         7659                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5301                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         585138                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         940224                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       480965                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            5008022                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.619731                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.599645                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.609812                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.624236                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.593083                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.610569                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.779064                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.427428                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.682577                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.097683                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.231389                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.071698                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.164233                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.249030                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.097683                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.483623                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.071698                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.241387                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.335987                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.097683                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.483623                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.071698                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.241387                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.335987                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5682.096642                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6265.410452                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5965.346042                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5705.328563                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5749.112576                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5723.987034                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 129782.984809                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102084.692882                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 125023.740938                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86913.306913                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96924.968857                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86066.491073                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97425.904663                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 119527.499467                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 121767.078911                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 86913.306913                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 121767.078911                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              9470                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      149                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      105                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     95.671141                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     90.190476                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1263454                       # number of writebacks
-system.l2c.writebacks::total                  1263454                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst           235                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            55                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst           249                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            31                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               570                       # number of ReadReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0.data            1                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total               1                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            235                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             56                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            249                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             31                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                571                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           235                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            56                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           249                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            31                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               571                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2623                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2323                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        65143                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       160660                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       295001                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2679                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2566                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        48313                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       132444                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       268900                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          980652                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       444602                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       139009                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total       583611                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        48239                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        46690                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        94929                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9164                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         9498                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18662                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        83587                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        58117                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        141704                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2623                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2323                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        65143                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       244247                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       295001                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2679                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2566                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        48313                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       190561                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       268900                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1122356                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         2623                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         2323                       # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.279221                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::total     0.247661                       # mshr miss rate for ReadReq accesses
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-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.684542                       # mshr miss rate for WriteInvalidateReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.642273                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.611806                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.607950                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.603655                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::total     0.574321                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.279221                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.075700                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.234919                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.279221                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.336277                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100365                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.261913                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.075700                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.234919                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.266822                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74769.755661                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 87169.627673                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75142.970070                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 86751.636095                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 113670.819035                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555                       # average WriteInvalidateReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 109478.788986                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113                       # average overall mshr miss latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495                       # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175                       # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316                       # average WriteReq mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888                       # average overall mshr uncacheable latency
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+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.619731                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.599645                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.609812                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.624236                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.593083                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 129803.636666                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114515.950499                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147660.628362                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133233.197874                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141629.718090                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151711.018680                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 131414.154018                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 125104.654348                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             1049844                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1049844                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38779                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38779                       # Transaction distribution
-system.membus.trans_dist::Writeback           1370148                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       687460                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       687460                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           443336                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         306800                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          120479                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            155568                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137698                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122614                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               59716                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1065238                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38264                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38264                       # Transaction distribution
+system.membus.trans_dist::Writeback           1398687                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           273545                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           431435                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         293289                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          115559                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            699678                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           679021                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1005522                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122766                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27506                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5597252                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5747450                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335773                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335773                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6083223                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155744                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25252                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5818316                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5966412                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342390                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342390                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6308802                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155873                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    189917440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    190128768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14086528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14086528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               204215296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           650589                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4133180                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    190243904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    190450853                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7261952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7261952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               197712805                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           632700                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4309210                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4133180    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4309210    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4133180                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98178497                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4309210                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98315494                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            22861986                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21255984                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         12090027529                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9692600374                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6852398799                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         9139212712                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          152088673                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229129958                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3772,49 +3840,50 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            4896771                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4889534                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38779                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38779                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2596817                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       959438                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       852557                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          496684                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        319053                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         815737                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          143                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          143                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           305200                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          305200                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8223954                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6618870                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              14842824                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    276507544                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    214143912                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              490651456                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1673717                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9649223                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012003                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.108901                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              59718                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4906213                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38264                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38264                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          4003012                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1629651                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          482692                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        305095                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         787787                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          148                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1150777                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1150777                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4853770                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9404841                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6602998                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16007839                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    297836822                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    190023375                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              487860197                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3506825                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         13882904                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.137454                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.344326                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9533399     98.80%     98.80% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115824      1.20%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               11974647     86.25%     86.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1908257     13.75%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9649223                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8593373447                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           13882904                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8939333587                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2556000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2427000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4622045284                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5448458649                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4138277748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4022349362                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13964                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    4812                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5482                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   13871                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index df0d44cf6..ef8414f55 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.320469                       # Number of seconds simulated
-sim_ticks                                51320468905000                       # Number of ticks simulated
-final_tick                               51320468905000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.323721                       # Number of seconds simulated
+sim_ticks                                51323721423000                       # Number of ticks simulated
+final_tick                               51323721423000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115752                       # Simulator instruction rate (inst/s)
-host_op_rate                                   136007                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6943747154                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 724128                       # Number of bytes of host memory used
-host_seconds                                  7390.89                       # Real time elapsed on the host
-sim_insts                                   855512158                       # Number of instructions simulated
-sim_ops                                    1005211605                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 113854                       # Simulator instruction rate (inst/s)
+host_op_rate                                   133781                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6847821533                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 727476                       # Number of bytes of host memory used
+host_seconds                                  7494.90                       # Real time elapsed on the host
+sim_insts                                   853325819                       # Number of instructions simulated
+sim_ops                                    1002674190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       202624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       193280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5755680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          42629000                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        415488                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49196072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5755680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5755680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69369152                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       203200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       189632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5727200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          73778504                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        419776                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             80318312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5727200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5727200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68723904                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69389732                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3020                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105885                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             666091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6492                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                784654                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1083893                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68744484                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3175                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         2963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105440                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1152802                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1270939                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1073811                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1086466                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3948                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               112152                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               830643                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  958605                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          112152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1351686                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1076384                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           3959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           3695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1437513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8179                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1564935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111590                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111590                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1339028                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1352087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1351686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3948                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              112152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              831044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8096                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2310692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        784654                       # Number of read requests accepted
-system.physmem.writeReqs                      1688539                       # Number of write requests accepted
-system.physmem.readBursts                      784654                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1688539                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 50184064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     33792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104909952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  49196072                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              107922404                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      528                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   49293                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          35218                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               46664                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51485                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               48018                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               46409                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               44064                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               51949                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               45895                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               48923                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               45299                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               70789                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              48156                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              46739                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              48771                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              48997                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              45133                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              46835                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               99610                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              104326                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              103481                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              102430                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              101747                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104971                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              100056                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              103888                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               99840                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              106110                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102643                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             100858                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103355                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             103593                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             100350                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             101960                       # Per bank write bursts
+system.physmem.bw_write::total                1339429                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1339028                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          3959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          3695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1437914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8179                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2904365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1270939                       # Number of read requests accepted
+system.physmem.writeReqs                      1076384                       # Number of write requests accepted
+system.physmem.readBursts                     1270939                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1076384                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 81299584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     40512                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68742976                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  80318312                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68744484                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      633                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         142017                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               76590                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               80112                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               82312                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               76894                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               75148                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               84486                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               75307                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               76047                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               76921                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104197                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              75653                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              81028                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              74845                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              77383                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              76622                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              76761                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64108                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67910                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               69982                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               67432                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               65959                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70786                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64733                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               66187                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67287                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               71812                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65064                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              69201                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65082                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              66370                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66024                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              66172                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         560                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51320467654000                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51323720227500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  763369                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1249654                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1685966                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    521104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    214865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29991                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12339                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       553                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       459                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1073811                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    646219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    339232                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    151287                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    128129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       684                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       502                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       533                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       812                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       936                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,160 +159,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    62903                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    63057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    90168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    80361                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    95410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    92759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   101527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    92557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    84728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   110064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    83833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    78687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    89131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    74275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    70833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    66282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     8883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     7376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     8392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     9232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     9334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     8685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     9103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     9266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     8544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     8245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     7856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     7810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     5765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     6644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     5091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     4890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     3916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     3295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     3011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     2474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     3139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     2181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     2765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                     1862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                     4424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                     1539                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       512637                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.540847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     171.812512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.509823                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207576     40.49%     40.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       124268     24.24%     64.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44401      8.66%     73.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23774      4.64%     78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        16232      3.17%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10193      1.99%     83.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8192      1.60%     84.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7548      1.47%     86.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        70453     13.74%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         512637                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         56080                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        13.981651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       75.084718                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           56073     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            5      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           56080                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         56080                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        29.229993                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       22.064414                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       40.823681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-31            46001     82.03%     82.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-63            3837      6.84%     88.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95            4190      7.47%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127            975      1.74%     98.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159           304      0.54%     98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191           127      0.23%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223            99      0.18%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255            80      0.14%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287           114      0.20%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-319           122      0.22%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-351            75      0.13%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383            40      0.07%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415            26      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-447            17      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479            12      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511             8      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543            13      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-575            10      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-607             5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-639             3      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-671             4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-703             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-735             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-767             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-799             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-927             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::992-1023            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1056-1087            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1184-1215            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           56080                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15388206863                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30090569363                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3920630000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19624.66                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    11927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    14439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    31518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    44897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    53343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    63481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    63532                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    67021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    67803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    70464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    69167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    70329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    66867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    85010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    86471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    65847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    69713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    62929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       481355                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.708207                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.914901                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     339.146013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         186832     38.81%     38.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       113175     23.51%     62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        45398      9.43%     71.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23450      4.87%     76.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18101      3.76%     80.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11671      2.42%     82.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10460      2.17%     84.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8315      1.73%     86.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        63953     13.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         481355                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61522                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.647411                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      265.936082                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          61519    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           61522                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61522                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.458942                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.948779                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.823778                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           58490     95.07%     95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             664      1.08%     96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             448      0.73%     96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             190      0.31%     97.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             308      0.50%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             527      0.86%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             143      0.23%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              33      0.05%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              36      0.06%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              18      0.03%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              32      0.05%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              22      0.04%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             426      0.69%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              45      0.07%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              33      0.05%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              35      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              13      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            31      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61522                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31530968444                       # Total ticks spent queuing
+system.physmem.totMemAccLat               55349205944                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6351530000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       24821.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38374.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.96                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43571.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.56                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     598254                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1312451                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.06                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20750692.59                       # Average gap between requests
-system.physmem.pageHitRate                      78.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1947569400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1062661875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2990566800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5316898320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352003380960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1226375853165                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29716511616000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34306208546520                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.470318                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49436040472112                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713703160000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.31                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1047361                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    815697                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21864788.20                       # Average gap between requests
+system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1828287720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  997577625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4889757600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3480388560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1226219398425                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29718601656750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34308233025720                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.467372                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49439480717043                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713811840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    170725136888                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    170428636707                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1927966320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1051965750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3125569200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5305234320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352003380960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1229368112910                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29713886826750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34306669056210                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.479291                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49431639282027                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713703160000                       # Time in different power states
+system.physmem_1.actEnergy                 1810756080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  988011750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5018598000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3479837760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1228704019020                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29716422156750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34308639338400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.475289                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49435820968594                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713811840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    175126075973                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    174088371406                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -336,15 +340,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               226088242                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         151212051                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12236747                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159576730                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104394184                       # Number of BTB hits
+system.cpu.branchPred.lookups               225557622                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         150824960                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12221670                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159273353                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104130221                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.419428                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31024336                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             344701                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.378307                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30957399                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             344598                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -375,86 +379,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    945525                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                945525                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        17037                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156802                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       426099                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       519426                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  1842.763936                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-32767       513062     98.77%     98.77% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-65535         3320      0.64%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-98303         1249      0.24%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::98304-131071         1137      0.22%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-163839          115      0.02%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::163840-196607          205      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-229375           84      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::229376-262143           60      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-294911           94      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::294912-327679            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-360447           21      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::360448-393215           44      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-425983           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       519426                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       477950                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       472923     98.95%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         4117      0.86%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          574      0.12%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          200      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           75      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    951838                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                951838                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16475                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156308                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435006                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       516832                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  1986.510123                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-32767       508349     98.36%     98.36% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-65535         5443      1.05%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-98303         1244      0.24%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::98304-131071         1085      0.21%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-163839          165      0.03%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::163840-196607          178      0.03%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-229375          121      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::229376-262143           54      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-294911           95      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::294912-327679            7      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-360447            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::360448-393215           38      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-425983           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::425984-458751            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       516832                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       485267                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       475094     97.90%     97.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         9290      1.91%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          546      0.11%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          199      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           82      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           20      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       477950                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 768700308080                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.730043                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.512304                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  766743156580     99.75%     99.75% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1060609500      0.14%     99.88% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     401667500      0.05%     99.94% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     174666000      0.02%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     138312000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    106588500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     24500000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     48487000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2321000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 768700308080                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        156803     90.20%     90.20% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         17037      9.80%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       173840                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       945525                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total       485267                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 776250627376                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.722476                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.519579                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  774163165376     99.73%     99.73% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1120728500      0.14%     99.88% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     435636500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     187638500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     148036000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    113935000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     26323500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     52542500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2621500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 776250627376                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        156309     90.46%     90.46% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16475      9.54%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       172784                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       951838                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       945525                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       173840                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       951838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       172784                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       173840                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1119365                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       172784                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1124622                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    170900022                       # DTB read hits
-system.cpu.dtb.read_misses                     675244                       # DTB read misses
-system.cpu.dtb.write_hits                   148749524                       # DTB write hits
-system.cpu.dtb.write_misses                    270281                       # DTB write misses
+system.cpu.dtb.read_hits                    170417440                       # DTB read hits
+system.cpu.dtb.read_misses                     677013                       # DTB read misses
+system.cpu.dtb.write_hits                   148384109                       # DTB write hits
+system.cpu.dtb.write_misses                    274825                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               39859                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1027                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72825                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       117                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10420                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               39714                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1025                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72556                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10696                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69816                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171575266                       # DTB read accesses
-system.cpu.dtb.write_accesses               149019805                       # DTB write accesses
+system.cpu.dtb.perms_faults                     70061                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171094453                       # DTB read accesses
+system.cpu.dtb.write_accesses               148658934                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         319649546                       # DTB hits
-system.cpu.dtb.misses                          945525                       # DTB misses
-system.cpu.dtb.accesses                     320595071                       # DTB accesses
+system.cpu.dtb.hits                         318801549                       # DTB hits
+system.cpu.dtb.misses                          951838                       # DTB misses
+system.cpu.dtb.accesses                     319753387                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -484,209 +489,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161869                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161869                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walks                    162167                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                162167                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       122204                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17648                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144221                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1045.076653                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  6935.040907                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143697     99.64%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          129      0.09%     99.73% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303          259      0.18%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           98      0.07%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839           18      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144221                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       141285                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 26183.154631                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       139260     98.57%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         1739      1.23%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          189      0.13%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           61      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           22      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       122178                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17760                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144407                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1087.128740                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  7079.961036                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       143546     99.40%     99.40% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          491      0.34%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          245      0.17%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           86      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           14      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144407                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       141371                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 27408.566821                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       138940     98.28%     98.28% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         2106      1.49%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          209      0.15%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           62      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           27      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       141285                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 652736132088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.935835                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.245289                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     41920855152      6.42%      6.42% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    610778213436     93.57%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        36269000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          794000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4             500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 652736132088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        122204     98.84%     98.84% # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total       141371                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 655988501088                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.936740                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.243710                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     41542191152      6.33%      6.33% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    614402729936     93.66%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        43110500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          467500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 655988501088                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        122178     98.84%     98.84% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123637                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       123611                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161869                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162167                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       162167                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123637                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123637                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       285506                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    359459512                       # ITB inst hits
-system.cpu.itb.inst_misses                     161869                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123611                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       123611                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       285778                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    358625455                       # ITB inst hits
+system.cpu.itb.inst_misses                     162167                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               39859                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1027                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53398                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               39714                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1025                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53363                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372095                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372145                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                359621381                       # ITB inst accesses
-system.cpu.itb.hits                         359459512                       # DTB hits
-system.cpu.itb.misses                          161869                       # DTB misses
-system.cpu.itb.accesses                     359621381                       # DTB accesses
-system.cpu.numCycles                       1580751099                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                358787622                       # ITB inst accesses
+system.cpu.itb.hits                         358625455                       # DTB hits
+system.cpu.itb.misses                          162167                       # DTB misses
+system.cpu.itb.accesses                     358787622                       # DTB accesses
+system.cpu.numCycles                       1590418745                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          647898483                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1008720689                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   226088242                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135418520                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     855549558                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26139542                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3573192                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                26865                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9268939                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1033386                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          427                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 359070671                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6123790                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48662                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1530420621                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.772272                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.159981                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          646410999                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1006402404                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225557622                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135087620                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     866562323                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26107474                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3678311                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                25439                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9275413                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1023850                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          676                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 358236204                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6112300                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   49056                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1540030748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.765724                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.157325                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                968902908     63.31%     63.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215807485     14.10%     77.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71036994      4.64%     82.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                274673234     17.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                979927440     63.63%     63.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215057699     13.96%     77.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70955696      4.61%     82.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                274089913     17.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1530420621                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.143026                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.638127                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526178421                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             508648126                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 435713994                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50619608                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9260472                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33861678                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3868815                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1093600087                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29077129                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9260472                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571338545                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                48532565                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      364379914                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 441167933                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              95741192                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1073752213                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6802962                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5086497                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 358848                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 628248                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               43820548                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20190                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1021575372                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1655508848                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1270030956                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1469892                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             955737015                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65838354                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27320538                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23636945                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 103635545                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            174900719                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           152333814                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9971771                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9081144                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1038303468                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27624460                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1054196021                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3299994                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60716319                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33847358                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         315461                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1530420621                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.688828                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.927358                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1540030748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.141823                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.632791                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                525466953                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             519947088                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 434864784                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50506307                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9245616                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33796734                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3867997                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1090931528                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29050280                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9245616                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                570424085                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50840114                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363017689                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 440398811                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             106104433                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1071115355                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6801917                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5040663                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 343395                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 645255                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               54344412                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20434                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1018974666                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1651092433                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1266893179                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1473696                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             953236782                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65737881                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27206823                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23528426                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 103688094                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            174464093                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           151959443                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9931077                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9032567                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1035787653                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27506074                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1051526043                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3293799                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60619533                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33780075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         314140                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1540030748                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.682795                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.925415                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           877745445     57.35%     57.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           337069342     22.02%     79.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           236293073     15.44%     94.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72729594      4.75%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6564084      0.43%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19083      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           888949202     57.72%     57.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           336251490     21.83%     79.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           235798342     15.31%     94.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72468185      4.71%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6544331      0.42%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19198      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1530420621                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1540030748                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58206836     35.09%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99242      0.06%     35.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26725      0.02%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              744      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44573023     26.87%     62.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62969604     37.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58035888     35.01%     35.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  99674      0.06%     35.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26738      0.02%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              574      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44566242     26.88%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63041416     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                57      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             725956407     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2542188      0.24%     69.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                123122      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             724142674     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2543730      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122779      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 376      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -708,102 +713,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         120904      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121012      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            174804143     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150649152     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            174312709     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150282706     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1054196021                       # Type of FU issued
-system.cpu.iq.rate                           0.666896                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   165876174                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157349                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3805514237                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1125839347                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1036122901                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2474593                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             946702                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909865                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1218517790                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1554348                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4347401                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1051526043                       # Type of FU issued
+system.cpu.iq.rate                           0.661163                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   165770532                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157648                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3809671307                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1123107931                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1033541701                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2475857                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             947397                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       910004                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1215741366                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1555198                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4333965                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13878328                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14961                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       143108                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6347044                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13839303                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14833                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143349                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6338712                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2552620                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1870361                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2540349                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1552925                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9260472                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6554396                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3651492                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1066150871                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9245616                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6389360                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5797347                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1063516239                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             174900719                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            152333814                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23208148                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  59700                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3513413                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         143108                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3675827                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5121930                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8797757                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1042985483                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             170888878                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10276947                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             174464093                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            151959443                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23100216                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  59008                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               5663632                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143349                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3667729                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5111764                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8779493                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1040328227                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             170406440                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10257681                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222943                       # number of nop insts executed
-system.cpu.iew.exec_refs                    319634404                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                197926826                       # Number of branches executed
-system.cpu.iew.exec_stores                  148745526                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.659804                       # Inst execution rate
-system.cpu.iew.wb_sent                     1037843882                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1037032766                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 441278048                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 713779914                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        222512                       # number of nop insts executed
+system.cpu.iew.exec_refs                    318786335                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                197400349                       # Number of branches executed
+system.cpu.iew.exec_stores                  148379895                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.654122                       # Inst execution rate
+system.cpu.iew.wb_sent                     1035262700                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1034451705                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 440415620                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 712619707                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.656038                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618227                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.650427                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618023                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51563874                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27308999                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8427448                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1518403714                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.662019                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.290608                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51498978                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27191934                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8413549                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1528028900                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.656188                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.286676                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1001866977     65.98%     65.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    290832617     19.15%     85.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121646355      8.01%     93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36740427      2.42%     95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28447666      1.87%     97.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14105700      0.93%     98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8667985      0.57%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4229973      0.28%     99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11866014      0.78%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1013092181     66.30%     66.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    289858237     18.97%     85.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121052617      7.92%     93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36682667      2.40%     95.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28563883      1.87%     97.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14105791      0.92%     98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8655946      0.57%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4198069      0.27%     99.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11819509      0.77%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1518403714                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            855512158                       # Number of instructions committed
-system.cpu.commit.committedOps             1005211605                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1528028900                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            853325819                       # Number of instructions committed
+system.cpu.commit.committedOps             1002674190                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      307009160                       # Number of memory references committed
-system.cpu.commit.loads                     161022390                       # Number of loads committed
-system.cpu.commit.membars                     6998413                       # Number of memory barriers committed
-system.cpu.commit.branches                  190975004                       # Number of branches committed
-system.cpu.commit.fp_insts                     896164                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 923410198                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25456304                       # Number of function calls committed.
+system.cpu.commit.refs                      306245520                       # Number of memory references committed
+system.cpu.commit.loads                     160624789                       # Number of loads committed
+system.cpu.commit.membars                     6977905                       # Number of memory barriers committed
+system.cpu.commit.branches                  190474151                       # Number of branches committed
+system.cpu.commit.fp_insts                     896785                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 921116747                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25400785                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        695830631     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2161783      0.22%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98401      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        694059947     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2158876      0.22%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98131      0.01%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
@@ -826,522 +831,535 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% #
 system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111588      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111674      0.01%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       161022390     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      145986770     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       160624789     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      145620731     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1005211605                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11866014                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2555711925                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2125474325                       # The number of ROB writes
-system.cpu.timesIdled                         8142220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        50330478                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101060186847                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   855512158                       # Number of Instructions Simulated
-system.cpu.committedOps                    1005211605                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.847725                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.847725                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.541206                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.541206                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1234726115                       # number of integer regfile reads
-system.cpu.int_regfile_writes               737118708                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1461359                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   784484                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 227546613                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                228200703                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2526906641                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27367002                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9794555                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.983548                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           285502634                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9795067                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.147594                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1659133250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.983548                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total        1002674190                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11819509                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2562796067                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2120254358                       # The number of ROB writes
+system.cpu.timesIdled                         8129447                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        50387997                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101057024238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   853325819                       # Number of Instructions Simulated
+system.cpu.committedOps                    1002674190                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.863788                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.863788                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.536542                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.536542                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1231590969                       # number of integer regfile reads
+system.cpu.int_regfile_writes               735370525                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462122                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782688                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 226859046                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                227515194                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2534481060                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27245755                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9758519                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983709                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           284707567                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9759031                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.173754                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1642601500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983709                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          409                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1246939843                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1246939843                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    148420477                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       148420477                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    129257116                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      129257116                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       380071                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        380071                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       323830                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       323830                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3338713                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3338713                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3738459                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3738459                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     277677593                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        277677593                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    278057664                       # number of overall hits
-system.cpu.dcache.overall_hits::total       278057664                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9529450                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9529450                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11422113                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11422113                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1191409                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1191409                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233320                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1233320                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       451226                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       451226                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20951563                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20951563                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22142972                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22142972                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 145395860730                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 336812014094                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  35299806246                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  35299806246                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6459718484                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6459718484                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       237001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       237001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 482207874824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 482207874824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 482207874824                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 482207874824                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    157949927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    157949927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140679229                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140679229                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1571480                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1571480                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557150                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1557150                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3789939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3789939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3738465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3738465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    298629156                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    298629156                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    300200636                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    300200636                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060332                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060332                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081193                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081193                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758145                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.758145                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.792037                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.792037                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119059                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119059                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1243872376                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1243872376                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147964440                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147964440                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128940955                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128940955                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       380183                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        380183                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       324678                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       324678                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3327415                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3327415                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3725844                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3725844                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     276905395                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        276905395                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    277285578                       # number of overall hits
+system.cpu.dcache.overall_hits::total       277285578                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9612542                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9612542                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11385353                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11385353                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1184834                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1184834                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1232047                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1232047                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20997895                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20997895                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22182729                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22182729                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 144669003500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 330867751444                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  63675897168                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  63675897168                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       251000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       251000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 475536754944                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 475536754944                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 475536754944                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 475536754944                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    157576982                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    157576982                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    140326308                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    140326308                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1565017                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1565017                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1556725                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1556725                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3777448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3777448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3725851                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3725851                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    297903290                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    297903290                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    299468307                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    299468307                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061002                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061002                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081135                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.757074                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.757074                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791435                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791435                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119137                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119137                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070159                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070159                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073761                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073761                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23015.365241                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21777.016871                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20545206                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070486                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070486                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074074                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074074                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22646.877458                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21437.252150                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     35158879                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1559097                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1606955                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.177632                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.879193                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7577660                       # number of writebacks
-system.cpu.dcache.writebacks::total           7577660                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4366240                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4366240                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9388231                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9388231                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7155                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7155                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       220115                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       220115                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13754471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13754471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13754471                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13754471                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5163210                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5163210                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2033882                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2033882                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1184642                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1184642                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1226165                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1226165                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       231111                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       231111                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7197092                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7197092                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8381734                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8381734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67343                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67343                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  73626554579                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  73626554579                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  56871439750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  56871439750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  19552019274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  19552019274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  33205804688                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  33205804688                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2956928250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2956928250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       227999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       227999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 130497994329                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 150050013603                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5746385500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5746385500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5629281968                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5629281968                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11375667468                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11375667468                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032689                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032689                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753838                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753838                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787442                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787442                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060980                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060980                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks      7549082                       # number of writebacks
+system.cpu.dcache.writebacks::total           7549082                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4467834                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4467834                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9360902                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9360902                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7079                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7079                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219205                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219205                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13828736                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13828736                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13828736                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13828736                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5144708                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5144708                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2024451                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2024451                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1178103                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1178103                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224968                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1224968                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7169159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7169159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8347262                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8347262                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75818409500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75818409500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  57062160713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  57062160713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20148080000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20148080000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  62191648168                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  62191648168                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       244000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       244000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 132880570213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 153028650213                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5828327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5828327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5707957967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5707957967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11536285467                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11536285467                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032649                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032649                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014427                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014427                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752773                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752773                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786888                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786888                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061107                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061107                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024100                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024100                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027920                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027920                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024065                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024065                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027874                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027874                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15070815                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.953323                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           343233622                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15071327                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.773948                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       14049577000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.953323                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements          15042093                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.944879                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           342405629                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15042605                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.762389                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       17214303500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.944879                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999892                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         374120916                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        374120916                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    343233622                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       343233622                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     343233622                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        343233622                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    343233622                       # number of overall hits
-system.cpu.icache.overall_hits::total       343233622                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15815747                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15815747                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15815747                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15815747                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15815747                       # number of overall misses
-system.cpu.icache.overall_misses::total      15815747                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208885866517                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208885866517                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208885866517                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208885866517                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208885866517                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    359049369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    359049369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    359049369                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    359049369                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    359049369                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    359049369                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044049                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044049                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044049                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044049                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044049                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13207.461305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13207.461305                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        13684                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         373257734                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        373257734                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    342405629                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       342405629                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     342405629                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        342405629                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total       342405629                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15809279                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15809279                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15809279                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15809279                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15809279                       # number of overall misses
+system.cpu.icache.overall_misses::total      15809279                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208403044384                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208403044384                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208403044384                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208403044384                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208403044384                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    358214908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    358214908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    358214908                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    358214908                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    358214908                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    358214908                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044134                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044134                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.044134                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.044134                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.044134                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.044134                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13182.324405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13182.324405                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        15030                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1126                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1210                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.152753                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    12.421488                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       744199                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       744199                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       744199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       744199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       744199                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       744199                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15071548                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15071548                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15071548                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15071548                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15071548                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15071548                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766453                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       766453                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       766453                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       766453                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       766453                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       766453                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15042826                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::total     15042826                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 179787086612                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 179787086612                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1585009250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1585009250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1585009250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   1585009250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041976                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041976                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041976                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041976                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 186915451392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 186915451392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1594412000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   1594412000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.041994                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.041994                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1159288                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65272.997993                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29043191                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1221496                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.776739                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       2756226000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   319.528316                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   474.614102                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7535.726920                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.568752                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004876                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007242                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114986                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300131                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          304                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61904                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          304                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          579                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2674                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5116                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53473                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004639                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.944580                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        272839925                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       272839925                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       805883                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       304376                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     14986718                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6321707                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       22418684                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7577660                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7577660                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       730602                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       730602                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9499                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9499                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1579833                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1579833                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       805883                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       304376                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14986718                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7901540                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23998517                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       805883                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       304376                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14986718                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7901540                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23998517                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3166                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3020                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        84629                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       253686                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       344501                       # number of ReadReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       495562                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       495562                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34430                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34430                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.replacements          1148683                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65278.817014                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46198537                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1210914                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.151790                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      15659706000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   301.460755                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   460.210435                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7626.713626                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572                       # Average occupied blocks per requestor
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
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+system.cpu.l2cache.overall_accesses::total     24671586                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.009787                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.005606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785148                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785148                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.205602                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.205602                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005596                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005596                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038739                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038739                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402131                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402131                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009787                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005596                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.077531                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030480                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009787                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005596                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.077531                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030480                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1350,182 +1368,196 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       977263                       # number of writebacks
-system.cpu.l2cache.writebacks::total           977263                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks       967181                       # number of writebacks
+system.cpu.l2cache.writebacks::total           967181                       # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3166                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3020                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        84629                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       253665                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       344480                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       495562                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       495562                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34430                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34430                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3175                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2963                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         6138                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1073                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1073                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34552                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        34552                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       413693                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       413693                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3166                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3020                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        84629                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       667358                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       758173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3166                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3020                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        84629                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       667358                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       758173                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       407912                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       407912                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        84184                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        84184                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       253725                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       253725                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       492598                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       492598                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3175                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2963                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        84184                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       661637                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3175                       # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst        84184                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       661637                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       751959                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33661                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54956                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33682                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33682                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67343                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88638                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    225518000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   6085544162                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  19591961036                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  26140194449                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  16855177398                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  16855177398                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    611252927                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    611252927                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       153001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       153001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31729551871                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31729551871                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    225518000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   6085544162                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51321512907                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  57869746320                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    237171251                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    225518000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   6085544162                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51321512907                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  57869746320                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1276231250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5274563500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6550794750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5186666500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5186666500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1276231250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10461230000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11737461250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.038578                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015133                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.404156                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.404156                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783765                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783765                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.207518                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.207518                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077881                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030625                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.003913                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009824                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005615                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077881                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030625                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88669                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    235749500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    480955500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    717374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    717374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       161500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       161500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31953716500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31953716500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   6240732500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   6240732500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19997854000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19997854000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  46277939000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  46277939000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    235749500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   6240732500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51951570500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  58673258500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    235749500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   6240732500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51951570500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  58673258500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407344500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6735569000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5315951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5315951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10723295500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12051520000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.205602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005596                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038736                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038736                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402131                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402131                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030479                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030479                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23293786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23285542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7577660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332936                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1226164                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43938                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1993526                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1993526                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30185484                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27390990                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       736951                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1962535                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          60275960                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    964906864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1112084525                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2459168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6472392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2085922949                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      583028                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     34275542                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.049559                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.217032                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        1633565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23227278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8622904                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     17438576                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        44010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        44017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1983984                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1983984                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15042826                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6558947                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1331632                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1224968                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45167572                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29499463                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       732865                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1940611                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77340511                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    963068272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1029563294                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2422088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6336984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2001390638                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1864369                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     52693428                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.056141                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.230194                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           32576878     95.04%     95.04% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1698664      4.96%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           49735173     94.39%     94.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            2958255      5.61%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       34275542                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    25901169608                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       52693428                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    33222815494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       909000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1182000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22654600125                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22592032956                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13659008538                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13487423434                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     430754363                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     430634727                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1154477924                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1148958035                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40283                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40283                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136558                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29894                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1536,17 +1568,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29496                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122652                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230950                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230950                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353682                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1557,17 +1589,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17529                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155805                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492123                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1588,7 +1620,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21908000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -1596,211 +1628,213 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607064814                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568813596                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92761000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148363066                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115456                       # number of replacements
-system.iocache.tags.tagsinuse               10.424607                       # Cycle average of tags in use
+system.iocache.tags.replacements               115455                       # number of replacements
+system.iocache.tags.tagsinuse               10.423947                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115472                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13092103918000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544640                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879967                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221540                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429998                       # Average percentage of cache occupancy
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+system.iocache.tags.warmup_cycle         13095311635000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544418                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879529                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221526                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429971                       # Average percentage of cache occupancy
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039632                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039632                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039623                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8811                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8848                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
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 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8811                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8851                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8811                       # number of overall misses
-system.iocache.overall_misses::total             8851                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1609809480                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1614881480                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19830913268                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19830913268                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1609809480                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1615233980                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1609809480                       # number of overall miss cycles
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+system.iocache.WriteLineReq_miss_latency::realview.ide  12610487430                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12610487430                       # number of WriteLineReq miss cycles
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+system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1621911166                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1627331166                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8811                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
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-system.iocache.demand_accesses::total            8851                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8811                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8851                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
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 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182513.729656                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 182704.514811                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182491.693594                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 182704.514811                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182491.693594                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        110252                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183901.906409                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31681                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16154                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3345                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.825059                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.471151                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8811                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8848                       # number of ReadReq MSHR misses
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+system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
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 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
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-system.iocache.overall_mshr_misses::total         8851                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1150531536                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1153673536                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14284309344                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14284309344                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1150531536                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1153867036                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1150531536                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1153867036                       # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1181411166                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1184630166                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1181411166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1184831166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1181411166                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1184831166                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 130365.725455                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 130365.725455                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              408284                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408284                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33682                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33682                       # Transaction distribution
-system.membus.trans_dist::Writeback           1083893                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       602073                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       602073                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35223                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
+system.membus.trans_dist::ReadResp             407867                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
+system.membus.trans_dist::Writeback           1073811                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           187846                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35358                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35226                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            413056                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           413056                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122652                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp           35361                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            899707                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           899707                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        352894                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3600651                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3730211                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4065512                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155805                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3753956                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3883578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4225292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    143052172                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    143222109                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14066304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14066304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               157288413                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3023                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2576774                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    141818700                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    141988686                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7244096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7244096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               149232782                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2955                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2747442                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2576774    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2747442    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2576774                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104078000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2747442                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           104159500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5439500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5443500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9540063820                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7279924206                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4726359104                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6776038462                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151502434                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228860056                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1845,6 +1879,6 @@ system.realview.ethernet.coalescedTotal             0                       # av
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16160                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16150                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index 347570290..b60b333d0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1198732                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1408707                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            62228718243                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 717580                       # Number of bytes of host memory used
-host_seconds                                   821.34                       # Real time elapsed on the host
+host_inst_rate                                1400836                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1646212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            72720385640                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 722712                       # Number of bytes of host memory used
+host_seconds                                   702.85                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       376512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5562740                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          74833672                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81627068                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103042944                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.itb.walker       376704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5543028                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         110110088                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            116884284                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5543028                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103060480                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103063524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103081060                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             127325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1169289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315843                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610046                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5886                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             127017                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1720483                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1866737                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610320                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612619                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1612893                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           7367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1464136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8644                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1597050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016056                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           7370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108450                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2154326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286865                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016399                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016459                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016056                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2016802                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016399                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          7367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1464539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3613509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          7370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108450                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2154729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303666                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -294,8 +294,8 @@ system.cpu.dcache.WriteReq_hits::cpu.data    159522870                       # n
 system.cpu.dcache.WriteReq_hits::total      159522870                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data       424020                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total        424020                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       337709                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       337709                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       337709                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       337709                       # number of WriteLineReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      4310545                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      4310545                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      4562464                       # number of StoreCondReq hits
@@ -310,8 +310,8 @@ system.cpu.dcache.WriteReq_misses::cpu.data      2570257                       #
 system.cpu.dcache.WriteReq_misses::total      2570257                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data      1584397                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total      1584397                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1245349                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1245349                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1245349                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1245349                       # number of WriteLineReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data       253721                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total       253721                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
@@ -326,8 +326,8 @@ system.cpu.dcache.WriteReq_accesses::cpu.data    162093127
 system.cpu.dcache.WriteReq_accesses::total    162093127                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data      2008417                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total      2008417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1583058                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1583058                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4564266                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      4564266                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      4562465                       # number of StoreCondReq accesses(hits+misses)
@@ -342,8 +342,8 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015857
 system.cpu.dcache.WriteReq_miss_rate::total     0.015857                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788879                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.788879                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786673                       # miss rate for WriteLineReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055589                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055589                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
@@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8921315                       # number of writebacks
-system.cpu.dcache.writebacks::total           8921315                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      8921279                       # number of writebacks
+system.cpu.dcache.writebacks::total           8921279                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14295641                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
@@ -412,96 +412,102 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1722692                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65341.862502                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29983424                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1785989                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            16.788135                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1722572                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.862554                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46968482                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1785868                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.300086                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.196824                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.735041                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6261.263092                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.566738                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.195568                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.733962                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6290.976194                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.566080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.323257                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095993                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.323461                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63019                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63018                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4          278                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2715                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4911                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2714                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4910                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54670                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961594                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        290307620                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       290307620                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961578                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        426199223                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       426199223                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255623                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     14211921                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      7504232                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       22478388                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8921315                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8921315                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       694333                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       694333                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255620                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         762232                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      8921279                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      8921279                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1692610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1692610                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1692559                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1692559                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14212229                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14212229                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7504111                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7504111                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       694322                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       694322                       # number of InvalidateReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       255623                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14211921                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9196842                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24170998                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::cpu.data      9196670                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24171131                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       255623                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14211921                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9196842                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24170998                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       255620                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.data      9196670                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24171131                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5883                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        84237                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       343966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       440529                       # number of ReadReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       551016                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       551016                       # number of WriteInvalidateReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5886                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        12329                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826507                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826507                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826558                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826558                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83929                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        83929                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344087                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       344087                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       551027                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       551027                       # number of InvalidateReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5883                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        84237                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1170473                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1267036                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::cpu.data      1170645                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1266903                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5883                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        84237                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1170473                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1267036                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         5886                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        83929                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1170645                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1266903                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst     14296158                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7848198                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     22918917                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::total      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       774561                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      8921279                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      2519117                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      2519117                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14296158                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     14296158                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7848198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7848198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1245349                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1245349                       # number of InvalidateReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker       513055                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker       261506                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst     14296158                       # number of demand (read+write) accesses
@@ -513,28 +519,30 @@ system.cpu.l2cache.overall_accesses::cpu.inst     14296158
 system.cpu.l2cache.overall_accesses::cpu.data     10367315                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total     25438034                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022497                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005892                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043827                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019221                       # miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.442459                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.442459                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022508                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015917                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328094                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005871                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043843                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442468                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442468                       # miss rate for InvalidateReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022497                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005892                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.112900                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049809                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022508                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005871                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.112917                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049803                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022497                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005892                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.112900                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049809                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022508                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005871                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.112917                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049803                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -543,48 +551,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1503415                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1503415                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1503689                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1503689                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23372119                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1227763                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8921315                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1245349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8921279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     16986503                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      2519117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      2519117                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     28678566                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32383245                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14296158                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7848198                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1245349                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42974207                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35074071                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758224                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1543944                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          63363979                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          80350446                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1314364326                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6175776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2238699610                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2158994970                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      116338                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     36258168                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.034933                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.183610                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples     53244635                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.023788                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.152389                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           34991563     96.51%     96.51% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1266605      3.49%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           51978030     97.62%     97.62% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1266605      2.38%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       36258168                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       53244635                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29851                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -648,8 +658,8 @@ system.iocache.ReadReq_misses::realview.ide         8817                       #
 system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
 system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
 system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
@@ -661,8 +671,8 @@ system.iocache.ReadReq_accesses::realview.ide         8817
 system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
@@ -674,8 +684,8 @@ system.iocache.ReadReq_miss_rate::realview.ide            1
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -693,46 +703,48 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              526062                       # Transaction distribution
-system.membus.trans_dist::ReadResp             526062                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525878                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610046                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       657675                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       657675                       # Transaction distribution
+system.membus.trans_dist::Writeback           1610320                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           228940                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            825948                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           825948                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377021                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377021                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        449199                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5310733                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5439925                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5777598                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5530871                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5660063                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6006568                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212730912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212899962                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               227117498                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212740640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212909690                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220300730                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3693822                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3922914                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3693822    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3922914    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3693822                       # Request fanout histogram
+system.membus.snoop_fanout::total             3922914                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 6328b25f9..5f37e786a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,74 +4,74 @@ sim_seconds                                 47.216814                       # Nu
 sim_ticks                                47216814145000                       # Number of ticks simulated
 final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1152960                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1356355                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            55808802200                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 723640                       # Number of bytes of host memory used
-host_seconds                                   846.05                       # Real time elapsed on the host
+host_inst_rate                                1322702                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1556041                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            64025133870                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 730036                       # Number of bytes of host memory used
+host_seconds                                   737.47                       # Real time elapsed on the host
 sim_insts                                   975457230                       # Number of instructions simulated
 sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       152320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       128704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3903156                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         35201416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       222016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       221568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2639368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         38466864                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        412736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81348148                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3903156                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2639368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6542524                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    100538752                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       152256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       127104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3638260                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         62923528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       221632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       219968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2412168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         46368688                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        419904                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            116483508                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3638260                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2412168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6050428                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    101038848                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         100559336                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2380                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2011                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            101394                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            550035                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3469                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         3462                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             41347                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            601061                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6449                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1311608                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1570918                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         101059432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2379                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1986                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             97255                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            983193                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3437                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             37797                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            724527                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6561                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1860598                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1578732                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1573492                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3226                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               82665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              745527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          4693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               55899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              814686                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8741                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1722864                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          82665                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          55899                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             138563                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2129300                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1581306                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2692                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               77054                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1332651                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4694                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               51087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              982038                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2466992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          77054                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          51087                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             128141                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2139891                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                436                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2129736                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2129300                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3226                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              82665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             745963                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         4693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              55899                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             814686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8741                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3852600                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2140327                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2139891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2692                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              77054                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1333087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              51087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             982038                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4607319                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -319,46 +319,46 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2            5
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.dcache.tags.tag_accesses        363162250                       # Number of tag accesses
 system.cpu0.dcache.tags.data_accesses       363162250                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     86214909                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       86214909                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     80919814                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      80919814                       # number of WriteReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data     86214911                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       86214911                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     80919787                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      80919787                       # number of WriteReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       215654                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       215654                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       262024                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       262024                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2076465                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      2076465                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036713                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2036713                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    167134723                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       167134723                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    167350377                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      167350377                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3309384                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3309384                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1475628                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1475628                       # number of WriteReq misses
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       262007                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       262007                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2076466                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      2076466                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036572                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2036572                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    167134698                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       167134698                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    167350352                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      167350352                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3309382                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3309382                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1475655                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1475655                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       772139                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total       772139                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       831696                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       831696                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119817                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       119817                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158430                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       158430                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4785012                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4785012                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5557151                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5557151                       # number of overall misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       831713                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       831713                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119816                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       119816                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158571                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       158571                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4785037                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4785037                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5557176                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5557176                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     89524293                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     89524293                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     82395442                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total     82395442                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       987793                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::total       987793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1093720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1093720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1093720                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1093720                       # number of WriteLineReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2196282                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total      2196282                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2195143                       # number of StoreCondReq accesses(hits+misses)
@@ -373,16 +373,16 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909
 system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781681                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781681                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.760429                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.760429                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760444                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760444                       # miss rate for WriteLineReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054554                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054554                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072173                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072173                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072237                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072237                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027833                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.027833                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032139                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032139                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032140                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032140                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -391,14 +391,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4471084                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4471084                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      4472506                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4472506                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5539078                       # number of replacements
+system.cpu0.icache.tags.replacements          5539081                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.989005                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          492212894                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5539590                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            88.853669                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          492212891                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5539593                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            88.853620                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       5759896500                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989005                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
@@ -409,20 +409,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          256
 system.cpu0.icache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses       1001044573                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses      1001044573                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    492212894                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      492212894                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    492212894                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       492212894                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    492212894                       # number of overall hits
-system.cpu0.icache.overall_hits::total      492212894                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5539595                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5539595                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5539595                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5539595                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5539595                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5539595                       # number of overall misses
+system.cpu0.icache.tags.tag_accesses       1001044576                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses      1001044576                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    492212891                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      492212891                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    492212891                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       492212891                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    492212891                       # number of overall hits
+system.cpu0.icache.overall_hits::total      492212891                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5539598                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      5539598                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5539598                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       5539598                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5539598                       # number of overall misses
+system.cpu0.icache.overall_misses::total      5539598                       # number of overall misses
 system.cpu0.icache.ReadReq_accesses::cpu0.inst    497752489                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total    497752489                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.demand_accesses::cpu0.inst    497752489                       # number of demand (read+write) accesses
@@ -450,131 +450,139 @@ system.cpu0.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2709460                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16213.748169                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          11555205                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2725459                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            4.239728                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements         2713035                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16212.776574                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          18780735                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2729020                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.881861                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  5709.903296                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    52.786445                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    57.022731                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4531.359232                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  5862.676466                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.348505                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003222                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003480                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.276572                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.357829                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989609                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           48                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15951                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           33                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          234                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1167                       # Occupied blocks per task id
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+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.354980                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.222116                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -583,43 +591,46 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1573136                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1573136                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks      1573891                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1573891                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      10363944                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        623009                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadResp     10363944                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        32419                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        32419                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      4471084                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       831334                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       831334                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       131760                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158430                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       290190                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1344230                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1344230                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     11165440                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17935148                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.trans_dist::Writeback      4472506                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      7339348                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       131801                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158571                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       290372                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1344233                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1344233                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5539598                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4201337                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       831334                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       831334                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16704527                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19737201                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       366654                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       728076                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         30195318                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    354706580                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    694464585                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         37536458                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    354706772                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    641350217                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1466616                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2912304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1053550085                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    3357578                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     20506010                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.181419                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.385365                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total        1000435909                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    3360861                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     27849165                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.133662                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.340289                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          16785836     81.86%     81.86% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           3720174     18.14%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          24126791     86.63%     86.63% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           3722374     13.37%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      20506010                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total      27849165                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -836,44 +847,44 @@ system.cpu1.dcache.tags.tag_accesses        348813711                       # Nu
 system.cpu1.dcache.tags.data_accesses       348813711                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data     83697564                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total       83697564                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     76990302                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      76990302                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     76990238                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      76990238                       # number of WriteReq hits
 system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187854                       # number of SoftPFReq hits
 system.cpu1.dcache.SoftPFReq_hits::total       187854                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        63438                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total        63438                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        63440                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        63440                       # number of WriteLineReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062256                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total      2062256                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048921                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      2048921                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    160687866                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       160687866                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    160875720                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      160875720                       # number of overall hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048840                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      2048840                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    160687802                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       160687802                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    160875656                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      160875656                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data      3358222                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      3358222                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1453174                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1453174                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1453238                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1453238                       # number of WriteReq misses
 system.cpu1.dcache.SoftPFReq_misses::cpu1.data       792351                       # number of SoftPFReq misses
 system.cpu1.dcache.SoftPFReq_misses::total       792351                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       427061                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       427061                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       427059                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       427059                       # number of WriteLineReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       146820                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total       146820                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158828                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       158828                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4811396                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4811396                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5603747                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5603747                       # number of overall misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158909                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       158909                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4811460                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4811460                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5603811                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5603811                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     87055786                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     87055786                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     78443476                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total     78443476                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       980205                       # number of SoftPFReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::total       980205                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       490499                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       490499                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       490499                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       490499                       # number of WriteLineReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2209076                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total      2209076                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2207749                       # number of StoreCondReq accesses(hits+misses)
@@ -884,20 +895,20 @@ system.cpu1.dcache.overall_accesses::cpu1.data    166479467
 system.cpu1.dcache.overall_accesses::total    166479467                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038576                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.038576                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018525                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018525                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018526                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018526                       # miss rate for WriteReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808352                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808352                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.870666                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.870666                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.870662                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.870662                       # miss rate for WriteLineReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066462                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066462                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071941                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071941                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071978                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071978                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029072                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     0.029072                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033660                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.033660                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033661                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.033661                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -906,8 +917,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      4032690                       # number of writebacks
-system.cpu1.dcache.writebacks::total          4032690                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks      4032489                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4032489                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements          4741297                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          496.426080                       # Cycle average of tags in use
@@ -964,133 +975,141 @@ system.cpu1.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2276750                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13455.535871                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          10863007                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2292767                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            4.737946                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9713557209000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5167.508425                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.262953                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    86.675159                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2849.798557                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5285.290777                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.315400                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004044                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005290                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.173938                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.322589                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.821261                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           96                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15921                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.replacements         2278625                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13455.366056                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17413486                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2294680                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.588634                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9726491516500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5192.867159                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.806245                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    99.441300                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2834.629918                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5261.621433                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.316947                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004078                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.006069                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.173012                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.321144                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.821250                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           98                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15957                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           49                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           34                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1571                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5986                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4452                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3831                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.971741                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       254014080                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      254014080                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       324472                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       140015                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4218186                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      3058286                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       7740959                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      4032690                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      4032690                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       161150                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       161150                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3831                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         3831                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614491                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       614491                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       324472                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       140015                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4218186                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3672777                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8355450                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       324472                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       140015                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4218186                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3672777                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8355450                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12267                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9705                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       523623                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data      1239107                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1784702                       # number of ReadReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       265696                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       265696                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133668                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       133668                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158828                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       158828                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       701399                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       701399                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12267                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9705                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       523623                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1940506                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2486101                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12267                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9705                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       523623                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1940506                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2486101                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       336739                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149720                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4741809                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      4297393                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total      9525661                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      4032690                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      4032690                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       426846                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       426846                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137499                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       137499                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       158828                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       158828                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1614                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5923                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4524                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3815                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005981                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.973938                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       360485676                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      360485676                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       324846                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       140054                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        464900                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      4032489                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      4032489                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3822                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         3822                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614016                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       614016                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4217303                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4217303                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3057649                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3057649                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       161208                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       161208                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       324846                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       140054                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4217303                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       140054                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4217303                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3671665                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8353868                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12306                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9777                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        22083                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133739                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       133739                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158909                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       158909                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       701874                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       701874                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       524506                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       524506                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1239744                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total      1239744                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265638                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       265638                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12306                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9777                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       524506                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1941618                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      2488207                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12306                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9777                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       524506                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1941618                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      2488207                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       337152                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149831                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       486983                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      4032489                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      4032489                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137561                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       137561                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       158909                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       158909                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1315890                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::total      1315890                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       336739                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149720                       # number of demand (read+write) accesses
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4741809                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      4741809                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4297393                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      4297393                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       426846                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       426846                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       337152                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149831                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.inst      4741809                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.data      5613283                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10841551                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       336739                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149720                       # number of overall (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10842075                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       337152                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149831                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.inst      4741809                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.data      5613283                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10841551                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.110427                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.288339                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.187357                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.622463                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.622463                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.972138                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.972138                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.overall_accesses::total     10842075                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036500                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065254                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.045347                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.972216                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.972216                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.533023                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.533023                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110427                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345699                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.229312                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110427                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345699                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.229312                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.533383                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.533383                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.110613                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.110613                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.288487                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.288487                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.622327                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.622327                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036500                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065254                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110613                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345897                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.229495                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036500                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065254                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110613                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345897                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.229495                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1099,48 +1118,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1183004                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1183004                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks      1184748                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1184748                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       9645413                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq        606211                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadResp      9645413                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         6383                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         6383                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      4032690                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       426846                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       426846                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       137499                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       158828                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       296327                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      4032489                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      6653857                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       137561                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       158909                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       296470                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExReq      1315890                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExResp      1315890                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9483878                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16731086                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4741809                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4297393                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       426846                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       426846                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14225175                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18643731                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       364008                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       835436                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         27414408                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         34068350                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    303476296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    644698812                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    617367804                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1456032                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3341744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         952972884                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    3837128                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     19395843                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.220254                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.414418                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total         925641876                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    3842126                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     26053175                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.164109                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.370374                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          15123827     77.97%     77.97% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           4272016     22.03%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          21777626     83.59%     83.59% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           4275549     16.41%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      19395843                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total      26053175                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136634                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29906                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136634                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47636                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1204,8 +1225,8 @@ system.iocache.ReadReq_misses::realview.ide         8876                       #
 system.iocache.ReadReq_misses::total             8913                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
 system.iocache.demand_misses::realview.ide         8876                       # number of demand (read+write) misses
 system.iocache.demand_misses::total              8916                       # number of demand (read+write) misses
@@ -1217,8 +1238,8 @@ system.iocache.ReadReq_accesses::realview.ide         8876
 system.iocache.ReadReq_accesses::total           8913                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::realview.ide         8876                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total            8916                       # number of demand (read+write) accesses
@@ -1230,8 +1251,8 @@ system.iocache.ReadReq_miss_rate::realview.ide            1
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -1249,205 +1270,192 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106694                       # number of writebacks
 system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1759191                       # number of replacements
-system.l2c.tags.tagsinuse                62867.167491                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3704436                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1817948                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.037702                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                483416500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35264.935108                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.422401                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    57.110376                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3318.609191                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6952.273283                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   314.594733                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   425.085194                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2976.403767                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    13512.733438                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.538100                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000693                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000871                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.050638                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.106083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004800                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006486                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.045416                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.206188                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.959277                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          227                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        58530                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          225                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3441                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5617                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48852                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003464                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.893097                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 66366738                       # Number of tag accesses
-system.l2c.tags.data_accesses                66366738                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         6239                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4535                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             509640                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             744526                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5366                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         3579                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             482377                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             691195                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2447457                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2756140                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2756140                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       121071                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data        98425                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       219496                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           13420                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           10778                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               24198                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          1497                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1278                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              2775                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           202220                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           170877                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               373097                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6239                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4535                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              509640                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              946746                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5366                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3579                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              482377                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              862072                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2820554                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6239                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4535                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             509640                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             946746                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5366                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3579                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             482377                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             862072                       # number of overall hits
-system.l2c.overall_hits::total                2820554                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2380                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2011                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            58293                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           183599                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         3469                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         3462                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            41246                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           189649                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               484109                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       479323                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       160634                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       639957                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         58449                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         54093                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            112542                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         7788                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         7462                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           15250                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         377640                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         418302                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             795942                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2380                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2011                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             58293                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            561239                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         3469                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         3462                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             41246                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            607951                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1280051                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2380                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2011                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            58293                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           561239                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         3469                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         3462                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            41246                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           607951                       # number of overall misses
-system.l2c.overall_misses::total              1280051                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         8619                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6546                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         567933                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         928125                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         8835                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         7041                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         523623                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         880844                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2931566                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2756140                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2756140                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       600394                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       259059                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       859453                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        71869                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        64871                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          136740                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         9285                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         8740                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         18025                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       579860                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       589179                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1169039                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8619                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          567933                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1507985                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8835                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7041                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          523623                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1470023                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4100605                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8619                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         567933                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1507985                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8835                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7041                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         523623                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1470023                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4100605                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.102641                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.197817                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.078770                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.215304                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.165137                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.798347                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.620067                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.744610                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.813271                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.833855                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.823036                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.838772                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.853776                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.846047                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.651261                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.709974                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.680852                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.102641                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.372178                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.078770                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.413566                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.312161                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.102641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.372178                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.078770                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.413566                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.312161                       # miss rate for overall accesses
+system.l2c.tags.replacements                  1751385                       # number of replacements
+system.l2c.tags.tagsinuse                62313.380560                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6017106                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1809468                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.325345                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   34286.931814                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    47.043983                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    59.106418                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3327.548165                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6997.138223                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   309.986034                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   428.835942                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3021.438473                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    13835.351509                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.523177                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000718                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.106768                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004730                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006544                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.046103                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.211111                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.950827                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          220                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        57863                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          218                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          545                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3434                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5577                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        48241                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.882919                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 85814440                       # Number of tag accesses
+system.l2c.tags.data_accesses                85814440                       # Number of data accesses
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+system.l2c.Writeback_hits::total              2758639                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           13259                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           10916                       # number of UpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::cpu0.data          1481                       # number of SCUpgradeReq hits
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+system.l2c.overall_hits::total                3047627                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         58599                       # number of UpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::cpu0.data         7811                       # number of SCUpgradeReq misses
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+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1986                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu0.data       180703                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3437                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu1.data       186059                       # number of ReadSharedReq misses
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+system.l2c.overall_misses::cpu0.data           996948                       # number of overall misses
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+system.l2c.overall_misses::cpu1.data           733404                       # number of overall misses
+system.l2c.overall_misses::total              1833467                       # number of overall misses
+system.l2c.Writeback_accesses::writebacks      2758639                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2758639                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        71858                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        65000                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::cpu0.data         9292                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8845                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7075                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       524506                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       881071                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      2934501                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8668                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6547                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          568738                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         2063884                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         8845                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7075                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          524506                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total             4881094                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8668                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6547                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.data        1692831                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4881094                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.815483                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.832062                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.823357                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.840616                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.857110                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.848581                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.719264                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.674269                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.700501                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.274458                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.303345                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.095218                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.194503                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.391521                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.485795                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.071870                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.211174                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.160122                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.274458                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.303345                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.095218                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.483045                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.391521                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.485795                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.071870                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.433241                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.375626                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.274458                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.303345                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.095218                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.483045                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.391521                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.485795                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.071870                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.433241                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.375626                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1456,49 +1464,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1464224                       # number of writebacks
-system.l2c.writebacks::total                  1464224                       # number of writebacks
+system.l2c.writebacks::writebacks             1472038                       # number of writebacks
+system.l2c.writebacks::total                  1472038                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              575153                       # Transaction distribution
-system.membus.trans_dist::ReadResp             575153                       # Transaction distribution
+system.membus.trans_dist::ReadReq               82131                       # Transaction distribution
+system.membus.trans_dist::ReadResp             560921                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38802                       # Transaction distribution
 system.membus.trans_dist::WriteResp             38802                       # Transaction distribution
-system.membus.trans_dist::Writeback           1570918                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       742110                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       742110                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           328170                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         314483                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          149857                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            965890                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           778455                       # Transaction distribution
+system.membus.trans_dist::Writeback           1578732                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           418758                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           328366                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         314759                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          149960                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1611572                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1341565                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        478790                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122570                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27558                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6331701                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6481921                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337982                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337982                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6819903                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6659521                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6809741                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       346873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7156614                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155677                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55116                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    215372636                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    215583633                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14229440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14229440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               229813073                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    210336476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    210547473                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7398848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7398848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               217946321                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4535526                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4958638                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4535526    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4958638    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4535526                       # Request fanout histogram
+system.membus.snoop_fanout::total             4958638                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1541,35 +1551,35 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            3711525                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3711525                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              82133                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3716153                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             38802                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            38802                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2756140                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       859453                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       859453                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          330303                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        317258                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         647561                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1356474                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1356474                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8686436                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7297334                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15983770                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    301115229                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    249782916                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              550898145                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          117325                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9485599                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012192                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.109740                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback          2758639                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2438361                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          330513                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        317480                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         647993                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2216600                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2216600                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3634020                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9937165                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8498931                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18436096                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    301383709                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    250013636                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              551397345                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          117333                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         11932192                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.009692                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.097969                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9369955     98.78%     98.78% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115644      1.22%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               11816548     99.03%     99.03% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115644      0.97%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9485599                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           11932192                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index a28434f3e..6f3d32b32 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1196191                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1405721                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            62096813616                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 713636                       # Number of bytes of host memory used
-host_seconds                                   823.09                       # Real time elapsed on the host
+host_inst_rate                                1372139                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1612489                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            71230678319                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 718244                       # Number of bytes of host memory used
+host_seconds                                   717.54                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       376512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5562740                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          74833672                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81627068                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103042944                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.itb.walker       376704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5543028                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         110110088                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            116884284                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5543028                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103060480                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103063524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103081060                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             127325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1169289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315843                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610046                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5886                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             127017                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1720483                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1866737                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610320                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612619                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1612893                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           7367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1464136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8644                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1597050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016056                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           7370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108450                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2154326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286865                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016399                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016459                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016056                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2016802                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016399                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          7367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1464539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3613509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          7370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108450                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2154729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303666                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -294,8 +294,8 @@ system.cpu.dcache.WriteReq_hits::cpu.data    159522870                       # n
 system.cpu.dcache.WriteReq_hits::total      159522870                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data       424020                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total        424020                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       337709                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       337709                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       337709                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       337709                       # number of WriteLineReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      4310545                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      4310545                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      4562464                       # number of StoreCondReq hits
@@ -310,8 +310,8 @@ system.cpu.dcache.WriteReq_misses::cpu.data      2570257                       #
 system.cpu.dcache.WriteReq_misses::total      2570257                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data      1584397                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total      1584397                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1245349                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1245349                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1245349                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1245349                       # number of WriteLineReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data       253721                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total       253721                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
@@ -326,8 +326,8 @@ system.cpu.dcache.WriteReq_accesses::cpu.data    162093127
 system.cpu.dcache.WriteReq_accesses::total    162093127                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data      2008417                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total      2008417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1583058                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1583058                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4564266                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      4564266                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      4562465                       # number of StoreCondReq accesses(hits+misses)
@@ -342,8 +342,8 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015857
 system.cpu.dcache.WriteReq_miss_rate::total     0.015857                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788879                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.788879                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786673                       # miss rate for WriteLineReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055589                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055589                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
@@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8921315                       # number of writebacks
-system.cpu.dcache.writebacks::total           8921315                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      8921279                       # number of writebacks
+system.cpu.dcache.writebacks::total           8921279                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14295641                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
@@ -412,96 +412,102 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1722692                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65341.862502                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29983424                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1785989                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            16.788135                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1722572                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.862554                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46968482                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1785868                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.300086                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.196824                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.735041                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6261.263092                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.566738                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.195568                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.733962                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6290.976194                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.566080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.323257                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095993                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.323461                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63019                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63018                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4          278                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2715                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4911                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2714                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4910                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54670                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961594                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        290307620                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       290307620                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961578                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        426199223                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       426199223                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255623                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     14211921                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      7504232                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       22478388                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8921315                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8921315                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       694333                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       694333                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255620                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         762232                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      8921279                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      8921279                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1692610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1692610                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1692559                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1692559                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14212229                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14212229                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7504111                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7504111                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       694322                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       694322                       # number of InvalidateReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       255623                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14211921                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9196842                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24170998                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       255620                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     14212229                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      9196670                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24171131                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       255623                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14211921                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9196842                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24170998                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       255620                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     14212229                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      9196670                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24171131                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5883                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        84237                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       343966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       440529                       # number of ReadReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       551016                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       551016                       # number of WriteInvalidateReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5886                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        12329                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826507                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826507                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826558                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826558                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83929                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        83929                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344087                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       344087                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       551027                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       551027                       # number of InvalidateReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5883                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        84237                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1170473                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1267036                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         5886                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        83929                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1170645                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1266903                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5883                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        84237                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1170473                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1267036                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         5886                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        83929                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1170645                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1266903                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst     14296158                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7848198                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     22918917                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::total      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       774561                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      8921279                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      2519117                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      2519117                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14296158                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     14296158                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7848198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7848198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1245349                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1245349                       # number of InvalidateReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker       513055                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker       261506                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst     14296158                       # number of demand (read+write) accesses
@@ -513,28 +519,30 @@ system.cpu.l2cache.overall_accesses::cpu.inst     14296158
 system.cpu.l2cache.overall_accesses::cpu.data     10367315                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total     25438034                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022497                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005892                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043827                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019221                       # miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.442459                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.442459                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022508                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015917                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328094                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005871                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043843                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442468                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442468                       # miss rate for InvalidateReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022497                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005892                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.112900                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049809                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022508                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005871                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.112917                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049803                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022497                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005892                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.112900                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049809                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022508                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005871                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.112917                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049803                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -543,48 +551,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1503415                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1503415                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1503689                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1503689                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23372119                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1227763                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8921315                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1245349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8921279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     16986503                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      2519117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      2519117                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     28678566                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32383245                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14296158                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7848198                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1245349                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42974207                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35074071                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758224                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1543944                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          63363979                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          80350446                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1314364326                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6175776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2238699610                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2158994970                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      116338                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     36258168                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.034933                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.183610                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples     53244635                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.023788                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.152389                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           34991563     96.51%     96.51% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1266605      3.49%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           51978030     97.62%     97.62% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1266605      2.38%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       36258168                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       53244635                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29851                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -648,8 +658,8 @@ system.iocache.ReadReq_misses::realview.ide         8817                       #
 system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
 system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
 system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
@@ -661,8 +671,8 @@ system.iocache.ReadReq_accesses::realview.ide         8817
 system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
@@ -674,8 +684,8 @@ system.iocache.ReadReq_miss_rate::realview.ide            1
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -693,46 +703,48 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              526062                       # Transaction distribution
-system.membus.trans_dist::ReadResp             526062                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525878                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610046                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       657675                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       657675                       # Transaction distribution
+system.membus.trans_dist::Writeback           1610320                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           228940                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            825948                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           825948                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377021                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377021                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        449199                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5310733                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5439925                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5777598                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5530871                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5660063                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6006568                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212730912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212899962                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               227117498                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212740640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212909690                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220300730                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3693822                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3922914                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3693822    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3922914    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3693822                       # Request fanout histogram
+system.membus.snoop_fanout::total             3922914                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 5570b9a7c..0006790d0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.526955                       # Number of seconds simulated
-sim_ticks                                47526954967000                       # Number of ticks simulated
-final_tick                               47526954967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.496387                       # Number of seconds simulated
+sim_ticks                                47496386980500                       # Number of ticks simulated
+final_tick                               47496386980500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 679404                       # Simulator instruction rate (inst/s)
-host_op_rate                                   799114                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36258651928                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 756696                       # Number of bytes of host memory used
-host_seconds                                  1310.78                       # Real time elapsed on the host
-sim_insts                                   890546366                       # Number of instructions simulated
-sim_ops                                    1047459319                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 708538                       # Simulator instruction rate (inst/s)
+host_op_rate                                   833484                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38555693115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 757988                       # Number of bytes of host memory used
+host_seconds                                  1231.89                       # Real time elapsed on the host
+sim_insts                                   872840522                       # Number of instructions simulated
+sim_ops                                    1026761155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       120896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       123520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3402100                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         13323656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     13846976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       139776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       143808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3041464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         11124432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     15361728                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        416704                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             61045060                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3402100                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3041464                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6443564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78583104                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        77248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        78464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2962612                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         38823816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     12701504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       109824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       113728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2837560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         15245328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12552128                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        438080                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             85940292                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2962612                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2837560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5800172                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     72817088                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78603688                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1930                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             93565                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            208195                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       216359                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2184                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2247                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             47611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            173832                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       240027                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6511                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                994350                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1227861                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          72837672                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1207                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1226                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             86698                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            606635                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       198461                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1716                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1777                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             44425                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            238221                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       196127                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6845                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1383338                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1137767                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1230435                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2544                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2599                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               71583                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              280339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       291350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2941                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               63995                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              234066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       323221                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1284430                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          71583                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          63995                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             135577                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1653443                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1140341                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1626                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               62376                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              817406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       267420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2394                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               59743                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              320979                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       264275                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9223                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1809407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          62376                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          59743                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             122118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1533108                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1653876                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1653443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2544                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2599                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              71583                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             280772                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       291350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2941                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              63995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             234066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       323221                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2938306                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        994350                       # Number of read requests accepted
-system.physmem.writeReqs                      1902822                       # Number of write requests accepted
-system.physmem.readBursts                      994350                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1902822                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 63617152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 118663680                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  61045060                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              121636456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   48679                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         115330                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               57482                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               61474                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               58055                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               62815                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               61744                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               72443                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62137                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               62898                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               53757                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               98485                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              53699                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              61424                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              50178                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              60766                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              57507                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              59154                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              114707                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              119877                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              118693                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              118700                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              118108                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              125436                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              113884                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              116296                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              112515                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              116242                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             112992                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             118745                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             107808                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             111387                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             114155                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             114575                       # Per bank write bursts
+system.physmem.bw_write::total                1533541                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1533108                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1626                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1652                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              62376                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             817839                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       267420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              59743                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             320979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       264275                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9223                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3342948                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1383338                       # Number of read requests accepted
+system.physmem.writeReqs                      1140341                       # Number of write requests accepted
+system.physmem.readBursts                     1383338                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1140341                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 88503808                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     29824                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  72836864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  85940292                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               72837672                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      466                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         218501                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               80378                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               85683                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               84533                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               91641                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               87506                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               92565                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               85373                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               87361                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               80689                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              125890                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              79879                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              87722                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              73371                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              83748                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              77275                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              79258                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               66779                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               71701                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               72134                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76164                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               73824                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               77776                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               71735                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               72120                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               69346                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               71851                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              68226                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              73306                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64374                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              72179                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              67114                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              69447                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         406                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47526951912500                       # Total gap between requests
+system.physmem.numWrRetry                          52                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47496383920000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  951125                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1340113                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1900248                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    698116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     83658                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     42191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     36638                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     31495                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     28119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     24839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     21358                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     17624                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4596                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1385                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1018                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      651                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      363                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      281                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1137767                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1131623                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     75605                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     35452                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30271                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     26331                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     23289                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     20581                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     17115                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     14732                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      848                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      676                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      510                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      250                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -188,169 +188,167 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    55966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    69244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    86453                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    95710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    99723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    98450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    98652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    98653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   101180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   101256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   102685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   108850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   104999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   104785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   118151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   108223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   102687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    99179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     6890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     5415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     5566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     6838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     6775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     6308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     6158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     7224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     5430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     4899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     4456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     5091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3523                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      818                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                     1611                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1054851                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      172.802142                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     106.115345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     242.100455                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         681651     64.62%     64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       201380     19.09%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48895      4.64%     88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24340      2.31%     90.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        17755      1.68%     92.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11649      1.10%     93.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8558      0.81%     94.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7940      0.75%     95.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        52683      4.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1054851                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         92018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        10.802300                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      106.341779                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          92015    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           92018                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         92018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.149536                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.827281                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.009129                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31           90131     97.95%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47             760      0.83%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              32      0.03%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              41      0.04%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             142      0.15%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            182      0.20%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           347      0.38%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           116      0.13%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            35      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            12      0.01%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            63      0.07%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            31      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            15      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             6      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             4      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             5      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             6      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            16      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             8      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            24      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             4      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           92018                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36585898476                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55223735976                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4970090000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       36806.07                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    16550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    19449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    57076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    64173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    65524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    69411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    70341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    73639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    73241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    74463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    72846                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    73821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    77361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    71631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    68870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    66897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      987                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      158                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       866706                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      186.153496                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     114.409994                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     244.608227                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         521785     60.20%     60.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       170596     19.68%     79.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        55940      6.45%     86.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28866      3.33%     89.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        19331      2.23%     91.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11894      1.37%     93.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9595      1.11%     94.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9879      1.14%     95.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        38820      4.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         866706                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         64746                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.358308                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      318.389928                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          64744    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           64746                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         64746                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.577549                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.073829                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.807966                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           61438     94.89%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             935      1.44%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             457      0.71%     97.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             214      0.33%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             283      0.44%     97.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             509      0.79%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             100      0.15%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.06%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              36      0.06%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              29      0.04%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              34      0.05%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              27      0.04%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             442      0.68%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              39      0.06%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              47      0.07%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              53      0.08%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              11      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            16      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           64746                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    34994473123                       # Total ticks spent queuing
+system.physmem.totMemAccLat               60923323123                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6914360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25305.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  55556.07                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.34                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.50                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.56                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44055.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.86                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     744165                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1049121                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.86                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  56.58                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16404601.42                       # Average gap between requests
-system.physmem.pageHitRate                      62.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4105851120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2240295750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3892535400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6128142480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3104229389040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1214897373855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27450471155250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31785964742895                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.798736                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45665609957576                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1587029340000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1113162                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    541079                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.50                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.54                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18820295.26                       # Average gap between requests
+system.physmem.pageHitRate                      65.62                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3392073720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1850833875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5421273000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3772869840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3102232782480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1205451752805                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27440415505500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31762537091220                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.735925                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45648791331206                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1586008580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    274315218424                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    261586624794                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3868822440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2110964625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3860766000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5886555120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3104229389040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1202076105075                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27461717882250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31783750484550                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.752146                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45684364167822                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1587029340000                       # Time in different power states
+system.physmem_1.actEnergy                 3160223640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1724328375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5365089600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3601862640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3102232782480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1192319355510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27451935144000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31760338786245                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.689642                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45667995849266                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1586008580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    255557515928                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    242377776984                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -414,69 +412,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   101631                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               101631                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9048                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76119                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           11                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       101620                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.113167                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    36.075158                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-1023       101619    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::11264-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       101620                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        85178                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        84047     98.67%     98.67% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          953      1.12%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           46      0.05%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           63      0.07%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           53      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   104839                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               104839                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10495                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        79742                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       104830                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.171707                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    55.594229                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       104829    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       104830                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        90246                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19548.112936                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18016.919113                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12415.253011                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        89555     99.23%     99.23% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          591      0.65%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           29      0.03%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           30      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           26      0.03%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        85178                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   6479942056                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.123756                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     -801929896    -12.38%    -12.38% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1     7281871952    112.38%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   6479942056                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        76120     89.38%     89.38% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         9048     10.62%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        85168                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101631                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        90246                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  -2134286464                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.271898                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      580308492    -27.19%    -27.19% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -2714594956    127.19%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  -2134286464                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        79742     88.37%     88.37% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10495     11.63%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        90237                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       104839                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101631                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85168                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       104839                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        90237                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85168                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       186799                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        90237                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       195076                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83767358                       # DTB read hits
-system.cpu0.dtb.read_misses                     74871                       # DTB read misses
-system.cpu0.dtb.write_hits                   75914688                       # DTB write hits
-system.cpu0.dtb.write_misses                    26760                       # DTB write misses
+system.cpu0.dtb.read_hits                    85272873                       # DTB read hits
+system.cpu0.dtb.read_misses                     78883                       # DTB read misses
+system.cpu0.dtb.write_hits                   76479493                       # DTB write hits
+system.cpu0.dtb.write_misses                    25956                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   32159                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   39585                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3900                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4176                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     8424                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                83842229                       # DTB read accesses
-system.cpu0.dtb.write_accesses               75941448                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10186                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                85351756                       # DTB read accesses
+system.cpu0.dtb.write_accesses               76505449                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        159682046                       # DTB hits
-system.cpu0.dtb.misses                         101631                       # DTB misses
-system.cpu0.dtb.accesses                    159783677                       # DTB accesses
+system.cpu0.dtb.hits                        161752366                       # DTB hits
+system.cpu0.dtb.misses                         104839                       # DTB misses
+system.cpu0.dtb.accesses                    161857205                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -506,235 +502,240 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    55722                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                55722                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          543                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        49598                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        55722                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          55722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        55722                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        50141                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        48785     97.30%     97.30% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1144      2.28%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607           57      0.11%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           79      0.16%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           56      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           13      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        50141                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   -241360296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     -241360296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   -241360296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        49598     98.92%     98.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          543      1.08%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        50141                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    57460                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                57460                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          729                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51308                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        57460                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          57460    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        57460                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52037                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 22020.322079                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19981.613647                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 15973.969343                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        48320     92.86%     92.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         2946      5.66%     98.52% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          248      0.48%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          406      0.78%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607            9      0.02%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           33      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            6      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911           15      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           16      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            8      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52037                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   -326738796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     -326738796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   -326738796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        51308     98.60%     98.60% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          729      1.40%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52037                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        55722                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        55722                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57460                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57460                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        50141                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        50141                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       105863                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   444122432                       # ITB inst hits
-system.cpu0.itb.inst_misses                     55722                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52037                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52037                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       109497                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   453477294                       # ITB inst hits
+system.cpu0.itb.inst_misses                     57460                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   22526                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27698                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               444178154                       # ITB inst accesses
-system.cpu0.itb.hits                        444122432                       # DTB hits
-system.cpu0.itb.misses                          55722                       # DTB misses
-system.cpu0.itb.accesses                    444178154                       # DTB accesses
-system.cpu0.numCycles                     95053909934                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               453534754                       # ITB inst accesses
+system.cpu0.itb.hits                        453477294                       # DTB hits
+system.cpu0.itb.misses                          57460                       # DTB misses
+system.cpu0.itb.accesses                    453534754                       # DTB accesses
+system.cpu0.numCycles                     94992773961                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  443872382                       # Number of instructions committed
-system.cpu0.committedOps                    521690846                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            479475231                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                421225                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26535732                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     67239811                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   479475231                       # number of integer instructions
-system.cpu0.num_fp_insts                       421225                       # number of float instructions
-system.cpu0.num_int_register_reads          693782505                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         380162379                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              701849                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             304628                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           115037577                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          114748059                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    159672530                       # number of memory refs
-system.cpu0.num_load_insts                   83761106                       # Number of load instructions
-system.cpu0.num_store_insts                  75911424                       # Number of store instructions
-system.cpu0.num_idle_cycles              93959856753.206024                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1094053180.793977                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011510                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988490                       # Percentage of idle cycles
-system.cpu0.Branches                         99058393                       # Number of branches fetched
+system.cpu0.committedInsts                  453209687                       # Number of instructions committed
+system.cpu0.committedOps                    531499422                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            488089676                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                379595                       # Number of float alu accesses
+system.cpu0.num_func_calls                   26785883                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     68737200                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   488089676                       # number of integer instructions
+system.cpu0.num_fp_insts                       379595                       # number of float instructions
+system.cpu0.num_int_register_reads          710027821                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         387728381                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              639718                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             261592                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           118698555                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          118319526                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    161743236                       # number of memory refs
+system.cpu0.num_load_insts                   85268904                       # Number of load instructions
+system.cpu0.num_store_insts                  76474332                       # Number of store instructions
+system.cpu0.num_idle_cycles              93849963781.964020                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1142810179.035976                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.012030                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.987970                       # Percentage of idle cycles
+system.cpu0.Branches                        100837041                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                361081858     69.17%     69.17% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1125018      0.22%     69.39% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    61306      0.01%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             43308      0.01%     69.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
-system.cpu0.op_class::MemRead                83761106     16.05%     85.46% # Class of executed instruction
-system.cpu0.op_class::MemWrite               75911424     14.54%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                368748107     69.34%     69.34% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1224660      0.23%     69.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    64156      0.01%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             29994      0.01%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::MemRead                85268904     16.03%     85.62% # Class of executed instruction
+system.cpu0.op_class::MemWrite               76474332     14.38%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 521984020                       # Class of executed instruction
+system.cpu0.op_class::total                 531810153                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5106                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          5414405                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.206026                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          154030593                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5414914                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.445621                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       4071814500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.206026                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937902                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.937902                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          344                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        324790756                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       324790756                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77996551                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77996551                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     71694037                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      71694037                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       187802                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       187802                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       131287                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       131287                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1831493                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1831493                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1787873                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1787873                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    149690588                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       149690588                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    149878390                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      149878390                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2964325                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      2964325                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1343066                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1343066                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       617580                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       617580                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       739156                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       739156                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       153043                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       153043                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195288                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       195288                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4307391                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4307391                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4924971                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4924971                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44154787210                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  44154787210                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  26046845450                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  26046845450                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  30884044772                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  30884044772                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2257944026                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2257944026                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4202199390                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4202199390                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2186500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2186500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  70201632660                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  70201632660                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  70201632660                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  70201632660                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80960876                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     80960876                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73037103                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     73037103                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       805382                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       805382                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       870443                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total       870443                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1984536                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1984536                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1983161                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1983161                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    153997979                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    153997979                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    154803361                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    154803361                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036614                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036614                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018389                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018389                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766816                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766816                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.849172                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.849172                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077118                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077118                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098473                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098473                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027970                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027970                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031814                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.031814                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090                       # average StoreCondReq miss latency
+system.cpu0.kern.inst.quiesce                   14069                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          5594005                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          472.878328                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          155905526                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5594517                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.867558                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       3986453000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   472.878328                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.923590                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.923590                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        329066714                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       329066714                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79426163                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       79426163                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     72239104                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      72239104                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186194                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       186194                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       137014                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       137014                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1774977                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1774977                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1742409                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1742409                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    151665267                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       151665267                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    151851461                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      151851461                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3027243                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3027243                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1374655                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1374655                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       667737                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       667737                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       757348                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       757348                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       163489                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       163489                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194173                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       194173                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4401898                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4401898                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5069635                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5069635                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  43551375000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  43551375000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  25743175500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  25743175500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46783649000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  46783649000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2342479000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2342479000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4171693500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4171693500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2590500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2590500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  69294550500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  69294550500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  69294550500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  69294550500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     82453406                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     82453406                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     73613759                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     73613759                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853931                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       853931                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       894362                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       894362                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1938466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1938466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1936582                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1936582                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    156067165                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    156067165                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    156921096                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    156921096                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036715                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036715                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018674                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018674                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781957                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781957                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.846803                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.846803                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.084339                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.084339                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.100266                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.100266                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028205                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028205                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032307                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032307                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14386.481363                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14386.481363                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18727.008231                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18727.008231                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61772.988111                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61772.988111                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14328.052652                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14328.052652                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21484.415959                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21484.415959                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15741.970963                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15741.970963                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13668.548229                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13668.548229                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -743,157 +744,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3655915                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3655915                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        33290                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        33290                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21376                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21376                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        42886                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        42886                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        54666                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        54666                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        54666                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        54666                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2931035                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2931035                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1321690                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1321690                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       611921                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       611921                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       739156                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       739156                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110157                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       110157                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195288                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       195288                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4252725                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4252725                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4864646                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4864646                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16584                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16584                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18033                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18033                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34617                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34617                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38329059920                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38329059920                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23455096050                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23455096050                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13388812156                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13388812156                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  29772038228                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  29772038228                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1440580476                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1440580476                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3899742610                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3899742610                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2117500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2117500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61784155970                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61784155970                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75172968126                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  75172968126                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2701006250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2701006250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2792188500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2792188500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5493194750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5493194750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036203                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036203                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018096                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018096                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759790                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759790                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.849172                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.849172                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055508                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055508                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098473                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098473                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027615                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027615                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031425                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031425                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3814789                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3814789                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        30828                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        30828                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21250                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21250                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41671                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41671                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        52078                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        52078                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        52078                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        52078                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2996415                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2996415                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1353405                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1353405                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       662134                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       662134                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       757348                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       757348                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121818                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121818                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194173                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       194173                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4349820                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4349820                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5011954                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5011954                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        27090                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        27090                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26689                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26689                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        53779                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        53779                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39330539500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  39330539500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23857005000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23857005000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13760399000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13760399000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  46026301000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  46026301000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1597973500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1597973500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3977579500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3977579500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2531500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2531500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  63187544500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  63187544500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  76947943500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  76947943500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4585847500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4585847500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4300128500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4300128500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   8885976000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8885976000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036341                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036341                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018385                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018385                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.775395                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.775395                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.846803                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.846803                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062842                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062842                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.100266                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.100266                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027871                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027871                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031939                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031939                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13125.865242                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13125.865242                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17627.395347                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17627.395347                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20781.894601                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20781.894601                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60772.988111                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60772.988111                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13117.712489                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13117.712489                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20484.719812                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20484.719812                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14526.473394                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14526.473394                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15352.883027                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15352.883027                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169281.930602                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169281.930602                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161119.880850                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 161119.880850                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165231.335651                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165231.335651                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5032307                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.899757                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          439089613                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5032819                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            87.245262                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      33435686250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.899757                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999804                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          4817420                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.881006                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          448659362                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          4817932                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            93.122809                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      42527405000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.881006                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999768                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999768                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        893277683                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       893277683                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    439089613                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      439089613                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    439089613                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       439089613                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    439089613                       # number of overall hits
-system.cpu0.icache.overall_hits::total      439089613                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5032819                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5032819                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5032819                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5032819                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5032819                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5032819                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  52854361147                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  52854361147                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  52854361147                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  52854361147                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  52854361147                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  52854361147                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    444122432                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    444122432                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    444122432                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    444122432                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    444122432                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    444122432                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011332                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011332                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011332                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011332                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011332                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011332                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10501.939598                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10501.939598                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        911772520                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       911772520                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    448659362                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      448659362                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    448659362                       # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu0.inst    448659362                       # number of overall hits
+system.cpu0.icache.overall_hits::total      448659362                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      4817932                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      4817932                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      4817932                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu0.inst      4817932                       # number of overall misses
+system.cpu0.icache.overall_misses::total      4817932                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  51018469500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  51018469500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  51018469500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  51018469500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  51018469500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  51018469500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    453477294                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    453477294                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    453477294                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    453477294                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    453477294                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    453477294                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010624                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.010624                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010624                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.010624                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010624                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.010624                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10589.287997                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10589.287997                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10589.287997                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10589.287997                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10589.287997                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10589.287997                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -902,239 +904,251 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5032819                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5032819                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5032819                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5032819                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5032819                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5032819                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4817932                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      4817932                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      4817932                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      4817932                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      4817932                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      4817932                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  47804251855                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  47804251855                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  47804251855                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  47804251855                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  47804251855                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  47804251855                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3811870500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3811870500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3811870500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   3811870500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011332                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011332                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011332                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9498.504090                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9498.504090                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9498.504090                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  48609503500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  48609503500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  48609503500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  48609503500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  48609503500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  48609503500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3777715000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   3777715000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010624                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010624                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010624                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10089.287997                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10089.287997                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10089.287997                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7211191                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7211221                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7903007                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7903048                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           35                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       945331                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2374120                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16169.428044                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          10531211                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2389368                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            4.407530                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      5341335500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  8264.618229                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    69.150581                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    77.449352                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3311.410043                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3382.587139                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1064.212699                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.504432                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004221                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004727                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.202112                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206457                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.064954                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.986904                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1373                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13790                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          173                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          780                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          417                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           54                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3709                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6679                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3275                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.083801                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.841675                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       244043620                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      244043620                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       211402                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       128647                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4517111                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data      2702351                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       7559511                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3655914                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3655914                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       175642                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total       175642                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       102383                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       102383                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        30801                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        30801                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       876779                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       876779                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       211402                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       128647                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4517111                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3579130                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8436290                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       211402                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       128647                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4517111                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3579130                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8436290                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10881                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8892                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       515708                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data       950762                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total      1486243                       # number of ReadReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       562136                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::total       562136                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       120119                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       120119                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       164484                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       164484                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       240029                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       240029                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10881                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8892                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       515708                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1190791                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1726272                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10881                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8892                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       515708                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1190791                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1726272                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    393469249                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    355451999                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  15907969852                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  31938942740                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  48595833840                       # number of ReadReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    181717619                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    181717619                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2563026586                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2563026586                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3399427212                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3399427212                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2070498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2070498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12166293140                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  12166293140                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    393469249                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    355451999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  15907969852                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  44105235880                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  60762126980                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    393469249                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    355451999                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15907969852                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  44105235880                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  60762126980                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       222283                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       137539                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5032819                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3653113                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      9045754                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3655914                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3655914                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       737778                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::total       737778                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       222502                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       222502                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195285                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       195285                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1116808                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1116808                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       222283                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       137539                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5032819                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4769921                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10162562                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       222283                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       137539                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5032819                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4769921                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10162562                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.102469                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.260261                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.164303                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.761931                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.761931                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.539856                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.539856                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.842277                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.842277                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1031104                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2447325                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15787.482525                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          17072683                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2462926                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.931870                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     38930323500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7763.481265                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.845053                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    94.926815                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3265.491531                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3523.056672                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1075.681189                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.473845                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003958                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005794                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.199310                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.215030                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.065654                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.963591                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1662                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13857                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          291                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          746                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          625                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           46                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2497                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5813                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5388                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.101440                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005005                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.845764                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       352133802                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      352133802                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       213691                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       129371                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        343062                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3814786                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3814786                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        99833                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        99833                       # number of UpgradeReq hits
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  15931119500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  15931119500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  30566703000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  30566703000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  43739049000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  43739049000                       # number of InvalidateReq miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15931119500                       # number of overall miss cycles
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+system.cpu0.l2cache.Writeback_accesses::writebacks      3814786                       # number of Writeback accesses(hits+misses)
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.214924                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.214924                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102469                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.249646                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.169866                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102469                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.249646                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.169866                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   323.262732                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   323.262732                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       690166                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       690166                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395                       # average overall miss latency
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+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.112485                       # miss rate for ReadCleanReq accesses
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+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.249158                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.768253                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.768253                       # miss rate for InvalidateReq accesses
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21841.197119                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20902.289584                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20902.289584                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 348856.857143                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 348856.857143                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47561.858180                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47561.858180                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29396.083934                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29396.083934                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32451.864246                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32451.864246                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 75291.038726                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 75291.038726                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32968.411153                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35878.808674                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29396.083934                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35585.649239                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 33652.840271                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32968.411153                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35878.808674                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29396.083934                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35585.649239                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 33652.840271                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1143,201 +1157,218 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1321734                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1321734                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          498                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          498                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         6011                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         6011                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6509                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6509                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6509                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6509                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10881                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8892                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       515708                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       950264                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total      1485745                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       659076                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       659076                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       562136                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       562136                       # number of WriteInvalidateReq MSHR misses
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-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       120119                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       164484                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       164484                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
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-system.cpu0.l2cache.ReadExReq_mshr_misses::total       234018                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10881                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8892                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1184282                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10881                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8892                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       515708                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1184282                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      2378839                       # number of overall MSHR misses
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+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        97439                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total        97439                       # number of CleanEvict MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       121358                       # number of UpgradeReq MSHR misses
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+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       580933                       # number of InvalidateReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16584                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        59709                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18033                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18033                       # number of WriteReq MSHR uncacheable
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 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34617                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        77742                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  25676104173                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  38833742573                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  32139076466                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  32139076466                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  24223804784                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  24223804784                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2466827080                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2466827080                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2435399890                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2435399890                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1771498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1771498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9980703954                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9980703954                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12538366148                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  35656808127                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  48814446527                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12538366148                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  35656808127                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  32139076466                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  80953522993                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3468251000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2568327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6036578500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2656940000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2656940000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3468251000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5225267500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8693518500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.260124                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.164248                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        53779                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        96904                       # number of overall MSHR uncacheable misses
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+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    461437500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28787351301                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  28787351301                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2500247000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2500247000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2505266500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2505266500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2087998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2087998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9802286000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9802286000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  12679437500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  12679437500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  24890887500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  24890887500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  40253451000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  40253451000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    243740500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12679437500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  34693173500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  47834048500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12679437500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  34693173500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28787351301                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  76621399801                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4369127500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7823405000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4099961000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4099961000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   8469088500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11923366000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.045422                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.761931                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.761931                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.539856                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.539856                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.842277                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.842277                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.548657                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.548657                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.830485                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.830485                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.209542                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.209542                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248281                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.169225                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248281                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.210464                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.210464                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.112485                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249073                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249073                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.768253                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.768253                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240073                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.172330                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240073                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.234079                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.239394                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28267.428326                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42471.874070                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20602.242951                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20602.242951                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15536.343735                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15536.343735                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 298285.428571                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 298285.428571                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40531.776945                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40531.776945                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23396.083934                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26434.981186                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26434.981186                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69291.038726                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69291.038726                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29315.755207                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27463.968291                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29315.755207                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31668.278488                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161281.930602                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111420.707826                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153619.880850                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153619.880850                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157479.471541                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 123043.073557                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      11389901                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9301467                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38146                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        18033                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3655914                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       950949                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1103178                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       737778                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       440847                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       362789                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       484218                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           43                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1248974                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1125262                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     10151888                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15745151                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       304033                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       517558                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         26718630                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    322272916                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    593126965                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1100312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1778264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         918278457                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    4307980                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     19190741                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.234424                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.423639                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        556196                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      9235290                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        37997                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        26689                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      7191964                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      8875110                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       964168                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       427001                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       350742                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       480184                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1494626                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1158048                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4817932                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5665215                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       862902                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       756174                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14539205                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18068890                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       308145                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       526057                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         33442297                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    308520148                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    566266158                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1093256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1781832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         877661394                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    9623929                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     31244724                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.314212                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.464201                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          14691964     76.56%     76.56% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           4498777     23.44%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          21427251     68.58%     68.58% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           9817473     31.42%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      19190741                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   11979643994                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      31244724                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14779167493                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    187059488                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    183875487                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7611089646                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7270023000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7824710310                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8020770875                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    166780001                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    171488000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    295551751                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    303329497                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1368,68 +1399,74 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   115983                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               115983                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11170                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89969                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       115964                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.064675                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    22.024176                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511       115963    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::7168-7679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       115964                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       101158                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        99918     98.77%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1061      1.05%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           33      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           72      0.07%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           53      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       101158                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   3223072220                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.344065                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.475063                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     2114124352     65.59%     65.59% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1108947868     34.41%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   3223072220                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        89969     88.96%     88.96% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        11170     11.04%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       101139                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       115983                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   102079                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               102079                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8198                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        78187                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       102062                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.078384                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    25.041362                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511       102061    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       102062                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        86402                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20584.963311                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18803.464379                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14594.922091                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        82288     95.24%     95.24% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         3069      3.55%     98.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          485      0.56%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          417      0.48%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839           20      0.02%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           14      0.02%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375           31      0.04%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           11      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           20      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679           27      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        86402                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -6989065760                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.774297                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.418044                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1577450036     22.57%     22.57% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -5411615724     77.43%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -6989065760                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        78188     90.51%     90.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         8198      9.49%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        86386                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       102079                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       115983                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       101139                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       102079                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86386                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       101139                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       217122                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86386                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       188465                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    83993689                       # DTB read hits
-system.cpu1.dtb.read_misses                     86321                       # DTB read misses
-system.cpu1.dtb.write_hits                   76478778                       # DTB write hits
-system.cpu1.dtb.write_misses                    29662                       # DTB write misses
+system.cpu1.dtb.read_hits                    79156855                       # DTB read hits
+system.cpu1.dtb.read_misses                     74074                       # DTB read misses
+system.cpu1.dtb.write_hits                   72945567                       # DTB write hits
+system.cpu1.dtb.write_misses                    28005                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   42752                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   34474                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4958                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4171                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11385                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                84080010                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76508440                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9254                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                79230929                       # DTB read accesses
+system.cpu1.dtb.write_accesses               72973572                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        160472467                       # DTB hits
-system.cpu1.dtb.misses                         115983                       # DTB misses
-system.cpu1.dtb.accesses                    160588450                       # DTB accesses
+system.cpu1.dtb.hits                        152102422                       # DTB hits
+system.cpu1.dtb.misses                         102079                       # DTB misses
+system.cpu1.dtb.accesses                    152204501                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1459,236 +1496,241 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    60651                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                60651                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          616                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54731                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        60651                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          60651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        60651                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        55347                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        53969     97.51%     97.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1178      2.13%     99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           42      0.08%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           68      0.12%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           60      0.11%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           20      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        55347                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   2053569352                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     2053569352    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   2053569352                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        54731     98.89%     98.89% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          616      1.11%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        55347                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    60277                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                60277                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          437                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54558                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        60277                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          60277    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        60277                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        54995                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 23406.355123                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21056.017834                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18686.344458                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        50855     92.47%     92.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         2976      5.41%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          347      0.63%     98.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          645      1.17%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           26      0.05%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           14      0.03%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           61      0.11%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            8      0.01%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           27      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        54995                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1687858036                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1687858036    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1687858036                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        54558     99.21%     99.21% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          437      0.79%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        54995                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60651                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60651                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60277                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60277                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55347                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55347                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       115998                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   446979774                       # ITB inst hits
-system.cpu1.itb.inst_misses                     60651                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54995                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54995                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       115272                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   419908062                       # ITB inst hits
+system.cpu1.itb.inst_misses                     60277                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29800                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   24325                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               447040425                       # ITB inst accesses
-system.cpu1.itb.hits                        446979774                       # DTB hits
-system.cpu1.itb.misses                          60651                       # DTB misses
-system.cpu1.itb.accesses                    447040425                       # DTB accesses
-system.cpu1.numCycles                     95053909934                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               419968339                       # ITB inst accesses
+system.cpu1.itb.hits                        419908062                       # DTB hits
+system.cpu1.itb.misses                          60277                       # DTB misses
+system.cpu1.itb.accesses                    419968339                       # DTB accesses
+system.cpu1.numCycles                     94992773961                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  446673984                       # Number of instructions committed
-system.cpu1.committedOps                    525768473                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            482657433                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                472663                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26533376                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     68272280                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   482657433                       # number of integer instructions
-system.cpu1.num_fp_insts                       472663                       # number of float instructions
-system.cpu1.num_int_register_reads          706740468                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         383340050                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              750974                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             430296                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           118015071                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          117677935                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    160465117                       # number of memory refs
-system.cpu1.num_load_insts                   83993061                       # Number of load instructions
-system.cpu1.num_store_insts                  76472056                       # Number of store instructions
-system.cpu1.num_idle_cycles              93999959015.450027                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1053950918.549978                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011088                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988912                       # Percentage of idle cycles
-system.cpu1.Branches                         99666047                       # Number of branches fetched
+system.cpu1.committedInsts                  419630835                       # Number of instructions committed
+system.cpu1.committedOps                    495261733                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            455389756                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                523939                       # Number of float alu accesses
+system.cpu1.num_func_calls                   25402387                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     63797614                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   455389756                       # number of integer instructions
+system.cpu1.num_fp_insts                       523939                       # number of float instructions
+system.cpu1.num_int_register_reads          660733277                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         360799808                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              826391                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             485612                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           108763380                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          108525865                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    152092816                       # number of memory refs
+system.cpu1.num_load_insts                   79152639                       # Number of load instructions
+system.cpu1.num_store_insts                  72940177                       # Number of store instructions
+system.cpu1.num_idle_cycles              94000482737.518021                       # Number of idle cycles
+system.cpu1.num_busy_cycles              992291223.481979                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010446                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989554                       # Percentage of idle cycles
+system.cpu1.Branches                         93826575                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                364374913     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1108574      0.21%     69.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    57501      0.01%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             68224      0.01%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::MemRead                83993061     15.97%     85.46% # Class of executed instruction
-system.cpu1.op_class::MemWrite               76472056     14.54%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                342323632     69.08%     69.08% # Class of executed instruction
+system.cpu1.op_class::IntMult                  986133      0.20%     69.28% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    54444      0.01%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             82001      0.02%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::MemRead                79152639     15.97%     85.28% # Class of executed instruction
+system.cpu1.op_class::MemWrite               72940177     14.72%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 526074372                       # Class of executed instruction
+system.cpu1.op_class::total                 495539069                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14059                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements          5413042                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          455.092206                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          154856630                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5413554                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.605354                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8382280704500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   455.092206                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.888852                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.888852                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          419                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        326337345                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       326337345                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     78172197                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       78172197                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     72471418                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      72471418                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       183858                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       183858                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       197039                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       197039                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1730902                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1730902                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1704111                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1704111                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    150643615                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       150643615                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    150827473                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      150827473                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3026410                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3026410                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1374450                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1374450                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       681215                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       681215                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       497314                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       497314                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       177400                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       177400                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202765                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       202765                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4400860                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4400860                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5082075                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5082075                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  44105582717                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  44105582717                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  23281173553                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  23281173553                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13579881027                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  13579881027                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2688373759                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2688373759                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4348203540                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4348203540                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1867000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1867000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  67386756270                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  67386756270                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  67386756270                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  67386756270                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     81198607                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     81198607                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     73845868                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     73845868                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       865073                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       865073                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       694353                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       694353                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1908302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1908302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1906876                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1906876                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    155044475                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    155044475                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    155909548                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    155909548                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037272                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.037272                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018612                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018612                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.787465                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.787465                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.716226                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.716226                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092962                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092962                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106334                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106334                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028385                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.028385                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032596                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.032596                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    5086                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements          4879882                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          454.664905                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          147036928                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4880392                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.128098                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8391455352000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   454.664905                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.888017                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.888017                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        309114667                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       309114667                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     73769374                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       73769374                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     69164773                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      69164773                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       181014                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       181014                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       188653                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       188653                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1698614                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1698614                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1666903                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1666903                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    142934147                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       142934147                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    143115161                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      143115161                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2759570                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2759570                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1240940                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1240940                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       581228                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       581228                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       477261                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       477261                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156018                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       156018                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       186042                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       186042                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4000510                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4000510                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      4581738                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      4581738                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  39233003500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  39233003500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  20835462500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  20835462500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14509055000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  14509055000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2381741000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2381741000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3985246000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3985246000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1637000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1637000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  60068466000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  60068466000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  60068466000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  60068466000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     76528944                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     76528944                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     70405713                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     70405713                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       762242                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       762242                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       665914                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       665914                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1854632                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1854632                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1852945                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1852945                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    146934657                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    146934657                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    147696899                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    147696899                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036059                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036059                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017626                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.017626                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.762524                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.762524                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.716701                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.716701                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.084123                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.084123                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100403                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100403                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027226                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027226                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031021                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.031021                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14217.071319                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14217.071319                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16790.064387                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16790.064387                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 30400.671750                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 30400.671750                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.809073                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15265.809073                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21421.216715                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21421.216715                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15015.202062                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15015.202062                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13110.410504                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13110.410504                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1697,158 +1739,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3550271                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3550271                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18006                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        18006                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          425                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          425                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44886                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44886                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        18431                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        18431                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        18431                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        18431                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3008404                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3008404                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1374025                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1374025                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       681215                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       681215                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       497314                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       497314                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       132514                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       132514                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202765                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       202765                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4382429                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4382429                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5063644                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5063644                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21725                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21725                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        20113                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        20113                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        41838                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        41838                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38446720676                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38446720676                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21137642197                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21137642197                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13605784836                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13605784836                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12830642973                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  12830642973                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1690394742                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1690394742                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4033173960                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4033173960                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1807000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1807000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  59584362873                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  59584362873                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  73190147709                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  73190147709                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3727466501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3727466501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3465674500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3465674500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7193141001                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7193141001                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037050                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037050                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018607                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018607                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.787465                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.787465                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.716226                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.716226                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069441                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069441                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106334                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106334                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028266                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028266                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032478                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032478                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3169454                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3169454                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14967                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        14967                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          437                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          437                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44200                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44200                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        15404                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        15404                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        15404                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        15404                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2744603                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2744603                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1240503                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1240503                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       581228                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       581228                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       477261                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       477261                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       111818                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       111818                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       186042                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       186042                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      3985106                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      3985106                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4566334                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4566334                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        11055                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        11055                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11308                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11308                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        22363                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        22363                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35762824500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35762824500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  19580379500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  19580379500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11426394500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11426394500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14031794000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14031794000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3799241000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3799241000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1600000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1600000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  55343204000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  55343204000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  66769598500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  66769598500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1911574500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1911574500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2027224500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2027224500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3938799000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3938799000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035864                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035864                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017619                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017619                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762524                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.762524                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.716701                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.716701                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060291                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060291                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100403                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100403                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027122                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027122                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030917                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.030917                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13030.235885                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13030.235885                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15784.225834                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15784.225834                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19659.057203                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19659.057203                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 29400.671750                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 29400.671750                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13603.426997                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13603.426997                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20421.415594                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20421.415594                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13887.511148                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13887.511148                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14622.145139                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14622.145139                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172914.925373                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172914.925373                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179273.478953                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179273.478953                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176130.170371                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 176130.170371                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          4892397                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.394395                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          442086860                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4892909                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            90.352561                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8382252985250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.394395                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969520                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969520                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5061942                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.285809                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          414845603                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5062454                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            81.945555                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8391427807000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.285809                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969308                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969308                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        898852462                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       898852462                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    442086860                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      442086860                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    442086860                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       442086860                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    442086860                       # number of overall hits
-system.cpu1.icache.overall_hits::total      442086860                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4892914                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4892914                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4892914                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4892914                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4892914                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4892914                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51771462698                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  51771462698                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  51771462698                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  51771462698                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  51771462698                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  51771462698                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    446979774                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    446979774                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    446979774                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    446979774                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    446979774                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    446979774                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.010947                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.010947                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.010947                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.010947                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.010947                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.010947                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10580.905918                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10580.905918                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        844878583                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       844878583                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    414845603                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      414845603                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    414845603                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       414845603                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    414845603                       # number of overall hits
+system.cpu1.icache.overall_hits::total      414845603                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5062459                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5062459                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5062459                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5062459                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5062459                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5062459                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51775886000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  51775886000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  51775886000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  51775886000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  51775886000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  51775886000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    419908062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    419908062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    419908062                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    419908062                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    419908062                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    419908062                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.012056                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.012056                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.012056                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.012056                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.012056                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.012056                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10227.418336                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10227.418336                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10227.418336                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10227.418336                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10227.418336                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10227.418336                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1857,243 +1898,256 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4892914                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      4892914                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      4892914                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      4892914                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      4892914                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      4892914                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5062459                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5062459                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5062459                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5062459                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5062459                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5062459                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  46862593334                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  46862593334                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  46862593334                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  46862593334                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  46862593334                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  46862593334                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10105750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10105750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10105750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10105750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.010947                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.010947                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.010947                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9577.645005                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9577.645005                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9577.645005                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  49244656500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  49244656500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  49244656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  49244656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  49244656500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  49244656500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9661500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9661500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9661500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9661500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.012056                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.012056                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.012056                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9727.418336                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9727.418336                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9727.418336                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 87831.818182                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 87831.818182                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7631682                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7631760                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           35                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6553328                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6553344                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       935080                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2142260                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13497.078408                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          10799538                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2158371                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.003560                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9893608612000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5297.531895                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    78.016993                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.104378                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3470.735386                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3768.987855                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   794.701900                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.323336                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004762                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005316                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.211837                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.230041                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048505                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.823796                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1633                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           75                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14403                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           31                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          128                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          713                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          761                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1571                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5509                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6302                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.099670                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004578                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.879089                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       240281832                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      240281832                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       248777                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141659                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4360207                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2869888                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       7620531                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3550270                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3550270                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       228063                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       228063                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        73786                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        73786                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35221                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        35221                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       953536                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       953536                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       248777                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141659                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4360207                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3823424                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8574067                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       248777                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141659                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4360207                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3823424                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8574067                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9961                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7958                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       532707                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data       952245                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1502871                       # number of ReadReq misses
+system.cpu1.l2cache.prefetcher.pfSpanPage       818232                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         1797985                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13499.130791                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17098114                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1814056                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            9.425351                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10027287971500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5261.606925                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    74.626364                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    80.602782                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3547.198081                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3740.075738                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   795.020901                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.321143                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004555                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004920                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.216504                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.228276                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048524                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.823922                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1537                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14473                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          338                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          563                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           23                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           24                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          884                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4486                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5048                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3979                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.093811                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.883362                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       335653129                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      335653129                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       217635                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       143511                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        361146                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3169452                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3169452                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        61375                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        61375                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        29429                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        29429                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       854276                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       854276                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4594945                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4594945                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2597133                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2597133                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       245829                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       245829                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       217635                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       143511                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4594945                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3451409                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8407500                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       217635                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       143511                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4594945                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3451409                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8407500                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9790                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8267                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        18057                       # number of ReadReq misses
 system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
 system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       267701                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       267701                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       120750                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       120750                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       167539                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       167539                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       120456                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       120456                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       156608                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       156608                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       227703                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       227703                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9961                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7958                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       532707                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1179948                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1730574                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9961                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7958                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       532707                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1179948                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1730574                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    394640977                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    358915726                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  16056528318                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  31264991014                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  48075076035                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    240883663                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    240883663                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2642176746                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2642176746                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3519293594                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3519293594                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1767000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1767000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9869071556                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   9869071556                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    394640977                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    358915726                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16056528318                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  41134062570                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  57944147591                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    394640977                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    358915726                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16056528318                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  41134062570                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  57944147591                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       258738                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149617                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4892914                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.Writeback_accesses::total      3550271                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       495764                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       495764                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       194536                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       194536                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       202760                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       202760                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2589720500                       # number of UpgradeReq miss cycles
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+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11700893500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  11700893500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    350581000                       # number of demand (read+write) miss cycles
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 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1181239                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1181239                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       258738                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149617                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       258738                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149617                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.data      5003372                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.108873                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.249140                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::total     0.047618                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
 system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.539977                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.539977                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.620708                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.620708                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.826292                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.826292                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.662461                       # miss rate for UpgradeReq accesses
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+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.841811                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.192766                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.192766                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.108873                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.235831                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.167941                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.108873                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.235831                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.167941                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   899.823546                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   899.823546                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       353400                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       353400                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670                       # average overall miss latency
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+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.092349                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.092349                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.244503                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.244503                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.483338                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.483338                       # miss rate for InvalidateReq accesses
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+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21499.306801                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20746.357147                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20746.357147                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 308799.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 308799.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41524.236940                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41524.236940                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 30469.401986                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 30469.401986                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31731.645204                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31731.645204                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 50879.422802                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 50879.422802                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35810.112360                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39034.655861                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30469.401986                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33660.088551                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32729.262145                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35810.112360                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39034.655861                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30469.401986                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33660.088551                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32729.262145                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2102,214 +2156,229 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1053113                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1053113                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          432                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          432                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            1                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            1                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7197                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         7197                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7629                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         7629                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7629                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         7629                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9961                       # number of ReadReq MSHR misses
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 system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
 system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       707306                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       707306                       # number of HardPFReq MSHR misses
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-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       267700                       # number of WriteInvalidateReq MSHR misses
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       120750                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       167539                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       167539                       # number of SCUpgradeReq MSHR misses
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 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21725                       # number of ReadReq MSHR uncacheable
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-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        20113                       # number of WriteReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        41838                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        41948                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  35407537019                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   9092223824                       # number of WriteInvalidateReq MSHR miss cycles
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-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2448079564                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2512705540                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1507000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1507000                       # number of SCUpgradeFailReq MSHR miss cycles
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-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  32581050384                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total  81202167382                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3553660750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3562902000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3314826000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3314826000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9241250                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   6868486750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6877728000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.249027                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.164680                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        22363                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        22473                       # number of overall MSHR uncacheable misses
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+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27533861444                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2500623000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2500623000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2389472000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2389472000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1321999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1321999                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6820721500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  11439788000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  11439788000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  21593362000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  21593362000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  10321018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  10321018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    291841000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu1.l2cache.demand_mshr_miss_latency::total  40418810000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8836500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1823134500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1831971000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1942414500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1942414500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8836500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3765549000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3774385500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.047618                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.539975                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.539975                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.620708                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.620708                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.826292                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.826292                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.662461                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.662461                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.841811                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.841811                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.186673                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.186673                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234306                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.167201                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234306                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.189475                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.189475                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092349                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.244402                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.244402                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.483333                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.483333                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.231453                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153592                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.231453                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.235840                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       301400                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       301400                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.214361                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31286.398627                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45583.901097                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.638374                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.638374                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15257.662444                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15257.662444                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 264399.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 264399.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33947.956121                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33947.956121                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24469.401986                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25701.243085                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25701.243085                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 44879.650043                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 44879.650043                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27292.760437                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.388038                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27292.760437                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31892.451076                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164914.925373                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164081.594268                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171773.478953                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171773.478953                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 168382.998703                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167952.009078                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      11407818                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9339972                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38146                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        20113                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3550271                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1013669                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1157980                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       495764                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       395206                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       367201                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       457834                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1341582                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1187599                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9786048                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15579584                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       330806                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       594855                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         26291293                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    313146936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    585201818                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1196936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2069904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         901615594                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    4634762                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     19271924                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.253755                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.435159                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        559173                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9082723                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        37997                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11308                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      6546630                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      9047745                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       872762                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           38                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       399618                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       347237                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       434764                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1786739                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1070352                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5062459                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5562594                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       582530                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       475802                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15186455                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15778247                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332058                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       524938                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         31821698                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    323997816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    497415771                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1214224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1819400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         824447211                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   10229580                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     30806602                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.338828                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.473311                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          14381570     74.62%     74.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           4890354     25.38%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          20368466     66.12%     66.12% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          10438136     33.88%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      19271924                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   11505600998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      30806602                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   13598256460                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    168563993                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    189037985                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7347478432                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7593798500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8042476622                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7185863072                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    181503274                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    180280000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    336447522                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    297513000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40366                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40366                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136641                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29913                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40323                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40323                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136623                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136623                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47688                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2324,13 +2393,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122716                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231218                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231218                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122622                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231190                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354014                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353892                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47708                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2345,13 +2414,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155823                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155729                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338776                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496797                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36274000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496591                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36209000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2379,781 +2448,754 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607607215                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569692377                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92806000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92730000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148515621                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147886000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              170500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115613                       # number of replacements
-system.iocache.tags.tagsinuse               11.298152                       # Cycle average of tags in use
+system.iocache.tags.replacements               115590                       # number of replacements
+system.iocache.tags.tagsinuse               11.304878                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115629                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115606                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9179138787000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.392909                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.905243                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.462057                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.244078                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706135                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9148728954000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.397645                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.907233                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.462353                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.244202                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706555                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040838                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040838                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040712                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040712                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8881                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8918                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8867                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8904                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8881                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8921                       # number of demand (read+write) misses
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+system.iocache.demand_misses::total              8907                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8881                       # number of overall misses
-system.iocache.overall_misses::total             8921                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5195500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1629816861                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1635012361                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8867                       # number of overall misses
+system.iocache.overall_misses::total             8907                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1652925028                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1658120028                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19901379733                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19901379733                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5564500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1629816861                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1635381361                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5564500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1629816861                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1635381361                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12636024349                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12636024349                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1652925028                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1658489028                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1652925028                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1658489028                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8881                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8918                       # number of ReadReq accesses(hits+misses)
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+system.iocache.ReadReq_accesses::total           8904                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8881                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8921                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8881                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8921                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8867                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8907                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183338.457165                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186413.107928                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 186221.925876                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183517.268438                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183318.166237                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183517.268438                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183318.166237                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        110961                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118394.651347                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118394.651347                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186413.107928                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 186200.631863                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 186413.107928                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 186200.631863                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32852                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16203                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3487                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.848176                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.421279                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106702                       # number of writebacks
-system.iocache.writebacks::total               106702                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8881                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8918                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8867                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8904                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8881                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8921                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8867                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8907                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8881                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8921                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3270500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1166890035                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1170160535                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14351455801                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14351455801                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3483500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1166890035                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1170373535                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3483500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1166890035                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1170373535                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8867                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8907                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1209575028                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1212920028                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7299624349                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7299624349                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1209575028                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1213139028                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1209575028                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1213139028                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131193.087658                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131193.087658                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136413.107928                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 136221.925876                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68394.651347                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68394.651347                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136413.107928                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 136200.631863                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136413.107928                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 136200.631863                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1448041                       # number of replacements
-system.l2c.tags.tagsinuse                64131.287175                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4245095                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1507106                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.816720                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              11172879000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   19347.050639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   116.894544                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   154.865125                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3200.431152                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7856.746302                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9704.320174                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   227.109782                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   297.906768                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3324.337079                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8639.334854                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.295213                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001784                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002363                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.048835                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.119884                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.148076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003465                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004546                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.050725                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.131826                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.171849                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.978566                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10716                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          318                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48031                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           38                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          439                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10237                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          318                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1326                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4887                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41702                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.163513                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004852                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.732895                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 58352089                       # Number of tag accesses
-system.l2c.tags.data_accesses                58352089                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         5485                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4305                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             465111                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             536784                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       265347                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5257                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         3875                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             485070                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             556488                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       285641                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2613363                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2374848                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2374848                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       123464                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       121626                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       245090                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           24332                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           31013                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               55345                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          5518                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          6203                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             11721                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            54595                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            49708                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               104303                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5485                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4305                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              465111                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              591379                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       265347                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5257                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3875                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              485070                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              606196                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       285641                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2717666                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5485                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4305                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             465111                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             591379                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       265347                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5257                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3875                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             485070                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             606196                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       285641                       # number of overall hits
-system.l2c.overall_hits::total                2717666                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1889                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1930                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            50597                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           131294                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       216525                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2185                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2247                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            47637                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           122248                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       240093                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               816645                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       431801                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       136823                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       568624                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         44180                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         43907                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             88087                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9646                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11002                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           20648                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          78703                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          53921                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             132624                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1889                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1930                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             50597                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            209997                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       216525                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2185                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2247                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             47637                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            176169                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       240093                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                949269                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1889                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1930                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            50597                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           209997                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       216525                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2185                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2247                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            47637                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           176169                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       240093                       # number of overall misses
-system.l2c.overall_misses::total               949269                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    170785750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    176668500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   4301026862                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  11907133634                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    192678771                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    202084771                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   4020493910                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  11059922872                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    90717840977                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     51822854                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     41218687                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total     93041541                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    233428095                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    271641854                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    505069949                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     51474876                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     56093222                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    107568098                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6900295884                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4492674608                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11392970492                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    170785750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    176668500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   4301026862                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  18807429518                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    192678771                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    202084771                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4020493910                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  15552597480                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    102110811469                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    170785750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    176668500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   4301026862                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  18807429518                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    192678771                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    202084771                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4020493910                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  15552597480                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   102110811469                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         7374                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6235                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         515708                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         668078                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       481872                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         7442                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6122                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         532707                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         678736                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       525734                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            3430008                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2374848                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2374848                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       555265                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       258449                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       813714                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        68512                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        74920                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          143432                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15164                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        17205                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         32369                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       133298                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       103629                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           236927                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         7374                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6235                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          515708                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          801376                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       481872                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         7442                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6122                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          532707                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          782365                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       525734                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3666935                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         7374                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6235                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         515708                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         801376                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       481872                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         7442                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6122                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         532707                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         782365                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       525734                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3666935                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.098112                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.196525                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.089424                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.180111                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.238088                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.777649                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.529400                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.698801                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.644851                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.586052                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.614138                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.636112                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.639465                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.637894                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.590429                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.520327                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.559767                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.098112                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.262046                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.089424                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.225175                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.258873                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.098112                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.262046                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.089424                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.225175                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.258873                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 111086.017764                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   120.015595                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   301.255542                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   163.625772                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5283.569375                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6186.755050                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5733.762632                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5336.396019                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5098.456826                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5209.613425                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85904.289510                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 107567.835323                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 107567.835323                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               328                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1309168                       # number of replacements
+system.l2c.tags.tagsinuse                63754.864014                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4916621                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1368931                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.591577                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   19091.859701                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   105.912894                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   155.127533                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3615.637235                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7840.243629                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  8325.501182                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   220.931545                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   308.618632                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3602.401841                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8895.404165                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11593.225658                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.291319                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001616                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002367                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.055170                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.119633                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.127037                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003371                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004709                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.054968                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.135733                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.176899                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.972822                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        11100                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        48385                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          212                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          379                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        10509                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1364                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4701                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        42219                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.169373                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.738297                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 62372649                       # Number of tag accesses
+system.l2c.tags.data_accesses                62372649                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2239360                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2239360                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           30980                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           24512                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               55492                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6081                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          5027                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11108                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           167543                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           144880                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               312423                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5175                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4181                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       498211                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       558223                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       295485                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         4952                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4009                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       423075                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       457635                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       236791                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2487737                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5175                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4181                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              498211                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              725766                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       295485                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          4952                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4009                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              423075                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              602515                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       236791                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2800160                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5175                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4181                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             498211                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             725766                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       295485                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         4952                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4009                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             423075                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             602515                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       236791                       # number of overall hits
+system.l2c.overall_hits::total                2800160                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         43560                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         41893                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             85453                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        11005                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         9001                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           20006                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::cpu1.data         139826                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             630940                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1207                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total         709650                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1207                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total               1340590                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1207                       # number of overall misses
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+system.l2c.overall_misses::total              1340590                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    242100000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    225831000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    467931000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     53618000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     45210000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     98828000                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadExReq_miss_latency::cpu1.data  11309941500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  52345129000                       # number of ReadExReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    150819000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.data   8959752500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  23335976587                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  74608061217                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    108698500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.dtb.walker    150819000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    156924500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.data  20269694000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::total    126953190217                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    108698500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu1.dtb.walker    150819000                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total   126953190217                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2239360                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2239360                       # number of Writeback accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        66405                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          140945                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        17086                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::total         31114                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.overall_accesses::total            4140750                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.584384                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.630871                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.606286                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.644095                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.641645                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.642990                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.745629                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.491124                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.668820                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.080702                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.175877                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.095054                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181674                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.221947                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu0.data       0.456766                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.095054                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.286068                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.323755                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.080702                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.456766                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.095054                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.286068                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.323755                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5557.851240                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5390.661924                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5475.887330                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4872.149023                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5022.775247                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4939.918025                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83555.320150                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80885.825955                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 82963.719213                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83529.255076                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88960.337779                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87889.860140                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83789.205428                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88188.276344                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 105133.602786                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 84610.478578                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83789.205428                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83958.902180                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 94699.490685                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 83529.255076                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 84610.478578                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87889.860140                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83789.205428                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83958.902180                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 94699.490685                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                67                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     23.428571                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs            67                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1121159                       # number of writebacks
-system.l2c.writebacks::total                  1121159                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst           120                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            25                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst           120                       # number of ReadReq MSHR hits
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-system.l2c.ReadReq_mshr_miss_rate::total     0.238002                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.777649                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.529400                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.698801                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.644851                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.586052                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.614138                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.636112                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.639465                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.637894                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.590429                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.520327                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.559767                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.256170                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.309543                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097879                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.262014                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.293469                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.367037                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.089199                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.225137                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.258792                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.256170                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.309543                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097879                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.262014                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.293469                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.367037                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.089199                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.225137                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.258792                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 95159.564794                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 95159.564794                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378                       # average overall mshr uncacheable latency
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        22361                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       119375                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    904276500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    870415500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1774692000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    228388000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    186718499                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    415106499                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   9911681500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  46035729000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3207900500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9405362000                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    133659000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    139154500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3272125000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   7942788500                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::total  67494346717                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   3207900500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  45529409500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.inst   3272125000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  17854470000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  21373896587                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 113530075717                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   3207900500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  45529409500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21824562130                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    133659000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    139154500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3272125000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  17854470000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  21373896587                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 113530075717                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3881489500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6856500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1624141500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8190514500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3646235000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1750167000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5396402000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   7527724500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6856500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3374308500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13586916500                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.584384                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.630871                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.606286                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.644095                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.641645                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.642990                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.745629                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.491124                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.668820                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.175852                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.257349                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.181642                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.221863                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.456754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.257349                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.286047                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.323690                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.456754                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.286047                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total     0.323690                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.331956                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20777.110734                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20768.047933                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20753.112222                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20744.194978                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20749.100220                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73555.320150                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70885.825955                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72963.719213                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78961.012140                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78192.444379                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95145.410882                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74610.489030                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73960.340671                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 84703.646154                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74610.489030                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73960.340671                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 84703.646154                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143281.266150                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146941.237673                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100647.773354                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136619.393758                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154772.461974                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142021.791194                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139975.166887                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150901.502616                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 113817.101571                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              906809                       # Transaction distribution
-system.membus.trans_dist::ReadResp             906809                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38146                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38146                       # Transaction distribution
-system.membus.trans_dist::Writeback           1227861                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       672387                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       672387                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           370275                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         320224                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          115346                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           24                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145002                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           128981                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122716                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               81378                       # Transaction distribution
+system.membus.trans_dist::ReadResp             799663                       # Transaction distribution
+system.membus.trans_dist::WriteReq              37997                       # Transaction distribution
+system.membus.trans_dist::WriteResp             37997                       # Transaction distribution
+system.membus.trans_dist::Writeback           1137767                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           200903                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           374437                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         306668                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          111797                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            646745                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           624605                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        718285                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122622                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24970                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5055890                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5203668                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335590                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335590                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5539258                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155823                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24438                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4799197                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4946349                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342551                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342551                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5288900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155729                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49940                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    168605292                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    168811259                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14076224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14076224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               182887483                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           594337                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3681134                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48876                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    151511532                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    151716341                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7266432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               158982773                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           594252                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3613210                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3681134    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3613210    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3681134                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           100790999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3613210                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101221000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21573500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21240500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         11112792344                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7773596350                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5991933811                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7468178118                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151912879                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229090524                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3197,45 +3239,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            4327568                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4320333                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38146                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38146                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2374848                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       920665                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       813714                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          419012                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        331945                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         750957                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           86                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           292509                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          292509                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7096014                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6270717                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              13366731                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    236480377                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    202778754                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              439259131                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1555479                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          8704899                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.013311                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.114603                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              81380                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4075375                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             37997                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            37997                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3377178                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1228761                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          423594                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        317776                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         741370                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           96                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1071890                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1071890                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4001246                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7774731                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5765311                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              13540042                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    240674354                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    168156931                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              408831285                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3034988                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         11680683                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.131880                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.338360                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                8589027     98.67%     98.67% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115872      1.33%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10140239     86.81%     86.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1540444     13.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8704899                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         7795939791                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           11680683                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         7606203373                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2526000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2481000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3978610795                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4538781481                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3846379763                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3532073491                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 7790849b2..61b2291b6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.824462                       # Number of seconds simulated
-sim_ticks                                51824462100500                       # Number of ticks simulated
-final_tick                               51824462100500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.832459                       # Number of seconds simulated
+sim_ticks                                51832458543500                       # Number of ticks simulated
+final_tick                               51832458543500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 684695                       # Simulator instruction rate (inst/s)
-host_op_rate                                   804548                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            39714246392                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 713112                       # Number of bytes of host memory used
-host_seconds                                  1304.93                       # Real time elapsed on the host
-sim_insts                                   893481288                       # Number of instructions simulated
-sim_ops                                    1049881338                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 757890                       # Simulator instruction rate (inst/s)
+host_op_rate                                   890582                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            44493723118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 717728                       # Number of bytes of host memory used
+host_seconds                                  1164.94                       # Real time elapsed on the host
+sim_insts                                   882895003                       # Number of instructions simulated
+sim_ops                                    1037473525                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       266048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       259456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5261620                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          50351624                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        398272                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             56537020                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5261620                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5261620                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     77705792                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       255168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       250176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5270964                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          81048392                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        390144                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             87214844                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5270964                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5270964                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     75813760                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          77726372                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         4157                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         4054                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             122620                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             786757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6223                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                923811                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1214153                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          75834340                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3987                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3909                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             122766                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1266394                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6096                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1403152                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1184590                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1216726                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           5134                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           5006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               101528                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               971580                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1090933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          101528                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             101528                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1499404                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1187163                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4827                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               101692                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1563661                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7527                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1682630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          101692                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             101692                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1462670                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1499801                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1499404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          5134                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          5006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              101528                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              971977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2590734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        923811                       # Number of read requests accepted
-system.physmem.writeReqs                      1833124                       # Number of write requests accepted
-system.physmem.readBursts                      923811                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1833124                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59092736                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     31168                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 114062016                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  56537020                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              117175844                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      487                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   50880                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          36215                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               57129                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               60965                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               52485                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               50413                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               54002                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59718                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               51713                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               51669                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               50247                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              101235                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              59848                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              58323                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              55369                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              55988                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              51743                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              52477                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              110630                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              112240                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              108805                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              108103                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              111102                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              113339                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              105567                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              107723                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              108849                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              115780                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             115663                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             113049                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             112494                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             116984                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             111502                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             110389                       # Per bank write bursts
+system.physmem.bw_write::total                1463067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1462670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4827                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              101692                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1564058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7527                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3145697                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1403152                       # Number of read requests accepted
+system.physmem.writeReqs                      1187163                       # Number of write requests accepted
+system.physmem.readBursts                     1403152                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1187163                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 89743360                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     58368                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  75832768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  87214844                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               75834340                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      912                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2250                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         142509                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               84707                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               87220                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               81347                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               82774                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               86841                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               98270                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               81495                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               83122                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               79285                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129613                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              85444                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              88159                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              83519                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              84779                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              82284                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              83381                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               72521                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               74576                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               72526                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               74694                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               74615                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               83452                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               71356                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               73404                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               69434                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               76014                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              73389                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              75855                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72723                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              74909                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              71861                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              73558                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         145                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51824459475500                       # Total gap between requests
+system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51832455911500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  880695                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1360036                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1830551                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    889155                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28186                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       462                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       528                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       746                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       480                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1765                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      152                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1184590                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1369724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     26989                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       311                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       443                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       479                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       493                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      363                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      161                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      142                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       91                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       47                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -159,165 +159,162 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    57524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    60978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    91825                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   117209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   106855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    97040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    98714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    93369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    94185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    92986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    93402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    98737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    96397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    94916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   105152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    97025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    94048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    92817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5441                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     5084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     5738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     7709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     7730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     6924                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     6738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     7452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     5737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     5138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     4676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     5004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3903                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      510                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      329                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       603787                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      286.780656                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.845955                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.273004                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         251324     41.62%     41.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       149673     24.79%     66.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        51779      8.58%     74.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        28017      4.64%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19714      3.27%     82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13055      2.16%     85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9885      1.64%     86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8959      1.48%     88.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        71381     11.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         603787                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         89136                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        10.358104                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      107.922360                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          89134    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           89136                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         89136                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.994379                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.728374                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.051434                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31           87330     97.97%     97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47             694      0.78%     98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              23      0.03%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              47      0.05%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             149      0.17%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            187      0.21%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           322      0.36%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           118      0.13%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            42      0.05%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            12      0.01%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            62      0.07%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            32      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            11      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             9      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             3      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             6      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            10      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             8      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            26      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           89136                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    12043609520                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29355934520                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4616620000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13043.75                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    15525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    18184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    68862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    70049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    70008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    69966                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    69777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    72690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    73075                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    75585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    74412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    74484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    71661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    71703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    72226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    69733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    69498                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    68867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      431                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       564142                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      293.500232                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     169.709934                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.462784                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         227896     40.40%     40.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       137874     24.44%     64.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        50148      8.89%     73.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27962      4.96%     78.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20021      3.55%     82.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        14110      2.50%     84.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        11549      2.05%     86.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        10920      1.94%     88.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        63662     11.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         564142                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         68197                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.561359                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      299.455370                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          68195    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           68197                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         68197                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.374474                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.924162                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.358180                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           65696     96.33%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             133      0.20%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             441      0.65%     97.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             195      0.29%     97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             359      0.53%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             498      0.73%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             123      0.18%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              30      0.04%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              34      0.05%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              28      0.04%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              38      0.06%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              22      0.03%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             434      0.64%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              35      0.05%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              41      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.04%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            26      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           68197                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    16916842552                       # Total ticks spent queuing
+system.physmem.totMemAccLat               43208842552                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7011200000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12064.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31793.75                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.14                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.20                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.09                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30814.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.73                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     694872                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1406883                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.26                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18797853.22                       # Average gap between requests
-system.physmem.pageHitRate                      77.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2251693080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1228602375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3417133200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5686258320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384921452640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1307306510865                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29947912845000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34652724495480                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.655841                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49820369752426                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730532440000                       # Time in different power states
+system.physmem.avgWrQLen                        22.64                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1132918                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    890066                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20010097.58                       # Average gap between requests
+system.physmem.pageHitRate                      78.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2149066080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1172605500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5349013800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3869493120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3385443743760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1308122393760                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29951995045500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34658101361520                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.656420                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49827055945457                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730799460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    273552725074                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    274602731543                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2312936640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1262019000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3784755000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5862520800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384921452640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1309001038785                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29946426417000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34653571139865                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.672178                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49817859630672                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730532440000                       # Time in different power states
+system.physmem_1.actEnergy                 2115847440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1154480250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5588419200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3808574640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3385443743760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1306419956235                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29953488411750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34658019433275                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.654839                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49829529145116                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730799460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    276069619328                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    272122791134                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -371,68 +368,76 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    211321                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                211321                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15784                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       163511                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       211307                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean     0.170368                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev    58.877055                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047       211305    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                    207675                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                207675                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15981                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       160171                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       207653                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean     0.182998                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev    62.840123                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047       207651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       211307                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       179309                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       177365     98.92%     98.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         1663      0.93%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          114      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           88      0.05%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           58      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           14      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       179309                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples   -200578036                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean    -2.729096                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0      -747974796    372.91%    372.91% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1       547396760   -272.91%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total   -200578036                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        163512     91.20%     91.20% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15784      8.80%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       179296                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       211321                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       207653                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       176174                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767       111064     63.04%     63.04% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535        63199     35.87%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303          999      0.57%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-131071          662      0.38%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839           15      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::163840-196607           88      0.05%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-229375           11      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::229376-262143           50      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911           52      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::294912-327679           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-360447            8      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::360448-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       176174                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   -781821628                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.029012                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.167839                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      -759139796     97.10%     97.10% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1       -22681832      2.90%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   -781821628                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        160172     90.93%     90.93% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         15981      9.07%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       176153                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       207675                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       211321                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       179296                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       207675                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       176153                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       179296                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       390617                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       176153                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       383828                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    167775531                       # DTB read hits
-system.cpu.dtb.read_misses                     155743                       # DTB read misses
-system.cpu.dtb.write_hits                   152648275                       # DTB write hits
-system.cpu.dtb.write_misses                     55578                       # DTB write misses
+system.cpu.dtb.read_hits                    165829611                       # DTB read hits
+system.cpu.dtb.read_misses                     153241                       # DTB read misses
+system.cpu.dtb.write_hits                   150793131                       # DTB write hits
+system.cpu.dtb.write_misses                     54434                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               42687                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1063                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    75520                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid               42000                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1055                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    75015                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   8371                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   8164                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     19881                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                167931274                       # DTB read accesses
-system.cpu.dtb.write_accesses               152703853                       # DTB write accesses
+system.cpu.dtb.perms_faults                     19719                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                165982852                       # DTB read accesses
+system.cpu.dtb.write_accesses               150847565                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         320423806                       # DTB hits
-system.cpu.dtb.misses                          211321                       # DTB misses
-system.cpu.dtb.accesses                     320635127                       # DTB accesses
+system.cpu.dtb.hits                         316622742                       # DTB hits
+system.cpu.dtb.misses                          207675                       # DTB misses
+system.cpu.dtb.accesses                     316830417                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -462,97 +467,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    122916                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                122916                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1122                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       110644                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       122916                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          122916    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       122916                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       111766                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 26583.507059                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-32767        56090     50.19%     50.19% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-65535        53429     47.80%     97.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-98303          753      0.67%     98.66% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-131071         1184      1.06%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-163839           19      0.02%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::163840-196607          105      0.09%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-229375           43      0.04%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::229376-262143           54      0.05%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-294911           30      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::294912-327679           11      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-360447           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::360448-393215           11      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-425983            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::425984-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-491519            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::491520-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       111766                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples   -853761296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      -853761296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total   -853761296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        110644     99.00%     99.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1122      1.00%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       111766                       # Table walker page sizes translated
+system.cpu.itb.walker.walks                    122431                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                122431                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1128                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       110257                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       122431                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          122431    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       122431                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       111385                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28118.386677                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       109197     98.04%     98.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         1895      1.70%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          129      0.12%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           78      0.07%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           51      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       111385                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   -887504296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      -887504296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   -887504296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        110257     98.99%     98.99% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1128      1.01%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       111385                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122916                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       122916                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122431                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       122431                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111766                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       111766                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       234682                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    894030670                       # ITB inst hits
-system.cpu.itb.inst_misses                     122916                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111385                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       111385                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       233816                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    883439249                       # ITB inst hits
+system.cpu.itb.inst_misses                     122431                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               42687                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1063                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53866                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               42000                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1055                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53485                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                894153586                       # ITB inst accesses
-system.cpu.itb.hits                         894030670                       # DTB hits
-system.cpu.itb.misses                          122916                       # DTB misses
-system.cpu.itb.accesses                     894153586                       # DTB accesses
-system.cpu.numCycles                     103648924201                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                883561680                       # ITB inst accesses
+system.cpu.itb.hits                         883439249                       # DTB hits
+system.cpu.itb.misses                          122431                       # DTB misses
+system.cpu.itb.accesses                     883561680                       # DTB accesses
+system.cpu.numCycles                     103664917087                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   893481288                       # Number of instructions committed
-system.cpu.committedOps                    1049881338                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             963989017                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 895873                       # Number of float alu accesses
-system.cpu.num_func_calls                    52999943                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    136446519                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    963989017                       # number of integer instructions
-system.cpu.num_fp_insts                        895873                       # number of float instructions
-system.cpu.num_int_register_reads          1405913792                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          764688301                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1443674                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              760516                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            234750393                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           234155899                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     320407593                       # number of memory refs
-system.cpu.num_load_insts                   167768846                       # Number of load instructions
-system.cpu.num_store_insts                  152638747                       # Number of store instructions
-system.cpu.num_idle_cycles               100474792122.552063                       # Number of idle cycles
-system.cpu.num_busy_cycles               3174132078.447939                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.030624                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.969376                       # Percentage of idle cycles
-system.cpu.Branches                         199584978                       # Number of branches fetched
+system.cpu.committedInsts                   882895003                       # Number of instructions committed
+system.cpu.committedOps                    1037473525                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             952709754                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 896425                       # Number of float alu accesses
+system.cpu.num_func_calls                    52419949                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    134729686                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    952709754                       # number of integer instructions
+system.cpu.num_fp_insts                        896425                       # number of float instructions
+system.cpu.num_int_register_reads          1388360502                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          755717952                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1444442                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              761348                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            231664947                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           231068644                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     316605789                       # number of memory refs
+system.cpu.num_load_insts                   165822487                       # Number of load instructions
+system.cpu.num_store_insts                  150783302                       # Number of store instructions
+system.cpu.num_idle_cycles               100487560505.254059                       # Number of idle cycles
+system.cpu.num_busy_cycles               3177356581.745939                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.030650                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.969350                       # Percentage of idle cycles
+system.cpu.Branches                         197184546                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 727639004     69.27%     69.27% # Class of executed instruction
-system.cpu.op_class::IntMult                  2217476      0.21%     69.48% # Class of executed instruction
-system.cpu.op_class::IntDiv                     99175      0.01%     69.49% # Class of executed instruction
+system.cpu.op_class::IntAlu                 719043510     69.27%     69.27% # Class of executed instruction
+system.cpu.op_class::IntMult                  2202813      0.21%     69.48% # Class of executed instruction
+system.cpu.op_class::IntDiv                     97927      0.01%     69.49% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     69.49% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     69.49% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     69.49% # Class of executed instruction
@@ -575,126 +574,126 @@ system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Cl
 system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.49% # Class of executed instruction
 system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.49% # Class of executed instruction
 system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             110553      0.01%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             110813      0.01%     69.50% # Class of executed instruction
 system.cpu.op_class::SimdFloatMult                  0      0.00%     69.50% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.50% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::MemRead                167768846     15.97%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               152638747     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                165822487     15.97%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               150783302     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1050473844                       # Class of executed instruction
+system.cpu.op_class::total                 1038060895                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16327                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements          10213653                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.965664                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           310015199                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10214165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             30.351497                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3500615250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.965664                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999933                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16280                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements          10067650                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.966034                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           306351638                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10068162                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.427762                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3466781500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.966034                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999934                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999934                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1291569953                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1291569953                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    156758765                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       156758765                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    144836105                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      144836105                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       393576                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        393576                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       334400                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       334400                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3672090                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3672090                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3974747                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3974747                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     301594870                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        301594870                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    301988446                       # number of overall hits
-system.cpu.dcache.overall_hits::total       301988446                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      5315823                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       5315823                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2219045                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2219045                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1297249                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1297249                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1232796                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1232796                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       304342                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       304342                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      7534868                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7534868                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      8832117                       # number of overall misses
-system.cpu.dcache.overall_misses::total       8832117                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  84066704475                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  84066704475                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  66382286210                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  66382286210                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  32849513005                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  32849513005                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4463810234                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4463810234                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 150448990685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 150448990685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 150448990685                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 150448990685                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    162074588                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    162074588                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    147055150                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    147055150                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1690825                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1690825                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1567196                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1567196                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3976432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3976432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3974749                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3974749                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    309129738                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    309129738                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    310820563                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    310820563                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032799                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032799                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015090                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015090                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.767228                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.767228                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786625                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786625                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076536                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076536                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024374                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024374                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028415                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028415                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825                       # average LoadLockedReq miss latency
+system.cpu.dcache.tags.tag_accesses        1276220350                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276220350                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    154968992                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       154968992                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    143085243                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      143085243                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       390390                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        390390                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       335374                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       335374                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3613361                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3613361                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3913213                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3913213                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     298054235                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        298054235                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    298444625                       # number of overall hits
+system.cpu.dcache.overall_hits::total       298444625                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      5249224                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       5249224                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2178798                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2178798                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1272425                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1272425                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1229487                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1229487                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       301533                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       301533                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      7428022                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7428022                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      8700447                       # number of overall misses
+system.cpu.dcache.overall_misses::total       8700447                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  82824595500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  82824595500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  63552242000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  63552242000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  50841662000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  50841662000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4423231500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4423231500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 146376837500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 146376837500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 146376837500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 146376837500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    160218216                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    160218216                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    145264041                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    145264041                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1662815                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1662815                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1564861                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1564861                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3914894                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3914894                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3913214                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3913214                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    305482257                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    305482257                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    307145072                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    307145072                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032763                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032763                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014999                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.014999                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.765223                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.765223                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.785684                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.785684                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.077022                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.077022                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024316                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024316                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028327                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028327                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15778.445633                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15778.445633                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29168.487395                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29168.487395                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 41351.931334                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 41351.931334                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14669.145666                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14669.145666                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19967.037337                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17034.306802                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19706.031767                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19706.031767                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16824.059442                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16824.059442                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -703,154 +702,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7878976                       # number of writebacks
-system.cpu.dcache.writebacks::total           7878976                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        16016                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        16016                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21118                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21118                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70685                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        70685                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        37134                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        37134                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        37134                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        37134                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5299807                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5299807                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2197927                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2197927                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1295520                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1295520                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1232796                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1232796                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       233657                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       233657                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7497734                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7497734                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8793254                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8793254                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7760504                       # number of writebacks
+system.cpu.dcache.writebacks::total           7760504                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23609                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        23609                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21261                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21261                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        71576                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        71576                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        44870                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        44870                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        44870                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        44870                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5225615                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5225615                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2157537                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2157537                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1270654                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1270654                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1229487                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1229487                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       229957                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       229957                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7383152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7383152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8653806                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8653806                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75489557525                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75489557525                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  62224351540                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  62224351540                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20153084274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20153084274                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  31000318995                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  31000318995                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2998156750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2998156750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 137713909065                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 157866993339                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5751194250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5751194250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5618584250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5618584250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11369778500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11369778500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.766206                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.766206                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786625                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786625                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058760                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058760                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024254                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024254                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028290                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028290                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  77028808000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  77028808000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  60744856000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  60744856000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20507265000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20507265000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  49612175000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  49612175000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3074046500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3074046500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137773664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 137773664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 158280929000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 158280929000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5831352000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5831352000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5695270000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5695270000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11526622000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11526622000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032616                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032616                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014853                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014853                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.764158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.764158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.785684                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.785684                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058739                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058739                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024169                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024169                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028175                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028175                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552                       # average overall mshr miss latency
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+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          13753173                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.880059                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           880276980                       # Total number of references to valid blocks.
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-system.cpu.icache.tags.warmup_cycle       35133104250                       # Cycle when the warmup percentage was hit.
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+system.cpu.icache.tags.warmup_cycle       43284980500                       # Cycle when the warmup percentage was hit.
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 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
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-system.cpu.icache.tags.data_accesses        907784360                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    880276980                       # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183                       # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::cpu.inst 184520052183                       # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::cpu.inst 184520052183                       # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst    894030670                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015384                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782                       # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 13416.039782                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13416.039782                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         897337839                       # Number of tag accesses
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13411.441988                       # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13411.441988                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13411.441988                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -859,213 +858,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3211087000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3211087000                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015384                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average overall mshr miss latency
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-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406                       # average ReadReq mshr uncacheable latency
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-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406                       # average overall mshr uncacheable latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12411.441988                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74879.026087                       # average ReadReq mshr uncacheable latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74879.026087                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1292250                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65291.754390                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           27666738                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1355280                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            20.414038                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       7588597000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   308.197317                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   420.773838                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6468.758735                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.585064                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5452                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54401                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004532                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.957230                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        264471216                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       371629                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       250715                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total       20850456                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7878976                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7878976                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       723057                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       723057                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9863                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9863                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1639498                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1639498                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       371629                       # number of demand (read+write) hits
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783297                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.tags.avg_refs            33.056126                       # Average number of references to valid blocks.
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.demand_miss_rate::total     0.037478                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011062                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.015912                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005783                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087731                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.037478                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383                       # average ReadReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     0.243254                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     0.243254                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.230467                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.230467                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005733                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005733                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.040612                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.040612                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.412824                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.412824                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.010860                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.015359                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005733                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.085988                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.036286                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.010860                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.015359                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005733                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.085988                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.036286                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87168.713226                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 86447.885005                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15441.150631                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15441.150631                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80629.323660                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80629.323660                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81724.710711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81724.710711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83325.601104                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83325.601104                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 79177.973331                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 79177.973331                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87168.713226                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81724.710711                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81598.411226                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81655.460633                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87168.713226                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81724.710711                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81598.411226                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81655.460633                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1074,31 +1084,35 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1107523                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1107523                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         4157                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4054                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        79532                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       275030                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       362773                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       509738                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       509738                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        35651                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        35651                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       512916                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       512916                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         4157                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4054                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        79532                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       787946                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       875689                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         4157                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4054                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        79532                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       787946                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       875689                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1077959                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1077959                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3987                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3909                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         7896                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1116                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1116                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        35285                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        35285                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       486856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       486856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        79678                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        79678                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       273164                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273164                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       507562                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       507562                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3987                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3909                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        79678                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       760020                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       847594                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3987                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3909                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        79678                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       760020                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       847594                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
@@ -1107,143 +1121,153 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33710
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    305848750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5531016720                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  19548409701                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25690889671                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  16058529504                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  16058529504                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    625079648                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    625079648                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       135000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       135000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35188398563                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35188398563                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    305848750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5531016720                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  54736808264                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  60879288234                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    305848750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5531016720                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  54736808264                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  60879288234                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2585776000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5279091500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7864867500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5180093000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5180093000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2585776000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10459184500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13044960500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.040274                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017101                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.413482                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.413482                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783297                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783297                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    301652500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    603632500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    728816500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    728816500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  34386310000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  34386310000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   5714881500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   5714881500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  20029914500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  20029914500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  35112110500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  35112110500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    301652500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5714881500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  54416224500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  60734738500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    301652500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5714881500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  54416224500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  60734738500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2690095500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5410027000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8100122500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5307605000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5307605000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2690095500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10717632000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13407727500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012702                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782998                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782998                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.238298                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.238298                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087731                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.037478                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087731                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.037478                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.230467                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.230467                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005733                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.040612                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.040612                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.412824                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.412824                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.085988                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.036286                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.085988                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.036286                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76447.885005                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20655.136744                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20655.136744                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70629.323660                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70629.323660                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71724.710711                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73325.601104                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73325.601104                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69177.973331                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69177.973331                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       21652739                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      21644705                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1048560                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      21674258                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7878976                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1339565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1232795                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        45517                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        45519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2152414                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2152414                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     27593630                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28534080                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       622119                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       992785                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          57742614                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    880408660                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1158207750                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2038152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3006288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2043660850                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      470306                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     33102923                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.033230                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.179236                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::Writeback      8945109                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     16396444                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        45067                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        45068                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2112473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2112473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     13898590                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6735107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1336151                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1229487                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41779933                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30429687                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       620392                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       972976                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          73802988                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    889682260                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1062595910                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2036024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2937088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         1957251282                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1844105                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     50552964                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.048758                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.215362                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           32002916     96.68%     96.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1100007      3.32%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           48088105     95.12%     95.12% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            2464859      4.88%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       33102923                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    25622352750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1278000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       50552964                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    32307276000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1324500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20698021683                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20891010000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14320653166                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13945928913                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     367823750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     365889000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     617486750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     605840000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40333                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40333                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40329                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40329                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1260,11 +1284,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231024                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231024                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231016                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231016                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353808                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353800                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1281,11 +1305,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334496                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334496                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492448                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492416                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1314,211 +1338,213 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           606968921                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568778648                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148463571                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115493                       # number of replacements
-system.iocache.tags.tagsinuse               10.456626                       # Cycle average of tags in use
+system.iocache.tags.replacements               115490                       # number of replacements
+system.iocache.tags.tagsinuse               10.455215                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115509                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115506                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13157260299000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.510556                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.946069                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219410                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434129                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653539                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13165278431000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.510021                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.945193                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219376                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434075                       # Average percentage of cache occupancy
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039965                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039965                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039929                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039929                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8848                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8885                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
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 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8848                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8888                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8848                       # number of overall misses
-system.iocache.overall_misses::total             8888                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1591055254                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1596127254                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19834612096                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19834612096                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1591055254                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1596479754                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1591055254                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1596479754                       # number of overall miss cycles
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 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
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-system.iocache.demand_accesses::total            8888                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
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-system.iocache.overall_accesses::total           8888                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
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 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 179642.909848                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 179820.892179                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 179621.934518                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 179820.892179                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 179621.934518                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        109316                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 176913.437451                       # average ReadReq miss latency
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+system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 177080.420398                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 176893.205538                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 177080.420398                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 176893.205538                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         29516                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16121                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3281                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.780969                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.996038                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8848                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8885                       # number of ReadReq MSHR misses
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 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
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 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
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-system.iocache.overall_mshr_misses::total         8888                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1129796362                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1132938362                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14288050130                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14288050130                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1129796362                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1133131862                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1129796362                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1133131862                       # number of overall MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1123899238                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1127118238                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total   1127319238                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1123899238                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1127319238                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 127490.083483                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 127490.083483                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 126893.205538                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 126893.205538                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              448489                       # Transaction distribution
-system.membus.trans_dist::ReadResp             448489                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
+system.membus.trans_dist::ReadResp             446450                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
-system.membus.trans_dist::Writeback           1214153                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       616398                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       616398                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36221                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36223                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            512353                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           512353                       # Transaction distribution
+system.membus.trans_dist::Writeback           1184590                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190005                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35851                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35852                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            993855                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           993855                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        369619                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4040402                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4170106                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4505175                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4133679                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4263383                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340829                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       340829                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4604212                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    159663776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    159833626                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14049088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14049088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               173882714                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3324                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2861471                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    155834656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    156004506                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7214528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7214528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               163219034                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3445                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2994110                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2861471    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2994110    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2861471                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107107000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2994110                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           107330000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5171500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5385500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         10418059043                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7724756059                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5433894864                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7445249237                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151694929                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228975298                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 1bcf52f34..0afb21efb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,71 +4,71 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1028340                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1208468                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            53383325140                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 714148                       # Number of bytes of host memory used
-host_seconds                                   957.44                       # Real time elapsed on the host
+host_inst_rate                                1174774                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1380553                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            60985034894                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 718504                       # Number of bytes of host memory used
+host_seconds                                   838.09                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker       203392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker       187968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3328564                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         37865864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3317876                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         64750152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker       208384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       188288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2234176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         36967936                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81626364                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3328564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2234176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103043072                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.itb.walker       188480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2225152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         45360128                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            116883644                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3317876                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2225152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103060608                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103063652                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103081188                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker         3178                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker         2937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             92416                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            591667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             92249                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1011734                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker         3256                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2942                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             34909                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            577624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315832                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610048                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             34768                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            708752                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1866727                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610322                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612621                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1612895                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          3979                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker          3678                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               65124                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              740853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               64915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1266850                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker          4077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              723285                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8644                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1597036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          65124                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43712                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016058                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               43536                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              887480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          64915                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          43536                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016402                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016461                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2016804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016402                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         3979                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker         3678                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              65124                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             741256                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              64915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1267252                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker         4077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             723285                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3613497                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              43536                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             887480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303656                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -317,9 +317,9 @@ system.cpu0.dcache.WriteReq_hits::total     159522868                       # nu
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       208530                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu1.data       215328                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       423858                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       146037                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       191672                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       337709                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       146037                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       191672                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       337709                       # number of WriteLineReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2127418                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      2183031                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total      4310449                       # number of LoadLockedReq hits
@@ -341,9 +341,9 @@ system.cpu0.dcache.WriteReq_misses::total      2570259                       # n
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       792908                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu1.data       791180                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total      1584088                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       765143                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       480206                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1245349                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       765143                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       480206                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1245349                       # number of WriteLineReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       123898                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       129919                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total       253817                       # number of LoadLockedReq misses
@@ -364,9 +364,9 @@ system.cpu0.dcache.WriteReq_accesses::total    162093127                       #
 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1001438                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data      1006508                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::total      2007946                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       911180                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       671878                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       911180                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       671878                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1583058                       # number of WriteLineReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2251316                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2312950                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total      4564266                       # number of LoadLockedReq accesses(hits+misses)
@@ -388,9 +388,9 @@ system.cpu0.dcache.WriteReq_miss_rate::total     0.015857
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.791769                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.786064                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788910                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.839728                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.714722                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.839728                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.714722                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786673                       # miss rate for WriteLineReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055034                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056170                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055610                       # miss rate for LoadLockedReq accesses
@@ -410,8 +410,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8921315                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8921315                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      8921279                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8921279                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements         14295641                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
@@ -677,8 +677,7 @@ system.cpu1.kern.inst.quiesce                       0                       # nu
 system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29851                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -742,8 +741,8 @@ system.iocache.ReadReq_misses::realview.ide         8817                       #
 system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
 system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
 system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
@@ -755,8 +754,8 @@ system.iocache.ReadReq_accesses::realview.ide         8817
 system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
@@ -768,8 +767,8 @@ system.iocache.ReadReq_miss_rate::realview.ide            1
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -787,133 +786,130 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1722682                       # number of replacements
-system.l2c.tags.tagsinuse                65341.862498                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   30065488                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1785979                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    16.834178                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1722562                       # number of replacements
+system.l2c.tags.tagsinuse                65341.862549                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47050546                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1785858                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    26.346185                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37141.097811                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   156.460660                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   243.495240                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3601.604762                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9619.799415                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.654107                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   201.240500                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2659.657984                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11566.852019                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.566728                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   37097.979539                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   156.460552                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   243.494258                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3630.477879                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9618.607320                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.652985                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   201.240388                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2660.497968                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11581.451661                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.566070                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002387                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.003715                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.054956                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.146786                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.055397                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.146768                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002314                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.003071                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040583                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.176496                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.040596                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.176719                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.997038                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023          276                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        63021                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        63020                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4          276                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2715                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4911                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54671                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2714                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4910                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54672                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.961624                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                290964090                       # Number of tag accesses
-system.l2c.tags.data_accesses               290964090                       # Number of data accesses
+system.l2c.tags.occ_task_id_percent::1024     0.961609                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                426855693                       # Number of tag accesses
+system.l2c.tags.data_accesses               426855693                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker       279435                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker       145257                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            7107195                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3754972                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker       276854                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       142760                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            7104726                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3749259                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               22560458                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         8921315                       # number of Writeback hits
-system.l2c.Writeback_hits::total              8921315                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       345123                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       349209                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       694332                       # number of WriteInvalidateReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       142757                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 844303                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         8921279                       # number of Writeback hits
+system.l2c.Writeback_hits::total              8921279                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data            5687                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data            5536                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total               11223                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           864873                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           827736                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1692609                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           864866                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           827692                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1692558                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       7107362                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       7104867                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          14212229                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      3754928                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data      3749182                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          7504110                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       345122                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       349199                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           694321                       # number of InvalidateReq hits
 system.l2c.demand_hits::cpu0.dtb.walker        279435                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker        145257                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7107195                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4619845                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             7107362                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4619794                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.dtb.walker        276854                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        142760                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7104726                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4576995                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24253067                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker        142757                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             7104867                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             4576874                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                24253200                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker       279435                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker       145257                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7107195                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4619845                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            7107362                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            4619794                       # number of overall hits
 system.l2c.overall_hits::cpu1.dtb.walker       276854                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       142760                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            7104726                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4576995                       # number of overall hits
-system.l2c.overall_hits::total               24253067                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker       142757                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            7104867                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4576874                       # number of overall hits
+system.l2c.overall_hits::total               24253200                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker         3178                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu0.inst            49315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           177059                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker         3256                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.inst            34922                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           166908                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               440517                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       420020                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       130997                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       551017                       # number of WriteInvalidateReq misses
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 system.l2c.UpgradeReq_misses::cpu0.data         19994                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data         19925                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total             39919                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         415064                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         411444                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             826508                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         415071                       # number of ReadExReq misses
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+system.l2c.ReadExReq_misses::total             826559                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        49148                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst        34781                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           83929                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       177103                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       166985                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         344088                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       420021                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       131007                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         551028                       # number of InvalidateReq misses
 system.l2c.demand_misses::cpu0.dtb.walker         3178                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker         2937                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             49315                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            592123                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             49148                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            592174                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker         3256                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2942                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             34922                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            578352                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1267025                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2945                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             34781                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            578473                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1266892                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker         3178                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker         2937                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            49315                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           592123                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            49148                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           592174                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker         3256                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2942                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            34922                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           578352                       # number of overall misses
-system.l2c.overall_misses::total              1267025                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2945                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            34781                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           578473                       # number of overall misses
+system.l2c.overall_misses::total              1266892                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu0.dtb.walker       282613                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker       148194                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst        7156510                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        3932031                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker       280110                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker       145702                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst        7139648                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data        3916167                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total           23000975                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      8921315                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          8921315                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       765143                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       480206                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             856619                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          8921279                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data        25681                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data        25461                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           51142                       # number of UpgradeReq accesses(hits+misses)
@@ -922,6 +918,15 @@ system.l2c.SCUpgradeReq_accesses::total             1                       # nu
 system.l2c.ReadExReq_accesses::cpu0.data      1279937                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data      1239180                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total          2519117                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      7156510                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      7139648                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      14296158                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3932031                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3916167                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      7848198                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       765143                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       480206                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1245349                       # number of InvalidateReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.dtb.walker       282613                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.itb.walker       148194                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.inst         7156510                       # number of demand (read+write) accesses
@@ -942,42 +947,44 @@ system.l2c.overall_accesses::cpu1.data        5155347                       # nu
 system.l2c.overall_accesses::total           25520092                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.011245                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.019819                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.006891                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.045030                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.011624                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.020192                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004891                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.042620                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.019152                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.548943                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.272793                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.442460                       # miss rate for WriteInvalidateReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.020212                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.014377                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.778552                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782569                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.780552                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.324285                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.332029                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.328094                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.324290                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.332065                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.328115                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006868                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004872                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045041                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042640                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.548944                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.272814                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.442469                       # miss rate for InvalidateReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011245                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.019819                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.113608                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006868                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.113618                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.dtb.walker     0.011624                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.020192                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.112185                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.049648                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.020212                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004872                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.112208                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.049643                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011245                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.019819                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.113608                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006868                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.113618                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.dtb.walker     0.011624                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.020192                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.112185                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.049648                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.020212                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004872                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.112208                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.049643                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -986,49 +993,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1503417                       # number of writebacks
-system.l2c.writebacks::total                  1503417                       # number of writebacks
+system.l2c.writebacks::writebacks             1503691                       # number of writebacks
+system.l2c.writebacks::total                  1503691                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              526050                       # Transaction distribution
-system.membus.trans_dist::ReadResp             526050                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525866                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610048                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       657676                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       657676                       # Transaction distribution
+system.membus.trans_dist::Writeback           1610322                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           228928                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            40486                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp           40487                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            825949                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           825949                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377023                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377023                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        449187                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5310719                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5439911                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337673                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5777584                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5530845                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5660037                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       346505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6006542                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212730400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    212899450                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14217536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               227116986                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212740128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    212909178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220300218                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3693816                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3922896                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3693816    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3922896    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3693816                       # Request fanout histogram
+system.membus.snoop_fanout::total             3922896                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1071,39 +1080,42 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           23464706                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            1320350                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp          23464706                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33606                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33606                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8921315                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1245349                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1245349                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          8921279                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        16986503                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq           51142                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp          51143                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq          2519117                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp         2519117                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     28678566                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32383249                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq      14296158                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7848198                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1245349                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1245349                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     42974207                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35074075                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       832126                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1655216                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              63549157                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              80535624                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1314364326                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3328504                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6620864                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2239440306                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2159735666                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                          116338                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         36350757                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.037391                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.189718                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples         53337224                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.025483                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.157587                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               34991565     96.26%     96.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1359192      3.74%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               51978032     97.45%     97.45% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1359192      2.55%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           36350757                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           53337224                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index cca0e71cb..4324d934c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,174 +1,174 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.274696                       # Number of seconds simulated
-sim_ticks                                51274696167500                       # Number of ticks simulated
-final_tick                               51274696167500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.235006                       # Number of seconds simulated
+sim_ticks                                51235005618500                       # Number of ticks simulated
+final_tick                               51235005618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 293957                       # Simulator instruction rate (inst/s)
-host_op_rate                                   345410                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17006997815                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 724900                       # Number of bytes of host memory used
-host_seconds                                  3014.92                       # Real time elapsed on the host
-sim_insts                                   886256415                       # Number of instructions simulated
-sim_ops                                    1041383802                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 299120                       # Simulator instruction rate (inst/s)
+host_op_rate                                   351506                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17342892504                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 728488                       # Number of bytes of host memory used
+host_seconds                                  2954.24                       # Real time elapsed on the host
+sim_insts                                   883670074                       # Number of instructions simulated
+sim_ops                                    1038432543                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       116160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       120000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2956980                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         25219400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        40192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        37376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           753536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          7117376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        92544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        94080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          2191808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data         17867136                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        430080                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             57036668                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2956980                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       753536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      2191808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5902324                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     77190720                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       126592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       125376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2934708                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         51720008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        38784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        35712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           741632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          9002048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        95296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        86336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          2270528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data         22315456                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        419776                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             89912252                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2934708                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       741632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      2270528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5946868                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     77430208                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          77211300                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1815                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1875                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             86610                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            394066                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          628                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          584                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             11774                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            111209                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker         1446                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker         1470                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             34247                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            279174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6720                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                931618                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1206105                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          77450788                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1978                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1959                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             86262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            808138                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          606                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             11588                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            140657                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker         1489                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker         1349                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             35477                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            348679                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1445299                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1209847                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1208678                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               57669                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              491849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           784                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               14696                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              138809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          1805                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker          1835                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               42746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              348459                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1112375                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          57669                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          14696                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          42746                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             115112                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1505435                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1505836                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1505435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2265                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              57669                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             492250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          784                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          729                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              14696                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             138809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         1805                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker         1835                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              42746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             348459                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8388                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2618211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        440592                       # Number of read requests accepted
-system.physmem.writeReqs                       615308                       # Number of write requests accepted
-system.physmem.readBursts                      440592                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     615308                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28181248                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     16640                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  38332736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28197888                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               39379712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      260                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   16359                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          18561                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25854                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28544                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25469                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27506                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               26728                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               30588                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26415                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27502                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               26500                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               31676                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27941                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              30917                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25895                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              27920                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25066                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25811                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               36067                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               36031                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               34636                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               37309                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               37132                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               40234                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               38375                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               37986                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               35542                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               42123                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              38624                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              39603                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              35582                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              38033                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              36333                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              35339                       # Per bank write bursts
+system.physmem.num_writes::total              1212420                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               57279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1009466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           697                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               14475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              175701                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker          1860                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker          1685                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               44316                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              435551                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8193                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1754899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          57279                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          14475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          44316                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             116070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1511275                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1511677                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1511275                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              57279                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1009868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          757                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          697                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              14475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             175701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker         1860                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker         1685                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              44316                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             435551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8193                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3266576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        540590                       # Number of read requests accepted
+system.physmem.writeReqs                       467319                       # Number of write requests accepted
+system.physmem.readBursts                      540590                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     467319                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 34576064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21696                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  29908416                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  34597760                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               29908416                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      339                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          52057                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               34722                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               34925                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               34806                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               34433                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               35553                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               39917                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               33295                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               34606                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               31417                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               34834                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              32861                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              34723                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              29445                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              31855                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              31705                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              31154                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               29588                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               28520                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               28987                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               29728                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               31002                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               33624                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               29096                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               30620                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               28064                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               30877                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              28622                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              29758                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              25484                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              27499                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              28130                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              27720                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          73                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51273531025000                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51233860786000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
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-system.physmem.readPktSize::6                  440592                       # Read request sizes (log2)
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-system.physmem.rdQLenPdf::1                     95022                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -180,183 +180,186 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
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 system.physmem.wrQLenPdf::6                       469                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::384-511        12377      4.47%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8866      3.21%     87.82% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::768-895         4514      1.63%     91.40% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151        20142      7.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         276595                       # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::32-47            1083      3.70%     98.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-63             204      0.70%     99.69% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-79              56      0.19%     99.88% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::128-143             2      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::176-191             2      0.01%     99.99% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::288-303             1      0.00%    100.00% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::total           29231                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         29231                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.490199                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.518949                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       18.634153                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               58      0.20%      0.20% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::32-47             804      2.75%     96.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63             250      0.86%     97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79             169      0.58%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             102      0.35%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             99      0.34%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           124      0.42%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            61      0.21%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159             8      0.03%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             5      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            19      0.06%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            14      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             5      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             2      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             2      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             3      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             2      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             7      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             7      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           29231                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10175638298                       # Total ticks spent queuing
-system.physmem.totMemAccLat               18431863298                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2201660000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23109.01                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           26815                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         26815                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.427522                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.974087                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.290252                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                17      0.06%      0.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                10      0.04%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               10      0.04%      0.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              46      0.17%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           25300     94.35%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             507      1.89%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             249      0.93%     97.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             127      0.47%     97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              87      0.32%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             125      0.47%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              58      0.22%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              14      0.05%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.07%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              19      0.07%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              12      0.04%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.03%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             123      0.46%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              19      0.07%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              20      0.07%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              17      0.06%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           26815                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12836932182                       # Total ticks spent queuing
+system.physmem.totMemAccLat               22966638432                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2701255000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23761.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41859.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.75                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.55                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.77                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42511.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.67                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.58                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.67                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     330665                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    432014                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                     48559078.53                       # Average gap between requests
-system.physmem.pageHitRate                      73.39                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1047672360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  569481000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1705126800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1929536640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3307165171440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1163738784870                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29596559989500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34072715762610                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.713146                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48842268608197                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1690779740000                       # Time in different power states
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.63                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     422337                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    326863                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   78.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     50831831.83                       # Average gap between requests
+system.physmem.pageHitRate                      74.36                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1022081760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  555373500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2201604600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1562664960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3304577109600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1165623840135                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29580668399250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34056211073805                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.700210                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48799941577250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1689456600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    102045610303                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    106076762500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1043355600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  567088500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1729462800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1951549200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3307165171440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1164487973490                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29604202640250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34081147241280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.697375                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48841133395944                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1690779740000                       # Time in different power states
+system.physmem_1.actEnergy                  931059360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  506149875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                2012353200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1465445520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3304577109600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1160291732670                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29572164937500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34041948787725                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.708167                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48807751567992                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1689456600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    103204176556                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     98247859258                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -416,48 +419,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   113114                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               113114                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples       113114                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         113114    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       113114                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 1113616699016                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.572841                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.494666                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   475691482516     42.72%     42.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   637925216500     57.28%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 1113616699016                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        82726     84.85%     84.85% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        14770     15.15%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        97496                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       113114                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   112814                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               112814                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples       112814                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         112814    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       112814                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 1116892952476                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.571172                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.494909                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   478954833976     42.88%     42.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   637938118500     57.12%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1116892952476                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        81756     84.41%     84.41% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        15104     15.59%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        96860                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       112814                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       113114                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        97496                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       112814                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        96860                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        97496                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       210610                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        96860                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       209674                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    78321186                       # DTB read hits
-system.cpu0.dtb.read_misses                     84847                       # DTB read misses
-system.cpu0.dtb.write_hits                   71529400                       # DTB write hits
-system.cpu0.dtb.write_misses                    28267                       # DTB write misses
+system.cpu0.dtb.read_hits                    78427319                       # DTB read hits
+system.cpu0.dtb.read_misses                     84483                       # DTB read misses
+system.cpu0.dtb.write_hits                   71558713                       # DTB write hits
+system.cpu0.dtb.write_misses                    28331                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        1285                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              20997                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    507                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   51007                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              21339                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    502                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   51365                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4028                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3702                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9780                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                78406033                       # DTB read accesses
-system.cpu0.dtb.write_accesses               71557667                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9826                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                78511802                       # DTB read accesses
+system.cpu0.dtb.write_accesses               71587044                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        149850586                       # DTB hits
-system.cpu0.dtb.misses                         113114                       # DTB misses
-system.cpu0.dtb.accesses                    149963700                       # DTB accesses
+system.cpu0.dtb.hits                        149986032                       # DTB hits
+system.cpu0.dtb.misses                         112814                       # DTB misses
+system.cpu0.dtb.accesses                    150098846                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -487,585 +490,585 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    63285                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                63285                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        63285                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          63285    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        63285                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 1113616695516                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.572887                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.494659                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   475639854016     42.71%     42.71% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   637976841500     57.29%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 1113616695516                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        55054     95.20%     95.20% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2776      4.80%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        57830                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    63116                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                63116                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        63116                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          63116    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        63116                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 1116892951476                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.571207                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.494904                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   478916115976     42.88%     42.88% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   637976835500     57.12%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 1116892951476                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        54727     95.15%     95.15% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2791      4.85%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        57518                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        63285                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        63285                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        63116                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        63116                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        57830                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        57830                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       121115                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   419986176                       # ITB inst hits
-system.cpu0.itb.inst_misses                     63285                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        57518                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        57518                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       120634                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   420544157                       # ITB inst hits
+system.cpu0.itb.inst_misses                     63116                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        1285                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              20997                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    507                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   35884                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21339                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    502                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   35909                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               420049461                       # ITB inst accesses
-system.cpu0.itb.hits                        419986176                       # DTB hits
-system.cpu0.itb.misses                          63285                       # DTB misses
-system.cpu0.itb.accesses                    420049461                       # DTB accesses
-system.cpu0.numCycles                       505091044                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               420607273                       # ITB inst accesses
+system.cpu0.itb.hits                        420544157                       # DTB hits
+system.cpu0.itb.misses                          63116                       # DTB misses
+system.cpu0.itb.accesses                    420607273                       # DTB accesses
+system.cpu0.numCycles                       505895917                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  419794202                       # Number of instructions committed
-system.cpu0.committedOps                    493796806                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            453197936                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                421943                       # Number of float alu accesses
-system.cpu0.num_func_calls                   25265539                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     63928321                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   453197936                       # number of integer instructions
-system.cpu0.num_fp_insts                       421943                       # number of float instructions
-system.cpu0.num_int_register_reads          668318275                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         360308744                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              682016                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             353392                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           110766057                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          110481712                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    149944655                       # number of memory refs
-system.cpu0.num_load_insts                   78394551                       # Number of load instructions
-system.cpu0.num_store_insts                  71550104                       # Number of store instructions
-system.cpu0.num_idle_cycles              493080351.361326                       # Number of idle cycles
-system.cpu0.num_busy_cycles              12010692.638674                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023779                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976221                       # Percentage of idle cycles
-system.cpu0.Branches                         93737042                       # Number of branches fetched
+system.cpu0.committedInsts                  420346594                       # Number of instructions committed
+system.cpu0.committedOps                    494579830                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            453915139                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                407993                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25255441                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     64064604                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   453915139                       # number of integer instructions
+system.cpu0.num_fp_insts                       407993                       # number of float instructions
+system.cpu0.num_int_register_reads          669796814                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         361015506                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              660600                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             338556                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           110996958                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          110750515                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    150079107                       # number of memory refs
+system.cpu0.num_load_insts                   78499668                       # Number of load instructions
+system.cpu0.num_store_insts                  71579439                       # Number of store instructions
+system.cpu0.num_idle_cycles              493874204.516617                       # Number of idle cycles
+system.cpu0.num_busy_cycles              12021712.483383                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023763                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976237                       # Percentage of idle cycles
+system.cpu0.Branches                         93830955                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                342973363     69.42%     69.42% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1071330      0.22%     69.63% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    48623      0.01%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             51721      0.01%     69.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.65% # Class of executed instruction
-system.cpu0.op_class::MemRead                78394551     15.87%     85.52% # Class of executed instruction
-system.cpu0.op_class::MemWrite               71550104     14.48%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                343614791     69.43%     69.43% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1086596      0.22%     69.65% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    48369      0.01%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             49130      0.01%     69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.67% # Class of executed instruction
+system.cpu0.op_class::MemRead                78499668     15.86%     85.54% # Class of executed instruction
+system.cpu0.op_class::MemWrite               71579439     14.46%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 494089735                       # Class of executed instruction
+system.cpu0.op_class::total                 494878036                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16313                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements         10220953                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999720                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          305187926                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10221465                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            29.857552                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   16312                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements         10193982                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999718                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          304221340                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10194494                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            29.841730                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.221457                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     6.755911                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     8.022352                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971136                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.013195                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.015669                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.636821                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.388351                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    10.974546                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.968041                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010524                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.021435                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          204                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1297346809                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1297346809                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     73103498                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     24004695                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     59713819                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      156822012                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67621876                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     22136915                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     50273570                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     140032361                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       191205                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58550                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       144781                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       394536                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       151179                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data        54099                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data       126065                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       331343                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1805832                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       567281                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1240318                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3613431                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1916828                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       614023                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data      1418006                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3948857                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    140725374                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     46141610                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data    109987389                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       296854373                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    140916579                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     46200160                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data    110132170                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      297248909                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2537446                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       778664                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data      4676407                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7992517                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1084233                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       329896                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data      4337927                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5752056                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       625359                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       184328                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       464541                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1274228                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       751309                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       143971                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data       338834                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1234114                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       111816                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        47069                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data       226989                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       385874                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1293146150                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1293146150                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     73192810                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     24078178                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data     59062839                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      156333827                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67632120                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     22097804                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data     49843167                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     139573091                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       193481                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58228                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data       144072                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       395781                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       150752                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data        54007                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu2.data       125506                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       330265                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1823556                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       547758                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1229270                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3600584                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1933646                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       595016                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data      1413472                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3942134                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    140824930                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     46175982                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data    108906006                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       295906918                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    141018411                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     46234210                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data    109050078                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      296302699                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2530012                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       810343                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data      4548856                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7889211                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1084459                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       324852                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data      4363130                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      5772441                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       629295                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       177552                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       467332                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1274179                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       753152                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       142541                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu2.data       338665                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1234358                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       110926                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        47584                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data       233520                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       392030                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3621679                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1108560                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      9014334                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13744573                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4247038                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1292888                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      9478875                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     15018801                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  12082220500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  71708819033                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  83791039533                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9788716367                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 139964630413                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 149753346780                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data   2906340501                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data   7459202639                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  10365543140                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    670206750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data   2926933738                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3597140488                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            7                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3614471                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1135195                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      8911986                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13661652                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4243766                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1312747                       # number of overall misses
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+system.cpu0.dcache.overall_misses::total     14935831                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  12443944000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  69833838000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  82277782000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9722892000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 137997538214                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 147720430214                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   3829880000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data  11756491801                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  15586371801                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    699957500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data   2904634000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3604591500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        26000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       190000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  21870936867                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 211673449446                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 233544386313                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  21870936867                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 211673449446                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 233544386313                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     75640944                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     24783359                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.ReadReq_accesses::total    164814529                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     68706109                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     22466811                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     54611497                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    145784417                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       816564                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       242878                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       609322                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1668764                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       902488                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       198070                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       464899                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1565457                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1917648                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       614350                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1467307                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3999305                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1916828                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       614025                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1418008                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3948861                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    144347053                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     47250170                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data    119001723                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    310598946                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    145163617                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     47493048                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data    119611045                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    312267710                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033546                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031419                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.072626                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.048494                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015781                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014684                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.079432                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.039456                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.765842                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.758932                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.762390                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.763576                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.832486                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.726869                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data     0.728834                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.788341                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.058309                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076616                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.154698                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.096485                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       111000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       275000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  22166836000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 207831376214                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 229998212214                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  22166836000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 207831376214                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 229998212214                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     75722822                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     24888521                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::cpu0.data     68716579                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     22422656                       # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::total    145345532                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       822776                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       235780                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       611404                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1669960                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       903904                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       196548                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       464171                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1564623                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1934482                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       595342                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1462790                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3992614                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       595018                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1413479                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3942143                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::cpu1.data     47311177                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data    117817992                       # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total    311238530                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033411                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032559                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.071510                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.048040                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015782                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014488                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.080491                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.039715                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764844                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.753041                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.764359                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.763000                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.833221                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.725222                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.729613                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788917                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.057341                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079927                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.159640                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.098189                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025090                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023462                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.075750                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044252                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029257                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027223                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079247                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048096                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15516.603439                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15334.169809                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10483.686120                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29672.128086                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32265.326367                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 26034.751188                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 20186.985580                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 22014.327485                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total  8399.177985                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14238.814294                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12894.606073                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9322.059760                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025024                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023994                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.075642                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.044131                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029215                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027609                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079198                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.047988                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15356.391059                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15351.956184                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10429.152167                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29930.220531                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31628.106019                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25590.634918                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26868.620257                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34714.221431                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 12627.108020                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14709.934011                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12438.480644                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9194.682805                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        47500                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19729.141289                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23481.873364                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16991.752768                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16916.342999                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22331.072986                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15550.135215                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     14700393                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        25808                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          1130734                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            457                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.000753                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    56.472648                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15857.142857                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30555.555556                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19526.897141                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23320.433427                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16835.314808                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16885.840150                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22158.474232                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15399.090430                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     17007920                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        25831                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          1141319                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            442                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.901986                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    58.441176                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7872498                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7872498                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2189                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2608868                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2611057                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1745                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3598244                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3599989                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data         2407                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         2407                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        10418                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       138207                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       148625                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         3934                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      6207112                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      6211046                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         3934                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      6207112                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      6211046                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       776475                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2067539                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2844014                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       328151                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       739683                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1067834                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       184212                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       454745                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       638957                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       143971                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data       336427                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       480398                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        36651                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        88782                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       125433                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7849789                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7849789                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2525238                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2527595                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1733                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3623036                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3624769                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data         2374                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2374                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        10549                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       144753                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       155302                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         4090                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      6148274                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      6152364                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         4090                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      6148274                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      6152364                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       807986                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2023618                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2831604                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       323119                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       740094                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1063213                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       177438                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       455361                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       632799                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       142541                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       336291                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       478832                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        37035                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        88767                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       125802                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      1104626                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      2807222                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      3911848                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1288838                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      3261967                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4550805                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5448                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         8279                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        13727                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         5373                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         7916                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13289                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        10821                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        16195                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        27016                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10846992750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30627833111                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41474825861                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9219061633                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  24093607640                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33312669273                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2717019500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   8086528259                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10803547759                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2690383999                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data   6865304661                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total   9555688660                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    463968000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1147138011                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1611106011                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        23000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       184000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  20066054383                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  54721440751                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  74787495134                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22783073883                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  62807969010                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  85591042893                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    895108750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1474898001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2370006751                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    895104500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1438317956                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2333422456                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1790213250                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2913215957                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4703429207                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031330                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.032110                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017256                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014606                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013544                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007325                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.758455                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.746313                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.382892                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.726869                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.723656                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.306874                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059658                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060507                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.031364                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      1131105                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      2763712                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      3894817                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1308543                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      3219073                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4527616                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         4998                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         8152                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        13150                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4942                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         7788                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        12730                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         9940                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        15940                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        25880                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  11585855500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  31062083000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42647938500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9355442500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  24215406665                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33570849165                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2741056000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   8202281000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10943337000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3687339000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data  11324765301                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  15012104301                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    496140000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1176567000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1672707000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       104000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       266000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  20941298000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  55277489665                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  76218787665                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  23682354000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  63479770665                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  87162124665                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    826187000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1474974000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2301161000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    827724000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1436870963                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2264594963                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1653911000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2911844963                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4565755963                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032464                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031812                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017242                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014410                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013653                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007315                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.752557                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.744779                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.378931                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725222                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.724498                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.306037                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062208                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060683                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.031509                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023378                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023590                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.012595                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027137                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027271                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.014573                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13969.532503                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14813.666446                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14583.200315                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28093.961722                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32572.882762                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31196.486788                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14749.416433                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 17782.555628                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.098290                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 18686.985567                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 20406.521061                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 19891.191595                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12659.081608                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12920.839934                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12844.355241                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        46000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18165.473548                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19493.093439                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164300.431351                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178149.293514                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172652.928608                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166593.057882                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181697.568974                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175590.522688                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165438.799556                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 179883.665144                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174097.912607                       # average overall mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023908                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023457                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.012581                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027521                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027181                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.014547                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14339.178525                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15349.775995                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15061.406362                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28953.551168                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32719.366276                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31574.904713                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.964923                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18012.699814                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17293.543447                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25868.620257                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33675.493251                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31351.505958                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13396.516808                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13254.554057                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13296.346640                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14857.142857                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29555.555556                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18514.017708                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20001.175833                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19569.285968                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18098.261960                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19719.891616                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19251.218448                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165303.521409                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180934.003925                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174993.231939                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167487.656819                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184498.069209                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177894.341163                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166389.436620                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 182675.342723                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176420.245866                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         14550991                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.976833                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          611237841                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         14551503                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            42.005135                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9058621500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   496.705744                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     5.210417                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.060673                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.970128                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.010177                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.019650                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         14504187                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.976820                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          610702941                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         14504699                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            42.103800                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9090101500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   497.013968                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.629060                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.333792                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.970730                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.009041                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.020183                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           87                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        640780747                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       640780747                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    413451033                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    134065919                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     63720889                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      611237841                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    413451033                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    134065919                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     63720889                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       611237841                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    413451033                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    134065919                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     63720889                       # number of overall hits
-system.cpu0.icache.overall_hits::total      611237841                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6592973                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      2115468                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      6282843                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     14991284                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6592973                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      2115468                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      6282843                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      14991284                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6592973                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      2115468                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      6282843                       # number of overall misses
-system.cpu0.icache.overall_misses::total     14991284                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  28339007992                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  82279227443                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 110618235435                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  28339007992                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  82279227443                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 110618235435                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  28339007992                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  82279227443                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 110618235435                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    420044006                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    136181387                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     70003732                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    626229125                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    420044006                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    136181387                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     70003732                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    626229125                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    420044006                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    136181387                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     70003732                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    626229125                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015696                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015534                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.089750                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023939                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015696                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015534                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.089750                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023939                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015696                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015534                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.089750                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023939                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13396.093910                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13095.859222                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7378.836625                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13396.093910                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13095.859222                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7378.836625                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13396.093910                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13095.859222                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7378.836625                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        51965                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        640161996                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       640161996                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    414014521                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    133530266                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     63158154                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      610702941                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    414014521                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    133530266                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     63158154                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       610702941                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    414014521                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    133530266                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     63158154                       # number of overall hits
+system.cpu0.icache.overall_hits::total      610702941                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6587154                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      2095893                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst      6271180                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     14954227                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6587154                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      2095893                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst      6271180                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      14954227                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6587154                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      2095893                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst      6271180                       # number of overall misses
+system.cpu0.icache.overall_misses::total     14954227                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  28071619000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  82050168313                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 110121787313                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  28071619000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst  82050168313                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 110121787313                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  28071619000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst  82050168313                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 110121787313                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    420601675                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    135626159                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     69429334                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    625657168                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    420601675                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    135626159                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     69429334                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    625657168                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    420601675                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    135626159                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     69429334                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    625657168                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015661                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015453                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.090325                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023902                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015661                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015453                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.090325                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.023902                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015661                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015453                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.090325                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023902                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13393.631736                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13083.688925                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7363.923746                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13393.631736                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13083.688925                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7363.923746                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13393.631736                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13083.688925                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7363.923746                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        53098                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3925                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             4092                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.239490                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.976051                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst       439662                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       439662                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst       439662                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       439662                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst       439662                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       439662                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      2115468                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      5843181                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      7958649                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      2115468                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      5843181                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      7958649                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      2115468                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      5843181                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      7958649                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  25161480508                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  69932206790                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  95093687298                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  25161480508                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  69932206790                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  95093687298                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  25161480508                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  69932206790                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  95093687298                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015534                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.083470                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012709                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015534                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.083470                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012709                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015534                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.083470                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012709                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.049217                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11968.173977                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11948.471066                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.049217                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11968.173977                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11948.471066                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.049217                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11968.173977                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11948.471066                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst       449399                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       449399                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst       449399                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       449399                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst       449399                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       449399                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      2095893                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      5821781                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      7917674                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      2095893                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      5821781                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      7917674                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      2095893                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      5821781                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      7917674                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  25975726000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  72655138349                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  98630864349                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  25975726000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  72655138349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  98630864349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  25975726000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  72655138349                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  98630864349                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015453                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.083852                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012655                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015453                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.083852                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012655                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015453                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.083852                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012655                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12393.631736                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12479.881732                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12457.050435                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12393.631736                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12479.881732                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12457.050435                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12393.631736                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12479.881732                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12457.050435                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1096,70 +1099,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    40069                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                40069                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         6011                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        28822                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            3                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        40066                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.287026                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    57.452621                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-1023        40065    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    40125                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                40125                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         6166                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        29054                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        40123                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.299080                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    59.907962                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-1023        40122    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::11264-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        40066                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        34836                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23148.919221                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19687.951217                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13456.896972                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        22742     65.28%     65.28% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        11809     33.90%     99.18% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          149      0.43%     99.61% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          100      0.29%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            2      0.01%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           13      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143            8      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911            9      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total        40123                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        35222                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25010.164102                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22134.109650                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13083.481555                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        22653     64.31%     64.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        12324     34.99%     99.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          130      0.37%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071           82      0.23%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           11      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            3      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            6      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            7      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        34836                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2552299344                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.586801                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.492408                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1054607500     41.32%     41.32% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1497691844     58.68%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2552299344                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        28822     82.74%     82.74% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         6011     17.26%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        34833                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        40069                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total        35222                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -2750429288                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     1.373730                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1027918000    -37.37%    -37.37% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -3778347288    137.37%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -2750429288                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        29054     82.49%     82.49% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         6166     17.51%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        35220                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        40125                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        40069                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        34833                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        40125                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        35220                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        34833                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        74902                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        35220                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        75345                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    25646035                       # DTB read hits
-system.cpu1.dtb.read_misses                     30818                       # DTB read misses
-system.cpu1.dtb.write_hits                   23287178                       # DTB write hits
-system.cpu1.dtb.write_misses                     9251                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    25724641                       # DTB read hits
+system.cpu1.dtb.read_misses                     30962                       # DTB read misses
+system.cpu1.dtb.write_hits                   23221976                       # DTB write hits
+system.cpu1.dtb.write_misses                     9163                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1277                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               6462                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    159                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   22057                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               6096                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    163                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   21958                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1362                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  1268                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2875                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                25676853                       # DTB read accesses
-system.cpu1.dtb.write_accesses               23296429                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2784                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25755603                       # DTB read accesses
+system.cpu1.dtb.write_accesses               23231139                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         48933213                       # DTB hits
-system.cpu1.dtb.misses                          40069                       # DTB misses
-system.cpu1.dtb.accesses                     48973282                       # DTB accesses
+system.cpu1.dtb.hits                         48946617                       # DTB hits
+system.cpu1.dtb.misses                          40125                       # DTB misses
+system.cpu1.dtb.accesses                     48986742                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1189,137 +1191,135 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    23826                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                23826                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1156                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        20921                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        23826                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          23826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        23826                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        22077                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26240.136794                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22930.281403                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 15976.450560                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        11277     51.08%     51.08% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535        10485     47.49%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          121      0.55%     99.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          153      0.69%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            3      0.01%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           13      0.06%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375            7      0.03%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            4      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            4      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        22077                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    23205                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                23205                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1161                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        20405                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        23205                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          23205    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        23205                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        21566                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27973.105815                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25131.407006                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 15236.984733                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        11031     51.15%     51.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535        10248     47.52%     98.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          108      0.50%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          142      0.66%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            2      0.01%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           12      0.06%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375            2      0.01%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           10      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            6      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        21566                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        20921     94.76%     94.76% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         1156      5.24%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        22077                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        20405     94.62%     94.62% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1161      5.38%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        21566                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        23826                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        23826                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        23205                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        23205                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        22077                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        22077                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        45903                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   136181387                       # ITB inst hits
-system.cpu1.itb.inst_misses                     23826                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        21566                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        21566                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        44771                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   135626159                       # ITB inst hits
+system.cpu1.itb.inst_misses                     23205                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1277                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               6462                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    159                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   16176                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               6096                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    163                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   16107                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               136205213                       # ITB inst accesses
-system.cpu1.itb.hits                        136181387                       # DTB hits
-system.cpu1.itb.misses                          23826                       # DTB misses
-system.cpu1.itb.accesses                    136205213                       # DTB accesses
-system.cpu1.numCycles                      1276125055                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               135649364                       # ITB inst accesses
+system.cpu1.itb.hits                        135626159                       # DTB hits
+system.cpu1.itb.misses                          23205                       # DTB misses
+system.cpu1.itb.accesses                    135649364                       # DTB accesses
+system.cpu1.numCycles                      1276121974                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  136088494                       # Number of instructions committed
-system.cpu1.committedOps                    159971532                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            146914767                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                136439                       # Number of float alu accesses
-system.cpu1.num_func_calls                    8067189                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     20777484                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   146914767                       # number of integer instructions
-system.cpu1.num_fp_insts                       136439                       # number of float instructions
-system.cpu1.num_int_register_reads          213265371                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         116491926                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              215836                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             125376                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            35465151                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           35400633                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     48930269                       # number of memory refs
-system.cpu1.num_load_insts                   25645213                       # Number of load instructions
-system.cpu1.num_store_insts                  23285056                       # Number of store instructions
-system.cpu1.num_idle_cycles              1249288140.787440                       # Number of idle cycles
-system.cpu1.num_busy_cycles              26836914.212560                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.021030                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.978970                       # Percentage of idle cycles
-system.cpu1.Branches                         30426471                       # Number of branches fetched
+system.cpu1.committedInsts                  135538016                       # Number of instructions committed
+system.cpu1.committedOps                    159130731                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            146160247                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                138681                       # Number of float alu accesses
+system.cpu1.num_func_calls                    7978033                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     20702063                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   146160247                       # number of integer instructions
+system.cpu1.num_fp_insts                       138681                       # number of float instructions
+system.cpu1.num_int_register_reads          211618661                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         115744147                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              219623                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             127108                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            35291781                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           35222922                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     48943439                       # number of memory refs
+system.cpu1.num_load_insts                   25723579                       # Number of load instructions
+system.cpu1.num_store_insts                  23219860                       # Number of store instructions
+system.cpu1.num_idle_cycles              1249309266.868014                       # Number of idle cycles
+system.cpu1.num_busy_cycles              26812707.131986                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021011                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978989                       # Percentage of idle cycles
+system.cpu1.Branches                         30260595                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                110766463     69.20%     69.20% # Class of executed instruction
-system.cpu1.op_class::IntMult                  334649      0.21%     69.41% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    13512      0.01%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             19532      0.01%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::MemRead                25645213     16.02%     85.45% # Class of executed instruction
-system.cpu1.op_class::MemWrite               23285056     14.55%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                109906813     69.03%     69.03% # Class of executed instruction
+system.cpu1.op_class::IntMult                  333855      0.21%     69.24% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    14527      0.01%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             20240      0.01%     69.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.26% # Class of executed instruction
+system.cpu1.op_class::MemRead                25723579     16.16%     85.42% # Class of executed instruction
+system.cpu1.op_class::MemWrite               23219860     14.58%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 160064425                       # Class of executed instruction
+system.cpu1.op_class::total                 159218874                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               97087615                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         66103650                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          4347660                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            66231841                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               47108077                       # Number of BTB hits
+system.cpu2.branchPred.lookups               96379868                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         65507682                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          4329047                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            66096416                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               46823178                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.126027                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS               12454763                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            133862                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            70.840722                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS               12400698                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            133614                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1349,88 +1349,86 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                   649855                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong               649855                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2        11017                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        66935                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksSquashedBefore       396890                       # Table walks squashed before starting
-system.cpu2.dtb.walker.walkWaitTime::samples       252965                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::mean  2053.590418                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::stdev 12193.038070                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0-65535       251454     99.40%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::65536-131071         1182      0.47%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::131072-196607          177      0.07%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::196608-262143           62      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::262144-327679           45      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walks                   662632                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong               662632                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2        11252                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        67139                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksSquashedBefore       410741                       # Table walks squashed before starting
+system.cpu2.dtb.walker.walkWaitTime::samples       251891                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::mean  2203.738919                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::stdev 12798.903480                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0-65535       250391     99.40%     99.40% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::65536-131071         1085      0.43%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::131072-196607          243      0.10%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::196608-262143           75      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::262144-327679           48      0.02%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu2.dtb.walker.walkWaitTime::327680-393215           26      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::393216-458751           17      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total       252965                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples       293492                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 21382.093181                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 17292.884496                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 15231.620197                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535       288902     98.44%     98.44% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-131071         4097      1.40%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607          265      0.09%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143          159      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679           56      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total       293492                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples 636867012660                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::mean     0.530422                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::stdev     0.615162                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0-3 636197778160     99.89%     99.89% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::4-7    383895000      0.06%     99.96% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::8-11    122059000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::12-15     78250500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::16-19     30640500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::20-23     15817000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::24-27     14461500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::28-31     20012000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::32-35      3793500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::36-39       253000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::40-43        22000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::44-47        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::48-51         6500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::52-55         3000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::56-59        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total 636867012660                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        66935     85.87%     85.87% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M        11017     14.13%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        77952                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data       649855                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkWaitTime::393216-458751           21      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total       251891                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples       304707                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 22494.824536                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 18425.462627                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 15718.326432                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-65535       298255     97.88%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-131071         5951      1.95%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-196607          243      0.08%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-262143          191      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-327679           38      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-393215           19      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total       304707                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 640151154620                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::mean     0.510260                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::stdev     0.628480                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0-3 639427998620     99.89%     99.89% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::4-7    404049000      0.06%     99.95% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::8-11    134377500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::12-15     87391000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::16-19     34713500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::20-23     17695000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::24-27     17014000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::28-31     22612000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::32-35      4758500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::36-39       448500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::40-43        50500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::44-47        27500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::48-51        19000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 640151154620                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K        67139     85.65%     85.65% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M        11252     14.35%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        78391                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data       662632                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total       649855                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        77952                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total       662632                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        78391                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        77952                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       727807                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        78391                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       741023                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    77417011                       # DTB read hits
-system.cpu2.dtb.read_misses                    450124                       # DTB read misses
-system.cpu2.dtb.write_hits                   59942200                       # DTB write hits
-system.cpu2.dtb.write_misses                   199731                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    76683824                       # DTB read hits
+system.cpu2.dtb.read_misses                    455088                       # DTB read misses
+system.cpu2.dtb.write_hits                   59509350                       # DTB write hits
+system.cpu2.dtb.write_misses                   207544                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1276                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid              14741                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    389                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   38279                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       93                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  6471                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid              14760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    390                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   38772                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       82                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  6499                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                    38915                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                77867135                       # DTB read accesses
-system.cpu2.dtb.write_accesses               60141931                       # DTB write accesses
+system.cpu2.dtb.perms_faults                    41159                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                77138912                       # DTB read accesses
+system.cpu2.dtb.write_accesses               59716894                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                        137359211                       # DTB hits
-system.cpu2.dtb.misses                         649855                       # DTB misses
-system.cpu2.dtb.accesses                    138009066                       # DTB accesses
+system.cpu2.dtb.hits                        136193174                       # DTB hits
+system.cpu2.dtb.misses                         662632                       # DTB misses
+system.cpu2.dtb.accesses                    136855806                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1460,395 +1458,394 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                    80378                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                80378                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         2425                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        55766                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksSquashedBefore        10589                       # Table walks squashed before starting
-system.cpu2.itb.walker.walkWaitTime::samples        69789                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::mean  1377.194114                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::stdev  8185.559112                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0-32767        69315     99.32%     99.32% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::32768-65535          221      0.32%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::65536-98303          162      0.23%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::98304-131071           61      0.09%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::163840-196607            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::262144-294911            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        69789                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        68780                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 26602.237307                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 22568.644275                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 16910.110071                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        37031     53.84%     53.84% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        30619     44.52%     98.36% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303          406      0.59%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071          526      0.76%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839           70      0.10%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607           66      0.10%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375           22      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143           14      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911            9      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::393216-425983            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                    81585                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                81585                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         2498                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        56536                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksSquashedBefore        10896                       # Table walks squashed before starting
+system.cpu2.itb.walker.walkWaitTime::samples        70689                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::mean  1473.991710                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::stdev  8586.891139                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0-32767        70027     99.06%     99.06% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::32768-65535          428      0.61%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::65536-98303          144      0.20%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::98304-131071           50      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::131072-163839           13      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::163840-196607           13      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::196608-229375            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::262144-294911            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::294912-327679            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        70689                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        69930                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 28234.749035                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 24509.520790                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 16350.855698                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        36490     52.18%     52.18% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        32158     45.99%     98.17% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303          628      0.90%     99.06% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071          491      0.70%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839           45      0.06%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           57      0.08%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375           23      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143           10      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::360448-393215            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        68780                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples 465075818820                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::mean     0.908790                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::stdev     0.288323                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0    42467517784      9.13%      9.13% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::1   422566839536     90.86%     99.99% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::2       36100000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::3        4751500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::4         426500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::5          73000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::6          66000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::7          44500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total 465075818820                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        55766     95.83%     95.83% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         2425      4.17%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        58191                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkCompletionTime::total        69930                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 485530683964                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::mean     0.892648                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::stdev     0.309939                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0    52174022580     10.75%     10.75% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::1   433310679884     89.24%     99.99% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::2       41019000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::3        4632000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::4         311000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::5          12000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::6           6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::7           1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 485530683964                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K        56536     95.77%     95.77% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         2498      4.23%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        59034                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        80378                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        80378                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        81585                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        81585                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        58191                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        58191                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total       138569                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    70175055                       # ITB inst hits
-system.cpu2.itb.inst_misses                     80378                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        59034                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        59034                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total       140619                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    69601857                       # ITB inst hits
+system.cpu2.itb.inst_misses                     81585                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1276                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid              14741                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    389                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   30057                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid              14760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    390                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   30530                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                   147979                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                   148496                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                70255433                       # ITB inst accesses
-system.cpu2.itb.hits                         70175055                       # DTB hits
-system.cpu2.itb.misses                          80378                       # DTB misses
-system.cpu2.itb.accesses                     70255433                       # DTB accesses
-system.cpu2.numCycles                       460136549                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                69683442                       # ITB inst accesses
+system.cpu2.itb.hits                         69601857                       # DTB hits
+system.cpu2.itb.misses                          81585                       # DTB misses
+system.cpu2.itb.accesses                     69683442                       # DTB accesses
+system.cpu2.numCycles                       461100419                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles         178152693                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     431776536                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   97087615                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          59562840                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    255654820                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                9805571                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                   1895155                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                7918                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1866                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles      3768954                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       115299                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         5484                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 70003785                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes              2663761                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                  31715                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         444504807                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.135202                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.375157                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles         177123206                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     428437277                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   96379868                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          59223876                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    257401667                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                9762973                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                   2005280                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                7949                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             2437                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles      3773015                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       114784                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         5106                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 69429398                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes              2656278                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                  32686                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         445314772                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.124877                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.366658                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0               338236255     76.09%     76.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                13308034      2.99%     79.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                13681319      3.08%     82.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 9908939      2.23%     84.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                20069262      4.51%     88.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                 6632314      1.49%     90.40% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 7130783      1.60%     92.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                 6321378      1.42%     93.43% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                29216523      6.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0               339836575     76.31%     76.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                13185142      2.96%     79.27% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                13574991      3.05%     82.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 9797674      2.20%     84.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                20004635      4.49%     89.02% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                 6578482      1.48%     90.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 7061868      1.59%     92.08% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                 6288982      1.41%     93.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                28986423      6.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           444504807                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.210997                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.938366                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles               145587242                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles            206867789                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 78822121                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              9322949                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               3902682                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved            14396196                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred              1015243                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts             471778409                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts              3111772                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               3902682                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles               151005109                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               15075303                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles     166939616                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 82595953                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             24983877                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             460482983                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                55875                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               1575989                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents               1122405                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents              11824382                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.FullRegisterEvents            2747                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands          440049969                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            701739830                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       543201034                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups           591948                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            368298602                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                71751367                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts          10111591                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts       8659381                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 51276485                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            74779146                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores           63098170                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          9504759                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores        10253668                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 437555873                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded           10088471                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                436351243                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           628919                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined       60028880                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     38531819                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        239828                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    444504807                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.981657                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.695270                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           445314772                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.209021                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.929163                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles               144945569                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles            209061419                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 78115064                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              9308814                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               3881927                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved            14332703                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred              1014310                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts             468249315                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts              3113109                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               3881927                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles               150342023                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               16281945                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles     167363518                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 81901775                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             25541188                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             457027313                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                55411                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               1577150                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents               1077305                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents              12432724                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.FullRegisterEvents            2850                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands          436738370                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            696876474                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       538877799                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups           611175                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            365603185                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                71135185                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts          10148334                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts       8698822                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 51282276                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            73817911                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores           62641049                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          9297155                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores        10241835                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 434108561                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded           10116895                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                433413553                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           631683                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined       59503474                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     37916216                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        236413                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    445314772                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.973275                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.689353                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0          276381275     62.18%     62.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1           68338590     15.37%     77.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2           31936602      7.18%     84.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3           22769301      5.12%     89.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           16982310      3.82%     93.68% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5           11978521      2.69%     96.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            8056839      1.81%     98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7            4822285      1.08%     99.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8            3239084      0.73%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0          278168249     62.47%     62.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1           68048730     15.28%     77.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2           31692331      7.12%     84.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3           22597394      5.07%     89.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           16978227      3.81%     93.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5           11874624      2.67%     96.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            7985798      1.79%     98.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7            4768189      1.07%     99.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8            3201230      0.72%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      444504807                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      445314772                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                2174414     25.25%     25.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                 16907      0.20%     25.44% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                   1448      0.02%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.46% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               3443156     39.98%     65.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite              2977212     34.57%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                2163580     25.08%     25.08% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                 17452      0.20%     25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                   1463      0.02%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               3490107     40.46%     65.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite              2952914     34.23%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass               20      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            295429003     67.70%     67.70% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult             1051015      0.24%     67.95% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                50004      0.01%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                103      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc         46521      0.01%     67.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     67.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            79012045     18.11%     86.07% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite           60762532     13.93%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            293684501     67.76%     67.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult             1025227      0.24%     68.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                47766      0.01%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                317      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   1      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc         48576      0.01%     68.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     68.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            78271434     18.06%     86.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite           60335731     13.92%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             436351243                       # Type of FU issued
-system.cpu2.iq.rate                          0.948308                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    8613137                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.019739                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads        1325660566                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        507771301                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    420349481                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             788783                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            391414                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       352523                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             444542452                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 421908                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads         3464909                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             433413553                       # Type of FU issued
+system.cpu2.iq.rate                          0.939955                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    8625516                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.019901                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads        1320585789                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        503812289                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    417285848                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             813288                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            405263                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       361974                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             441604210                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 434859                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads         3381259                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads     12199650                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses        16692                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation       497657                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores      6603925                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads     11998288                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses        16552                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation       496769                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores      6557326                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      2708670                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked      5665546                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      2684885                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked      5754188                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               3902682                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               10385108                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              3443992                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          447742813                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts          1337786                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             74779146                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts            63098170                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts           8466807                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                165633                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              3216656                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents        497657                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect       2020710                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect      1734931                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts             3755641                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            431226765                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             77404459                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts          4484174                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               3881927                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               10679636                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              4407291                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          444323917                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts          1337797                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             73817911                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts            62641049                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts           8508217                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                157244                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              4192594                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents        496769                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect       2009659                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect      1725096                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts             3734755                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            428275662                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             76671253                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts          4484086                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        98469                       # number of nop insts executed
-system.cpu2.iew.exec_refs                   137346126                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                80126150                       # Number of branches executed
-system.cpu2.iew.exec_stores                  59941667                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.937171                       # Inst execution rate
-system.cpu2.iew.wb_sent                     421619050                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    420702004                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                208179390                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                361509938                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        98461                       # number of nop insts executed
+system.cpu2.iew.exec_refs                   136179692                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                79539500                       # Number of branches executed
+system.cpu2.iew.exec_stores                  59508439                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.928812                       # Inst execution rate
+system.cpu2.iew.wb_sent                     418566552                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    417647822                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                206637380                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                358874398                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.914298                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.575861                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.905763                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.575793                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts       60056737                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls        9848643                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts          3347389                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    434346973                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.892410                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.889968                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts       59540982                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls        9880482                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts          3329329                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    435241532                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.883928                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.881300                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0    295032576     67.93%     67.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1     66481508     15.31%     83.23% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2     24486149      5.64%     88.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     11154018      2.57%     91.44% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4      8043816      1.85%     93.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5      4878030      1.12%     94.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      4540806      1.05%     95.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7      2951206      0.68%     96.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8     16778864      3.86%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0    296713491     68.17%     68.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1     66287598     15.23%     83.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2     24183303      5.56%     88.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     11166549      2.57%     91.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      8012002      1.84%     93.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5      4870056      1.12%     94.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      4489994      1.03%     95.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7      2918433      0.67%     96.19% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8     16600106      3.81%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    434346973                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           330373719                       # Number of instructions committed
-system.cpu2.commit.committedOps             387615464                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    435241532                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           327785464                       # Number of instructions committed
+system.cpu2.commit.committedOps             384721982                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                     119073741                       # Number of memory references committed
-system.cpu2.commit.loads                     62579496                       # Number of loads committed
-system.cpu2.commit.membars                    2588612                       # Number of memory barriers committed
-system.cpu2.commit.branches                  73762518                       # Number of branches committed
-system.cpu2.commit.fp_insts                    337914                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                356071087                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             9588871                       # Number of function calls committed.
+system.cpu2.commit.refs                     117903346                       # Number of memory references committed
+system.cpu2.commit.loads                     61819623                       # Number of loads committed
+system.cpu2.commit.membars                    2573370                       # Number of memory barriers committed
+system.cpu2.commit.branches                  73211237                       # Number of branches committed
+system.cpu2.commit.fp_insts                    346819                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                353394375                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             9534563                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       267662094     69.05%     69.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult         802922      0.21%     69.26% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           37337      0.01%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc        39370      0.01%     69.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead       62579496     16.14%     85.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite      56494245     14.57%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       265954850     69.13%     69.13% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult         786882      0.20%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           35653      0.01%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc        41251      0.01%     69.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead       61819623     16.07%     85.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite      56083723     14.58%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        387615464                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events             16778864                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   862595097                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  905518660                       # The number of ROB writes
-system.cpu2.timesIdled                        2960768                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       15631742                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                 99536690500                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  330373719                       # Number of Instructions Simulated
-system.cpu2.committedOps                    387615464                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.392776                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.392776                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.717991                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.717991                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               507371314                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              300778245                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                   673893                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                  409456                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                 92253105                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                93114012                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads              838596406                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes               9943766                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40265                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40265                       # Transaction distribution
+system.cpu2.commit.op_class_0::total        384721982                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events             16600106                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   860271406                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  898612976                       # The number of ROB writes
+system.cpu2.timesIdled                        2954119                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       15785647                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                 99456385277                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  327785464                       # Number of Instructions Simulated
+system.cpu2.committedOps                    384721982                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.406714                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.406714                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.710877                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.710877                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               503674657                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              298593848                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                   690106                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                  421944                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                 91580916                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                92419773                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads              837090025                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes               9982057                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40263                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40263                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136537                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29873                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136537                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1865,11 +1862,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122568                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230956                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353604                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1886,93 +1883,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155698                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334240                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492040                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13825000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492024                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13118000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             8203000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             7299000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy               33000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy            16991000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           196611881                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           175678218                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            39351000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            37744000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36922037                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            35540000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy               80000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115459                       # number of replacements
-system.iocache.tags.tagsinuse               10.421568                       # Cycle average of tags in use
+system.iocache.tags.replacements               115457                       # number of replacements
+system.iocache.tags.tagsinuse               10.416552                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13085930884009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.547277                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.874291                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221705                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429643                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651348                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13085993128009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.913060                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.503492                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.369566                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.281468                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651035                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039659                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039659                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039641                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039641                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8814                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8851                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8812                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8849                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8812                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8852                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
-system.iocache.overall_misses::total             8854                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8812                       # number of overall misses
+system.iocache.overall_misses::total             8852                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      2432000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide     61206163                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     63638163                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6636577681                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6636577681                       # number of WriteInvalidateReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     80359879                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     82791879                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   3987954339                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   3987954339                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      2432000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide     61206163                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     63638163                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide     80359879                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     82791879                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      2432000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide     61206163                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     63638163                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide     80359879                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     82791879                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8812                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8849                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8812                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8852                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8812                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8852                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -1980,409 +1977,424 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide  6944.198207                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total  7189.940459                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 62219.471246                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 62219.471246                       # average WriteInvalidateReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide  9119.368929                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total  9356.071760                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 37388.006628                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 37388.006628                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet        60800                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide  6944.198207                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total  7187.504292                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide  9119.368929                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total  9352.900926                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet        60800                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide  6944.198207                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total  7187.504292                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         24555                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide  9119.368929                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total  9352.900926                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1026                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3712                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                  106                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.615032                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.679245                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           16                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide          424                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          440                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        35584                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        35584                       # number of WriteInvalidateReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          518                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          534                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        33736                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        33736                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           16                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          424                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          440                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          518                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          534                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           16                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          424                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          440                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      1600000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     38938201                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     40538201                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4786173717                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4786173717                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      1600000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     38938201                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     40538201                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      1600000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     38938201                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     40538201                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide          518                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          534                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      1632000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     54459879                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     56091879                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2301154339                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2301154339                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      1632000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     54459879                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     56091879                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      1632000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     54459879                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     56091879                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet     0.432432                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.048105                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.049712                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.333608                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.333608                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.058783                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.060346                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.316283                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.316283                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.048105                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.049695                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.058783                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.060325                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.048105                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.049695                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet       100000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 91835.379717                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 92132.275000                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134503.532964                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134503.532964                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet       100000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 91835.379717                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 92132.275000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet       100000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 91835.379717                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 92132.275000                       # average overall mshr miss latency
+system.iocache.overall_mshr_miss_rate::realview.ide     0.058783                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.060325                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet       102000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105134.901544                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105040.971910                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68210.645571                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68210.645571                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet       102000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 105134.901544                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 105040.971910                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet       102000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 105134.901544                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 105040.971910                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1296366                       # number of replacements
-system.l2c.tags.tagsinuse                65320.100787                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   28848747                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1358615                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.233938                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1303829                       # number of replacements
+system.l2c.tags.tagsinuse                65263.667418                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   45613639                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1366689                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    33.375288                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37068.766455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   192.906222                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   268.941849                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3824.960525                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8195.071890                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    57.414493                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    82.820036                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      874.447112                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2433.555862                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    94.156487                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker   158.776869                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2237.420000                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     9830.862987                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.565624                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002944                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004104                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.058364                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.125047                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000876                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001264                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.013343                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037133                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001437                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.002423                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034140                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.150007                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996706                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          358                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61891                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          358                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          590                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2804                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4928                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53429                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005463                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.944382                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                273721010                       # Number of tag accesses
-system.l2c.tags.data_accesses               273721010                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       197948                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       127305                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            6549451                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3139875                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        71739                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        49467                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            2103694                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             962152                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       389616                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker       148852                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst            5808812                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data            2494651                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               22043562                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7872498                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7872498                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       348712                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       112622                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu2.data       261017                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       722351                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data            4748                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1579                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            3377                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9704                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           802024                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           244881                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           560523                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1607428                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        197948                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        127305                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6549451                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3941899                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         71739                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         49467                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             2103694                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             1207033                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        389616                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker        148852                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             5808812                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             3055174                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                23650990                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       197948                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       127305                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6549451                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3941899                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        71739                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        49467                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            2103694                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            1207033                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       389616                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker       148852                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            5808812                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            3055174                       # number of overall hits
-system.l2c.overall_hits::total               23650990                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1815                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1875                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            43522                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           134746                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          628                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker          584                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            11774                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data            35186                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker         1454                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker         1485                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst            34248                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data           112174                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               379491                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       402597                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data        31349                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu2.data        75410                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       509356                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         17318                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          5542                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data         12758                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             35618                       # number of UpgradeReq misses
+system.l2c.tags.occ_blocks::writebacks   37041.292991                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   185.441819                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   257.864893                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3799.344283                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     8420.169172                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    49.795293                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    72.886191                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      899.312109                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2654.836821                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker   113.517705                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker   173.967622                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2205.940609                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     9389.297910                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.565205                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002830                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003935                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.057973                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.128482                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000760                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.001112                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.013722                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.040510                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001732                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.002655                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.033660                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.143269                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995845                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          366                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62494                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          365                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          561                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2733                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4954                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54104                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005585                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.953583                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                407870689                       # Number of tag accesses
+system.l2c.tags.data_accesses               407870689                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       197247                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       127080                       # number of ReadReq hits
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 system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadReq_accesses::cpu1.itb.walker        49596                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker       391386                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker       154398                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             998491                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      7849789                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          7849789                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        22564                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         6874                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data        16146                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           45584                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1062167                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       321030                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       727789                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2110986                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       199763                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       129180                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         6592973                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         4336788                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        72367                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        50051                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         2115468                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1318368                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       391070                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker       150337                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst         5843060                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data         3334614                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            24534039                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       199763                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       129180                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        6592973                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4336788                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        72367                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        50051                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        2115468                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1318368                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       391070                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker       150337                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        5843060                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        3334614                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           24534039                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009086                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.014515                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.006601                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.041149                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008678                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011668                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.005566                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.035280                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003718                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.009878                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.005861                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.043031                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016924                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.535861                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.217745                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu2.data     0.224150                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.413537                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784827                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.778261                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.790703                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.785888                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_accesses::cpu2.data            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             9                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data       316245                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data       728126                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          2106266                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      6587154                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      2095893                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst      5821643                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      14504690                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3270233                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      1022459                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data      2563568                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6856260                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       753152                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       142541                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data       336291                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1231984                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       199225                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       129039                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.data         1338704                       # number of demand (read+write) accesses
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+system.l2c.overall_accesses::cpu0.dtb.walker       199225                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       129039                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total           24465707                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009928                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.015181                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008097                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011251                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003833                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008880                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.007984                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.783859                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784841                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.785953                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.784749                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.244917                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.237202                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.229828                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.238542                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009086                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.014515                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006601                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.091056                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008678                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.011668                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005566                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.084449                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003718                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.009878                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.005861                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.083800                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.035993                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009086                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.014515                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006601                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.091056                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008678                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.011668                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005566                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.084449                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003718                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.009878                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005861                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.083800                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.035993                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84450.238854                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87988.869863                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81296.394598                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 83212.016143                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 90213.551582                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89692.767003                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86197.814471                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 92670.946485                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 46381.178378                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data     0.988835                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu2.data    11.974155                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total     1.833629                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15156.584807                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 16080.532842                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  8118.177073                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.142857                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.246195                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.242929                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.229013                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.239765                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006554                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005529                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006094                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.006221                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042390                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034586                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.043043                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.041471                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.542888                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.200405                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.213975                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.413480                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009928                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.015181                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006554                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.092347                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008097                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.011251                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005529                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.083803                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003833                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.008880                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.006094                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.084180                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.036277                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009928                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.015181                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006554                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.092347                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008097                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.011251                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005529                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.083803                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003833                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.008880                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.006094                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.084180                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.036277                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87405.115512                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88004.480287                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87642.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89278.993435                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 44648.645258                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15418.350324                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15993.892829                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  7999.119423                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80514.506756                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100866.366111                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 45680.165480                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84450.238854                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87988.869863                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81296.394598                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 81367.020030                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 90213.551582                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89692.767003                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 86197.814471                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 97576.525712                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 45981.426323                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84450.238854                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87988.869863                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81296.394598                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 81367.020030                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 90213.551582                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89692.767003                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 86197.814471                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 97576.525712                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 45981.426323                       # average overall miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        53000                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80389.886105                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 99519.277361                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 45089.963921                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81136.002761                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85587.758611                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 44067.891179                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82704.889291                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 92370.527623                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 46133.324306                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79702.793531                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 106667.166959                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 19537.350732                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87405.115512                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88004.480287                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 81136.002761                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 81119.602810                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87642.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89278.993435                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 85587.758611                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 96672.511855                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 45316.329842                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87405.115512                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88004.480287                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 81136.002761                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 81119.602810                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87642.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89278.993435                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 85587.758611                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 96672.511855                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 45316.329842                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2391,251 +2403,270 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1099475                       # number of writebacks
-system.l2c.writebacks::total                  1099475                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker            8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.itb.walker           15                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                25                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.dtb.walker            8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.itb.walker           15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 25                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.dtb.walker            8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.itb.walker           15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                25                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          628                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          584                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        11774                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data        35186                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker         1446                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu2.data       112172                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          197508                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data        31349                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu2.data        75410                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total       106759                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         5542                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data        12758                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        18300                       # number of UpgradeReq MSHR misses
+system.l2c.writebacks::writebacks             1103217                       # number of writebacks
+system.l2c.writebacks::total                  1103217                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker           11                       # number of ReadReq MSHR hits
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+system.l2c.ReadReq_mshr_hits::total                33                       # number of ReadReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.dtb.walker           11                       # number of demand (read+write) MSHR hits
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+system.l2c.demand_mshr_hits::cpu2.data              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 38                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.dtb.walker           11                       # number of overall MSHR hits
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+system.l2c.ReadReq_mshr_misses::total            4002                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks          328                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total          328                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         5395                       # number of UpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::total        18085                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        76149                       # number of ReadExReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::total        243415                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker          628                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          584                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.data       111335                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu2.data       279438                       # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.dtb.walker          628                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total          440923                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5448                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         8279                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        13727                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5373                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         7916                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13289                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10821                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data        16195                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        27016                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     45139750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     44046000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    809585750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data   2487118500                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu2.data   8999138499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15134168260                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data    987692501                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data   2488109529                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total   3475802030                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     97166042                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    226510254                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    323676296                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       135000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       135000                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14796575906                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  19975212231                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     45139750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     44046000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    809585750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   7665754825                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    113691259                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu2.data  23795714405                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  35109380491                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     45139750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     44046000                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu2.data  23795714405                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  35109380491                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    818834500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1358915500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2177750000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    825245000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1335319496                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2160564496                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1644079500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2694234996                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4338314496                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008678                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011668                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005566                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.035280                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003698                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.009778                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005861                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.043030                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.008808                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.217745                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.224150                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.086676                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.778261                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.790703                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.403777                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
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+system.l2c.InvalidateReq_mshr_misses::total       100524                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker          606                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker          558                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        11588                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       112188                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker         1489                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker         1349                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst        35478                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data       277089                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           440345                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker          606                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker          558                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        11588                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       112188                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker         1489                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker         1349                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst        35478                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data       277089                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          440345                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         4998                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         8152                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        13150                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4942                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         7788                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        12730                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         9940                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data        15940                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        25880                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     46907500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     43526500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker    115771000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    107384500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    313589500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    111371500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    263334500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    374706000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       139000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        20500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       159500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5407703000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14927339500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  20335042500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    824324000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2681702500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   3506026500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2571063000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   9088897000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  11659960000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1991130000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   6955976000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total   8947106000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     46907500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     43526500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    824324000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   7978766000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker    115771000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    107384500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   2681702500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data  24016236500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  35814618500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     46907500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     43526500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    824324000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   7978766000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker    115771000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    107384500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   2681702500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data  24016236500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  35814618500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    763712000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1373074000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2136786000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    770891000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1347269000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2118160000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1534603000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2720343000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4254946000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008097                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011251                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003804                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.008737                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.004008                       # mshr miss rate for ReadReq accesses
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784841                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.785953                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.396740                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.237202                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.229828                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.115309                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008678                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011668                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005566                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.084449                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003698                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.009778                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005861                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.083799                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.017972                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008678                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011668                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005566                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.084449                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003698                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.009778                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005861                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.083799                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.017972                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68760.467980                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70684.888876                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73676.090575                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 80226.246291                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 76625.596229                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31506.347922                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 32994.424201                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32557.461479                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17532.667268                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17754.370121                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17687.229290                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68006.622871                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 88461.348427                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 82062.371797                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68760.467980                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68853.054520                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73676.090575                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 85155.613786                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 79627.010818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68760.467980                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68853.054520                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 79627.010818                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150300.018355                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 164140.053147                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 158647.191666                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 153591.103666                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 168686.141486                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162582.925427                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151934.155808                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 166362.148564                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 160583.154279                       # average overall mshr uncacheable latency
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.142857                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.242929                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.229013                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.115643                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005529                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006094                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003245                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034586                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.043041                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021251                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.200405                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.213975                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.081595                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008097                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005529                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.083803                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003804                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008737                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006094                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.084178                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.017998                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008097                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005529                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.083803                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003804                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008737                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006094                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.084178                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.017998                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 78358.195902                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20643.466172                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20751.339638                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20719.159524                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        20500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70389.886105                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 89519.277361                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 83485.753875                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71136.002761                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75587.758611                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74491.703140                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72704.889291                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 82372.479359                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80026.080630                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69702.793531                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 96667.166959                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 89004.675500                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71136.002761                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71119.602810                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75587.758611                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86673.366680                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 81333.087693                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71136.002761                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71119.602810                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75587.758611                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86673.366680                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 81333.087693                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152803.521409                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168434.003925                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 162493.231939                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 155987.656819                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 172992.937853                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 166391.201885                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154386.619718                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 170661.417817                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 164410.587326                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              465050                       # Transaction distribution
-system.membus.trans_dist::ReadResp             465050                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76733                       # Transaction distribution
+system.membus.trans_dist::ReadResp             468089                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33644                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33644                       # Transaction distribution
-system.membus.trans_dist::Writeback           1206105                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       615969                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       615969                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36256                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36258                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            502974                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           502974                       # Transaction distribution
+system.membus.trans_dist::Writeback           1209847                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           210029                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36410                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36413                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1013774                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1013774                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        391356                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122568                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4046690                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4176068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4513354                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4261294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4390673                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       345792                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       345792                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4736465                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155698                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159620960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    159790354                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14192960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14192960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               173983314                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              541                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2860073                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    160146208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    160315602                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7368448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7368448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               167684050                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              579                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3078821                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2860073    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3078821    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2860073                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            47655000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3078821                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            45758500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1342002                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1294500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3662717737                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3125844189                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2514330197                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2930708426                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37911963                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           61033927                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2679,51 +2710,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           22942749                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          22942559                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            1510117                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          22871416                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33644                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33644                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7872498                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1267320                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1231707                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45322                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45326                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2110986                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2110986                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29189373                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28540858                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       848998                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1760970                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              60340199                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    931468564                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1158220350                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3098688                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6299696                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2099087298                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          376855                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         34352020                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.045142                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.207615                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback          8317119                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        16946911                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           45584                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             9                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          45593                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2106266                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2106266                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      14504828                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6856794                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1265720                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1231984                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     43598497                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30808593                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       852484                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1760318                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              77019892                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    928472660                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1076191614                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3123312                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6312032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2014099618                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          938060                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         51670008                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.040962                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.198203                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               32801302     95.49%     95.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1550718      4.51%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               49553478     95.90%     95.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                2116530      4.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           34352020                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        13384646524                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           51670008                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        17416968994                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           375000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           316500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       11949873226                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       11880834300                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7318478020                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7217033015                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         275201891                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         275805669                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         650856160                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         649517949                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index f9affe46b..fa15729bd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,157 +1,157 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.318118                       # Number of seconds simulated
-sim_ticks                                51318118168000                       # Number of ticks simulated
-final_tick                               51318118168000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.321386                       # Number of seconds simulated
+sim_ticks                                51321386217000                       # Number of ticks simulated
+final_tick                               51321386217000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134879                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158483                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7620199718                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 732720                       # Number of bytes of host memory used
-host_seconds                                  6734.48                       # Real time elapsed on the host
-sim_insts                                   908340493                       # Number of instructions simulated
-sim_ops                                    1067303522                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 131020                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153952                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7451916901                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 738104                       # Number of bytes of host memory used
+host_seconds                                  6887.00                       # Real time elapsed on the host
+sim_insts                                   902332774                       # Number of instructions simulated
+sim_ops                                    1060266688                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       160000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       146112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3855296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         28386264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       162496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       145216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3634496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         27952240                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        430656                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             64872776                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3855296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3634496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7489792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     83283200                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       154240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       142464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4107136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         45245848                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       165376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       158016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3334400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         43223216                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        435264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             96965960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4107136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3334400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7441536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     82289920                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          83303780                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2500                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2283                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             60239                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            443543                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2539                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2269                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56789                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            436759                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6729                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1013650                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1301300                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          82310500                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2410                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2226                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             64174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            706974                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2584                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2469                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             52100                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            675368                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6801                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1515106                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1285780                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1303873                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2847                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               75125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              553143                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3166                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               70823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              544686                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8392                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1264130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          75125                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          70823                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             145948                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1622881                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1288353                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2776                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               80028                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              881618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64971                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              842207                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1889387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          80028                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64971                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             144999                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1603424                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1623282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1622881                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2847                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              75125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             553544                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3166                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              70823                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             544686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2887412                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1013650                       # Number of read requests accepted
-system.physmem.writeReqs                      1930075                       # Number of write requests accepted
-system.physmem.readBursts                     1013650                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1930075                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 64838144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     35456                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 120356480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  64872776                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              123380708                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      554                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   49498                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          37388                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               61871                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               62981                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               60043                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               58309                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               58023                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               70636                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62371                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               61877                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57508                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               84884                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              63101                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              65471                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              60660                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              66399                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              58532                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              60430                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              115217                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              115969                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              118272                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              117255                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              115771                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              124355                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              120059                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              119259                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              113485                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              118397                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             117107                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             118510                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             116303                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             122603                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             113656                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             114352                       # Per bank write bursts
+system.physmem.bw_write::total                1603825                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1603424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3005                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2776                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              80028                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             882019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              64971                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             842207                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3493212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1515106                       # Number of read requests accepted
+system.physmem.writeReqs                      1288353                       # Number of write requests accepted
+system.physmem.readBursts                     1515106                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1288353                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 96901440                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     65344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  82309952                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  96965960                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               82310500                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1021                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         144011                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               91435                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               93225                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               89718                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               87919                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               92611                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              102433                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               93232                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               90056                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               87362                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              117909                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              95229                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              97284                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              90073                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             103730                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              91691                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              90178                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               77827                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               79309                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               76608                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               77829                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               80050                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               85847                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               79718                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               79449                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               76360                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               83802                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              81643                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              83145                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              78123                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              87627                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              79500                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              79256                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         644                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51318117066500                       # Total gap between requests
+system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51321385112000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1013635                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1515091                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1927502                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    564185                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    294633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    102008                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     45915                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       557                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       502                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       491                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      126                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      115                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1285780                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    688629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    426852                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    228074                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    164413                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       987                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       541                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       875                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       956                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      461                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      128                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -162,175 +162,189 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      736                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    29010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    66066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    62259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    89013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    88926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   107579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   106733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   116711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   108023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   122723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   101978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   129145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   103612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    95256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   108517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    90319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    86324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    81769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     9575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     8389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     8185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     9213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     9986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     8806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     9359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     9979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     8573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     8083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     7257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     7806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     7695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     6239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     6318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     5151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     4640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     3740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     3115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     3218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     3055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     2506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     3036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     2297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     2830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                     2028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                     4689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                     2118                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       627585                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      295.090291                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     168.534210                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.652886                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         259317     41.32%     41.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       149298     23.79%     65.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        56496      9.00%     74.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        28437      4.53%     78.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21665      3.45%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12676      2.02%     84.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        11310      1.80%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8646      1.38%     87.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        79740     12.71%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         627585                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         69573                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.561338                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       62.076495                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           69566     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           69573                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         69573                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.030170                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.998159                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       37.100716                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-31            59064     84.90%     84.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-63            4267      6.13%     91.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95            4153      5.97%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127            990      1.42%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159           298      0.43%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191           151      0.22%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223            89      0.13%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255            92      0.13%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287           109      0.16%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-319           106      0.15%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-351            80      0.11%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383            57      0.08%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415            25      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-447            19      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479            14      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511            19      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543            11      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-575             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-607             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-639             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-671             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-703             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-767             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-799             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::960-991             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1152-1183            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1600-1631            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           69573                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    27603415095                       # Total ticks spent queuing
-system.physmem.totMemAccLat               46598965095                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5065480000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27246.59                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::12                      728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      722                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::32                    77173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      734                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::51                      258                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       590002                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.746442                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.840046                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.017877                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         235290     39.88%     39.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       136180     23.08%     62.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        56828      9.63%     72.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27605      4.68%     77.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        24232      4.11%     81.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        13797      2.34%     83.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        13359      2.26%     85.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9785      1.66%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        72926     12.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         590002                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         74241                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.393489                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      234.888851                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          74237     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::61440-63487            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           74241                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         74241                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.323218                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.863934                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.335765                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                39      0.05%      0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                11      0.01%      0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               20      0.03%      0.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              65      0.09%      0.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           70112     94.44%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1316      1.77%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             568      0.77%     97.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             346      0.47%     97.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             342      0.46%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             528      0.71%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             134      0.18%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.05%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              41      0.06%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              27      0.04%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              42      0.06%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              26      0.04%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             396      0.53%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              32      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              46      0.06%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              38      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               9      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            24      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           74241                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    44116098728                       # Total ticks spent queuing
+system.physmem.totMemAccLat               72505192478                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7570425000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29137.13                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45996.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.26                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.35                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.26                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.40                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47887.13                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.19                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     781690                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1484389                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17433054.06                       # Average gap between requests
-system.physmem.pageHitRate                      78.31                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2390683680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1304440500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3869626800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6131097360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3351849795840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1233875646405                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29708521981500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34307943272085                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.534751                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49422598441359                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713624640000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        11.13                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1245847                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    964327                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.28                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18306451.11                       # Average gap between requests
+system.physmem.pageHitRate                      78.93                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2222337600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1212585000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5776859400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4125407760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1232605432755                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29711598339000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34309604352555                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.524518                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49427675587817                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713733840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    181894714141                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    179976420183                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2353858920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1284347625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4032475200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               6054996240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3351849795840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1235994503985                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29706663342750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34308233320560                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.540403                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49419482573169                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713624640000                       # Time in different power states
+system.physmem_1.actEnergy                 2238077520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1221173250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6032956800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4208474880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1237235987925                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29707536448500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34310536509915                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.542681                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49420862619804                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713733840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    185010821331                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    186788845196                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -360,15 +374,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              133240776                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         90773806                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5898398                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            90806413                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               65300191                       # Number of BTB hits
+system.cpu0.branchPred.lookups              132571032                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         90050105                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5878539                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            90490581                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               64975080                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.911431                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17271308                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            187435                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.803142                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17318147                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            190057                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -399,86 +413,94 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   900960                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               900960                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16847                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        91388                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       546326                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       354634                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2141.455698                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 12590.575916                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       352292     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1866      0.53%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          247      0.07%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143           95      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           68      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           37      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       354634                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       411836                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 21432.646658                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17288.307814                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16337.255715                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       405278     98.41%     98.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         5723      1.39%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          333      0.08%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          332      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           90      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           39      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           17      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   913008                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               913008                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16692                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        92976                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       560771                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       352237                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2376.777567                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 13703.858808                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-32767       344408     97.78%     97.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-65535         5384      1.53%     99.31% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-98303          983      0.28%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-131071          725      0.21%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-163839          276      0.08%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::163840-196607          169      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-229375           94      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::229376-262143           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-294911           59      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::294912-327679           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-360447           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::360448-393215           25      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-425983           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::425984-458751            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-491519            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::491520-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       352237                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       421207                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22517.986406                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18384.767938                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16267.103719                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       412281     97.88%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8071      1.92%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          392      0.09%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          363      0.09%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       411836                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 323720569592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.132299                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.681450                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 322818413592     99.72%     99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    497609500      0.15%     99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    179612000      0.06%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    106469500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     44651500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     21065000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     19836500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     27755000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      4822000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       304000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        19500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47         8500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51         3000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 323720569592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        91388     84.43%     84.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        16847     15.57%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       108235                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       900960                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total       421207                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 353008884868                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.117411                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.682149                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 352021835868     99.72%     99.72% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    541843500      0.15%     99.87% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    193463500      0.05%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    118741500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     46634500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     24285000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     23543000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     31748500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      6046000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       436000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        56500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47        38500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        27500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::52-55       185000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 353008884868                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        92977     84.78%     84.78% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        16692     15.22%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       109669                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       913008                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       900960                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       108235                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       913008                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       109669                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       108235                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total      1009195                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       109669                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total      1022677                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   105886901                       # DTB read hits
-system.cpu0.dtb.read_misses                    623655                       # DTB read misses
-system.cpu0.dtb.write_hits                   81874264                       # DTB write hits
-system.cpu0.dtb.write_misses                   277305                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1077                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   104802286                       # DTB read hits
+system.cpu0.dtb.read_misses                    628192                       # DTB read misses
+system.cpu0.dtb.write_hits                   81730320                       # DTB write hits
+system.cpu0.dtb.write_misses                   284816                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1079                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              22243                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    520                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   54719                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      205                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9949                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   54383                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      188                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9307                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    55268                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               106510556                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82151569                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56122                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               105430478                       # DTB read accesses
+system.cpu0.dtb.write_accesses               82015136                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        187761165                       # DTB hits
-system.cpu0.dtb.misses                         900960                       # DTB misses
-system.cpu0.dtb.accesses                    188662125                       # DTB accesses
+system.cpu0.dtb.hits                        186532606                       # DTB hits
+system.cpu0.dtb.misses                         913008                       # DTB misses
+system.cpu0.dtb.accesses                    187445614                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -508,851 +530,847 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   103995                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               103995                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2920                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        70184                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        13953                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        90042                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1564.791986                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  9356.128105                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        89344     99.22%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          299      0.33%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          238      0.26%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          101      0.11%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           19      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375           12      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                   102934                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               102934                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2830                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69670                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14211                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        88723                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1670.198257                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  9993.098637                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        87793     98.95%     98.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          509      0.57%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          243      0.27%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           94      0.11%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           34      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           21      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        90042                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        87057                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26438.085553                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21999.622082                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 18398.516639                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        48630     55.86%     55.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535        36690     42.14%     98.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          630      0.72%     98.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          790      0.91%     99.64% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839          103      0.12%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           96      0.11%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           32      0.04%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           31      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           24      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447           10      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        87057                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 276399275336                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.905006                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -250074257964    -90.48%    -90.48% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   526414060300    190.45%     99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       52102500      0.02%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        6093500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         943000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         232500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6          42500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::7          59000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 276399275336                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        70184     96.01%     96.01% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2920      3.99%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        73104                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::total        88723                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        86711                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 27827.271050                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23655.790569                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18399.370737                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        84751     97.74%     97.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1686      1.94%     99.68% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          179      0.21%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           53      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        86711                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 499035191932                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.085193                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -42443239012     -8.51%     -8.51% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   541415505444    108.49%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       55393500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        6761000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         722500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          48000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6            500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 499035191932                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        69670     96.10%     96.10% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2830      3.90%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72500                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       103995                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       103995                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102934                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102934                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        73104                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        73104                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       177099                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    95374234                       # ITB inst hits
-system.cpu0.itb.inst_misses                    103995                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72500                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72500                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       175434                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    95094277                       # ITB inst hits
+system.cpu0.itb.inst_misses                    102934                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1077                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1079                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              22243                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    520                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40386                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   40091                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   207806                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   207907                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                95478229                       # ITB inst accesses
-system.cpu0.itb.hits                         95374234                       # DTB hits
-system.cpu0.itb.misses                         103995                       # DTB misses
-system.cpu0.itb.accesses                     95478229                       # DTB accesses
-system.cpu0.numCycles                       670757384                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                95197211                       # ITB inst accesses
+system.cpu0.itb.hits                         95094277                       # DTB hits
+system.cpu0.itb.misses                         102934                       # DTB misses
+system.cpu0.itb.accesses                     95197211                       # DTB accesses
+system.cpu0.numCycles                       675702202                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         244295585                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     592642803                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  133240776                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          82571499                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    387821427                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13413764                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2417197                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               21066                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             3440                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5441880                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       164758                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         2028                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 95148929                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3635106                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  41714                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         646873994                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.071808                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.317751                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         244757501                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     589419880                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  132571032                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          82293227                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    391738714                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13356245                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2509355                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               22606                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             4900                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5469917                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       167540                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         2725                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 94868898                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3621980                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  41300                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         651351111                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.059349                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.306953                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               500514392     77.37%     77.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18314774      2.83%     80.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18453367      2.85%     83.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13440049      2.08%     85.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                29078999      4.50%     89.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 9061143      1.40%     91.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9714650      1.50%     92.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8499613      1.31%     93.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39797007      6.15%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               505677761     77.64%     77.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                18279909      2.81%     80.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18243298      2.80%     83.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13516535      2.08%     85.32% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28852465      4.43%     89.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8999693      1.38%     91.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9719421      1.49%     92.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8528805      1.31%     93.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                39533224      6.07%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           646873994                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.198642                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.883543                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               198183326                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            323426019                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105981621                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13950733                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5329290                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19638547                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1397625                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             646526277                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4318123                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5329290                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               205971985                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               23697587                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     259101155                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                111995163                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             40775442                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             631047036                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                83751                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2209243                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1613560                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              20761963                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3444                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          605295621                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            976490610                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       746368883                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           733214                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            508351996                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96943625                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15774650                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13795198                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 78408950                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           101681556                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           86254396                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13698017                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14540360                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 598113520                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15856672                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                599090036                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           857856                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       81807793                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     52627296                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        360655                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    646873994                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.926131                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.649248                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           651351111                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.196197                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.872307                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               198764731                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            327769223                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                105831567                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13682981                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5300378                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19660361                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1397395                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             643175990                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4312729                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5300378                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               206434504                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               26397501                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     257870314                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                111703786                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             43642083                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             627780362                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                81911                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1880696                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1582827                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              24120192                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3699                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          601307944                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            969598831                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       742471294                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           750947                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            504947564                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                96360375                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15500464                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13524428                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 76866665                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           101145902                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           86060501                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13628383                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14576675                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 595266457                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15567772                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                595602490                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           860155                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       81220997                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     52302062                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        356361                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    651351111                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.914411                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.641831                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          410738698     63.50%     63.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          100810060     15.58%     79.08% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43443549      6.72%     85.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           31018554      4.80%     90.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           22931602      3.54%     94.14% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16104373      2.49%     96.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           11033021      1.71%     98.33% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6462279      1.00%     99.33% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4331858      0.67%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          416907124     64.01%     64.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           99553383     15.28%     79.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           43434757      6.67%     85.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           30928180      4.75%     90.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           22872426      3.51%     94.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           16003542      2.46%     96.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10950121      1.68%     98.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6425711      0.99%     99.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4275867      0.66%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      646873994                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      651351111                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2999808     25.24%     25.24% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 22948      0.19%     25.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2663      0.02%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               3      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4871857     40.99%     66.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3988147     33.55%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2977313     25.58%     25.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 21726      0.19%     25.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2146      0.02%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4737742     40.71%     66.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3899084     33.50%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                4      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            406422040     67.84%     67.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1476912      0.25%     68.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                65361      0.01%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 96      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         58788      0.01%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           108073598     18.04%     86.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82993236     13.85%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               69      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            404218599     67.87%     67.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1425375      0.24%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                67506      0.01%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                 50      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         58410      0.01%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           106977397     17.96%     86.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           82855084     13.91%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             599090036                       # Type of FU issued
-system.cpu0.iq.rate                          0.893155                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11885426                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019839                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1856813329                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        695962848                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    576693438                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             984019                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            489184                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       438468                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             610449620                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 525838                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4726109                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             595602490                       # Type of FU issued
+system.cpu0.iq.rate                          0.881457                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11638012                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019540                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1854047614                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        692214073                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    573874162                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1006644                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            498985                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       447097                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             606702343                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 538090                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4757420                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16731454                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        21127                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       684950                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      9161643                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16585910                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        22662                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       668240                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      9092320                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3853062                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      8592397                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3863731                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      7820378                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5329290                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               14836046                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              7169747                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          614106722                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1810261                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            101681556                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            86254396                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13499171                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                248453                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              6830033                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        684950                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2723761                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2339558                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5063319                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            592213762                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            105878130                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5990174                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5300378                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15293530                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              9669423                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          610970772                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1799898                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            101145902                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            86060501                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13228626                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                242900                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              9335617                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        668240                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2719159                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2323934                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5043093                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            588743474                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            104791307                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5960112                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       136530                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   187756937                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               109862908                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81878807                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.882903                       # Inst execution rate
-system.cpu0.iew.wb_sent                     578421970                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    577131906                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                284711853                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                494921051                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       136543                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   186525171                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               109265890                       # Number of branches executed
+system.cpu0.iew.exec_stores                  81733864                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.871306                       # Inst execution rate
+system.cpu0.iew.wb_sent                     575597633                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    574321259                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                283300170                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                492230600                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.860418                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575267                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.849962                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575544                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       81841846                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15496017                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4520537                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    632994694                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.840706                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.831217                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       81268346                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15211411                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4500525                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    637573218                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.830670                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.824266                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    436057133     68.89%     68.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     98370072     15.54%     84.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33369017      5.27%     89.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15116509      2.39%     92.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10820224      1.71%     93.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6529796      1.03%     94.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6075579      0.96%     95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3929496      0.62%     96.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22726868      3.59%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    442173264     69.35%     69.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     97173464     15.24%     84.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     33154077      5.20%     89.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15182673      2.38%     92.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10793922      1.69%     93.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6469162      1.01%     94.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6019139      0.94%     95.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3912878      0.61%     96.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22694639      3.56%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    632994694                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           453175477                       # Number of instructions committed
-system.cpu0.commit.committedOps             532162399                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    637573218                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           450633299                       # Number of instructions committed
+system.cpu0.commit.committedOps             529613227                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     162042855                       # Number of memory references committed
-system.cpu0.commit.loads                     84950102                       # Number of loads committed
-system.cpu0.commit.membars                    3716655                       # Number of memory barriers committed
-system.cpu0.commit.branches                 101218853                       # Number of branches committed
-system.cpu0.commit.fp_insts                    419354                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                488117298                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13243427                       # Number of function calls committed.
+system.cpu0.commit.refs                     161528172                       # Number of memory references committed
+system.cpu0.commit.loads                     84559991                       # Number of loads committed
+system.cpu0.commit.membars                    3687184                       # Number of memory barriers committed
+system.cpu0.commit.branches                 100678778                       # Number of branches committed
+system.cpu0.commit.fp_insts                    428537                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                486019598                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13276351                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       368889724     69.32%     69.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1132190      0.21%     69.53% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           48139      0.01%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        49491      0.01%     69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84950102     15.96%     85.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      77092753     14.49%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       366882155     69.27%     69.27% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1103700      0.21%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           50072      0.01%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        49128      0.01%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       84559991     15.97%     85.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      76968181     14.53%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        532162399                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22726868                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1220262369                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1241914021                       # The number of ROB writes
-system.cpu0.timesIdled                        4040058                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       23883390                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 52531652861                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  453175477                       # Number of Instructions Simulated
-system.cpu0.committedOps                    532162399                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.480127                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.480127                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.675618                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.675618                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               698520758                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              411524007                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   797183                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  468068                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                128308023                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               129504102                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1200484287                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15629054                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10737693                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.983333                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          307043958                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10738205                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.593602                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1675743000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   201.777727                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   310.205606                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.394097                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.605870                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999967                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total        529613227                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22694639                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1221719500                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1235563732                       # The number of ROB writes
+system.cpu0.timesIdled                        4062222                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       24351091                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 46889510422                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  450633299                       # Number of Instructions Simulated
+system.cpu0.committedOps                    529613227                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.499450                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.499450                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.666911                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.666911                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               694532138                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              409756453                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   813886                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  470480                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                126655644                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               127915254                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1202729248                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15348526                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10661519                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.983500                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          305118964                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10662031                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.617340                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1659069500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   285.071495                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   226.912005                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.556780                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.443188                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1354997138                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1354997138                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80652766                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     81489620                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      162142386                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67583074                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     68792819                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     136375893                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       205065                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202220                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       407285                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       153643                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       172343                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       325986                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1812235                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1802328                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3614563                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2053127                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2077480                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4130607                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    148235840                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    150282439                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       298518279                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    148440905                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    150484659                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      298925564                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6532573                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6224591                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12757164                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6661148                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6436273                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     13097421                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       707910                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       622488                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1330398                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       634041                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       606833                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1240874                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       305625                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       336516                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       642141                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            9                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses       1346452186                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1346452186                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     80589927                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     80681589                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      161271516                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67520868                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     67884168                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     135405036                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204627                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       201539                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       406166                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174874                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       149966                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       324840                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1793684                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1773233                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3566917                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2041252                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2056052                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4097304                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    148110795                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148565757                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       296676552                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    148315422                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    148767296                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      297082718                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6173656                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6486433                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     12660089                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6585609                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6413253                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     12998862                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       647829                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       671589                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1319418                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       637368                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       603972                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1241340                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       307807                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       348230                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       656037                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            3                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13193721                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12660864                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25854585                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13901631                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13283352                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     27184983                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101439335987                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  96122979264                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 197562315251                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 231140325721                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 230924128196                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 462064453917                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  18916873838                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  17351565044                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  36268438882                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3997419982                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4421548736                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8418968718                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       187500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       109500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       297000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 332579661708                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 327047107460                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 659626769168                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 332579661708                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 327047107460                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 659626769168                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     87185339                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     87714211                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    174899550                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74244222                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     75229092                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    149473314                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       912975                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       824708                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1737683                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       787684                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       779176                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1566860                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2117860                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2138844                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4256704                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2053136                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2077483                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4130619                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    161429561                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    162943303                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    324372864                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    162342536                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    163768011                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    326110547                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074927                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.070964                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.072940                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.089719                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.085556                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087624                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.775388                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.754798                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765616                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.804943                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.778814                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.791950                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.144308                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.157335                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.150854                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     12759265                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     12899686                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      25658951                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     13407094                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     13571275                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     26978369                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  95102935500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  99484470500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 194587406000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227327993853                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 219936608514                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 447264602367                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  33983690404                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  32156071893                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  66139762297                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4002448500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4417133500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   8419582000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       243500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       108000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       351500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 322430929353                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 319421079014                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 641852008367                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 322430929353                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 319421079014                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 641852008367                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     86763583                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     87168022                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    173931605                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     74106477                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297421                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    148403898                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       852456                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       873128                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1725584                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       812242                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       753938                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1566180                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2101491                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2121463                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4222954                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2041260                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2056055                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4097315                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160870060                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    161465443                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    322335503                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161722516                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    162338571                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    324061087                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071155                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074413                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.072788                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088867                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086319                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.087591                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759956                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.769176                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764621                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.784702                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.801090                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792591                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.146471                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.164146                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.155350                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081731                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.077701                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.079706                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085631                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.081111                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.083361                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15528.236116                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15442.457065                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15486.382024                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34699.773331                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35878.547755                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35279.041112                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 29835.411019                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28593.641157                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 29228.139909                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13079.492784                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13139.193191                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13110.778969                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20833.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        36500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        24750                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25207.419628                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25831.341957                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25512.951346                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23923.787195                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24620.826690                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24264.380418                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     52126007                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        51266                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3578465                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1028                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.566583                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    49.869650                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079314                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079891                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.079603                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.082902                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.083599                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.083251                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15404.637949                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15337.315671                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15370.145186                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34518.902330                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34294.079543                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 34407.981435                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53318.789779                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 53240.997750                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53280.940191                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13003.110715                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12684.528903                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12834.004789                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 30437.500000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        36000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31954.545455                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25270.337230                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24761.926687                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25014.740796                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24049.277894                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23536.556367                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23791.357008                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     66975280                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        45752                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3575735                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1017                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.730493                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    44.987217                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8209351                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8209351                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3628927                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3346283                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6975210                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5547863                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5347347                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10895210                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         3396                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3377                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         6773                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       184138                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       204631                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       388769                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9176790                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8693630                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17870420                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9176790                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8693630                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17870420                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2903646                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2878308                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5781954                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1113285                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1088926                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2202211                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       695379                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       617800                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1313179                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       630645                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       603456                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1234101                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121487                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       131885                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253372                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            9                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      8160945                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8160945                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3346545                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3573146                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6919691                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5483385                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5330407                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10813792                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3566                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3327                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6893                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       188282                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       213819                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       402101                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8829930                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8903553                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17733483                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8829930                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8903553                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17733483                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2827111                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2913287                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5740398                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1102224                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1082846                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2185070                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       638719                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       656171                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1294890                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       633802                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       600645                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234447                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       119525                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       134411                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253936                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4016931                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3967234                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7984165                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4712310                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4585034                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9297344                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16397                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17283                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3929335                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3996133                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7925468                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4568054                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4652304                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9220358                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17396                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16284                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33680                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        17951                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        15746                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18911                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14786                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34348                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33029                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        36307                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        31070                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67377                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43556644701                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  43095096417                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  86651741118                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39142786504                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  39217956097                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  78360742601                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  11875956517                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   9839614769                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21715571286                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  17839341538                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  16312287276                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  34151628814                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1586128009                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1744790264                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3330918273                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       174000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43970285000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44965591500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  88935876500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39469232389                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38108394120                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  77577626509                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10196891500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11887921500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22084813000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  33197271404                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  31430048393                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64627319797                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1640365500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1815773000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3456138500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       235500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       105000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       279000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  82699431205                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82313052514                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 165012483719                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94575387722                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  92152667283                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 186728055005                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2796204500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2965118250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5761322750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2832162536                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2783504957                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5615667493                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5628367036                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5748623207                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11376990243                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033304                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032815                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033059                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014995                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014475                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014733                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.761663                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.749114                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.755707                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.800632                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.774480                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787627                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057363                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061662                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059523                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       340500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83439517389                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83073985620                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 166513503009                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  93636408889                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  94961907120                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 188598316009                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3034885000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2806255000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841140000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3049818991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2643724500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5693543491                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6084703991                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5449979500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11534683491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032584                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033422                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033004                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014874                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014574                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014724                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.749269                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.751518                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750407                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.780312                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.796677                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.788190                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056876                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063358                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060132                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024883                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024347                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024614                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029027                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027997                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028510                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15000.673188                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14972.371413                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14986.584314                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35159.717866                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36015.262834                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35582.758692                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17078.393965                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15926.861070                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16536.642214                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 28287.454175                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27031.444341                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27673.285099                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13055.948447                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13229.633878                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13146.355055                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024426                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024749                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024588                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028246                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028658                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028453                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15553.080512                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15434.659029                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15492.980887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35808.721629                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35192.810538                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35503.497146                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15964.597108                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18117.108955                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.358370                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52377.984613                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 52327.162289                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52353.255990                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13724.036812                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13509.110117                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13610.273849                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 29437.500000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        35000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        23250                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20587.715150                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20748.222191                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170531.469171                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171562.706127                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171060.651722                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157771.853156                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176775.368792                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166651.853073                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 163863.020729                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174047.752187                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168855.696202                       # average overall mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30954.545455                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21235.022565                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20788.593778                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21009.926860                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20498.095883                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20411.801791                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20454.554586                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174458.783628                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172332.043724                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173430.522565                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161272.222040                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178799.168132                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168962.919281                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167590.381772                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175409.703894                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171196.157309                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16169102                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.955735                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          173971503                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16169614                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.759162                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      13124671250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   233.058192                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   278.897543                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.455192                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.544722                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999914                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         16142168                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.947517                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          172883065                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16142680                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.709688                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      16340342500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   273.082606                       # Average occupied blocks per requestor
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
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 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
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+system.cpu0.icache.overall_mshr_uncacheable_misses::total        20640                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 100646775925                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 100551252932                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 201198028857                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 100646775925                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 100551252932                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 201198028857                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 100646775925                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 100551252932                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 201198028857                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1598498000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   1598498000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084847                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.084847                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.084847                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12463.621069                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              133788555                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90573571                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5908759                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            92439735                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               65341745                       # Number of BTB hits
+system.cpu1.branchPred.lookups              132830364                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         90187101                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5886537                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            91288458                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               64898028                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            70.685777                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17599042                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            188594                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.091165                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17334778                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            185732                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1382,90 +1400,96 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   918015                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               918015                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17288                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94464                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       562013                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       356002                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2214.229134                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 13073.684616                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       353584     99.32%     99.32% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1851      0.52%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          299      0.08%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          120      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           79      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           40      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       356002                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       421643                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21453.513266                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17357.718896                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16015.202358                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       415023     98.43%     98.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         5756      1.37%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          364      0.09%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          366      0.09%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           85      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           33      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       421643                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 354035793664                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.135779                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.675726                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 353071895664     99.73%     99.73% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    535230500      0.15%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    190116000      0.05%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    115191500      0.03%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     44312000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     22451500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     21588500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     29378000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      5201500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       359000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        41000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        22500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51         6000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 354035793664                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        94465     84.53%     84.53% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17288     15.47%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       111753                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       918015                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   905180                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               905180                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17142                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92306                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       553484                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       351696                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2321.493563                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 13592.585679                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       349244     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1804      0.51%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          390      0.11%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          114      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           67      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       351696                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       414217                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22492.792425                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18361.243775                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 16253.124731                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767       322417     77.84%     77.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        82857     20.00%     97.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303         6808      1.64%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071         1275      0.31%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839          173      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607          198      0.05%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375          298      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           83      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           62      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679           12      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447           13      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       414217                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 326963093592                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.083701                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.672512                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 325992368092     99.70%     99.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    539476500      0.16%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    187726500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    115407500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     46500000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     23809500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     21473500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     29946500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      5666000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       571000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        55000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        32500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51        25000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::52-55         4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::56-59        32000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 326963093592                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        92306     84.34%     84.34% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17142     15.66%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       109448                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       905180                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       918015                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       111753                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       905180                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109448                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       111753                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1029768                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109448                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total      1014628                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   105548583                       # DTB read hits
-system.cpu1.dtb.read_misses                    631805                       # DTB read misses
-system.cpu1.dtb.write_hits                   82907544                       # DTB write hits
-system.cpu1.dtb.write_misses                   286210                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1083                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   105776812                       # DTB read hits
+system.cpu1.dtb.read_misses                    627964                       # DTB read misses
+system.cpu1.dtb.write_hits                   81868125                       # DTB write hits
+system.cpu1.dtb.write_misses                   277216                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1087                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21604                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    553                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   56278                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      216                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9625                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55232                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      212                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8920                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    55021                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               106180388                       # DTB read accesses
-system.cpu1.dtb.write_accesses               83193754                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    54701                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               106404776                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82145341                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        188456127                       # DTB hits
-system.cpu1.dtb.misses                         918015                       # DTB misses
-system.cpu1.dtb.accesses                    189374142                       # DTB accesses
+system.cpu1.dtb.hits                        187644937                       # DTB hits
+system.cpu1.dtb.misses                         905180                       # DTB misses
+system.cpu1.dtb.accesses                    188550117                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1495,397 +1519,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   104751                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               104751                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2979                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        72067                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14103                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        90648                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1509.569985                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  8604.112743                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        89986     99.27%     99.27% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          255      0.28%     99.55% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          242      0.27%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          116      0.13%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839           27      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           14      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        90648                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        89149                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26484.081515                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22228.139492                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17447.399907                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        48433     54.33%     54.33% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535        39159     43.93%     98.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          575      0.64%     98.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          708      0.79%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           93      0.10%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           80      0.09%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           45      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           20      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           15      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        89149                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 396982969624                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     1.388871                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0   -154312061728    -38.87%    -38.87% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   551239764852    138.86%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       48839000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        5683000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         518000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         149500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6           6000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::7           9000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::8           9000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::9           8500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::10         44500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 396982969624                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        72067     96.03%     96.03% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         2979      3.97%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        75046                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   106266                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               106266                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3111                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        73302                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14293                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        91973                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1630.543747                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  9941.577304                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        90961     98.90%     98.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          588      0.64%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          258      0.28%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071           90      0.10%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839           38      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::458752-491519            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        91973                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        90706                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28271.216899                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24128.368541                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18525.575548                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        88461     97.52%     97.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1926      2.12%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          212      0.23%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           62      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           21      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        90706                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 610372252128                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.878972                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.326581                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    73947141376     12.12%     12.12% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   536358552252     87.87%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       59179000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        6640000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         645500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          94000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 610372252128                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        73302     95.93%     95.93% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3111      4.07%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        76413                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       104751                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       104751                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       106266                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       106266                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        75046                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        75046                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       179797                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    96448537                       # ITB inst hits
-system.cpu1.itb.inst_misses                    104751                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        76413                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        76413                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       182679                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    95636263                       # ITB inst hits
+system.cpu1.itb.inst_misses                    106266                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1083                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1087                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21604                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    553                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   42139                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   41371                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   204302                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   202868                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                96553288                       # ITB inst accesses
-system.cpu1.itb.hits                         96448537                       # DTB hits
-system.cpu1.itb.misses                         104751                       # DTB misses
-system.cpu1.itb.accesses                     96553288                       # DTB accesses
-system.cpu1.numCycles                       667631540                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                95742529                       # ITB inst accesses
+system.cpu1.itb.hits                         95636263                       # DTB hits
+system.cpu1.itb.misses                         106266                       # DTB misses
+system.cpu1.itb.accesses                     95742529                       # DTB accesses
+system.cpu1.numCycles                       670348620                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         247941482                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     595071407                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  133788555                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          82940787                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    381163571                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13497944                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2492160                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               22589                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             3825                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5325029                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       172051                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         1992                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 96222293                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3665245                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  41130                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         643871402                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.082515                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.328245                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         245802953                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     590871754                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  132830364                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          82232806                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    386445016                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13431293                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2639306                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               21635                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             4572                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5276880                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       167481                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         2239                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 95410634                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3652057                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  41964                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         647075459                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.068807                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.316374                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               496782409     77.16%     77.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18583795      2.89%     80.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18517016      2.88%     82.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13597412      2.11%     85.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28667245      4.45%     89.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9152993      1.42%     90.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9918803      1.54%     92.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8570268      1.33%     93.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                40081461      6.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               501080801     77.44%     77.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18371493      2.84%     80.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18561867      2.87%     83.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13401625      2.07%     85.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                28513625      4.41%     89.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 9105805      1.41%     91.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9777924      1.51%     92.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8450851      1.31%     93.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39811468      6.15%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           643871402                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.200393                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.891317                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               201631753                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            315887121                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                107474204                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13522341                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5353840                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            20035378                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1415024                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             649950843                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4347472                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5353840                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               209303047                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               22542941                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     254388545                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                113174340                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             39106401                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             634340427                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                84329                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1777036                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1562975                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              19949989                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3657                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          605941232                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            974899397                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       750081260                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           811718                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            508709616                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                97231611                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15188925                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13206274                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 75533982                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           102194667                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           87314859                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13957552                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14774854                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 601797044                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15287986                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                601499543                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           865295                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       81943902                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     52376442                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        362406                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    643871402                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.934192                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.656161                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           647075459                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.198151                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.881440                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               199983147                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            321798427                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                106352633                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13609650                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5329449                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19773591                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1406143                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             644884461                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4323616                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5329449                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               207655640                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               26665473                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     252746187                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                112130376                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             42545968                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             629384575                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                84102                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2156884                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1598140                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              23186474                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3948                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          602389573                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            968798649                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       744085505                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           803060                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            505488932                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                96900641                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15182115                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13209558                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 75938042                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101507501                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           86179777                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13679637                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14662477                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 596915130                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15279603                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                597602438                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           863336                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       81541272                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     52071117                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        356106                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    647075459                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.923544                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.649381                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          408171960     63.39%     63.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           99067431     15.39%     78.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           44002532      6.83%     85.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31313283      4.86%     90.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23144485      3.59%     94.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16264635      2.53%     96.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           11075626      1.72%     98.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6519272      1.01%     99.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4312178      0.67%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          412751344     63.79%     63.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           98711881     15.26%     79.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43578879      6.73%     85.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           31028755      4.80%     90.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           23162473      3.58%     94.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16109238      2.49%     96.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10961200      1.69%     98.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6490260      1.00%     99.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4281429      0.66%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      643871402                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      647075459                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3037678     26.20%     26.20% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 24339      0.21%     26.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   2694      0.02%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               4      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4607398     39.74%     66.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3921783     33.83%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3038725     25.54%     25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 25345      0.21%     25.76% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   3128      0.03%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               3      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4885830     41.07%     66.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3943683     33.15%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            408162511     67.86%     67.86% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1426997      0.24%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                69303      0.01%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                134      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             22      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         70416      0.01%     68.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           107729216     17.91%     86.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           84040920     13.97%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               46      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            405061818     67.78%     67.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1472658      0.25%     68.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                66179      0.01%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                 56      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             16      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         71237      0.01%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           107954973     18.06%     86.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82975408     13.88%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             601499543                       # Type of FU issued
-system.cpu1.iq.rate                          0.900945                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11593896                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019275                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1858238935                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        699228429                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    579923061                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1090744                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            540881                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       488146                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             612510547                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 582891                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4820885                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             597602438                       # Type of FU issued
+system.cpu1.iq.rate                          0.891480                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11896714                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019907                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1853948472                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        693931681                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    575193406                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1091913                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            542260                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       485773                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             608916098                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 583008                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4685337                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16648209                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        23106                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       751890                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      9224511                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16615869                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        21909                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       749717                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      9068365                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      4009170                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      7426024                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3952894                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      8300380                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5353840                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               14516681                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              6539646                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          617219827                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1819635                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            102194667                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            87314859                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12911400                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                240081                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              6211315                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        751890                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2725767                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2332140                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5057907                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            594561904                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            105538370                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6033124                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5329449                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               14829127                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             10212979                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          612328593                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1790117                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            101507501                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            86179777                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12919930                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                237071                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              9891044                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        749717                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2710919                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2329182                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5040101                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            590723670                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            105766513                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5987554                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       134797                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   188445888                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               110364560                       # Number of branches executed
-system.cpu1.iew.exec_stores                  82907518                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.890554                       # Inst execution rate
-system.cpu1.iew.wb_sent                     581679133                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    580411207                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                286057076                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                496538403                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       133860                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   187634979                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               109483047                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81868466                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.881219                       # Inst execution rate
+system.cpu1.iew.wb_sent                     576950915                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    575679179                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                284156915                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                493402851                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.869359                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.576103                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.858776                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575913                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       81975668                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14925580                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4513358                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    629946041                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.849503                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.842378                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       81583045                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14923497                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4500070                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    633204147                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.838045                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.832186                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    433603733     68.83%     68.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     96615693     15.34%     84.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33704251      5.35%     89.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15419971      2.45%     91.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10970958      1.74%     93.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6585832      1.05%     94.75% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6182969      0.98%     95.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3954863      0.63%     96.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22907771      3.64%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    438438352     69.24%     69.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     96042056     15.17%     84.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     33088291      5.23%     89.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15382536      2.43%     92.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10958189      1.73%     93.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6612249      1.04%     94.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6082014      0.96%     95.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3902550      0.62%     96.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22697910      3.58%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    629946041                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           455165016                       # Number of instructions committed
-system.cpu1.commit.committedOps             535141123                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    633204147                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           451699475                       # Number of instructions committed
+system.cpu1.commit.committedOps             530653461                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     163636805                       # Number of memory references committed
-system.cpu1.commit.loads                     85546457                       # Number of loads committed
-system.cpu1.commit.membars                    3765916                       # Number of memory barriers committed
-system.cpu1.commit.branches                 101697828                       # Number of branches committed
-system.cpu1.commit.fp_insts                    467953                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                491500354                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13521989                       # Number of function calls committed.
+system.cpu1.commit.refs                     162003044                       # Number of memory references committed
+system.cpu1.commit.loads                     84891632                       # Number of loads committed
+system.cpu1.commit.membars                    3738235                       # Number of memory barriers committed
+system.cpu1.commit.branches                 100868221                       # Number of branches committed
+system.cpu1.commit.fp_insts                    465542                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                487126697                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13297594                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       370285651     69.19%     69.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1106053      0.21%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           52121      0.01%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        60451      0.01%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       85546457     15.99%     85.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      78090348     14.59%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       367411373     69.24%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1128741      0.21%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           49317      0.01%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        60944      0.01%     69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84891632     16.00%     85.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      77111412     14.53%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        535141123                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22907771                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1220174232                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1248183780                       # The number of ROB writes
-system.cpu1.timesIdled                        4134360                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       23760138                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 48765821681                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  455165016                       # Number of Instructions Simulated
-system.cpu1.committedOps                    535141123                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.466790                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.466790                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.681761                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.681761                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               701277155                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              414494210                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   871148                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  523684                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                126609999                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               127812398                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1197834701                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15057964                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40297                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40297                       # Transaction distribution
+system.cpu1.commit.op_class_0::total        530653461                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22697910                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1218827033                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1238367651                       # The number of ROB writes
+system.cpu1.timesIdled                        4095381                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       23273161                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 54406850213                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  451699475                       # Number of Instructions Simulated
+system.cpu1.committedOps                    530653461                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.484059                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.484059                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.673828                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.673828                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               696515100                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              411090108                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   864151                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  531144                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                126615327                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               127765048                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1196239956                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15044847                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40301                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40301                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1902,11 +1918,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353744                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1923,11 +1939,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492192                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1956,437 +1972,448 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607055505                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569059287                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148389509                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147720000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115457                       # number of replacements
-system.iocache.tags.tagsinuse               10.425424                       # Cycle average of tags in use
+system.iocache.tags.replacements               115460                       # number of replacements
+system.iocache.tags.tagsinuse               10.424672                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115476                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13090073143000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544298                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.881126                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221519                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430070                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651589                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13093329887000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544075                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.880598                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221505                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430037                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651542                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039641                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039641                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039677                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8812                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8849                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8812                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8852                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8812                       # number of overall misses
-system.iocache.overall_misses::total             8852                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1661250694                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1666322694                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19868709302                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19868709302                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1661250694                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1666675194                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1661250694                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1666675194                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
+system.iocache.overall_misses::total             8856                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1614263059                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1619332059                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12613364228                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12613364228                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1614263059                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1619683059                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1614263059                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1619683059                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8812                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8849                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8812                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8852                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8812                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8852                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 188521.413300                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 188306.327721                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186273.806551                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186273.806551                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 188521.413300                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 188282.330999                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 188521.413300                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 188282.330999                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        113607                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183106.063861                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 182913.369366                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118253.245969                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118253.245969                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 182891.040989                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 182891.040989                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31017                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16342                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3459                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.951842                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.967042                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
+system.iocache.writebacks::writebacks          106629                       # number of writebacks
+system.iocache.writebacks::total               106629                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8812                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8849                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8812                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8852                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8812                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8852                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1201855604                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1204997604                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14322073410                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14322073410                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1201855604                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1205191104                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1201855604                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1205191104                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1173463059                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1176682059                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7280164228                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7280164228                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1173463059                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1176883059                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1173463059                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1176883059                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136388.516114                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136173.308170                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134272.795039                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134272.795039                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136388.516114                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 136149.017623                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136388.516114                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 136149.017623                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133106.063861                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 132913.369366                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68253.245969                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68253.245969                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1412518                       # number of replacements
-system.l2c.tags.tagsinuse                65354.490513                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   31645259                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1474766                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.457817                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               2643820000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35783.123237                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   158.967100                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   249.670952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3744.975731                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    12205.230455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   164.981843                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   255.022053                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3435.700252                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9356.818889                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.546007                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002426                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003810                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.057144                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.186237                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002517                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003891                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.052425                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.142774                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997230                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          337                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61911                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          333                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          503                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2841                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5066                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53373                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005142                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.944687                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                297548374                       # Number of tag accesses
-system.l2c.tags.data_accesses               297548374                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       541623                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       186900                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            7965775                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3551683                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       548604                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       190887                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            8107304                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3470388                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               24563164                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         8209351                       # number of Writeback hits
-system.l2c.Writeback_hits::total              8209351                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       352587                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       361830                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       714417                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data            4898                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5089                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9987                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             8                       # number of SCUpgradeReq hits
+system.l2c.tags.replacements                  1395026                       # number of replacements
+system.l2c.tags.tagsinuse                65295.492166                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   50144400                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1458293                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    34.385682                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              15281090500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35597.818988                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   166.792374                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   227.419292                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3927.975659                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9604.860217                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   170.331373                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   255.084245                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3398.092398                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11947.117619                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.543180                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002545                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003470                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.059936                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.146559                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002599                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003892                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.051851                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.182299                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996330                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          361                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62906                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          360                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          593                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2785                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5017                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54411                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005508                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.959869                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                445809940                       # Number of tag accesses
+system.l2c.tags.data_accesses               445809940                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       538533                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       183659                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker       537301                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       193067                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1452560                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         8160945                       # number of Writeback hits
+system.l2c.Writeback_hits::total              8160945                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            5106                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            5035                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               10141                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           814701                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           785760                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1600461                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        541623                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        186900                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7965775                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4366384                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        548604                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        190887                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             8107304                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4256148                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                26163625                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       541623                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       186900                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7965775                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4366384                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       548604                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       190887                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            8107304                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4256148                       # number of overall hits
-system.l2c.overall_hits::total               26163625                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2520                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2317                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            47910                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           162942                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2554                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2304                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            48528                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           151193                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               420268                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       278058                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       241626                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       519684                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         18363                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         18249                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             36612                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           801127                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           795359                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1596486                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       7998143                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       8048835                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          16046978                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      3426730                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data      3533561                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          6960291                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       362301                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       359177                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           721478                       # number of InvalidateReq hits
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+system.l2c.ReadSharedReq_accesses::cpu0.data      3578598                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3697693                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      7276291                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       633802                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       600645                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1234447                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       540962                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       185923                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         8049865                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         4664086                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       539894                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       195574                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         8092796                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         4763509                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            27032609                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       540962                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       185923                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        8049865                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        4664086                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       539894                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       195574                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        8092796                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        4763509                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           27032609                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006697                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782659                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783058                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.782857                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.250000                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.333333                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.166667                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.256599                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.267015                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.261750                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004631                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005979                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.092329                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004634                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.011926                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005950                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.093198                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.036378                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004631                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005979                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.092329                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004634                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.011926                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005950                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.093198                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.036378                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89701.394048                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89040.790246                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85896.541307                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 92135.269237                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89613.159358                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88756.190538                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85061.001690                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 90154.449948                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 89829.089226                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data     8.444015                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data     9.179182                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total     8.785829                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15383.023852                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16107.353828                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15744.061155                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101755.896789                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101622.844246                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 101688.780814                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89701.394048                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89040.790246                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85896.541307                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 98226.464760                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89613.159358                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88756.190538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85061.001690                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 97658.943628                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 96642.554195                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89701.394048                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89040.790246                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85896.541307                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 98226.464760                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89613.159358                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88756.190538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85061.001690                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 97658.943628                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 96642.554195                       # average overall miss latency
+system.l2c.SCUpgradeReq_miss_rate::total     0.272727                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.261966                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.253756                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.257898                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006425                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005432                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005927                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042438                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.044388                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043429                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.428369                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.402015                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.415546                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.data       0.091233                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.036115                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006425                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 88043.245175                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15185.783434                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15718.719049                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15450.698832                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        80250                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        80000                       # average SCUpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100806.272346                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 100602.522809                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85282.665017                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84567.025318                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 84953.868503                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88815.036742                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91819.197353                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 90375.412975                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 101957.388739                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107836.450379                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 104724.817679                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 95632.636788                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 96372.525669                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 95632.636788                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2395,279 +2422,295 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1194670                       # number of writebacks
-system.l2c.writebacks::total                  1194670                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           20                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           34                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           15                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           35                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data             9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               126                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker           20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           34                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           35                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                126                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker           20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.itb.walker           34                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.dtb.walker           15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.itb.walker           35                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               126                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2500                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2283                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        47910                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       162930                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2539                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2269                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        48527                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       151184                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          420142                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       278058                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       241626                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total       519684                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        18363                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        18249                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        36612                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.writebacks::writebacks             1179151                       # number of writebacks
+system.l2c.writebacks::total                  1179151                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           19                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           38                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            9                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           38                       # number of ReadReq MSHR hits
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+system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           10                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           12                       # number of ReadSharedReq MSHR hits
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.785682                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.demand_mshr_miss_latency::total  83594959000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   3893746000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  37677656000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3278041000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  37987819500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  83594959000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2817435000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2602704500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6698691999                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2830764496                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2473673500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5304437996                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5648199496                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5076378000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12003129995                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006626                       # mshr miss rate for ReadReq accesses
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.782659                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783058                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.782857                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.256599                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.267015                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.261750                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004594                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012066                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005979                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.092327                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004607                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011745                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005950                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.093196                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.036374                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004594                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012066                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005979                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.092327                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004607                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011745                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005950                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.093196                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036374                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73383.389814                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 79682.628798                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72551.661137                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77675.511291                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77355.208270                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33717.092556                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34183.846403                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33934.108791                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17759.726624                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17756.082251                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17757.910111                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        68500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        68500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89351.153103                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89221.557305                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 89285.780821                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73383.389814                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 85804.315022                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72551.661137                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85230.972836                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 84210.269261                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73383.389814                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 85804.315022                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 84210.269261                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156516.496920                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157547.431002                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 120004.326258                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144678.402317                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163761.748762                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153595.705730                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150329.655293                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160509.998668                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 132864.814284                       # average overall mshr uncacheable latency
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.261966                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.253756                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.257898                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005927                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042435                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.044384                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043426                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.428369                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.402015                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.415546                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.036111                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.036111                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 78201.723604                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.431174                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.044239                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.244660                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90408.735727                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90806.272346                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 90602.522809                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74954.401037                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78816.641204                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81822.005240                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80377.637051                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 91957.388739                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97836.450379                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94724.817679                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161958.783628                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159832.013019                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123319.072147                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149688.778806                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167298.356553                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157415.734220                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155567.782962                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 163385.194722                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 136372.859732                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              483310                       # Transaction distribution
-system.membus.trans_dist::ReadResp             483310                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54320                       # Transaction distribution
+system.membus.trans_dist::ReadResp             484522                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
-system.membus.trans_dist::Writeback           1301300                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       626202                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       626202                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37394                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           37396                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            566817                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           566817                       # Transaction distribution
+system.membus.trans_dist::Writeback           1285780                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           222453                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37353                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           37356                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1066998                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1066998                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        430202                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4328173                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4457819                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335539                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335539                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4793358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4492142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4621788                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4963983                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    174172012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    174343786                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14081472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14081472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               188425258                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2786                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3049369                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    172016940                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    172188714                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7259520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7259520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               179448234                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2724                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3239737                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3049369    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3239737    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3049369                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113801500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3239737                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           113920999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               51156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5469002                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5444004                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         11041524273                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8690318133                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6008607805                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8114396828                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151555991                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228917368                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2711,54 +2754,57 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           25599599                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25591523                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2074158                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25494018                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8209351                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1340869                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1234101                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46602                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46614                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2167911                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2167911                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     32380531                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29914539                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       911927                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2596271                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              65803268                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1036169984                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1212884202                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3059264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8762408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2260875858                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          669395                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         37398155                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.057385                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.232578                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback          9446739                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        18863436                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46705                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46716                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2151304                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2151304                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16142823                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7285144                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1341111                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1234447                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48465856                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32213596                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       910891                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2571300                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              84161643                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1034451264                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1125904618                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3051976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8646848                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2172054706                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2184416                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         57389162                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.063529                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.243911                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               35252045     94.26%     94.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                2146110      5.74%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               53743303     93.65%     93.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                3645859      6.35%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           37398155                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        28102852815                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           57389162                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        36059386455                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1161000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1120500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24319536063                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24257498228                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       15088594286                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14835156686                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         530670154                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         529789657                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1505035766                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1493165292                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16426                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   16399                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 793637493..4ce945989 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,159 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.824541                       # Number of seconds simulated
-sim_ticks                                51824540977500                       # Number of ticks simulated
-final_tick                               51824540977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.832615                       # Number of seconds simulated
+sim_ticks                                51832614542500                       # Number of ticks simulated
+final_tick                               51832614542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 636803                       # Simulator instruction rate (inst/s)
-host_op_rate                                   748315                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            37012113234                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 715168                       # Number of bytes of host memory used
-host_seconds                                  1400.21                       # Real time elapsed on the host
-sim_insts                                   891654507                       # Number of instructions simulated
-sim_ops                                    1047794539                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 677235                       # Simulator instruction rate (inst/s)
+host_op_rate                                   795801                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            39828045805                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 719272                       # Number of bytes of host memory used
+host_seconds                                  1301.41                       # Real time elapsed on the host
+sim_insts                                   881360160                       # Number of instructions simulated
+sim_ops                                    1035663034                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       127104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       129344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2579072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24306544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       138752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       130240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2657396                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         26223832                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        397184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             56689468                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2579072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2657396                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5236468                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     77843520                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       134080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       130496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2944516                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         40297840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       118912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       116992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2475952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         40549336                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        378752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             87146876                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2944516                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2475952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5420468                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     75611328                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          77864100                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2021                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             64583                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            379793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2035                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             57644                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            409757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6206                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                926193                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1216305                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          75631908                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2095                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2039                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             70534                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            629657                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1858                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1828                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             54568                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            633593                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           5918                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1402090                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1181427                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1218878                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2453                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2496                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               49765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              469016                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2677                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               51277                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              506012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1093873                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          49765                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          51277                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             101042                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1502059                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1184000                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2587                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               56808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              777461                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2294                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               47768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              782313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1681314                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          56808                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          47768                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             104576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1458760                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1502456                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1502059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              49765                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             469016                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              51277                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             506409                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2596329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        926193                       # Number of read requests accepted
-system.physmem.writeReqs                      1833424                       # Number of write requests accepted
-system.physmem.readBursts                      926193                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1833424                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59238720                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37632                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 114125056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  56689468                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              117195044                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      588                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   50220                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          36075                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               58169                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               57047                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               56978                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               51307                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               56070                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               62899                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               54110                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               52791                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               52847                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              102886                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              57805                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              59371                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              53186                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              52009                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              46290                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              51840                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              107643                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              108842                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              112436                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              109534                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              114716                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              117944                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              106840                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              109826                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              110854                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              118905                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             115046                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             114249                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             112384                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             111972                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104755                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             107258                       # Per bank write bursts
+system.physmem.bw_write::total                1459157                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1458760                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              56808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             777461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              47768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             782710                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3140470                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1402090                       # Number of read requests accepted
+system.physmem.writeReqs                      1184000                       # Number of write requests accepted
+system.physmem.readBursts                     1402090                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1184000                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 89692096                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     41664                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  75632192                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  87146876                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               75631908                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      651                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         142152                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               86151                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               87375                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               80357                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               81721                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               87059                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               94652                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               87531                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               83073                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               80243                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              128909                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              86457                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              85414                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              83586                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              88109                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              80365                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              80437                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               72704                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               74469                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               70529                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               72860                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75808                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               80444                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               76110                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               73633                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70562                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               76081                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              73660                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              73767                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72713                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              77059                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              70231                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              71123                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         141                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51824538352500                       # Total gap between requests
+system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51832611910500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  883077                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1358974                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1830851                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    891893                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     27772                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       548                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       744                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       447                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1849                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      126                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1181427                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1369118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     26985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       299                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       442                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       427                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       463                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       477                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       766                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       841                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       49                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -165,186 +165,183 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    57426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    60838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    91061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   116478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   105808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    96280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    97400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    91891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    93113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    91599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    92000                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    96823                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    95841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    93430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   103137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    95750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    92354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    90761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     5036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     5548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     7290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     7464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     6868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     7069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     7549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     5718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     5353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     5228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      235                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       605479                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      286.324474                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.442500                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.472553                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         252649     41.73%     41.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       150060     24.78%     66.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52055      8.60%     75.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27939      4.61%     79.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19251      3.18%     82.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12886      2.13%     85.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9838      1.62%     86.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9006      1.49%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        71795     11.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         605479                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         88964                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        10.404208                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       91.787630                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          88960    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::21504-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           88964                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         88964                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.044108                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.711925                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.727362                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15              349      0.39%      0.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31           86750     97.51%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47             775      0.87%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              22      0.02%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              52      0.06%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             153      0.17%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            193      0.22%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           316      0.36%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           104      0.12%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            25      0.03%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            21      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            53      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            28      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            13      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             3      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             4      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             7      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303            10      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             6      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             6      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            10      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            22      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             6      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             4      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             4      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           88964                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    11987590194                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29342683944                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4628025000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12951.09                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::0                      1627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      1574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      1554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      1528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      1510                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      1499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      1486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      1478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      1460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                     1444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                     1433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     1423                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     1412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     1406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    16205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    18522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    67973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    68856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    68869                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    68651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    68381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    71263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    71520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    74085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    72568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    72467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    69770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    69647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    70062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    67493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    67216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    66673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      423                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      325                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      102                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       564759                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      292.733658                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     169.256086                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.085017                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         228658     40.49%     40.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       138332     24.49%     64.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49531      8.77%     73.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28277      5.01%     78.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20268      3.59%     82.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        14095      2.50%     84.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        11027      1.95%     86.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        10949      1.94%     88.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        63622     11.27%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         564759                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         67625                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.723608                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      277.022721                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          67622    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           67625                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         67625                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.475091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.957142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.452813                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                76      0.11%      0.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                68      0.10%      0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               65      0.10%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15             131      0.19%      0.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           63823     94.38%     94.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             440      0.65%     95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             742      1.10%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             499      0.74%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             390      0.58%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             489      0.72%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             119      0.18%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              25      0.04%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              63      0.09%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              45      0.07%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              39      0.06%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              22      0.03%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             448      0.66%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              23      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              39      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              24      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               5      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            23      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           67625                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    16718468525                       # Total ticks spent queuing
+system.physmem.totMemAccLat               42995449775                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7007195000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11929.50                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31701.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.14                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.20                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.09                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30679.50                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.73                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.43                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     697250                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1406079                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18779612.66                       # Average gap between requests
-system.physmem.pageHitRate                      77.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2300840640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1255419000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3505093800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5752820880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384927046800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1312402504095                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29943494064750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34653637789965                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.672359                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49812972038958                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730535300000                       # Time in different power states
+system.physmem.avgWrQLen                        12.63                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1132210                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    886222                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20042849.21                       # Average gap between requests
+system.physmem.pageHitRate                      78.14                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2158387560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1177691625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5365768200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3865689360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3385453914960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1313258572845                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29947583060250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34658863084800                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.669107                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49819671489024                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730804660000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    281033227292                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    282130972226                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2276580600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1242181875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3714586200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5802341040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384927046800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1307965107960                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29947386517500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34653314361975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.666118                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49819438757970                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730535300000                       # Time in different power states
+system.physmem_1.actEnergy                 2111190480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1151939250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5565417000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3792070080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3385453914960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1310153724135                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29950306611750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34658534867655                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.662774                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49824215805224                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730804660000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    274566508280                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    277593670776                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -398,64 +395,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   132927                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               132927                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20422                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        96268                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           16                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       132911                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         132911    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       132911                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       116706                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23749.820061                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 20399.632740                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 13626.974720                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       115779     99.21%     99.21% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          796      0.68%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           50      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           35      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           34      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       116706                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  17050777148                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.002177                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      -37117796     -0.22%     -0.22% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    17087894944    100.22%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  17050777148                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        96268     82.50%     82.50% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        20422     17.50%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       116690                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       132927                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   130428                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               130428                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20426                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94161                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       130414                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         130414    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       130414                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       114601                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 25025.623686                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.133741                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14193.681922                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       113576     99.11%     99.11% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          877      0.77%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           64      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           43      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           23      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       114601                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   -626546628                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.597966                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.490309                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     -251893296     40.20%     40.20% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1     -374653332     59.80%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   -626546628                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        94162     82.17%     82.17% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        20426     17.83%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       114588                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       130428                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       132927                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       116690                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       130428                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       114588                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       116690                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       249617                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       114588                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       245016                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83832092                       # DTB read hits
-system.cpu0.dtb.read_misses                    101357                       # DTB read misses
-system.cpu0.dtb.write_hits                   76051604                       # DTB write hits
-system.cpu0.dtb.write_misses                    31570                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51833                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    82615908                       # DTB read hits
+system.cpu0.dtb.read_misses                     99897                       # DTB read misses
+system.cpu0.dtb.write_hits                   75294881                       # DTB write hits
+system.cpu0.dtb.write_misses                    30531                       # DTB write misses
+system.cpu0.dtb.flush_tlb                       51838                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21426                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    523                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   72699                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              21162                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    519                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   72657                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4640                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4653                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9921                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                83933449                       # DTB read accesses
-system.cpu0.dtb.write_accesses               76083174                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9875                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                82715805                       # DTB read accesses
+system.cpu0.dtb.write_accesses               75325412                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        159883696                       # DTB hits
-system.cpu0.dtb.misses                         132927                       # DTB misses
-system.cpu0.dtb.accesses                    160016623                       # DTB accesses
+system.cpu0.dtb.hits                        157910789                       # DTB hits
+system.cpu0.dtb.misses                         130428                       # DTB misses
+system.cpu0.dtb.accesses                    158041217                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -485,96 +483,90 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    78456                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                78456                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4330                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68323                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        78456                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          78456    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        78456                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        72653                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26725.888828                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23461.567658                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 16011.465624                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        35910     49.43%     49.43% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535        35653     49.07%     98.50% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          362      0.50%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          571      0.79%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           51      0.07%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           22      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           28      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           22      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        72653                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   -294752296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     -294752296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   -294752296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        68323     94.04%     94.04% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         4330      5.96%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72653                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    77694                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                77694                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4299                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67844                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        77694                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          77694    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        77694                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        72143                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 28108.645329                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 25072.463875                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 16528.773937                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        70985     98.39%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          998      1.38%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607           60      0.08%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           53      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           28      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        72143                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   -294780296                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     -294780296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   -294780296                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        67844     94.04%     94.04% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         4299      5.96%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72143                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        78456                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        78456                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77694                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77694                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72653                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72653                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       151109                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   446243730                       # ITB inst hits
-system.cpu0.itb.inst_misses                     78456                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72143                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72143                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       149837                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   440762049                       # ITB inst hits
+system.cpu0.itb.inst_misses                     77694                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51833                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                       51838                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21426                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    523                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   53592                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21162                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    519                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   53801                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               446322186                       # ITB inst accesses
-system.cpu0.itb.hits                        446243730                       # DTB hits
-system.cpu0.itb.misses                          78456                       # DTB misses
-system.cpu0.itb.accesses                    446322186                       # DTB accesses
-system.cpu0.numCycles                     51824649281                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               440839743                       # ITB inst accesses
+system.cpu0.itb.hits                        440762049                       # DTB hits
+system.cpu0.itb.misses                          77694                       # DTB misses
+system.cpu0.itb.accesses                    440839743                       # DTB accesses
+system.cpu0.numCycles                     51832801454                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  445966277                       # Number of instructions committed
-system.cpu0.committedOps                    524229812                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            481463261                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                467774                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26556698                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     68063516                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   481463261                       # number of integer instructions
-system.cpu0.num_fp_insts                       467774                       # number of float instructions
-system.cpu0.num_int_register_reads          701970788                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         382111523                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              750606                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             404844                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           116882787                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          116605188                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    159874579                       # number of memory refs
-system.cpu0.num_load_insts                   83829017                       # Number of load instructions
-system.cpu0.num_store_insts                  76045562                       # Number of store instructions
-system.cpu0.num_idle_cycles              50231597014.033707                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1593052266.966292                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.030739                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.969261                       # Percentage of idle cycles
-system.cpu0.Branches                         99615402                       # Number of branches fetched
+system.cpu0.committedInsts                  440492275                       # Number of instructions committed
+system.cpu0.committedOps                    517776891                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            475595742                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                442272                       # Number of float alu accesses
+system.cpu0.num_func_calls                   26261796                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     67159010                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   475595742                       # number of integer instructions
+system.cpu0.num_fp_insts                       442272                       # number of float instructions
+system.cpu0.num_int_register_reads          692983656                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         377245689                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              706646                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             389336                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           115273932                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          114990138                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    157900832                       # number of memory refs
+system.cpu0.num_load_insts                   82612008                       # Number of load instructions
+system.cpu0.num_store_insts                  75288824                       # Number of store instructions
+system.cpu0.num_idle_cycles              50243492062.967224                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1589309391.032773                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.030662                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.969338                       # Percentage of idle cycles
+system.cpu0.Branches                         98397494                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                363413760     69.28%     69.28% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1135542      0.22%     69.50% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49216      0.01%     69.51% # Class of executed instruction
+system.cpu0.op_class::IntAlu                358993131     69.29%     69.29% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1071583      0.21%     69.50% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    48336      0.01%     69.51% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
@@ -597,174 +589,174 @@ system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Cl
 system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
 system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
 system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             60094      0.01%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             58966      0.01%     69.52% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::MemRead                83829017     15.98%     85.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite               76045562     14.50%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                82612008     15.95%     85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite               75288824     14.53%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 524533192                       # Class of executed instruction
+system.cpu0.op_class::total                 518072849                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16327                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements         10196087                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.965694                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          309323716                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10196599                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.335969                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       3500850250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   229.651609                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   282.314085                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.448538                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.551395                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   16267                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements         10037940                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.966034                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          305864730                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10038452                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.469312                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       3466781500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   221.416582                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   290.549452                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.432454                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.567479                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999934                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          398                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1288720346                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1288720346                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     78289930                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     78118799                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      156408729                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     72116454                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     72389955                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     144506409                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       198225                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       194517                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       392742                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       165535                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       168546                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       334081                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1870803                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1796237                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3667040                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2023404                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1945934                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3969338                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    150406384                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    150508754                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       300915138                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    150604609                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    150703271                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      301307880                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2655491                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2654704                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      5310195                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1102314                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1104773                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2207087                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       646482                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       651674                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1298156                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       617789                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       615381                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1233170                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       153457                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       150527                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       303984                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1274123450                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1274123450                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77217599                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     77513026                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      154730625                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     71443407                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     71419351                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     142862758                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195522                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       192929                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       388451                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       168757                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       166793                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       335550                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1811257                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1789885                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3601142                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1962197                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1939338                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3901535                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    148661006                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148932377                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       297593383                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    148856528                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    149125306                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      297981834                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2588533                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      2647536                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      5236069                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1081685                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1087089                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2168774                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       633947                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       631509                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1265456                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       612829                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       615985                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1228814                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       151773                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       150295                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       302068                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3757805                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3759477                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       7517282                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4404287                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      4411151                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      8815438                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41854028250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42227875003                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  84081903253                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  32373542448                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33874267614                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  66247810062                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  16528493005                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  16264164501                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  32792657506                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2255480492                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2210676726                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4466157218                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data      3670218                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      3734625                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       7404843                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4304165                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      4366134                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      8670299                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41004192000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41620421500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  82624613500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  31575309500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  31406770000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  62982079500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25211350000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  25725023500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  50936373500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2229514000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2184997000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4414511000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        82000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  74227570698                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  76102142617                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 150329713315                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  74227570698                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  76102142617                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 150329713315                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80945421                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     80773503                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    161718924                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73218768                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     73494728                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    146713496                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       844707                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       846191                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1690898                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       783324                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       783927                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1567251                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2024260                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1946764                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3971024                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2023405                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1945935                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3969340                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    154164189                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    154268231                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    308432420                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    155008896                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    155114422                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    310123318                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032806                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032866                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032836                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015055                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015032                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015044                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.765333                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.770126                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767732                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.788676                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.784998                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786836                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075809                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077322                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.076551                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        33000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       115000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  72579501500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  73027191500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 145606693000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  72579501500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  73027191500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 145606693000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     79806132                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     80160562                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    159966694                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     72525092                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     72506440                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    145031532                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       829469                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       824438                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1653907                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       781586                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       782778                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1564364                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1963030                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1940180                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3903210                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1962198                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1939339                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3901537                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    152331224                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    152667002                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    304998226                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    153160693                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    153491440                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    306652133                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032435                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033028                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032732                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014915                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014993                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.014954                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764281                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.765987                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765131                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.784084                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.786922                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785504                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077316                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077464                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077390                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024375                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024370                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.024373                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028413                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028438                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.028426                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15761.314292                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15906.811081                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15834.051904                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29368.712044                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30661.744643                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30015.948652                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 26754.268860                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 26429.422587                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 26592.162886                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14697.801286                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14686.247158                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.079906                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024094                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024463                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.024278                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028102                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028445                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028274                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15840.706686                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15720.436474                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15779.893943                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29190.854546                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28890.707201                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29040.406930                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 41139.290079                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41762.418728                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 41451.654604                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14689.793310                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14538.055158                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14614.295457                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19752.906470                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20242.747227                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19997.881324                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16853.481778                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17252.218892                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17053.005570                       # average overall miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        33000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        57500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19775.256265                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19554.089500                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19663.711033                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16862.620624                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16725.824608                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16793.733757                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -773,220 +765,220 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7866652                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7866652                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7707                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         8547                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        16254                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10563                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        10564                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21127                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35866                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35610                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71476                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        18270                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        19111                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        37381                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        18270                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        19111                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        37381                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2647784                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2646157                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5293941                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1091751                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1094209                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2185960                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       645721                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       650689                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1296410                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       617789                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       615381                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1233170                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       117591                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       114917                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       232508                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7725236                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7725236                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11311                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        11844                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        23155                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9967                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11283                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21250                       # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35738                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71880                       # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::cpu1.data        23127                       # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::cpu1.data        23127                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        44405                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2577222                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2635692                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5212914                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1071718                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1075806                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2147524                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       633158                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       630543                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1263701                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       612829                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       615985                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1228814                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115631                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       114557                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       230188                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3739535                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3740366                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7479901                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4385256                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4391055                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      8776311                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17713                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15993                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16112                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        17598                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33825                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33591                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37598794000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  37923223247                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  75522017247                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30337029302                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31768716886                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62105746188                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   9761049258                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10401680524                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20162729782                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  15601809495                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  15341092999                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  30942902494                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1519625500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1476118000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2995743500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        80500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        80500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  67935823302                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69691940133                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 137627763435                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  77696872560                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  80093620657                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 157790493217                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2993163000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2758056250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5751219250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2831783000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2786803750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5618586750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5824946000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5544860000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11369806000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032711                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032760                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032735                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014911                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014888                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014900                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.764432                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.768962                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766699                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.788676                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.784998                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786836                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058091                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059030                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058551                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3648940                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3711498                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7360438                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4282098                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4342041                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      8624139                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17286                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16418                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33704                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16057                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        17652                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33709                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33343                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34070                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67413                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38167566000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38688442500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76856008500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30213193500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  29970900500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  60184094000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10061362000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10320868500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20382230500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24598521000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  25109038500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  49707559500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1553845500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1517429500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3071275000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        81000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        32000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       113000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  68380759500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  68659343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 137040102500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  78442121500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  78980211500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 157422333000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2977259000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2853920500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5831179500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2866948000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2828284500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5695232500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5844207000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5682205000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11526412000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032294                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032880                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032587                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014777                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014837                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014807                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.763329                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.764816                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.764070                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.784084                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.786922                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785504                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059045                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058974                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024257                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024246                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024251                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028290                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028308                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028299                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14200.098649                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14331.433565                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14265.745925                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27787.498525                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29033.499894                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28411.199742                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15116.512020                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15985.640642                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15552.741634                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 25254.268844                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 24929.422584                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25092.162876                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12922.974547                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12845.079492                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12884.474943                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18166.917358                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18632.385209                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168981.143793                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172453.964234                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.945885                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175756.144489                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158359.117513                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.184218                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172208.307465                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165069.810366                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168651.447728                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023954                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024311                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024133                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027958                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028288                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028124                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14809.576358                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14678.665982                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14743.387000                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28191.365173                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27859.019656                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28024.876090                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15890.760284                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16368.223103                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16128.997682                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 40139.290079                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40762.418728                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 40451.654604                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13437.966462                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13246.065278                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13342.463552                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        81000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        32000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        56500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18739.896929                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18499.092011                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18618.471143                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18318.618934                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18189.651249                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18253.686890                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172235.277103                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173828.755025                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.497152                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178548.172137                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160224.592114                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168952.876087                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175275.380140                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166780.305254                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170982.036106                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         13976964                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.880033                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          878227495                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13977476                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            62.831622                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      35142475250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   257.003288                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   254.876744                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.501960                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.497806                       # Average percentage of cache occupancy
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+system.cpu0.icache.tags.total_refs          868036851                       # Total number of references to valid blocks.
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 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          213                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
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 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        906182457                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       906182457                       # Number of data accesses
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-system.cpu0.icache.overall_miss_latency::total 187406089157                       # number of overall miss cycles
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13398.365927                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.106262                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.715536                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13398.365927                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.106262                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13407.715536                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13398.365927                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.106262                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13407.715536                       # average overall miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.317514                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13422.827309                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13387.317514                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13422.827309                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.374735                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13387.317514                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13422.827309                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -995,60 +987,60 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7004074                       # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6973407                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::cpu0.inst      7004074                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6973407                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13977481                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25928                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17197                       # number of ReadReq MSHR uncacheable
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+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        26185                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        16940                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25928                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17197                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        26185                       # number of overall MSHR uncacheable misses
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 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  83323187568                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  83088246273                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841                       # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  83088246273                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 166411433841                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  83323187568                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  83088246273                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 166411433841                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1928508500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1282516750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3211025250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1928508500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1282516750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   3211025250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015666                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.015666                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.015666                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.681277                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74458.556522                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74458.556522                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  86336960500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  85935504000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 172272464500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  86336960500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  85935504000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 172272464500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  86336960500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  85935504000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 172272464500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959231000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1269892000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3229123000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959231000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1269892000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   3229123000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015724                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.015724                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.015724                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12422.827309                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12422.827309                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12422.827309                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74878.214493                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74878.214493                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1079,73 +1071,76 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   130358                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               130358                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20442                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94115                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       130351                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.276177                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    74.962722                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       130349    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   127806                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               127806                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20371                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91874                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       127789                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.297365                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    80.104866                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047       127787    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       130351                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       114564                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23894.842621                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 20601.133760                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13695.118153                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        72946     63.67%     63.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        40612     35.45%     99.12% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          507      0.44%     99.56% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          353      0.31%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           19      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           47      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           10      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           28      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           26      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       127789                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       112262                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24820.406727                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21828.616459                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13574.434559                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        72880     64.92%     64.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        38528     34.32%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          428      0.38%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          314      0.28%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            5      0.00%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           36      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            8      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           20      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           22      0.02%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::294912-327679            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::327680-360447            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       114564                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples     26318568                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean    31.814872                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -811003296  -3081.49%  -3081.49% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1      837321864   3181.49%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total     26318568                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        94116     82.16%     82.16% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        20442     17.84%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       114558                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       130358                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       112262                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   8237382924                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.971809                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.165518                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0      232218204      2.82%      2.82% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     8005164720     97.18%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   8237382924                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        91874     81.85%     81.85% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        20371     18.15%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       112245                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       127806                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       130358                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       114558                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       127806                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       112245                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       114558                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       244916                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       112245                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       240051                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    83582440                       # DTB read hits
-system.cpu1.dtb.read_misses                     99281                       # DTB read misses
-system.cpu1.dtb.write_hits                   76249670                       # DTB write hits
-system.cpu1.dtb.write_misses                    31077                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51825                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    82941587                       # DTB read hits
+system.cpu1.dtb.read_misses                     97218                       # DTB read misses
+system.cpu1.dtb.write_hits                   75253518                       # DTB write hits
+system.cpu1.dtb.write_misses                    30588                       # DTB write misses
+system.cpu1.dtb.flush_tlb                       51836                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21270                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   73142                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              20662                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   71746                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4747                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4678                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9967                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                83681721                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76280747                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9800                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                83038805                       # DTB read accesses
+system.cpu1.dtb.write_accesses               75284106                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        159832110                       # DTB hits
-system.cpu1.dtb.misses                         130358                       # DTB misses
-system.cpu1.dtb.accesses                    159962468                       # DTB accesses
+system.cpu1.dtb.hits                        158195105                       # DTB hits
+system.cpu1.dtb.misses                         127806                       # DTB misses
+system.cpu1.dtb.accesses                    158322911                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1175,135 +1170,133 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    77021                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                77021                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4430                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        67244                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        77021                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          77021    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        77021                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        71674                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27071.277590                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23813.549051                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 16581.978010                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        34935     48.74%     48.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535        35570     49.63%     98.37% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          418      0.58%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          591      0.82%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            6      0.01%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           60      0.08%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           17      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           30      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           20      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    77092                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                77092                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4382                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        67241                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        77092                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          77092    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        77092                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        71623                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28009.703587                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25156.150396                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 15232.175605                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        36121     50.43%     50.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535        34500     48.17%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          359      0.50%     99.10% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          519      0.72%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           46      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           17      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           23      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        71674                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   -853687296                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     -853687296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   -853687296                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        67244     93.82%     93.82% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         4430      6.18%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        71674                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        71623                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   -887431296                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     -887431296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   -887431296                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        67241     93.88%     93.88% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         4382      6.12%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        71623                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77021                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77021                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77092                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77092                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71674                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71674                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       148695                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   445961246                       # ITB inst hits
-system.cpu1.itb.inst_misses                     77021                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71623                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71623                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       148715                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   441142214                       # ITB inst hits
+system.cpu1.itb.inst_misses                     77092                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51825                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                       51836                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21270                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   52758                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              20662                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   52225                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               446038267                       # ITB inst accesses
-system.cpu1.itb.hits                        445961246                       # DTB hits
-system.cpu1.itb.misses                          77021                       # DTB misses
-system.cpu1.itb.accesses                    446038267                       # DTB accesses
-system.cpu1.numCycles                     51824432674                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               441219306                       # ITB inst accesses
+system.cpu1.itb.hits                        441142214                       # DTB hits
+system.cpu1.itb.misses                          77092                       # DTB misses
+system.cpu1.itb.accesses                    441219306                       # DTB accesses
+system.cpu1.numCycles                     51832427631                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  445688230                       # Number of instructions committed
-system.cpu1.committedOps                    523564727                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            480567684                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                428483                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26273151                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     68126466                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   480567684                       # number of integer instructions
-system.cpu1.num_fp_insts                       428483                       # number of float instructions
-system.cpu1.num_int_register_reads          701499135                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         381123451                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              693452                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             356440                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           117557193                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          117240637                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    159825990                       # number of memory refs
-system.cpu1.num_load_insts                   83579816                       # Number of load instructions
-system.cpu1.num_store_insts                  76246174                       # Number of store instructions
-system.cpu1.num_idle_cycles              50239290608.732407                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1585142065.267594                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030587                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969413                       # Percentage of idle cycles
-system.cpu1.Branches                         99529261                       # Number of branches fetched
+system.cpu1.committedInsts                  440867885                       # Number of instructions committed
+system.cpu1.committedOps                    517886143                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            475513559                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                454227                       # Number of float alu accesses
+system.cpu1.num_func_calls                   26111235                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     67284853                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   475513559                       # number of integer instructions
+system.cpu1.num_fp_insts                       454227                       # number of float instructions
+system.cpu1.num_int_register_reads          692532840                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         377153809                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              737892                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             372156                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           115804323                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          115491463                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    158189082                       # number of memory refs
+system.cpu1.num_load_insts                   82939410                       # Number of load instructions
+system.cpu1.num_store_insts                  75249672                       # Number of store instructions
+system.cpu1.num_idle_cycles              50245805753.829796                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1586621877.170202                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030611                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969389                       # Percentage of idle cycles
+system.cpu1.Branches                         98435537                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                362846766     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1082718      0.21%     69.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    48965      0.01%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             50459      0.01%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::MemRead                83579816     15.95%     85.45% # Class of executed instruction
-system.cpu1.op_class::MemWrite               76246174     14.55%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                358757749     69.23%     69.23% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1128666      0.22%     69.45% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    49961      0.01%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             51912      0.01%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::MemRead                82939410     16.01%     85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite               75249672     14.52%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 523854940                       # Class of executed instruction
+system.cpu1.op_class::total                 518177412                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq                40327                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40327                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40326                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40326                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1320,11 +1313,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231012                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231012                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231010                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353796                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353794                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1341,11 +1334,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334480                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334472                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334472                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492400                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1374,431 +1367,444 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           606981976                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568807378                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148423298                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements               115487                       # number of replacements
-system.iocache.tags.tagsinuse               10.456623                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               10.455201                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs               115503                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13157342382000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.510546                       # Average occupied blocks per requestor
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-system.iocache.demand_avg_miss_latency::total 176912.781806                       # average overall miss latency
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-system.iocache.overall_avg_miss_latency::total 176912.781806                       # average overall miss latency
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+system.iocache.overall_avg_miss_latency::realview.ide 178628.462504                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 178434.212026                       # average overall miss latency
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-system.iocache.blocked::no_mshrs                16113                       # number of cycles access was blocked
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-system.iocache.avg_blocked_cycles::no_mshrs     6.673307                       # average number of cycles each access was blocked
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 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
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-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
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-system.iocache.ReadReq_mshr_misses::total         8879                       # number of ReadReq MSHR misses
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-system.iocache.overall_mshr_misses::total         8882                       # number of overall MSHR misses
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-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1105053392                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1108195392                       # number of ReadReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::realview.ide   1105053392                       # number of demand (read+write) MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::realview.ide   1105053392                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1108388892                       # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide   1137204237                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1140624237                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
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 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
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-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::total 124810.833652                       # average ReadReq mshr miss latency
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-system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
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-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133623.873866                       # average WriteInvalidateReq mshr miss latency
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-system.iocache.demand_avg_mshr_miss_latency::realview.ide 124977.764307                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 124790.462959                       # average overall mshr miss latency
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-system.iocache.overall_avg_mshr_miss_latency::realview.ide 124977.764307                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 124790.462959                       # average overall mshr miss latency
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+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 128628.462504                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 128454.971503                       # average ReadReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 128628.462504                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 128434.212026                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 128628.462504                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 128434.212026                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1294928                       # number of replacements
-system.l2c.tags.tagsinuse                65284.624377                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   28063625                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1358068                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    20.664374                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7589253000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38468.321907                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   163.057226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   246.703748                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3367.231509                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9600.385059                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   149.839093                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   239.160217                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3055.361096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9994.564521                       # Average occupied blocks per requestor
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-system.l2c.UpgradeReq_misses::total             35517                       # number of UpgradeReq misses
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 system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
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-system.l2c.UpgradeReq_accesses::cpu1.data        22584                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           45375                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.InvalidateReq_miss_latency::cpu1.data  20428221500                       # number of InvalidateReq miss cycles
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 system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.416764                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.406925                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.411854                       # miss rate for WriteInvalidateReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780287                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.782744                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781951                       # miss rate for UpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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-system.l2c.overall_miss_rate::total          0.036940                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85777.693857                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87811.479466                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82274.943923                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85947.878229                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.data 83816.171463                       # average ReadReq miss latency
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-system.l2c.WriteInvalidateReq_avg_miss_latency::total     0.244141                       # average WriteInvalidateReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15482.335149                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15471.683926                       # average UpgradeReq miss latency
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+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.419151                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.414851                       # miss rate for InvalidateReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15280.042981                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15457.681956                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80845.940457                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81223.656354                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 81041.636804                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85777.693857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87811.479466                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 81442.990751                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 81493.965054                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1807,255 +1813,269 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1109675                       # number of writebacks
-system.l2c.writebacks::total                  1109675                       # number of writebacks
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data        17622                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        26185                       # number of overall MSHR uncacheable misses
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+system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        16940                       # number of overall MSHR uncacheable misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    143576000                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    355619500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    721407500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        69500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        20500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        90000                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  16833400500                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2684393500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   5861699500                       # number of ReadCleanReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10024806000                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  17846311500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  35216676000                       # number of InvalidateReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1058142000                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2625286500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5273982000                       # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total     0.009714                       # mshr miss rate for ReadReq accesses
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781889                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781951                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.781920                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.231584                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.248366                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.239985                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007993                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012004                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005522                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.084925                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008832                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012166                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005802                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.091507                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.036940                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007993                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012004                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005522                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.084925                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008832                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012166                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005802                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.091507                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036940                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70584.855526                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71285.881179                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 70730.178710                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31502.460477                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31502.184387                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 31502.324350                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17535.115563                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17534.651061                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17534.885097                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68338.774797                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68719.459499                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 68536.009295                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69123.439889                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69620.930581                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69446.512064                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69123.439889                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69446.512064                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154974.947778                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158447.133121                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102365.321290                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162747.486346                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145352.227526                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.231313                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.226518                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.228910                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005914                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.040908                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040593                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040750                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.410529                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.419151                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.414851                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.008714                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012363                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.086564                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011087                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.084774                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.035963                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.008714                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012363                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.086564                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011087                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.084774                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.035963                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77005.498721                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20655.485911                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.137364                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20655.314093                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        20500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        45000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70537.296580                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70520.567486                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70529.000862                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71471.937718                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 73037.508636                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73047.399754                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73042.475457                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69043.995246                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69120.579339                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69082.783581                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71435.531058                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71442.990751                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 71493.965054                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71435.531058                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71442.990751                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 71493.965054                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159735.277103                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161328.755025                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105428.158638                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167048.172137                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148724.592114                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157452.876087                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163256.950484                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154798.415028                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 121293.301851                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              450083                       # Transaction distribution
-system.membus.trans_dist::ReadResp             450083                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
-system.membus.trans_dist::Writeback           1216305                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       614546                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       614546                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36081                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76829                       # Transaction distribution
+system.membus.trans_dist::ReadResp             448840                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33709                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33709                       # Transaction distribution
+system.membus.trans_dist::Writeback           1181427                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191531                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35493                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36083                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            513152                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           513152                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35495                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            990576                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           990576                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        372011                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4043368                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4173072                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335046                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335046                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4508118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4129743                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4259441                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       340465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4599906                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159836512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    160006362                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14048000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14048000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               174054362                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3335                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2864020                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    155575648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    155745486                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7203136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7203136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               162948622                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3620                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2991422                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2864020    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2991422    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2864020                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107121000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2991422                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           107341500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5172000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5250000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         10421674858                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7710006309                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5445003775                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7440287022                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151621202                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228944719                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2099,51 +2119,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           22091229                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          22083154                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7866652                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1339933                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1233169                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45378                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            1264904                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          21840032                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33709                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33709                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          8906693                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        16372534                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           44670                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45380                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2140586                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2140586                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     28041212                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28486273                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       793018                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1241724                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              58562227                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    894731284                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1156290950                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2684984                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3951520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2057658738                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          492069                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         33517490                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.039407                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.194561                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp          44672                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2102857                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2102857                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      13867412                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6715681                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1335478                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1228814                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41686402                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30339787                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       785213                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1207911                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              74019313                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    887686868                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1058482234                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2638496                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3801896                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             1952609494                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1875627                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         50645688                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.052912                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.223858                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               32196665     96.06%     96.06% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1320825      3.94%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               47965928     94.71%     94.71% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                2679760      5.29%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           33517490                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        25817690750                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1207500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           50645688                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        32319092000                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy          1371000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       21033645158                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       20844243000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14294630789                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       13901838902                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         457872249                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         455401000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         748277250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         732674000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index ebffe6201..6393b5a08 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.122213                       # Number of seconds simulated
-sim_ticks                                5122212682000                       # Number of ticks simulated
-final_tick                               5122212682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.130109                       # Number of seconds simulated
+sim_ticks                                5130108675000                       # Number of ticks simulated
+final_tick                               5130108675000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 178126                       # Simulator instruction rate (inst/s)
-host_op_rate                                   352092                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2236626113                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 810964                       # Number of bytes of host memory used
-host_seconds                                  2290.15                       # Real time elapsed on the host
-sim_insts                                   407934867                       # Number of instructions simulated
-sim_ops                                     806343968                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 175723                       # Simulator instruction rate (inst/s)
+host_op_rate                                   347336                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2210269457                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 810456                       # Number of bytes of host memory used
+host_seconds                                  2321.03                       # Real time elapsed on the host
+sim_insts                                   407858109                       # Number of instructions simulated
+sim_ops                                     806179275                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1047104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10801152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1044544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10779584                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11881280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1047104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1047104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9569088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9569088                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           66                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16361                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168768                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11857088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1044544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1044544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9583168                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9583168                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           67                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16321                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168431                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185645                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149517                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149517                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               204424                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2108689                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5535                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2319560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          204424                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             204424                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1868155                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1868155                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1868155                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           825                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              204424                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2108689                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5535                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4187715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185645                       # Number of read requests accepted
-system.physmem.writeReqs                       196237                       # Number of write requests accepted
-system.physmem.readBursts                      185645                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     196237                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11872960                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10880320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11881280                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               12559168                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   26214                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1708                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11253                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10547                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11972                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11655                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11971                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11254                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11364                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11315                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11445                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11672                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11062                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11423                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12308                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12737                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11748                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11789                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               11864                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10686                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10651                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9860                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               10294                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               10368                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9733                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9712                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9632                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10471                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              10725                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              10392                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              11457                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              11384                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              11667                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              11109                       # Per bank write bursts
+system.physmem.num_reads::total                185267                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149737                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149737                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               203611                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2101239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5527                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2311274                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          203611                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             203611                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1868024                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1868024                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1868024                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              203611                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2101239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5527                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4179299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185267                       # Number of read requests accepted
+system.physmem.writeReqs                       149737                       # Number of write requests accepted
+system.physmem.readBursts                      185267                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149737                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11846656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9581440                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11857088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9583168                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          48775                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11590                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11256                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12288                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11911                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11840                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11665                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10867                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10808                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11222                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11056                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11302                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11775                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11547                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12196                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11932                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11849                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10246                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9545                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9025                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8913                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9024                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9097                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8779                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8697                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8886                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9043                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9545                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9380                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9802                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9849                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10052                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9827                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          85                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5122212630000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5130108625500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185645                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185267                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 196237                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    171240                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1948                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       451                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149737                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170610                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11668                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2033                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        36                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,302 +156,301 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7542                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     2479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      200                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        73901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      307.887796                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.352303                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.737558                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          28243     38.22%     38.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17330     23.45%     61.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7468     10.11%     71.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4217      5.71%     77.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3016      4.08%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1973      2.67%     84.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1390      1.88%     86.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1267      1.71%     87.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8997     12.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          73901                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6788                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.329258                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      584.024068                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6787     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2978                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7955                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9979                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        9                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        72239                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.626919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.108811                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     319.147383                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27668     38.30%     38.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17613     24.38%     62.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7498     10.38%     73.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4242      5.87%     78.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2823      3.91%     82.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1928      2.67%     85.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1515      2.10%     87.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1131      1.57%     89.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7821     10.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          72239                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7351                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.179159                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      561.374907                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7350     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6788                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6788                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.044932                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.591825                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       43.260290                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            6382     94.02%     94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              87      1.28%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               9      0.13%     95.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               9      0.13%     95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              22      0.32%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             15      0.22%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            29      0.43%     96.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            26      0.38%     96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            35      0.52%     97.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             9      0.13%     97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            41      0.60%     98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            54      0.80%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             7      0.10%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             6      0.09%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.01%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             4      0.06%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.03%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.06%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.04%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             5      0.07%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            19      0.28%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             6      0.09%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             1      0.01%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.01%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             1      0.01%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             3      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             4      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6788                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2015945224                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5494351474                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    927575000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10866.75                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7351                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7351                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.365937                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.603384                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.112022                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6287     85.53%     85.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              96      1.31%     86.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             185      2.52%     89.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              82      1.12%     90.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             111      1.51%     91.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             202      2.75%     94.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              31      0.42%     95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              14      0.19%     95.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              14      0.19%     95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.14%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               9      0.12%     95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.07%     95.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             246      3.35%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               8      0.11%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.05%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.11%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             7      0.10%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.19%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7351                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1992019456                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5462719456                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    925520000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10761.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29616.75                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.32                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.45                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29511.62                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.03                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     152167                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    129451                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.14                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13413076.89                       # Average gap between requests
-system.physmem.pageHitRate                      79.21                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  269256960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  146916000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 712374000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                538928640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           334557721680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           129214187775                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2959979121750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3425418506805                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.738637                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4924130039468                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    171041780000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     151846                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110728                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.03                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15313574.24                       # Average gap between requests
+system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  269393040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  146990250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 719355000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                475152480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           129448929735                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2964510370500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3430643592525                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.727957                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4931666056220                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    171305420000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27040752032                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27131976280                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  289434600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  157925625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 734635200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                562703760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           334557721680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           129751534755                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2959507764750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3425561720370                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.766596                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4923333713433                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    171041780000                       # Time in different power states
+system.physmem_1.actEnergy                  276733800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  150995625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 724448400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                494968320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           129698055360                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2964291831000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3430710434025                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.740988                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4931307220986                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    171305420000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27832687817                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27495924014                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86818912                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86818912                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            895085                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80098723                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78142837                       # Number of BTB hits
+system.cpu.branchPred.lookups                86802866                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86802866                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            898884                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79915985                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78142205                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.558156                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1551403                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             180089                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.780444                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1557172                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             181109                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449999443                       # number of cpu cycles simulated
+system.cpu.numCycles                        449354840                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27536923                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      428761982                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86818912                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79694240                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     418469892                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1877186                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     142405                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                58257                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        203994                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles          110                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          541                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9116293                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                453128                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4723                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          447350715                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.891249                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.050769                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27419696                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      428691862                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86802866                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79699377                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417944649                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1884104                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     141232                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                57475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        210217                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           60                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          747                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9135683                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                451645                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5364                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          446716128                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.893620                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051973                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                282061925     63.05%     63.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2147503      0.48%     63.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72168287     16.13%     79.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1568006      0.35%     80.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2127596      0.48%     80.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2318806      0.52%     81.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1512611      0.34%     81.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1884650      0.42%     81.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81561331     18.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281460190     63.01%     63.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2138894      0.48%     63.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72152839     16.15%     79.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1576063      0.35%     79.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2129707      0.48%     80.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2325949      0.52%     80.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1505469      0.34%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1859854      0.42%     81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81567163     18.26%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            447350715                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.192931                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.952806                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22908567                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             265367852                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150702709                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7432994                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 938593                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              837990299                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 938593                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25758226                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               223276953                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12890661                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154592541                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29893741                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834466404                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                451836                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12178537                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 145180                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               14794285                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           996780528                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1812316725                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114082490                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               470                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964296204                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 32484322                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             461178                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         464876                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38644871                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17242919                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10123129                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1280249                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1072002                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  828945592                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1192163                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 823760090                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            244912                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23793782                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     35793426                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         146866                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     447350715                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.841419                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.417821                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            446716128                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193172                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.954016                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 22817532                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264818622                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150719822                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7418100                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 942052                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              837890793                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 942052                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25656597                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               222831809                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12884327                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154608390                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29792953                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              834381209                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                449377                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12218260                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 146025                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14738284                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           996692347                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1812155414                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1113986633                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               357                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964101925                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 32590420                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             461964                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         466029                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  38550499                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17267645                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10120270                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1295034                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1078818                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  828854264                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1188467                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 823634023                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            239226                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23863451                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     35922872                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         148640                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     446716128                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.843753                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418621                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           263279849     58.85%     58.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13891965      3.11%     61.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9851915      2.20%     64.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7048956      1.58%     65.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74303394     16.61%     82.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4391366      0.98%     83.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72807233     16.28%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1204673      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              571364      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262749029     58.82%     58.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13824325      3.09%     61.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9784338      2.19%     64.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7058515      1.58%     65.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74344613     16.64%     82.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4389971      0.98%     83.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72797188     16.30%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1191150      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              576999      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       447350715                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       446716128                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1986394     72.18%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 608344     22.10%     94.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                157420      5.72%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1965794     71.96%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 607707     22.24%     94.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                158405      5.80%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            285236      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795541833     96.57%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150365      0.02%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                127447      0.02%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            286388      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795396124     96.57%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150331      0.02%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                127202      0.02%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 108      0.00%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  98      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.64% # Type of FU issued
@@ -475,98 +474,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.64% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18320687      2.22%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9334414      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18333764      2.23%     98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9340116      1.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              823760090                       # Type of FU issued
-system.cpu.iq.rate                           1.830580                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2752158                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003341                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2097867450                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         853943468                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819213197                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 514                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                630                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          182                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826226763                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     249                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1860072                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              823634023                       # Type of FU issued
+system.cpu.iq.rate                           1.832926                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2731906                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003317                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2096954851                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         853918294                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819080568                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 454                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                494                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          158                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826079323                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     218                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1864091                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3252614                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14803                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3276332                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15288                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        14318                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1702580                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores      1695886                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2208153                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         72229                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2207587                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         71306                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 938593                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               204923881                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              10223668                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830137755                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            158534                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17242919                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10123129                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             698460                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 397050                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8973453                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                 942052                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               204779875                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9950427                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830042731                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            154301                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17267645                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10120270                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             698404                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 395340                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8703386                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          14318                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         514177                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       531213                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1045390                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822137992                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17928402                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1491599                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         517416                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       531852                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1049268                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822011733                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17933627                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1492341                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27038601                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83256358                       # Number of branches executed
-system.cpu.iew.exec_stores                    9110199                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.826976                       # Inst execution rate
-system.cpu.iew.wb_sent                      821634339                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819213379                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640695638                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1049922326                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27049256                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83240327                       # Number of branches executed
+system.cpu.iew.exec_stores                    9115629                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.829315                       # Inst execution rate
+system.cpu.iew.wb_sent                      821506514                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819080726                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640638640                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1049832937                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.820476                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610231                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.822793                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610229                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23667492                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1045297                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            906773                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443789392                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.816952                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.674122                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        23734474                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1039827                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            910229                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443141458                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.819237                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.674506                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272960111     61.51%     61.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11180384      2.52%     64.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3592831      0.81%     64.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74586039     16.81%     81.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2426818      0.55%     82.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1631046      0.37%     82.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       941888      0.21%     82.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71056225     16.01%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5414050      1.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272292366     61.45%     61.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11181272      2.52%     63.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3605802      0.81%     64.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74611152     16.84%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2465682      0.56%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1626284      0.37%     82.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       958421      0.22%     82.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70995563     16.02%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5404916      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443789392                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407934867                       # Number of instructions committed
-system.cpu.commit.committedOps              806343968                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443141458                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407858109                       # Number of instructions committed
+system.cpu.commit.committedOps              806179275                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22410853                       # Number of memory references committed
-system.cpu.commit.loads                      13990304                       # Number of loads committed
-system.cpu.commit.membars                      471837                       # Number of memory barriers committed
-system.cpu.commit.branches                   82192569                       # Number of branches committed
+system.cpu.commit.refs                       22415696                       # Number of memory references committed
+system.cpu.commit.loads                      13991312                       # Number of loads committed
+system.cpu.commit.membars                      468143                       # Number of memory barriers committed
+system.cpu.commit.branches                   82176077                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735158454                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155650                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171552      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783497766     97.17%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144918      0.02%     97.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121442      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735014201                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155537                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171593      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783328307     97.17%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144946      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121298      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -593,231 +592,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13987725      1.73%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8420549      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13988731      1.74%     98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8424384      1.04%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806343968                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5414050                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1268308634                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1663603607                       # The number of ROB writes
-system.cpu.timesIdled                          289860                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2648728                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9794423343                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407934867                       # Number of Instructions Simulated
-system.cpu.committedOps                     806343968                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.103116                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.103116                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.906523                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.906523                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1091825743                       # number of integer regfile reads
-system.cpu.int_regfile_writes               655727641                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       182                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416065488                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321934300                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265346710                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 399949                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1659310                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993990                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19061899                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1659822                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.484303                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          41264250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993990                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999988                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total         806179275                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5404916                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1267572015                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1663421472                       # The number of ROB writes
+system.cpu.timesIdled                          288126                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2638712                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9810859930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407858109                       # Number of Instructions Simulated
+system.cpu.committedOps                     806179275                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.101743                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.101743                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907653                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907653                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1091670765                       # number of integer regfile reads
+system.cpu.int_regfile_writes               655627629                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       158                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416000684                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321879904                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265310647                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 400047                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1661478                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997539                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19061070                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1661990                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.468824                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997539                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          212                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88087332                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88087332                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10917280                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10917280                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8077307                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8077307                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64579                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64579                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      18994587                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18994587                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19059166                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19059166                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1807757                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1807757                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       333541                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       333541                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406408                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406408                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2141298                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2141298                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2547706                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2547706                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  27202744445                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  27202744445                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13955718277                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13955718277                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  41158462722                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  41158462722                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  41158462722                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  41158462722                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12725037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12725037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8410848                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8410848                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470987                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470987                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21135885                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21135885                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21606872                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21606872                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142063                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142063                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039656                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039656                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.862886                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.862886                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101311                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101311                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117912                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117912                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19221.267998                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16155.106877                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       414660                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88124232                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88124232                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10914055                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10914055                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8079827                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8079827                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        64080                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         64080                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      18993882                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18993882                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19057962                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19057962                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1815960                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1815960                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       334906                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       334906                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406730                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406730                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2150866                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2150866                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2557596                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2557596                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  27033028000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  27033028000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  13819339247                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  13819339247                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40852367247                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::cpu.data  40852367247                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40852367247                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12730015                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12730015                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8414733                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8414733                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       470810                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       470810                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21144748                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21144748                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21615558                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21615558                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142652                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.142652                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039800                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039800                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863894                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.863894                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.101721                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.101721                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118322                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118322                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18993.450660                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15972.955559                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       469124                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43514                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             51580                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.529347                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.095076                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1560749                       # number of writebacks
-system.cpu.dcache.writebacks::total           1560749                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       839489                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       839489                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        42702                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        42702                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       882191                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       882191                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       882191                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       882191                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       968268                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       968268                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290839                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290839                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402958                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402958                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1259107                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1259107                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1662065                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1662065                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       604701                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total       604701                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13919                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13919                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       618620                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       618620                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12834468768                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12834468768                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12344104823                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12344104823                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5960784250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5960784250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25178573591                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25178573591                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31139357841                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31139357841                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97454292000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97454292000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2593348000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2593348000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076092                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076092                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034579                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034579                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059572                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059572                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076923                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076923                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590                       # average overall mshr uncacheable latency
+system.cpu.dcache.writebacks::writebacks      1562865                       # number of writebacks
+system.cpu.dcache.writebacks::total           1562865                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       845003                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       845003                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44547                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44547                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       889550                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       889550                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       889550                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       889550                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970957                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       970957                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290359                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290359                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403239                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       403239                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1261316                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1261316                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1664555                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1664555                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13333994500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13333994500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12420799750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12420799750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6058828500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6058828500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25754794250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25754794250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31813622750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31813622750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793670000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793670000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2615433000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2615433000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076273                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076273                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034506                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034506                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856479                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856479                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059652                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059652                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077007                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077007                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        77765                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    13.263782                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       104942                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        77779                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.349233                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.263782                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.828986                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.828986                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       446439                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       446439                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       104946                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       104946                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       104946                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       104946                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       104946                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       104946                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        78849                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        78849                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        78849                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        78849                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        78849                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        78849                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    941548961                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    941548961                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    941548961                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    941548961                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    941548961                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    941548961                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       183795                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       183795                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       183795                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       183795                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       183795                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       183795                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.429005                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.429005                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.429005                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.429005                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.429005                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.429005                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.replacements        72618                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    14.793557                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       113213                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        72633                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.558699                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.793557                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.924597                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.924597                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       447394                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       447394                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113219                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       113219                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113219                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       113219                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113219                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       113219                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        73652                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        73652                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        73652                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        73652                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        73652                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        73652                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    910717000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    910717000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    910717000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    910717000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    910717000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    910717000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       186871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       186871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       186871                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       186871                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       186871                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       186871                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.394133                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.394133                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.394133                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -826,180 +825,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        22745                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        22745                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        78849                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        78849                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        78849                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        78849                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        78849                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        78849                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    823159683                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    823159683                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    823159683                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    823159683                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    823159683                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    823159683                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.429005                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.429005                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.429005                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.429005                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.429005                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.429005                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        18815                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        18815                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        73652                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        73652                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        73652                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        73652                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        73652                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        73652                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    837065000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    837065000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    837065000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.394133                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.394133                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.394133                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            996925                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.357790                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8050243                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            997437                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.070929                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      148006664250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.357790                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994839                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994839                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            991040                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.607437                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8073267                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            991552                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.142051                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147914027500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.607437                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995327                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995327                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10113779                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10113779                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8050243                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8050243                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8050243                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8050243                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8050243                       # number of overall hits
-system.cpu.icache.overall_hits::total         8050243                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1066046                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1066046                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1066046                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1066046                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1066046                       # number of overall misses
-system.cpu.icache.overall_misses::total       1066046                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14875004411                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14875004411                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14875004411                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14875004411                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14875004411                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14875004411                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9116289                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9116289                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9116289                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9116289                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9116289                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9116289                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116939                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116939                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116939                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116939                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116939                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116939                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13953.435791                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13953.435791                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7127                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10127588                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10127588                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8073267                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8073267                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8073267                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8073267                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8073267                       # number of overall hits
+system.cpu.icache.overall_hits::total         8073267                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1062411                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1062411                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1062411                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1062411                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1062411                       # number of overall misses
+system.cpu.icache.overall_misses::total       1062411                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14792091486                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14792091486                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14792091486                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14792091486                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14792091486                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14792091486                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9135678                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9135678                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9135678                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9135678                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9135678                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9135678                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116293                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.116293                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.116293                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.116293                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.116293                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.116293                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13923.134725                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13923.134725                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7978                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               341                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               382                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.900293                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.884817                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68556                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        68556                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        68556                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        68556                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        68556                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        68556                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       997490                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       997490                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       997490                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       997490                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       997490                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       997490                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12688553873                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12688553873                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12688553873                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12688553873                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12688553873                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12688553873                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109418                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109418                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109418                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109418                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109418                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109418                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70501                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        70501                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        70501                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        70501                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        70501                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        70501                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991910                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       991910                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       991910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       991910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       991910                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       991910                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13114232487                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13114232487                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13114232487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13114232487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13114232487                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13114232487                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108575                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108575                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108575                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        13512                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.614352                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        26763                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        13525                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.978780                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.614352                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.413397                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.413397                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements        15565                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.022675                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26231                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        15578                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.683849                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.022675                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376417                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.376417                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        96721                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        96721                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26775                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26775                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses       101828                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses       101828                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26240                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        26240                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26777                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26777                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26777                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26777                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14389                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        14389                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14389                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        14389                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14389                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        14389                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    168738994                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    168738994                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    168738994                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    168738994                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    168738994                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    168738994                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41164                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        41164                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26242                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        26242                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26242                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        26242                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        16448                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        16448                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        16448                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        16448                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        16448                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        16448                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    193358500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    193358500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    193358500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    193358500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    193358500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    193358500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        42688                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        42688                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41166                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        41166                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41166                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        41166                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.349553                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.349553                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.349536                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.349536                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.349536                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.349536                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        42690                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        42690                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        42690                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        42690                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.385307                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.385307                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.385289                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.385289                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.385289                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.385289                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1008,177 +1007,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3066                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3066                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14389                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14389                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14389                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        14389                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14389                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        14389                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    147144512                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    147144512                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    147144512                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    147144512                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    147144512                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    147144512                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.349553                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.349553                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.349536                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.349536                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.349536                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.349536                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         3018                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         3018                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        16448                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        16448                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        16448                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        16448                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        16448                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        16448                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    176910500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    176910500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    176910500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    176910500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    176910500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    176910500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.385307                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.385307                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.385289                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.385289                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112729                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64831.922119                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3833002                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176853                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.673378                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112892                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64819.691770                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4938747                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176773                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.938356                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.577905                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.126849                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3105.817202                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.771095                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000222                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000017                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047391                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.170531                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989257                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64124                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          694                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3262                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7383                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52712                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978455                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         35081373                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        35081373                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68578                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12140                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       981027                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1334830                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2396575                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1586560                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1586560                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.322898                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.136173                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3138.561208                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.771016                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000310                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047891                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.169851                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989070                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63881                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          774                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3319                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54573                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974747                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43864381                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43864381                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1584698                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1584698                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data          310                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total          310                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       154702                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       154702                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        68578                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        12140                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       981027                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1489532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2551277                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        68578                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        12140                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       981027                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1489532                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2551277                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           66                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16363                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        35684                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        52120                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1439                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1439                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134046                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       134046                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           66                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16363                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169730                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        186166                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           66                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16363                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169730                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       186166                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6097000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       666500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1366410532                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3072121000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4445295032                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     22717321                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     22717321                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10374564266                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10374564266                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6097000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       666500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1366410532                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13446685266                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14819859298                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6097000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       666500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1366410532                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13446685266                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14819859298                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        68644                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12147                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       997390                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1370514                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2448695                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1586560                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1586560                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1749                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1749                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       288748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       288748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        68644                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        12147                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       997390                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1659262                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2737443                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        68644                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        12147                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       997390                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1659262                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2737443                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000961                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000576                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016406                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026037                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021285                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.822756                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.822756                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464232                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.464232                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000961                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000576                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016406                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102292                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068007                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000961                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000576                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016406                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102292                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068007                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1187,176 +1192,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102850                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102850                       # number of writebacks
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
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-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       604701                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total       604701                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13919                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13919                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       618620                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       618620                       # number of overall MSHR uncacheable misses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     26446420                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88988446000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88988446000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2411352000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2411352000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91399798000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91399798000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000961                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000576                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016404                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026036                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021284                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.822756                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.822756                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464232                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464232                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000961                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000576                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016404                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068006                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000961                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000576                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016404                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068006                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           90                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total           90                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1787                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1787                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133737                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133737                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16321                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16321                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           67                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35671                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35743                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           67                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16321                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185801                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           67                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16321                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169408                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185801                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37875000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37875000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8960834500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8960834500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195971500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195971500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       365000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2711142000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2717014500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195971500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11671976500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12873820500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       365000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195971500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11671976500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12873820500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257461500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257461500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2455867500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2455867500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92713329000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92713329000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.852170                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.852170                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464442                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464442                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016461                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025971                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024570                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067954                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067954                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3067430                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3066889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13919                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13919                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1586560                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46781                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       288754                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       288754                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1643                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            4                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1994880                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6121448                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29602                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       170238                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8316168                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63832960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207882816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       973632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5848896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278538304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       63315                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5007317                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.009852                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.098766                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq         602896                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3059319                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13875                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13875                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1734439                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1113474                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287963                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287963                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       991910                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1465068                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1642                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2973341                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6222105                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        35861                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       172954                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9404261                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63456832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208155201                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1084160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5514304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278210497                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      220375                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6313792                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.033219                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.179209                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4957986     99.01%     99.01% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              49331      0.99%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            6104051     96.68%     96.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             209741      3.32%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5007317                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4072528967                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6313792                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4643672976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       555000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       564000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1500637871                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1489388443                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3138590336                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3104272690                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      21588991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      24683477                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     118331389                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     110523908                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               223899                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              223899                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57753                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              11033                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               222096                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              222096                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57708                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57708                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1642                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1642                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       423734                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
@@ -1366,21 +1382,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       468050                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95254                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95254                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  566590                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       464350                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3284                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3284                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  562892                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       211867                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
@@ -1390,19 +1406,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       240311                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027800                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027800                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3274683                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3915016                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       238452                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3272836                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3914184                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1414,7 +1430,7 @@ system.iobus.reqLayer7.occupancy                50000                       # La
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            211868000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1432,177 +1448,179 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           257302678                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           242657095                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           457017000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           453362000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50364257                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47572                       # number of replacements
-system.iocache.tags.tagsinuse                0.078977                       # Cycle average of tags in use
+system.iocache.tags.replacements                47574                       # number of replacements
+system.iocache.tags.tagsinuse                0.103760                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47588                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4993305876000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.078977                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.004936                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.004936                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4993210499000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103760                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006485                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.006485                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428643                       # Number of tag accesses
-system.iocache.tags.data_accesses              428643                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          907                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               907                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          907                       # number of overall misses
-system.iocache.overall_misses::total              907                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142095944                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    142095944                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8602345477                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8602345477                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    142095944                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    142095944                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    142095944                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    142095944                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          907                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             907                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          907                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            907                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
+system.iocache.tags.data_accesses              428661                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
+system.iocache.overall_misses::total              909                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141558677                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    141558677                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5512975418                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5512975418                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    141558677                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    141558677                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    141558677                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    141558677                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 156665.869901                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 156665.869901                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 156665.869901                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         29724                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 155730.117712                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 155730.117712                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 155730.117712                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 4480                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.634821                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          907                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          907                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          907                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          907                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          907                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     94520448                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     94520448                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6172895487                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6172895487                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     94520448                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     94520448                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     94520448                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     94520448                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     96108677                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3176975418                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3176975418                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     96108677                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     96108677                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 104212.180816                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 104212.180816                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              657725                       # Transaction distribution
-system.membus.trans_dist::ReadResp             657721                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13919                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13919                       # Transaction distribution
-system.membus.trans_dist::Writeback            149517                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2208                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1727                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133760                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133758                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            4                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       468050                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477841                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            8                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1715089                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141457                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141457                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1859832                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       240311                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538377                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18435328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20214016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                26225708                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1635                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1005577                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001634                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040388                       # Request fanout histogram
+system.membus.trans_dist::ReadReq              602896                       # Transaction distribution
+system.membus.trans_dist::ReadResp             655847                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13875                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13875                       # Transaction distribution
+system.membus.trans_dist::Writeback            149737                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            10183                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2524                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2074                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133454                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133450                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         52973                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1642                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1642                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           22                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464350                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769192                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       487788                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           44                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141823                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141823                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1866481                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238452                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538381                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18425216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20202049                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                23223657                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1607                       # Total snoops (count)
+system.membus.snoop_fanout::samples           1014551                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001618                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.040197                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1003934     99.84%     99.84% # Request fanout histogram
-system.membus.snoop_fanout::2                    1643      0.16%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 1012909     99.84%     99.84% # Request fanout histogram
+system.membus.snoop_fanout::2                    1642      0.16%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             1005577                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           357821000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1014551                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           354940000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           388531000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           388594500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3284000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1203162900                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1018302522                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                5000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               27500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1642000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2211768878                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2206598693                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           51465743                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           86075861                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index 4c2a41024..7d82f190a 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.305853                       # Number of seconds simulated
-sim_ticks                                5305853045500                       # Number of ticks simulated
-final_tick                               5305853045500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.305855                       # Number of seconds simulated
+sim_ticks                                5305855051000                       # Number of ticks simulated
+final_tick                               5305855051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 178751                       # Simulator instruction rate (inst/s)
-host_op_rate                                   342595                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8842177355                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 856496                       # Number of bytes of host memory used
-host_seconds                                   600.06                       # Real time elapsed on the host
-sim_insts                                   107261902                       # Number of instructions simulated
-sim_ops                                     205578300                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 186796                       # Simulator instruction rate (inst/s)
+host_op_rate                                   357991                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9246678170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1105624                       # Number of bytes of host memory used
+host_seconds                                   573.81                       # Real time elapsed on the host
+sim_insts                                   107186053                       # Number of instructions simulated
+sim_ops                                     205419480                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11415232                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           11415232                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9161984                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total         9161984                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       178363                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              178363                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       143156                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             143156                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0      2151441                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total               2151441                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0      1726769                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total              1726769                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0      3878211                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total              3878211                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      178363                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     143156                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    178363                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   143156                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               11360576                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   54656                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                 9153536                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                11415232                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys              9161984                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    854                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   108                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11371136                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           11371136                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9131456                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total         9131456                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       177674                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              177674                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       142679                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             142679                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0      2143130                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total               2143130                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0      1721015                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total              1721015                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0      3864145                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total              3864145                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      177674                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     142679                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    177674                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   142679                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               11313280                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   57856                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                 9121152                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                11371136                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys              9131456                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    904                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   135                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             10856                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             10881                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             10729                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             11226                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             11595                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             12060                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             11357                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             10544                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8             10640                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9             10408                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10            10338                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11            14247                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12            10851                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13            10291                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14            10803                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15            10683                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0              8741                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1              8453                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2              8515                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3              9195                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4              9530                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5              9557                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6              9142                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7              8665                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8              8844                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9              8855                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10             8455                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11             9314                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12             8873                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13             8616                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14             9161                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15             9108                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             10805                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             10794                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             10981                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             11389                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             11550                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             12175                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             10978                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             10407                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8             10706                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9             10369                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10            10514                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11            13718                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12            10819                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13            10294                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14            10714                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15            10557                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0              8779                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1              8773                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2              8745                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3              9209                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4              9395                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5              9648                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6              8754                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7              8594                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8              8776                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9              8713                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10             8651                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11             9041                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12             8739                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13             8605                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14             9111                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15             8985                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                  5305852911000                       # Total gap between requests
+system.mem_ctrls.totGap                  5305854916500                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                178363                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                177674                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               143156                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                  177440                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                      69                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               142679                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                  176703                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                      67                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                   2057                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                   2808                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                   8578                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   9141                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   8600                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                   9229                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                   9219                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                   8361                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                   9057                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                   9077                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                   8449                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                   8526                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                   8348                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                   8471                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                   8060                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                   8092                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                   8178                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                   7986                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                    125                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    114                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                    101                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                     94                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                     84                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                     73                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                     59                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                     33                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                     27                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                     19                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                      9                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                   2059                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                   2790                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                   8563                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   9122                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   8572                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                   9212                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                   9228                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                   8314                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                   9034                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                   9060                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                   8413                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                   8500                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                   8357                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                   8453                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                   8029                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                   8097                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                   8147                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                   7952                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                    108                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                     85                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                     89                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                     75                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                     64                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                     28                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                     18                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                      9                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::44                      4                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
@@ -184,213 +184,211 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples        60721                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    337.841076                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   199.411090                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   344.057801                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        20489     33.74%     33.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        14673     24.16%     57.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383         6364     10.48%     68.39% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511         3396      5.59%     73.98% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639         2745      4.52%     78.50% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         1826      3.01%     81.51% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         1362      2.24%     83.75% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023         1430      2.36%     86.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151         8436     13.89%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total        60721                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples         7928                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      22.388118                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev    317.537098                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023         7922     99.92%     99.92% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::1024-2047            2      0.03%     99.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::2048-3071            2      0.03%     99.97% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples        60336                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    338.676213                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   200.551275                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   343.723517                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        20068     33.26%     33.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        14736     24.42%     57.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383         6373     10.56%     68.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511         3491      5.79%     74.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639         2657      4.40%     78.44% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         1861      3.08%     81.52% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         1364      2.26%     83.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023         1338      2.22%     86.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151         8448     14.00%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total        60336                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples         7897                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      22.382170                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev    317.489285                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-1023         7891     99.92%     99.92% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total          7928                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples         7928                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      18.040363                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.696882                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      3.983964                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16             5814     73.34%     73.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17               14      0.18%     73.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18              181      2.28%     75.79% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19               14      0.18%     75.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20               36      0.45%     76.43% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21              489      6.17%     82.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22              149      1.88%     84.47% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23               53      0.67%     85.14% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24              653      8.24%     93.38% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25              113      1.43%     94.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26                3      0.04%     94.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27               13      0.16%     95.01% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28              312      3.94%     98.94% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29                4      0.05%     98.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30               10      0.13%     99.12% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31                5      0.06%     99.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32                9      0.11%     99.29% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33                9      0.11%     99.41% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34                2      0.03%     99.43% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35                3      0.04%     99.47% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36                4      0.05%     99.52% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37                5      0.06%     99.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::38                2      0.03%     99.61% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::39                3      0.04%     99.65% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40                6      0.08%     99.72% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41                2      0.03%     99.75% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42                1      0.01%     99.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43                3      0.04%     99.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44                6      0.08%     99.87% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45                2      0.03%     99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::46                1      0.01%     99.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48                1      0.01%     99.94% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::49                2      0.03%     99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::51                3      0.04%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total          7928                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                   1963261998                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat              5291555748                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                  887545000                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                     11060.07                       # Average queueing delay per DRAM burst
+system.mem_ctrls.rdPerTurnAround::total          7897                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples         7897                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      18.047106                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     17.696875                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      4.065797                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16             5800     73.45%     73.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                9      0.11%     73.56% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18              169      2.14%     75.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19               20      0.25%     75.95% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20               37      0.47%     76.42% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21              500      6.33%     82.75% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22              145      1.84%     84.59% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23               43      0.54%     85.13% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24              653      8.27%     93.40% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25              111      1.41%     94.81% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26               12      0.15%     94.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27               19      0.24%     95.20% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28              304      3.85%     99.05% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29                7      0.09%     99.14% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30                3      0.04%     99.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::31                6      0.08%     99.25% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32                6      0.08%     99.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::33                2      0.03%     99.35% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::35                3      0.04%     99.40% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::37                1      0.01%     99.42% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::38                3      0.04%     99.46% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::39                7      0.09%     99.54% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::40                3      0.04%     99.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::41                3      0.04%     99.62% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::42                6      0.08%     99.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::43                2      0.03%     99.72% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::44                6      0.08%     99.80% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::45                1      0.01%     99.81% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::48                4      0.05%     99.87% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::51                9      0.11%     99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::52                1      0.01%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total          7897                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                   1934453242                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat              5248890742                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                  883850000                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                     10943.33                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                29810.07                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                         2.14                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                         1.73                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                      2.15                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                      1.73                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                29693.33                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                         2.13                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                         1.72                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                      2.14                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                      1.72                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
 system.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.94                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   141459                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  118352                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.69                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                82.74                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                   16502455.25                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    81.05                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                231139440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                126117750                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy               696134400                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy              465251040                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy         346552109280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy         149731396200                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy         3052164794250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy           3549966942360                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            669.066980                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF  177173880000                       # Time in different power states
+system.mem_ctrls.avgWrQLen                      24.42                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   140774                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  118177                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 79.64                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                82.91                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                   16562526.08                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.10                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                229839120                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                125408250                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy               694816200                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy              465892560                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         346552617840                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy         149179147425                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy         3052653894750                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy           3549901616145                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            669.053686                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF  177174140000                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT   51294057500                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT   50484766750                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                227911320                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                124356375                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy               688428000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy              461544480                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy         346552109280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy         149042883510                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy         3052768752750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy           3549865985715                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            669.047952                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF  177173880000                       # Time in different power states
+system.mem_ctrls_1.actEnergy                226301040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                123477750                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy               683982000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy              457624080                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         346552617840                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy         148537848690                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy         3053216437500                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy           3549798288900                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            669.034212                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF  177174140000                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT   50287445500                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT   49544125250                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                     10611706091                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10611710102                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   59111887                       # Number of instructions committed
-system.cpu0.committedOps                    113456709                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            106426265                       # Number of integer alu accesses
+system.cpu0.committedInsts                   59039296                       # Number of instructions committed
+system.cpu0.committedOps                    113305650                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            106292214                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1016173                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     10055603                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   106426265                       # number of integer instructions
+system.cpu0.num_func_calls                    1017385                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     10037497                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   106292214                       # number of integer instructions
 system.cpu0.num_fp_insts                           48                       # number of float instructions
-system.cpu0.num_int_register_reads          200823032                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          90335124                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          200616677                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          90211380                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            61044422                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           44109295                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     12452626                       # number of memory refs
-system.cpu0.num_load_insts                    7522002                       # Number of load instructions
-system.cpu0.num_store_insts                   4930624                       # Number of store instructions
-system.cpu0.num_idle_cycles              10088968020.334099                       # Number of idle cycles
-system.cpu0.num_busy_cycles              522738070.665901                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049261                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950739                       # Percentage of idle cycles
-system.cpu0.Branches                         11433567                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass               130284      0.11%      0.11% # Class of executed instruction
-system.cpu0.op_class::IntAlu                100735872     88.79%     88.90% # Class of executed instruction
-system.cpu0.op_class::IntMult                   86129      0.08%     88.98% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    56904      0.05%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                     16      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.03% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7517799      6.63%     95.65% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4930624      4.35%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            60966470                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           44030878                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     12456031                       # number of memory refs
+system.cpu0.num_load_insts                    7518228                       # Number of load instructions
+system.cpu0.num_store_insts                   4937803                       # Number of store instructions
+system.cpu0.num_idle_cycles              10088651138.334099                       # Number of idle cycles
+system.cpu0.num_busy_cycles              523058963.665901                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049291                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950709                       # Percentage of idle cycles
+system.cpu0.Branches                         11416966                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               131109      0.12%      0.12% # Class of executed instruction
+system.cpu0.op_class::IntAlu                100580264     88.77%     88.88% # Class of executed instruction
+system.cpu0.op_class::IntMult                   86269      0.08%     88.96% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    57079      0.05%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                     16      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.01% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7514027      6.63%     95.64% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4937803      4.36%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 113457628                       # Class of executed instruction
+system.cpu0.op_class::total                 113306567                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu1.numCycles                     10608768454                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10608777066                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48150015                       # Number of instructions committed
-system.cpu1.committedOps                     92121591                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             88447957                       # Number of integer alu accesses
+system.cpu1.committedInsts                   48146757                       # Number of instructions committed
+system.cpu1.committedOps                     92113830                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             88441893                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1752470                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8220366                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    88447957                       # number of integer instructions
+system.cpu1.num_func_calls                    1752446                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      8219760                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    88441893                       # number of integer instructions
 system.cpu1.num_fp_insts                           48                       # number of float instructions
-system.cpu1.num_int_register_reads          171418672                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          73201138                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          171408328                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          73196137                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            50927853                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           32747912                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     14125902                       # number of memory refs
-system.cpu1.num_load_insts                    9133895                       # Number of load instructions
-system.cpu1.num_store_insts                   4992007                       # Number of store instructions
-system.cpu1.num_idle_cycles              10273983246.713898                       # Number of idle cycles
-system.cpu1.num_busy_cycles              334785207.286102                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031557                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968443                       # Percentage of idle cycles
-system.cpu1.Branches                         10582274                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               169782      0.18%      0.18% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 77660290     84.30%     84.49% # Class of executed instruction
-system.cpu1.op_class::IntMult                   98483      0.11%     84.59% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    71910      0.08%     84.67% # Class of executed instruction
+system.cpu1.num_cc_register_reads            50924734                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           32745964                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     14124901                       # number of memory refs
+system.cpu1.num_load_insts                    9133293                       # Number of load instructions
+system.cpu1.num_store_insts                   4991608                       # Number of store instructions
+system.cpu1.num_idle_cycles              10274072284.207695                       # Number of idle cycles
+system.cpu1.num_busy_cycles              334704781.792306                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031550                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968450                       # Percentage of idle cycles
+system.cpu1.Branches                         10581617                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               169787      0.18%      0.18% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 77653530     84.30%     84.49% # Class of executed instruction
+system.cpu1.op_class::IntMult                   98479      0.11%     84.59% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    71918      0.08%     84.67% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     84.67% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     84.67% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                     16      0.00%     84.67% # Class of executed instruction
@@ -417,17 +415,17 @@ system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.67% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.67% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.67% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.67% # Class of executed instruction
-system.cpu1.op_class::MemRead                 9129754      9.91%     94.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite                4992007      5.42%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 9129153      9.91%     94.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite                4991608      5.42%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  92122242                       # Class of executed instruction
+system.cpu1.op_class::total                  92114491                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq               857753                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              857753                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               36065                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              36065                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               842290                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              842290                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               35657                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              35657                       # Transaction distribution
 system.iobus.trans_dist::MessageReq              1791                       # Transaction distribution
 system.iobus.trans_dist::MessageResp             1791                       # Transaction distribution
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1702                       # Packet count per connected master and slave (bytes)
@@ -440,15 +438,15 @@ system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.p
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           66                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       917434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          964                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14814                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       742772                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       729402                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          158                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1702492                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1671974                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5284                       # Packet count per connected master and slave (bytes)
@@ -456,9 +454,9 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          396                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           28                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        30942                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        30330                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          384                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31030                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        30418                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12448                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
@@ -466,8 +464,8 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4614                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        85378                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 1791218                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        84154                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 1759476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3404                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6696                       # Cumulative packet size per connected master and slave (bytes)
@@ -478,15 +476,15 @@ system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           33                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       458717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1928                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7407                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1485538                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1458798                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          316                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1970762                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1935448                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3394                       # Cumulative packet size per connected master and slave (bytes)
@@ -494,9 +492,9 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          198                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           14                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15471                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15165                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          768                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15515                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15209                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
@@ -504,53 +502,53 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9225                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        51075                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2028533                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy                50000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        50463                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  1992607                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy                43500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 7000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy             10224000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy              9032500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               143500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               154500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy              1064000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               940000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                97500                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                92000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                56000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                52500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy             20660000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy             20247500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            700937500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            458718000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy              1276000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1157500                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy            31144500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy            30508000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            23664000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            20468500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           468374820                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           369412820                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             7594080                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             7528580                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy             1329500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy             1593000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             2404400                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             2422900                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy          2023552000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy          1846190500                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy            60655000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy            57610000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
@@ -567,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.ruby.clk_domain.clock                      500                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples               10895286                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.442462                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.830078                       # delay histogram for all message
-system.ruby.delayHist                    |    10293202     94.47%     94.47% |        1309      0.01%     94.49% |      600320      5.51%    100.00% |         166      0.00%    100.00% |         230      0.00%    100.00% |          12      0.00%    100.00% |          47      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                 10895286                       # delay histogram for all message
+system.ruby.delayHist::samples               10891010                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.442869                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.830823                       # delay histogram for all message
+system.ruby.delayHist                    |    10288616     94.47%     94.47% |        1282      0.01%     94.48% |      600649      5.52%    100.00% |         161      0.00%    100.00% |         257      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                 10891010                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples    152835089                      
+system.ruby.outstanding_req_hist::samples    152756591                      
 system.ruby.outstanding_req_hist::mean       1.000166                      
 system.ruby.outstanding_req_hist::gmean      1.000115                      
-system.ruby.outstanding_req_hist::stdev      0.012900                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152809653     99.98%     99.98% |       25436      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total     152835089                      
-system.ruby.latency_hist::bucket_size             256                      
-system.ruby.latency_hist::max_bucket             2559                      
-system.ruby.latency_hist::samples           152835088                      
-system.ruby.latency_hist::mean               3.434218                      
-system.ruby.latency_hist::gmean              3.107238                      
-system.ruby.latency_hist::stdev              5.763390                      
-system.ruby.latency_hist                 |   152826003     99.99%     99.99% |        6324      0.00%    100.00% |        2683      0.00%    100.00% |          40      0.00%    100.00% |          37      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total             152835088                      
+system.ruby.outstanding_req_hist::stdev      0.012901                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152731162     99.98%     99.98% |       25429      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total     152756591                      
+system.ruby.latency_hist::bucket_size             128                      
+system.ruby.latency_hist::max_bucket             1279                      
+system.ruby.latency_hist::samples           152756590                      
+system.ruby.latency_hist::mean               3.433707                      
+system.ruby.latency_hist::gmean              3.107293                      
+system.ruby.latency_hist::stdev              5.733578                      
+system.ruby.latency_hist                 |   152719525     99.98%     99.98% |       28048      0.02%     99.99% |        2695      0.00%    100.00% |        3637      0.00%    100.00% |        2109      0.00%    100.00% |         523      0.00%    100.00% |           9      0.00%    100.00% |          20      0.00%    100.00% |          17      0.00%    100.00% |           7      0.00%    100.00%
+system.ruby.latency_hist::total             152756590                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples       150173511                      
+system.ruby.hit_latency_hist::samples       150094333                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   150173511    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total         150173511                      
-system.ruby.miss_latency_hist::bucket_size          256                      
-system.ruby.miss_latency_hist::max_bucket         2559                      
-system.ruby.miss_latency_hist::samples        2661577                      
-system.ruby.miss_latency_hist::mean         27.933971                      
-system.ruby.miss_latency_hist::gmean        22.542647                      
-system.ruby.miss_latency_hist::stdev        36.007178                      
-system.ruby.miss_latency_hist            |     2652492     99.66%     99.66% |        6324      0.24%     99.90% |        2683      0.10%    100.00% |          40      0.00%    100.00% |          37      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total          2661577                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits     11100819                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses       532265                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses     11633084                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits     68582952                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses       323144                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses     68906096                       # Number of cache demand accesses
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   150094333    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total         150094333                      
+system.ruby.miss_latency_hist::bucket_size          128                      
+system.ruby.miss_latency_hist::max_bucket         1279                      
+system.ruby.miss_latency_hist::samples        2662257                      
+system.ruby.miss_latency_hist::mean         27.885506                      
+system.ruby.miss_latency_hist::gmean        22.530762                      
+system.ruby.miss_latency_hist::stdev        35.745831                      
+system.ruby.miss_latency_hist            |     2625192     98.61%     98.61% |       28048      1.05%     99.66% |        2695      0.10%     99.76% |        3637      0.14%     99.90% |        2109      0.08%     99.98% |         523      0.02%    100.00% |           9      0.00%    100.00% |          20      0.00%    100.00% |          17      0.00%    100.00% |           7      0.00%    100.00%
+system.ruby.miss_latency_hist::total          2662257                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits     11119260                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses       532503                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses     11651763                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits     68488995                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses       323914                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses     68812909                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -618,13 +616,13 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles            15                       # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits     12795046                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses      1313851                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14108897                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits     57694694                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses       492317                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses     58187011                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles            16                       # cycles for which number of transistions == max transitions
+system.ruby.l1_cntrl1.L1Dcache.demand_hits     12794938                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses      1313574                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14108512                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits     57691140                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses       492266                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses     58183406                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -635,71 +633,71 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits            0
 system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl1.fully_busy_cycles             7                       # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits      2434372                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       227205                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses      2661577                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.fully_busy_cycles             1                       # cycles for which number of transistions == max transitions
+system.ruby.l2_cntrl0.L2cache.demand_hits      2435460                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       226797                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses      2662257                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.fully_busy_cycles             5                       # cycles for which number of transistions == max transitions
 system.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     0.029987                      
-system.ruby.network.routers0.msg_count.Control::0       855409                      
-system.ruby.network.routers0.msg_count.Request_Control::2        42371                      
-system.ruby.network.routers0.msg_count.Response_Data::1       883866                      
-system.ruby.network.routers0.msg_count.Response_Control::1       509923                      
-system.ruby.network.routers0.msg_count.Response_Control::2       507294                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0       298509                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          176                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0       170526                      
-system.ruby.network.routers0.msg_bytes.Control::0      6843272                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       338968                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1     63638352                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1      4079384                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2      4058352                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0     21492648                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        12672                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1364208                      
-system.ruby.network.routers1.percent_links_utilized     0.057152                      
-system.ruby.network.routers1.msg_count.Control::0      1806168                      
-system.ruby.network.routers1.msg_count.Request_Control::2        40332                      
-system.ruby.network.routers1.msg_count.Response_Data::1      1830141                      
-system.ruby.network.routers1.msg_count.Response_Control::1      1256659                      
-system.ruby.network.routers1.msg_count.Response_Control::2      1255808                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0       276119                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          194                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0       942229                      
-system.ruby.network.routers1.msg_bytes.Control::0     14449344                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       322656                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1    131770152                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1     10053272                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2     10046464                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0     19880568                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        13968                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7537832                      
-system.ruby.network.routers2.percent_links_utilized     0.091505                      
-system.ruby.network.routers2.msg_count.Control::0      2839493                      
-system.ruby.network.routers2.msg_count.Request_Control::2        81198                      
-system.ruby.network.routers2.msg_count.Response_Data::1      2891200                      
-system.ruby.network.routers2.msg_count.Response_Control::1      1848800                      
-system.ruby.network.routers2.msg_count.Response_Control::2      1763102                      
-system.ruby.network.routers2.msg_count.Writeback_Data::0       574628                      
-system.ruby.network.routers2.msg_count.Writeback_Data::1          370                      
-system.ruby.network.routers2.msg_count.Writeback_Control::0      1112755                      
-system.ruby.network.routers2.msg_bytes.Control::0     22715944                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2       649584                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1    208166400                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1     14790400                      
-system.ruby.network.routers2.msg_bytes.Response_Control::2     14104816                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41373216                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1        26640                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8902040                      
-system.ruby.network.routers3.percent_links_utilized     0.006812                      
-system.ruby.network.routers3.msg_count.Control::0       177916                      
-system.ruby.network.routers3.msg_count.Response_Data::1       276580                      
-system.ruby.network.routers3.msg_count.Response_Control::1       130228                      
+system.ruby.network.routers0.percent_links_utilized     0.030013                      
+system.ruby.network.routers0.msg_count.Control::0       856417                      
+system.ruby.network.routers0.msg_count.Request_Control::2        42660                      
+system.ruby.network.routers0.msg_count.Response_Data::1       884950                      
+system.ruby.network.routers0.msg_count.Response_Control::1       510141                      
+system.ruby.network.routers0.msg_count.Response_Control::2       507455                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0       298492                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          178                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0       170402                      
+system.ruby.network.routers0.msg_bytes.Control::0      6851336                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2       341280                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1     63716400                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1      4081128                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2      4059640                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0     21491424                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        12816                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1363216                      
+system.ruby.network.routers1.percent_links_utilized     0.057139                      
+system.ruby.network.routers1.msg_count.Control::0      1805840                      
+system.ruby.network.routers1.msg_count.Request_Control::2        40537                      
+system.ruby.network.routers1.msg_count.Response_Data::1      1830038                      
+system.ruby.network.routers1.msg_count.Response_Control::1      1255303                      
+system.ruby.network.routers1.msg_count.Response_Control::2      1254313                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0       276120                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          190                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0       940436                      
+system.ruby.network.routers1.msg_bytes.Control::0     14446720                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2       324296                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1    131762736                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1     10042424                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2     10034504                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0     19880640                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        13680                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7523488                      
+system.ruby.network.routers2.percent_links_utilized     0.091475                      
+system.ruby.network.routers2.msg_count.Control::0      2839469                      
+system.ruby.network.routers2.msg_count.Request_Control::2        81710                      
+system.ruby.network.routers2.msg_count.Response_Data::1      2890401                      
+system.ruby.network.routers2.msg_count.Response_Control::1      1846120                      
+system.ruby.network.routers2.msg_count.Response_Control::2      1761768                      
+system.ruby.network.routers2.msg_count.Writeback_Data::0       574612                      
+system.ruby.network.routers2.msg_count.Writeback_Data::1          368                      
+system.ruby.network.routers2.msg_count.Writeback_Control::0      1110838                      
+system.ruby.network.routers2.msg_bytes.Control::0     22715752                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2       653680                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1    208108872                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1     14768960                      
+system.ruby.network.routers2.msg_bytes.Response_Control::2     14094144                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41372064                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1        26496                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8886704                      
+system.ruby.network.routers3.percent_links_utilized     0.006783                      
+system.ruby.network.routers3.msg_count.Control::0       177212                      
+system.ruby.network.routers3.msg_count.Response_Data::1       275392                      
+system.ruby.network.routers3.msg_count.Response_Control::1       129266                      
 system.ruby.network.routers3.msg_count.Writeback_Control::0        47545                      
 system.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers3.msg_bytes.Control::0      1423328                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1     19913760                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1      1041824                      
+system.ruby.network.routers3.msg_bytes.Control::0      1417696                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1     19828224                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1      1034128                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0       380360                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers4.percent_links_utilized     0.000239                      
@@ -710,120 +708,120 @@ system.ruby.network.routers4.msg_bytes.Response_Data::1        58248
 system.ruby.network.routers4.msg_bytes.Writeback_Control::0       380360                      
 system.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers5.percent_links_utilized            0                      
-system.ruby.network.routers6.percent_links_utilized     0.030950                      
-system.ruby.network.routers6.msg_count.Control::0      2839493                      
-system.ruby.network.routers6.msg_count.Request_Control::2        82703                      
-system.ruby.network.routers6.msg_count.Response_Data::1      2941298                      
-system.ruby.network.routers6.msg_count.Response_Control::1      1872805                      
-system.ruby.network.routers6.msg_count.Response_Control::2      1763102                      
-system.ruby.network.routers6.msg_count.Writeback_Data::0       574628                      
-system.ruby.network.routers6.msg_count.Writeback_Data::1          370                      
-system.ruby.network.routers6.msg_count.Writeback_Control::0      1160300                      
+system.ruby.network.routers6.percent_links_utilized     0.030942                      
+system.ruby.network.routers6.msg_count.Control::0      2839469                      
+system.ruby.network.routers6.msg_count.Request_Control::2        83197                      
+system.ruby.network.routers6.msg_count.Response_Data::1      2940795                      
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 system.ruby.network.routers4.throttle0.msg_count.Response_Data::1          809                      
@@ -835,43 +833,43 @@ system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        475
 system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380360                      
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+system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       574612                      
+system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          368                      
+system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1110838                      
+system.ruby.network.routers6.throttle2.msg_bytes.Control::0     21298056                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14602536                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1       985240                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14094144                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41372064                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        26496                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8886704                      
+system.ruby.network.routers6.throttle3.link_utilization     0.005259                      
+system.ruby.network.routers6.throttle3.msg_count.Control::0       177212                      
+system.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97371                      
+system.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15060                      
 system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47545                      
-system.ruby.network.routers6.throttle3.msg_bytes.Control::0      1423328                      
-system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7045560                      
-system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       122304                      
+system.ruby.network.routers6.throttle3.msg_bytes.Control::0      1417696                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7010712                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       120480                      
 system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380360                      
 system.ruby.network.routers6.throttle4.link_utilization     0.000255                      
 system.ruby.network.routers6.throttle4.msg_count.Response_Data::1          809                      
@@ -881,176 +879,176 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       3738
 system.ruby.network.routers6.throttle5.link_utilization            0                      
 system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       6112062                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         0.754100                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        2.339998                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     5536581     90.58%     90.58% |         390      0.01%     90.59% |      574653      9.40%     99.99% |         162      0.00%    100.00% |         217      0.00%    100.00% |          12      0.00%    100.00% |          47      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         6112062                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       6109475                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         0.754420                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        2.340404                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     5533989     90.58%     90.58% |         406      0.01%     90.59% |      574630      9.41%     99.99% |         158      0.00%    100.00% |         247      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         6109475                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       4700521                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.045023                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.596216                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     4673467     99.42%     99.42% |         451      0.01%     99.43% |         352      0.01%     99.44% |         567      0.01%     99.45% |       25509      0.54%    100.00% |         158      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |          10      0.00%    100.00% |           3      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         4700521                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       4698338                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.045583                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.599791                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     4670953     99.42%     99.42% |         477      0.01%     99.43% |         336      0.01%     99.43% |         540      0.01%     99.45% |       25880      0.55%    100.00% |         139      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |          10      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         4698338                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples         82703                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.000121                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.015550                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |       82698     99.99%     99.99% |           0      0.00%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total           82703                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples         83197                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.000192                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.019611                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |       83189     99.99%     99.99% |           0      0.00%     99.99% |           8      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total           83197                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          128                      
 system.ruby.LD.latency_hist::max_bucket          1279                      
-system.ruby.LD.latency_hist::samples         15017729                      
-system.ruby.LD.latency_hist::mean            4.875603                      
-system.ruby.LD.latency_hist::gmean           3.591894                      
-system.ruby.LD.latency_hist::stdev           9.357158                      
-system.ruby.LD.latency_hist              |    15001612     99.89%     99.89% |       13925      0.09%     99.99% |         816      0.01%     99.99% |         883      0.01%    100.00% |         364      0.00%    100.00% |         107      0.00%    100.00% |           3      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.LD.latency_hist::total           15017729                      
+system.ruby.LD.latency_hist::samples         15027912                      
+system.ruby.LD.latency_hist::mean            4.869020                      
+system.ruby.LD.latency_hist::gmean           3.591147                      
+system.ruby.LD.latency_hist::stdev           9.231737                      
+system.ruby.LD.latency_hist              |    15011958     99.89%     99.89% |       13851      0.09%     99.99% |         851      0.01%     99.99% |         792      0.01%    100.00% |         329      0.00%    100.00% |         121      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.LD.latency_hist::total           15027912                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples     13626729                      
+system.ruby.LD.hit_latency_hist::samples     13637263                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13626729    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total       13626729                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13637263    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total       13637263                      
 system.ruby.LD.miss_latency_hist::bucket_size          128                      
 system.ruby.LD.miss_latency_hist::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist::samples      1391000                      
-system.ruby.LD.miss_latency_hist::mean      23.249676                      
-system.ruby.LD.miss_latency_hist::gmean     20.961439                      
-system.ruby.LD.miss_latency_hist::stdev     23.942041                      
-system.ruby.LD.miss_latency_hist         |     1374883     98.84%     98.84% |       13925      1.00%     99.84% |         816      0.06%     99.90% |         883      0.06%     99.96% |         364      0.03%     99.99% |         107      0.01%    100.00% |           3      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total       1391000                      
-system.ruby.ST.latency_hist::bucket_size          256                      
-system.ruby.ST.latency_hist::max_bucket          2559                      
-system.ruby.ST.latency_hist::samples          9551572                      
-system.ruby.ST.latency_hist::mean            5.175450                      
-system.ruby.ST.latency_hist::gmean           3.300315                      
-system.ruby.ST.latency_hist::stdev          17.651145                      
-system.ruby.ST.latency_hist              |     9545751     99.94%     99.94% |        3768      0.04%     99.98% |        2002      0.02%    100.00% |          25      0.00%    100.00% |          25      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total            9551572                      
+system.ruby.LD.miss_latency_hist::samples      1390649                      
+system.ruby.LD.miss_latency_hist::mean      23.197386                      
+system.ruby.LD.miss_latency_hist::gmean     20.952196                      
+system.ruby.LD.miss_latency_hist::stdev     23.468925                      
+system.ruby.LD.miss_latency_hist         |     1374695     98.85%     98.85% |       13851      1.00%     99.85% |         851      0.06%     99.91% |         792      0.06%     99.97% |         329      0.02%     99.99% |         121      0.01%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total       1390649                      
+system.ruby.ST.latency_hist::bucket_size          128                      
+system.ruby.ST.latency_hist::max_bucket          1279                      
+system.ruby.ST.latency_hist::samples          9558783                      
+system.ruby.ST.latency_hist::mean            5.170026                      
+system.ruby.ST.latency_hist::gmean           3.300098                      
+system.ruby.ST.latency_hist::stdev          17.579302                      
+system.ruby.ST.latency_hist              |     9544781     99.85%     99.85% |        8164      0.09%     99.94% |        1330      0.01%     99.95% |        2504      0.03%     99.98% |        1628      0.02%    100.00% |         340      0.00%    100.00% |           7      0.00%    100.00% |          12      0.00%    100.00% |          11      0.00%    100.00% |           6      0.00%    100.00%
+system.ruby.ST.latency_hist::total            9558783                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples      9200825                      
+system.ruby.ST.hit_latency_hist::samples      9207752                      
 system.ruby.ST.hit_latency_hist::mean               3                      
 system.ruby.ST.hit_latency_hist::gmean       3.000000                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9200825    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total        9200825                      
-system.ruby.ST.miss_latency_hist::bucket_size          256                      
-system.ruby.ST.miss_latency_hist::max_bucket         2559                      
-system.ruby.ST.miss_latency_hist::samples       350747                      
-system.ruby.ST.miss_latency_hist::mean      62.242032                      
-system.ruby.ST.miss_latency_hist::gmean     40.314149                      
-system.ruby.ST.miss_latency_hist::stdev     71.440751                      
-system.ruby.ST.miss_latency_hist         |      344926     98.34%     98.34% |        3768      1.07%     99.41% |        2002      0.57%     99.99% |          25      0.01%     99.99% |          25      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        350747                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9207752    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total        9207752                      
+system.ruby.ST.miss_latency_hist::bucket_size          128                      
+system.ruby.ST.miss_latency_hist::max_bucket         1279                      
+system.ruby.ST.miss_latency_hist::samples       351031                      
+system.ruby.ST.miss_latency_hist::mean      62.091086                      
+system.ruby.ST.miss_latency_hist::gmean     40.236579                      
+system.ruby.ST.miss_latency_hist::stdev     71.074662                      
+system.ruby.ST.miss_latency_hist         |      337029     96.01%     96.01% |        8164      2.33%     98.34% |        1330      0.38%     98.72% |        2504      0.71%     99.43% |        1628      0.46%     99.89% |         340      0.10%     99.99% |           7      0.00%     99.99% |          12      0.00%    100.00% |          11      0.00%    100.00% |           6      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        351031                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
 system.ruby.IFETCH.latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist::samples    127093107                      
-system.ruby.IFETCH.latency_hist::mean        3.119052                      
-system.ruby.IFETCH.latency_hist::gmean       3.036517                      
-system.ruby.IFETCH.latency_hist::stdev       2.234317                      
-system.ruby.IFETCH.latency_hist          |   127086452     99.99%     99.99% |        5646      0.00%    100.00% |         489      0.00%    100.00% |         322      0.00%    100.00% |         142      0.00%    100.00% |          52      0.00%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total      127093107                      
+system.ruby.IFETCH.latency_hist::samples    126996315                      
+system.ruby.IFETCH.latency_hist::mean        3.119134                      
+system.ruby.IFETCH.latency_hist::gmean       3.036572                      
+system.ruby.IFETCH.latency_hist::stdev       2.233716                      
+system.ruby.IFETCH.latency_hist          |   126989642     99.99%     99.99% |        5673      0.00%    100.00% |         484      0.00%    100.00% |         317      0.00%    100.00% |         137      0.00%    100.00% |          55      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total      126996315                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist::samples    126277646                      
+system.ruby.IFETCH.hit_latency_hist::samples    126180135                      
 system.ruby.IFETCH.hit_latency_hist::mean            3                      
 system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   126277646    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total    126277646                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   126180135    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total    126180135                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist::samples       815461                      
-system.ruby.IFETCH.miss_latency_hist::mean    21.554760                      
-system.ruby.IFETCH.miss_latency_hist::gmean    19.772157                      
-system.ruby.IFETCH.miss_latency_hist::stdev    20.880175                      
-system.ruby.IFETCH.miss_latency_hist     |      808806     99.18%     99.18% |        5646      0.69%     99.88% |         489      0.06%     99.94% |         322      0.04%     99.98% |         142      0.02%     99.99% |          52      0.01%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total       815461                      
+system.ruby.IFETCH.miss_latency_hist::samples       816180                      
+system.ruby.IFETCH.miss_latency_hist::mean    21.537108                      
+system.ruby.IFETCH.miss_latency_hist::gmean    19.766480                      
+system.ruby.IFETCH.miss_latency_hist::stdev    20.855244                      
+system.ruby.IFETCH.miss_latency_hist     |      809507     99.18%     99.18% |        5673      0.70%     99.88% |         484      0.06%     99.94% |         317      0.04%     99.98% |         137      0.02%     99.99% |          55      0.01%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total       816180                      
 system.ruby.RMW_Read.latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.latency_hist::samples       493320                      
-system.ruby.RMW_Read.latency_hist::mean      6.020587                      
-system.ruby.RMW_Read.latency_hist::gmean     3.953175                      
-system.ruby.RMW_Read.latency_hist::stdev    10.251324                      
-system.ruby.RMW_Read.latency_hist        |      493147     99.96%     99.96% |         127      0.03%     99.99% |          17      0.00%     99.99% |          15      0.00%    100.00% |           9      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.latency_hist::total       493320                      
+system.ruby.RMW_Read.latency_hist::samples       494272                      
+system.ruby.RMW_Read.latency_hist::mean      6.020764                      
+system.ruby.RMW_Read.latency_hist::gmean     3.952362                      
+system.ruby.RMW_Read.latency_hist::stdev    10.313773                      
+system.ruby.RMW_Read.latency_hist        |      494092     99.96%     99.96% |         129      0.03%     99.99% |          18      0.00%     99.99% |          18      0.00%    100.00% |          11      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.latency_hist::total       494272                      
 system.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.RMW_Read.hit_latency_hist::samples       428060                      
+system.ruby.RMW_Read.hit_latency_hist::samples       428940                      
 system.ruby.RMW_Read.hit_latency_hist::mean            3                      
 system.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428060    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.hit_latency_hist::total       428060                      
+system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428940    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.hit_latency_hist::total       428940                      
 system.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.miss_latency_hist::samples        65260                      
-system.ruby.RMW_Read.miss_latency_hist::mean    25.833527                      
-system.ruby.RMW_Read.miss_latency_hist::gmean    24.149766                      
-system.ruby.RMW_Read.miss_latency_hist::stdev    18.493474                      
-system.ruby.RMW_Read.miss_latency_hist   |       65087     99.73%     99.73% |         127      0.19%     99.93% |          17      0.03%     99.96% |          15      0.02%     99.98% |           9      0.01%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.miss_latency_hist::total        65260                      
+system.ruby.RMW_Read.miss_latency_hist::samples        65332                      
+system.ruby.RMW_Read.miss_latency_hist::mean    25.853716                      
+system.ruby.RMW_Read.miss_latency_hist::gmean    24.153784                      
+system.ruby.RMW_Read.miss_latency_hist::stdev    18.748956                      
+system.ruby.RMW_Read.miss_latency_hist   |       65152     99.72%     99.72% |         129      0.20%     99.92% |          18      0.03%     99.95% |          18      0.03%     99.98% |          11      0.02%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.miss_latency_hist::total        65332                      
 system.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
 system.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.latency_hist::samples       339680                      
-system.ruby.Locked_RMW_Read.latency_hist::mean     5.345204                      
-system.ruby.Locked_RMW_Read.latency_hist::gmean     3.780937                      
-system.ruby.Locked_RMW_Read.latency_hist::stdev     8.076413                      
-system.ruby.Locked_RMW_Read.latency_hist |      339429     99.93%     99.93% |         234      0.07%     99.99% |          11      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total       339680                      
+system.ruby.Locked_RMW_Read.latency_hist::samples       339654                      
+system.ruby.Locked_RMW_Read.latency_hist::mean     5.351331                      
+system.ruby.Locked_RMW_Read.latency_hist::gmean     3.780101                      
+system.ruby.Locked_RMW_Read.latency_hist::stdev     8.370233                      
+system.ruby.Locked_RMW_Read.latency_hist |      339398     99.92%     99.92% |         231      0.07%     99.99% |          12      0.00%    100.00% |           6      0.00%    100.00% |           4      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total       339654                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples       300571                      
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples       300589                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300571    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total       300571                      
+system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300589    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist::total       300589                      
 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples        39109                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.369199                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.378025                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.121215                      
-system.ruby.Locked_RMW_Read.miss_latency_hist |       38858     99.36%     99.36% |         234      0.60%     99.96% |          11      0.03%     99.98% |           3      0.01%     99.99% |           1      0.00%     99.99% |           2      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total        39109                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::samples        39065                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.443850                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.382210                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    15.468459                      
+system.ruby.Locked_RMW_Read.miss_latency_hist |       38809     99.34%     99.34% |         231      0.59%     99.94% |          12      0.03%     99.97% |           6      0.02%     99.98% |           4      0.01%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist::total        39065                      
 system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.latency_hist::samples       339680                      
+system.ruby.Locked_RMW_Write.latency_hist::samples       339654                      
 system.ruby.Locked_RMW_Write.latency_hist::mean            3                      
 system.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339680    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total       339680                      
+system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.latency_hist::total       339654                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339680                      
+system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339654                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339680    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist::total       339680                      
-system.ruby.Directory_Controller.Fetch         177916      0.00%      0.00%
-system.ruby.Directory_Controller.Data           97855      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       178363      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       143156      0.00%      0.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist::total       339654                      
+system.ruby.Directory_Controller.Fetch         177212      0.00%      0.00%
+system.ruby.Directory_Controller.Data           97371      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       177674      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       142679      0.00%      0.00%
 system.ruby.Directory_Controller.DMA_READ          809      0.00%      0.00%
 system.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement        15288      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       177916      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_READ          447      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE        45301      0.00%      0.00%
-system.ruby.Directory_Controller.ID.Memory_Data          447      0.00%      0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack        45301      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data         96058      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_READ          362      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE         1435      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement        15288      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       177916      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack        96058      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRD.Data          362      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack          362      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWR.Data         1435      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1435      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement        15060      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch       177212      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_READ          462      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE        45308      0.00%      0.00%
+system.ruby.Directory_Controller.ID.Memory_Data          462      0.00%      0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack        45308      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data         95596      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_READ          347      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE         1428      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement        15060      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       177212      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack        95596      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRD.Data          347      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack          347      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWR.Data         1428      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1428      0.00%      0.00%
 system.ruby.DMA_Controller.ReadRequest   |         809    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.ReadRequest::total          809                      
 system.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
@@ -1067,169 +1065,169 @@ system.ruby.DMA_Controller.BUSY_RD.Data  |         809    100.00%    100.00% |
 system.ruby.DMA_Controller.BUSY_RD.Data::total          809                      
 system.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
-system.ruby.L1Cache_Controller.Load      |     6268725     41.74%     41.74% |     8749004     58.26%    100.00%
-system.ruby.L1Cache_Controller.Load::total     15017729                      
-system.ruby.L1Cache_Controller.Ifetch    |    68906101     54.22%     54.22% |    58187012     45.78%    100.00%
-system.ruby.L1Cache_Controller.Ifetch::total    127093113                      
-system.ruby.L1Cache_Controller.Store     |     5364359     50.02%     50.02% |     5359893     49.98%    100.00%
-system.ruby.L1Cache_Controller.Store::total     10724252                      
-system.ruby.L1Cache_Controller.Inv       |       15938     47.70%     47.70% |       17476     52.30%    100.00%
-system.ruby.L1Cache_Controller.Inv::total        33414                      
-system.ruby.L1Cache_Controller.L1_Replacement |      827888     31.76%     31.76% |     1778547     68.24%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      2606435                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |       12260     51.09%     51.09% |       11738     48.91%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total        23998                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |       14169     56.03%     56.03% |       11118     43.97%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total        25287                      
+system.ruby.L1Cache_Controller.Load      |     6279317     41.78%     41.78% |     8748595     58.22%    100.00%
+system.ruby.L1Cache_Controller.Load::total     15027912                      
+system.ruby.L1Cache_Controller.Ifetch    |    68812914     54.18%     54.18% |    58183407     45.82%    100.00%
+system.ruby.L1Cache_Controller.Ifetch::total    126996321                      
+system.ruby.L1Cache_Controller.Store     |     5372446     50.06%     50.06% |     5359917     49.94%    100.00%
+system.ruby.L1Cache_Controller.Store::total     10732363                      
+system.ruby.L1Cache_Controller.Inv       |       16157     48.07%     48.07% |       17455     51.93%    100.00%
+system.ruby.L1Cache_Controller.Inv::total        33612                      
+system.ruby.L1Cache_Controller.L1_Replacement |      828605     31.79%     31.79% |     1777971     68.21%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      2606576                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |       12248     51.07%     51.07% |       11736     48.93%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total        23984                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |       14251     55.67%     55.67% |       11346     44.33%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total        25597                      
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.Data      |         828     44.64%     44.64% |        1027     55.36%    100.00%
-system.ruby.L1Cache_Controller.Data::total         1855                      
-system.ruby.L1Cache_Controller.Data_Exclusive |      252860     19.71%     19.71% |     1029835     80.29%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total      1282695                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |       11118     43.96%     43.96% |       14173     56.04%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total        25291                      
-system.ruby.L1Cache_Controller.Data_all_Acks |      578454     43.51%     43.51% |      751132     56.49%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total      1329586                      
-system.ruby.L1Cache_Controller.Ack       |       12149     54.85%     54.85% |       10001     45.15%    100.00%
-system.ruby.L1Cache_Controller.Ack::total        22150                      
-system.ruby.L1Cache_Controller.Ack_all   |       12977     54.06%     54.06% |       11028     45.94%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total        24005                      
-system.ruby.L1Cache_Controller.WB_Ack    |      469035     27.80%     27.80% |     1218348     72.20%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total      1687383                      
-system.ruby.L1Cache_Controller.NP.Load   |      280457     20.44%     20.44% |     1091772     79.56%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total      1372229                      
-system.ruby.L1Cache_Controller.NP.Ifetch |      323032     39.65%     39.65% |      491723     60.35%    100.00%
-system.ruby.L1Cache_Controller.NP.Ifetch::total       814755                      
-system.ruby.L1Cache_Controller.NP.Store  |      225423     53.48%     53.48% |      196076     46.52%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       421499                      
-system.ruby.L1Cache_Controller.NP.Inv    |        4849     53.95%     53.95% |        4139     46.05%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         8988                      
-system.ruby.L1Cache_Controller.I.Load    |        8492     45.24%     45.24% |       10279     54.76%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total        18771                      
-system.ruby.L1Cache_Controller.I.Ifetch  |         112     15.86%     15.86% |         594     84.14%    100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total          706                      
-system.ruby.L1Cache_Controller.I.Store   |        5744     50.09%     50.09% |        5723     49.91%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total        11467                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |        9001     51.76%     51.76% |        8389     48.24%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total        17390                      
-system.ruby.L1Cache_Controller.S.Load    |      552961     51.86%     51.86% |      513218     48.14%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total      1066179                      
-system.ruby.L1Cache_Controller.S.Ifetch  |    68582952     54.31%     54.31% |    57694694     45.69%    100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total    126277646                      
-system.ruby.L1Cache_Controller.S.Store   |       12149     54.85%     54.85% |       10001     45.15%    100.00%
-system.ruby.L1Cache_Controller.S.Store::total        22150                      
-system.ruby.L1Cache_Controller.S.Inv     |       10866     45.32%     45.32% |       13108     54.68%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total        23974                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |      349852     38.80%     38.80% |      551810     61.20%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total       901662                      
-system.ruby.L1Cache_Controller.E.Load    |     1151502     29.73%     29.73% |     2721068     70.27%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total      3872570                      
-system.ruby.L1Cache_Controller.E.Store   |       80746     48.37%     48.37% |       86187     51.63%    100.00%
-system.ruby.L1Cache_Controller.E.Store::total       166933                      
-system.ruby.L1Cache_Controller.E.Inv     |          47     57.32%     57.32% |          35     42.68%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total           82                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |      170526     15.32%     15.32% |      942229     84.68%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total      1112755                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |         332     72.81%     72.81% |         124     27.19%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          456                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |         992     45.23%     45.23% |        1201     54.77%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2193                      
-system.ruby.L1Cache_Controller.M.Load    |     4275313     49.21%     49.21% |     4412667     50.79%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total      8687980                      
-system.ruby.L1Cache_Controller.M.Store   |     5040297     49.89%     49.89% |     5061906     50.11%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total     10102203                      
-system.ruby.L1Cache_Controller.M.Inv     |         176     47.57%     47.57% |         194     52.43%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total          370                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |      298509     51.95%     51.95% |      276119     48.05%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       574628                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |       11928     50.67%     50.67% |       11614     49.33%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23542                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |       13177     57.06%     57.06% |        9917     42.94%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total        23094                      
+system.ruby.L1Cache_Controller.Data      |         818     44.46%     44.46% |        1022     55.54%    100.00%
+system.ruby.L1Cache_Controller.Data::total         1840                      
+system.ruby.L1Cache_Controller.Data_Exclusive |      252712     19.73%     19.73% |     1028027     80.27%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total      1280739                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |       11346     44.32%     44.32% |       14255     55.68%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total        25601                      
+system.ruby.L1Cache_Controller.Data_all_Acks |      579316     43.50%     43.50% |      752306     56.50%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total      1331622                      
+system.ruby.L1Cache_Controller.Ack       |       12225     54.44%     54.44% |       10230     45.56%    100.00%
+system.ruby.L1Cache_Controller.Ack::total        22455                      
+system.ruby.L1Cache_Controller.Ack_all   |       13043     53.69%     53.69% |       11252     46.31%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total        24295                      
+system.ruby.L1Cache_Controller.WB_Ack    |      468894     27.82%     27.82% |     1216556     72.18%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total      1685450                      
+system.ruby.L1Cache_Controller.NP.Load   |      280382     20.44%     20.44% |     1091184     79.56%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total      1371566                      
+system.ruby.L1Cache_Controller.NP.Ifetch |      323814     39.71%     39.71% |      491732     60.29%    100.00%
+system.ruby.L1Cache_Controller.NP.Ifetch::total       815546                      
+system.ruby.L1Cache_Controller.NP.Store  |      225433     53.48%     53.48% |      196079     46.52%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       421512                      
+system.ruby.L1Cache_Controller.NP.Inv    |        4849     54.09%     54.09% |        4115     45.91%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         8964                      
+system.ruby.L1Cache_Controller.I.Load    |        8724     45.72%     45.72% |       10359     54.28%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total        19083                      
+system.ruby.L1Cache_Controller.I.Ifetch  |         100     15.77%     15.77% |         534     84.23%    100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total          634                      
+system.ruby.L1Cache_Controller.I.Store   |        5739     50.07%     50.07% |        5722     49.93%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total        11461                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |        8993     51.78%     51.78% |        8375     48.22%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total        17368                      
+system.ruby.L1Cache_Controller.S.Load    |      555624     51.88%     51.88% |      515377     48.12%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total      1071001                      
+system.ruby.L1Cache_Controller.S.Ifetch  |    68488995     54.28%     54.28% |    57691140     45.72%    100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total    126180135                      
+system.ruby.L1Cache_Controller.S.Store   |       12225     54.44%     54.44% |       10230     45.56%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total        22455                      
+system.ruby.L1Cache_Controller.S.Inv     |       11078     45.79%     45.79% |       13115     54.21%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total        24193                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |      350718     38.81%     38.81% |      553040     61.19%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total       903758                      
+system.ruby.L1Cache_Controller.E.Load    |     1152084     29.74%     29.74% |     2722150     70.26%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total      3874234                      
+system.ruby.L1Cache_Controller.E.Store   |       80726     48.37%     48.37% |       86165     51.63%    100.00%
+system.ruby.L1Cache_Controller.E.Store::total       166891                      
+system.ruby.L1Cache_Controller.E.Inv     |          52     59.77%     59.77% |          35     40.23%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total           87                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |      170402     15.34%     15.34% |      940436     84.66%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total      1110838                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |         330     72.53%     72.53% |         125     27.47%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          455                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |         996     45.17%     45.17% |        1209     54.83%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2205                      
+system.ruby.L1Cache_Controller.M.Load    |     4282503     49.27%     49.27% |     4409525     50.73%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total      8692028                      
+system.ruby.L1Cache_Controller.M.Store   |     5048323     49.93%     49.93% |     5061721     50.07%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total     10110044                      
+system.ruby.L1Cache_Controller.M.Inv     |         178     48.37%     48.37% |         190     51.63%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total          368                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |      298492     51.95%     51.95% |      276120     48.05%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       574612                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |       11918     50.65%     50.65% |       11611     49.35%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23529                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |       13255     56.66%     56.66% |       10137     43.34%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total        23392                      
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |      252860     19.71%     19.71% |     1029835     80.29%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1282695                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11118     43.96%     43.96% |       14173     56.04%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25291                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |      348115     38.75%     38.75% |      550360     61.25%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       898475                      
-system.ruby.L1Cache_Controller.IM.Data   |         828     44.64%     44.64% |        1027     55.36%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total         1855                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |      230339     53.43%     53.43% |      200772     46.57%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431111                      
-system.ruby.L1Cache_Controller.SM.Ack    |       12149     54.85%     54.85% |       10001     45.15%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total        22150                      
-system.ruby.L1Cache_Controller.SM.Ack_all |       12977     54.06%     54.06% |       11028     45.94%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total        24005                      
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |      252712     19.73%     19.73% |     1028027     80.27%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1280739                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11346     44.32%     44.32% |       14255     55.68%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25601                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |      348962     38.75%     38.75% |      551527     61.25%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       900489                      
+system.ruby.L1Cache_Controller.IM.Data   |         818     44.46%     44.46% |        1022     55.54%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total         1840                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |      230354     53.43%     53.43% |      200779     46.57%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431133                      
+system.ruby.L1Cache_Controller.SM.Ack    |       12225     54.44%     54.44% |       10230     45.56%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total        22455                      
+system.ruby.L1Cache_Controller.SM.Ack_all |       13043     53.69%     53.69% |       11252     46.31%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total        24295                      
 system.ruby.L1Cache_Controller.M_I.Ifetch |           5     83.33%     83.33% |           1     16.67%    100.00%
 system.ruby.L1Cache_Controller.M_I.Ifetch::total            6                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |      469035     27.80%     27.80% |     1218348     72.20%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1687383                      
-system.ruby.L2Cache_Controller.L1_GET_INSTR       815461      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS        1391156      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         432966      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE        22150      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX        1687383      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement        95998      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean        15348      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        177916      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         113143      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data          23468      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean         2193      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               1505      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all           7534      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock          25291      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock      1737811      0.00%      0.00%
-system.ruby.L2Cache_Controller.MEM_Inv           3594      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16427      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS        34220      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       127269      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       799004      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS        83018      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX         1958      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE        22150      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement          257      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7192      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack |      468894     27.82%     27.82% |     1216556     72.18%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1685450                      
+system.ruby.L2Cache_Controller.L1_GET_INSTR       816180      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS        1390821      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         432975      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE        22455      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX        1685450      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement        95536      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean        15120      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        177212      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         112431      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data          23764      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean         2205      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               1487      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all           7462      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock          25601      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock      1736167      0.00%      0.00%
+system.ruby.L2Cache_Controller.MEM_Inv           3550      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16316      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS        33914      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       126982      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       799834      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS        84313      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX         1944      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE        22455      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement          252      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7120      0.00%      0.00%
 system.ruby.L2Cache_Controller.SS.MEM_Inv            3      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS      1248475      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX       279741      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement        95619      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean         8056      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv         1564      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS      1246825      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX       280063      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement        95163      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean         7896      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv         1542      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS        25287      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX        23998      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX      1687383      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement          122      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          100      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS        25597      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX        23984      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX      1685450      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement          121      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          104      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT.MEM_Inv          230      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       113143      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv         1564      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data          310      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all           42      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       112431      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv         1542      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data          308      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all           43      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_I.MEM_Inv          230      0.00%      0.00%
 system.ruby.L2Cache_Controller.MCT_I.WB_Data           60      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all           40      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           1245      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         7192      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack            260      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all          260      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           1232      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         7120      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack            255      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all          255      0.00%      0.00%
 system.ruby.L2Cache_Controller.S_I.MEM_Inv            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data        34220      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data        16427      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       127269      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS          115      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24108      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS           41      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1713703      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data        23085      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2191      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock           15      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock        25276      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data        33914      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data        16316      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       126982      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS          122      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24399      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS           50      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1711768      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data        23385      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2205      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock        25590      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 81562c0f3..99542453a 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,157 +1,157 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.133731                       # Number of seconds simulated
-sim_ticks                                5133731116500                       # Number of ticks simulated
-final_tick                               5133731116500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.134211                       # Number of seconds simulated
+sim_ticks                                5134211428000                       # Number of ticks simulated
+final_tick                               5134211428000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 268887                       # Simulator instruction rate (inst/s)
-host_op_rate                                   534560                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5655392824                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1025452                       # Number of bytes of host memory used
-host_seconds                                   907.76                       # Real time elapsed on the host
-sim_insts                                   244084329                       # Number of instructions simulated
-sim_ops                                     485251122                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 263536                       # Simulator instruction rate (inst/s)
+host_op_rate                                   523907                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5540037627                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1021876                       # Number of bytes of host memory used
+host_seconds                                   926.75                       # Real time elapsed on the host
+sim_insts                                   244230745                       # Number of instructions simulated
+sim_ops                                     485529516                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           445760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5319424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           180800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1995776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           334336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3134080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           393536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5140544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           149632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1859072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         2496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           422208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          3469952                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11441152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       445760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       180800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       334336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          960896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9198080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9198080                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11466176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       393536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       149632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       422208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          965376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9230336                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9230336                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             83116                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             31184                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           35                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5224                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             48970                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6149                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             80321                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2338                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             29048                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           39                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              6597                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             54218                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                178768                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143720                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                179159                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          144224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               144224                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               86830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1036171                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               35218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              388757                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               65125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              610488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2228623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          86830                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          35218                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          65125                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             187173                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1791695                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1791695                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1791695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               76650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1001233                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               29144                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              362095                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               82234                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              675849                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5522                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2233289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          76650                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          29144                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          82234                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             188028                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1797810                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1797810                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1797810                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              86830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1036171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              35218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             388757                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              65125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             610488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4020318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         88682                       # Number of read requests accepted
-system.physmem.writeReqs                       112966                       # Number of write requests accepted
-system.physmem.readBursts                       88682                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     112966                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5672000                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6262656                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5675648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7229824                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       57                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   15112                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1053                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5542                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5155                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5253                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5290                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5356                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4920                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5387                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5003                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5335                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5304                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5486                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5354                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5802                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6837                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6164                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6437                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6158                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6179                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6254                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6080                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5432                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5660                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6180                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5898                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5226                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5788                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6663                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6618                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6477                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6666                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5929                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6646                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst              76650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1001233                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              29144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             362095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              82234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             675849                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5522                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4031099                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         92684                       # Number of read requests accepted
+system.physmem.writeReqs                        79104                       # Number of write requests accepted
+system.physmem.readBursts                       92684                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      79104                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5924224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5060672                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5931776                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5062656                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          20933                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6439                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5501                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5319                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5591                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5862                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5383                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5425                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                4840                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6025                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5959                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5660                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5754                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5715                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6523                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5966                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6604                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5842                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5111                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4865                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5025                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5489                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4924                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4816                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4154                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4431                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4666                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4446                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4728                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4725                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5504                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4686                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5661                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          21                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5132592336000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5133211221000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   88682                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   92684                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 112966                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     81919                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      5154                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1007                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        47                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  79104                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     86281                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4975                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       180                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -165,986 +165,984 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       124                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        53                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4956                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4558                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      961                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        40590                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.012121                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     173.528709                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     319.654231                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15917     39.21%     39.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9832     24.22%     63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4000      9.85%     73.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2295      5.65%     78.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1624      4.00%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1126      2.77%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          717      1.77%     87.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          617      1.52%     89.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4462     10.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          40590                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3784                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.420983                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      192.521538                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3781     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.03%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-6655            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3784                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.859937                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.216089                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       44.163335                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               82      2.17%      2.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            3425     90.51%     92.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              68      1.80%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              12      0.32%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               7      0.18%     94.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              15      0.40%     95.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             10      0.26%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            22      0.58%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            22      0.58%     96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            17      0.45%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             6      0.16%     97.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            22      0.58%     97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            36      0.95%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             7      0.18%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             2      0.05%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.08%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             1      0.03%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             1      0.03%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             5      0.13%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             4      0.11%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             6      0.16%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.13%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3784                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1019929900                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2681648650                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    443125000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11508.38                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        52                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15                     1288                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::20                     4217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4200                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29                     4886                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::38                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       75                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49                       67                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::51                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       34                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        9                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        40692                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      269.949081                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     163.456020                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     296.352111                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16538     40.64%     40.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10119     24.87%     65.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4173     10.26%     75.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2507      6.16%     81.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1551      3.81%     85.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1073      2.64%     88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          750      1.84%     90.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          656      1.61%     91.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3325      8.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          40692                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4120                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.462136                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      184.101810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            4117     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-6655            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4120                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4120                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.192476                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.355155                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.050068                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                67      1.63%      1.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.15%      1.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               4      0.10%      1.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3537     85.85%     87.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              61      1.48%     89.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             102      2.48%     91.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              51      1.24%     92.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              38      0.92%     93.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              95      2.31%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              16      0.39%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.15%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.22%     96.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.05%     96.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.05%     96.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.05%     97.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              98      2.38%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.05%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.12%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.05%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.07%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.15%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4120                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1055441928                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2791054428                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    462830000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11402.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30258.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.10                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.22                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30152.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.99                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.16                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.85                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      70792                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     75088                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.88                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                     25453227.09                       # Average gap between requests
-system.physmem.pageHitRate                      78.23                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  147351960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   80169375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 326866800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                309938400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250042678080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            94629197520                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2236697889750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2582234091885                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.903813                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3683333970938                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    127833680000                       # Time in different power states
+system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         9.29                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      74063                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     56883                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.01                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                     29881081.46                       # Average gap between requests
+system.physmem.pageHitRate                      76.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  149294880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   81184125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 345992400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                260664480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250017250080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            94809930840                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2241062736000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2586727052805                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.763806                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3682666821734                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    127820680000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     17533181312                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     17822753766                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  159410160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   86781750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 364408200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                323974080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250042678080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            95188577850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2235010334250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2581176164370                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.974824                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3682508953468                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    127833680000                       # Time in different power states
+system.physmem_1.actEnergy                  158336640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   86183625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 376006800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                251728560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250017250080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            95265143955                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2233496235000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2579650884660                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.996985                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3682005807728                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    127820680000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     18355082532                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     18463901522                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                       819384850                       # number of cpu cycles simulated
+system.cpu0.numCycles                       814812843                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   70809878                       # Number of instructions committed
-system.cpu0.committedOps                    144569383                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            132504639                       # Number of integer alu accesses
+system.cpu0.committedInsts                   70855773                       # Number of instructions committed
+system.cpu0.committedOps                    144639705                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            132581707                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     914830                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14060186                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   132504639                       # number of integer instructions
+system.cpu0.num_func_calls                     911803                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14069363                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   132581707                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          242769596                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         113987635                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          242934374                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         114063964                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            82531896                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55153606                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13358556                       # number of memory refs
-system.cpu0.num_load_insts                    9930193                       # Number of load instructions
-system.cpu0.num_store_insts                   3428363                       # Number of store instructions
-system.cpu0.num_idle_cycles              778171794.138464                       # Number of idle cycles
-system.cpu0.num_busy_cycles              41213055.861536                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050298                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949702                       # Percentage of idle cycles
-system.cpu0.Branches                         15315720                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                88912      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                131019698     90.63%     90.69% # Class of executed instruction
-system.cpu0.op_class::IntMult                   57722      0.04%     90.73% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    46561      0.03%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.76% # Class of executed instruction
-system.cpu0.op_class::MemRead                 9928558      6.87%     97.63% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3428363      2.37%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            82574901                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55200628                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13389972                       # number of memory refs
+system.cpu0.num_load_insts                    9966183                       # Number of load instructions
+system.cpu0.num_store_insts                   3423789                       # Number of store instructions
+system.cpu0.num_idle_cycles              774643417.179050                       # Number of idle cycles
+system.cpu0.num_busy_cycles              40169425.820950                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049299                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950701                       # Percentage of idle cycles
+system.cpu0.Branches                         15322983                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                87668      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                131058913     90.61%     90.67% # Class of executed instruction
+system.cpu0.op_class::IntMult                   57724      0.04%     90.71% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47555      0.03%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.74% # Class of executed instruction
+system.cpu0.op_class::MemRead                 9964546      6.89%     97.63% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3423789      2.37%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 144569814                       # Class of executed instruction
+system.cpu0.op_class::total                 144640195                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          1636339                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999246                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19643358                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1636851                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            12.000700                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1639692                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999446                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19677629                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1640204                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.997062                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   232.510577                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   255.541861                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data    23.946808                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.454122                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.499105                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.046771                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   231.527826                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   256.098734                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    24.372886                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.452203                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.500193                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.047603                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88441515                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88441515                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4745925                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2412981                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4334563                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11493469                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3299103                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1688891                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3099986                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8087980                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19676                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data         9874                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30514                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        60064                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8045028                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4101872                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7434549                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19581449                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8064704                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4111746                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7465063                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19641513                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       345343                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       160729                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       822143                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1328215                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       125592                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        64251                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       135437                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       325280                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       145872                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        63796                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       196481                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406149                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       470935                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       224980                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       957580                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1653495                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       616807                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       288776                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1154061                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2059644                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2230470250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12318599402                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14549069652                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2662717793                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4381161307                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7043879100                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4893188043                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  16699760709                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  21592948752                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4893188043                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  16699760709                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  21592948752                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5091268                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2573710                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      5156706                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12821684                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3424695                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1753142                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3235423                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8413260                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       165548                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        73670                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       226995                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466213                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8515963                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4326852                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      8392129                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21234944                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8681511                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4400522                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      8619124                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21701157                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067830                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.062450                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.159432                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.103591                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036672                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036649                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.041861                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038663                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.881146                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.865970                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.865574                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871166                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055300                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.051996                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114105                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.077867                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071048                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.065623                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.133895                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.094909                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13877.211020                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14983.524037                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10953.851336                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41442.433472                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32348.333963                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21654.817696                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21749.435697                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17439.546261                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13058.974325                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16944.580031                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14470.431553                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10483.825725                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       172709                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88605943                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88605943                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4782117                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2413671                       # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19899                       # number of SoftPFReq hits
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+system.cpu0.dcache.overall_hits::cpu0.data      8098372                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total       19675826                       # number of overall hits
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+system.cpu0.dcache.SoftPFReq_accesses::total       466253                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067527                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.061855                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total     0.103671                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036240                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.035950                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043029                       # miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.879108                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.865675                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866418                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.870780                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055009                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.051324                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115220                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.078006                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070577                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.064952                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135080                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.095008                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13760.441998                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14618.117504                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10718.591734                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39933.866818                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34387.685678                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 22405.427553                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21213.406413                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17462.222346                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13017.098596                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16481.908084                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14501.119895                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10458.530264                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       191338                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            19385                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            22795                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.909414                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.393858                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1546428                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1546428                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           54                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       384012                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       384066                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1567                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32068                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        33635                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1621                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       416080                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       417701                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1621                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       416080                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       417701                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       160675                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       438131                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       598806                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62684                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       103369                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       166053                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        63795                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       193085                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       256880                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       223359                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       541500                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       764859                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       287154                       # number of overall MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total      1021739                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       186614                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       205311                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       391925                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3448                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3872                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7320                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       190062                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       209183                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       399245                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1988518250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5713340764                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7701859014                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2470174689                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3635352900                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6105527589                       # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2770809752                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3703058752                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4458692939                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9348693664                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13807386603                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5390941939                       # number of overall MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total  17510445355                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30496812500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33031149000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63527961500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    600115500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    761942500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1362058000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31096928000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33793091500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64890019500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.062429                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084963                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.046703                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035755                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031949                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019737                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.865956                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850613                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.550993                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.051622                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.064525                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.036019                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065255                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.085227                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.047082                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.027696                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13040.256827                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12862.027124                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39406.781459                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35168.695644                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36768.547325                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14613.198527                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14350.207173                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14415.519900                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19962.002601                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17264.438899                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163421.889569                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 160883.484080                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174047.418794                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 163614.652061                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 161547.981911                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks      1548927                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1548927                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           51                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       386553                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       386604                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1542                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32157                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        33699                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1593                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       418710                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       420303                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1593                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       418710                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       420303                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       159090                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       441199                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       600289                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        61815                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       106936                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       168751                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        63873                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       194014                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       257887                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       220905                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       548135                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       769040                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       284778                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       742149                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1026927                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       185834                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       205183                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total       391017                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3059                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4433                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7492                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       188893                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       209616                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398509                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2030358500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5964591000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7994949500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2384524000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4092527864                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6477051864                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    931095000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2819292000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3750387000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4414882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10057118864                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  14472001364                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5345977500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12876410864                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  18222388364                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30572400500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33247121500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63819522000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    547435500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    878869500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1426305000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31119836000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34125991000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65245827000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.061835                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085525                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.046679                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035075                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.033081                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.020053                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.865675                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.851435                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.553105                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050956                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065322                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.036147                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.064591                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086105                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.047234                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.326356                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13519.049227                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13318.500755                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38575.167840                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38270.814917                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38382.302114                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14577.286177                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14531.384333                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14542.753221                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19985.434915                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18347.886678                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18818.268704                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18772.438531                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17350.169392                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17744.580057                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164514.569454                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162036.433330                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163214.187618                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178958.973521                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198256.147079                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190377.068873                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164748.487239                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162802.414892                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163724.851885                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           871419                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.241344                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          127964014                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           871931                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           146.759335                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     150504235000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   260.667168                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   143.237667                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   106.336510                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.509116                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.279761                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.207688                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.996565                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           881776                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.250144                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          127955824                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           882288                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           145.027275                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     149037485500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   260.904392                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   141.200601                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   108.145151                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.509579                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.275782                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.211221                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.996582                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        129734477                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       129734477                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     86118928                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     38597787                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3247299                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      127964014                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     86118928                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     38597787                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3247299                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       127964014                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     86118928                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     38597787                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3247299                       # number of overall hits
-system.cpu0.icache.overall_hits::total      127964014                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       294029                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       171033                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       433450                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       898512                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       294029                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       171033                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       433450                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        898512                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       294029                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       171033                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       433450                       # number of overall misses
-system.cpu0.icache.overall_misses::total       898512                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2424026997                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5943573307                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8367600304                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2424026997                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5943573307                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8367600304                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2424026997                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5943573307                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8367600304                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     86412957                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     38768820                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3680749                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    128862526                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     86412957                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     38768820                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3680749                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    128862526                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     86412957                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     38768820                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3680749                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    128862526                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003403                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004412                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117761                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006973                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003403                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004412                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117761                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006973                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003403                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004412                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117761                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006973                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14172.861360                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.246642                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9312.730719                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14172.861360                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.246642                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9312.730719                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14172.861360                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.246642                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9312.730719                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7161                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              313                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.878594                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        129749175                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       129749175                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     86200122                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     38494727                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3260975                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      127955824                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     86200122                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     38494727                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3260975                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       127955824                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     86200122                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     38494727                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3260975                       # number of overall hits
+system.cpu0.icache.overall_hits::total      127955824                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       293889                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       163550                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       453609                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       911048                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       293889                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       163550                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       453609                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        911048                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       293889                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       163550                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       453609                       # number of overall misses
+system.cpu0.icache.overall_misses::total       911048                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2290465000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6298842980                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8589307980                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2290465000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   6298842980                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8589307980                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2290465000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   6298842980                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8589307980                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     86494011                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     38658277                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3714584                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    128866872                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     86494011                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     38658277                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3714584                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    128866872                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     86494011                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     38658277                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3714584                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    128866872                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003398                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004231                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122116                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.007070                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003398                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004231                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122116                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.007070                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003398                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004231                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122116                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.007070                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14004.677469                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13886.062622                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9427.942304                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14004.677469                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13886.062622                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9427.942304                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14004.677469                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13886.062622                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9427.942304                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6492                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets           22                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              290                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.386207                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           22                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        26561                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        26561                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        26561                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        26561                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        26561                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        26561                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       171033                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       406889                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       577922                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       171033                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       406889                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       577922                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       171033                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       406889                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       577922                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2166425503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5084799831                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7251225334                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2166425503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5084799831                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7251225334                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2166425503                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5084799831                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7251225334                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004412                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110545                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004485                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004412                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110545                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004485                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004412                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110545                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004485                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12666.710535                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12496.773889                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12547.065753                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12666.710535                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12496.773889                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12547.065753                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12666.710535                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12496.773889                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12547.065753                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        28745                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        28745                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        28745                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        28745                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        28745                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        28745                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       163550                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       424864                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       588414                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       163550                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       424864                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       588414                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       163550                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       424864                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       588414                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2126915000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5601122480                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7728037480                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2126915000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5601122480                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7728037480                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2126915000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5601122480                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7728037480                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004231                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.114377                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004566                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004231                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.114377                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004566                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004231                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.114377                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004566                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13004.677469                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13183.330383                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13133.673706                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13004.677469                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13183.330383                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13133.673706                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13004.677469                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13183.330383                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13133.673706                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2604016269                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606017483                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35221864                       # Number of instructions committed
-system.cpu1.committedOps                     68477973                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             63543554                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35137560                       # Number of instructions committed
+system.cpu1.committedOps                     68325691                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             63404843                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     474559                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6488284                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    63543554                       # number of integer instructions
+system.cpu1.num_func_calls                     475454                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6463819                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    63404843                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          117503426                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          54764358                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          117292769                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          54636862                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            35994299                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26824776                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4585615                       # number of memory refs
-system.cpu1.num_load_insts                    2831531                       # Number of load instructions
-system.cpu1.num_store_insts                   1754084                       # Number of store instructions
-system.cpu1.num_idle_cycles              2478252415.347472                       # Number of idle cycles
-system.cpu1.num_busy_cycles              125763853.652528                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.048296                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.951704                       # Percentage of idle cycles
-system.cpu1.Branches                          7131846                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                33642      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 63809884     93.18%     93.23% # Class of executed instruction
-system.cpu1.op_class::IntMult                   28068      0.04%     93.27% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    22761      0.03%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.31% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2829816      4.13%     97.44% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1754084      2.56%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            35859650                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26723526                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4592942                       # number of memory refs
+system.cpu1.num_load_insts                    2829969                       # Number of load instructions
+system.cpu1.num_store_insts                   1762973                       # Number of store instructions
+system.cpu1.num_idle_cycles              2483716878.762911                       # Number of idle cycles
+system.cpu1.num_busy_cycles              122300604.237089                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.046930                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.953070                       # Percentage of idle cycles
+system.cpu1.Branches                          7109683                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                33619      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 63651336     93.16%     93.21% # Class of executed instruction
+system.cpu1.op_class::IntMult                   27621      0.04%     93.25% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    22176      0.03%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.28% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2828254      4.14%     97.42% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1762973      2.58%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  68478255                       # Class of executed instruction
+system.cpu1.op_class::total                  68325979                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29642945                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29642945                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           342109                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26793966                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               26087449                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29728292                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29728292                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           354491                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26875418                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               26145153                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.363149                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 617263                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             68240                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       154815215                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.282777                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 627673                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             71339                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       156747191                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          11226493                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     146138571                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29642945                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26704712                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    142088964                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 715876                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    100355                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                5095                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             9800                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        59006                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           22                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1044                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3680756                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               177933                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3589                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         153848066                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.868751                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.040918                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          11575217                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     146531331                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29728292                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26772826                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    143455759                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 740896                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    117693                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                8882                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             9184                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        67495                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles           36                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          614                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3714591                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               185121                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   4402                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         155604677                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.852545                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.032784                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                97905187     63.64%     63.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  902052      0.59%     64.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23780045     15.46%     79.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  607949      0.40%     80.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  861058      0.56%     80.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  871308      0.57%     81.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  586027      0.38%     81.58% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  774714      0.50%     82.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27559726     17.91%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                99528214     63.96%     63.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  894883      0.58%     64.54% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23827863     15.31%     79.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  616054      0.40%     80.25% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  865023      0.56%     80.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  874152      0.56%     81.36% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  593045      0.38%     81.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  766815      0.49%     82.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27638628     17.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           153848066                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.191473                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.943955                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10308577                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             93114688                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 23867360                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              5032797                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                358589                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             284536277                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                358589                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12446525                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76456474                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4505534                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 26483485                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             12431465                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             283232358                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               203213                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5874103                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 62488                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4343022                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          338256341                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            618855518                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       379959971                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              144                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            325490778                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12765563                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            164991                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        166448                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 24511654                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6973831                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3905800                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           411343                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          337090                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 281177337                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             428187                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                278961410                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           111637                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        9401758                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     14188384                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         65116                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    153848066                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.813227                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.402216                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           155604677                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.189658                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.934826                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10653655                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             94438460                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23846115                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5077401                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                371099                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             285226302                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                371099                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12813669                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               77065666                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4747202                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 26484696                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             12904465                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             283889044                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               204785                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5893747                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 54074                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4792782                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          339006774                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            620283621                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       380802622                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              280                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            325933868                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                13072904                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            167839                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        169378                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 24708176                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6969767                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3922969                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           416514                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          341941                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 281777756                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             433047                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                279489336                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           112446                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        9646678                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     14520235                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         68066                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    155604677                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.796150                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.396491                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           90533816     58.85%     58.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5362080      3.49%     62.33% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3874219      2.52%     64.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3850508      2.50%     67.35% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           22615321     14.70%     82.05% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2805299      1.82%     83.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           24069627     15.65%     99.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             503741      0.33%     99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             233455      0.15%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           92126087     59.21%     59.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5408193      3.48%     62.68% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3871909      2.49%     65.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3896687      2.50%     67.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           22645736     14.55%     82.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2817206      1.81%     84.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           24121295     15.50%     99.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             489992      0.31%     99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             227572      0.15%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      153848066                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      155604677                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1762451     85.95%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     85.95% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                222010     10.83%     96.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                66103      3.22%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1782744     86.25%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    2      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                219490     10.62%     96.87% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                64665      3.13%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            83756      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            267874850     96.03%     96.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               60171      0.02%     96.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                55540      0.02%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 52      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             7279557      2.61%     98.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3607484      1.29%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            84223      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            268409283     96.04%     96.07% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               60791      0.02%     96.09% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                54867      0.02%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                128      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             7262488      2.60%     98.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3617556      1.29%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             278961410                       # Type of FU issued
-system.cpu2.iq.rate                          1.801899                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2050564                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007351                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         713932890                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        291011736                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    277302749                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                197                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               156                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           76                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             280928122                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     96                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          764231                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             279489336                       # Type of FU issued
+system.cpu2.iq.rate                          1.783058                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2066901                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007395                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         716762296                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        291861984                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    277802443                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                399                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes               402                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses          161                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             281471819                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                    195                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          741069                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1280710                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6256                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5226                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       665708                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1314442                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6549                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5531                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       685228                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       750625                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        30616                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       750208                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        28435                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                358589                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               70562607                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              2840752                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          281605524                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            45396                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6973831                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3905800                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            251212                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                165628                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              2346507                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5226                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        195667                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       202777                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              398444                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            278332986                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              7126227                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           571848                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                371099                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               70840326                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              3147966                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          282210803                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            45613                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6969767                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3922969                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            254598                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                166407                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              2652713                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5531                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        201920                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       210112                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              412032                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            278837771                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              7102995                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           592219                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    10641796                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                28281444                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3515569                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.797840                       # Inst execution rate
-system.cpu2.iew.wb_sent                     278129863                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    277302825                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                216123267                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                354504830                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                    10623704                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                28332312                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3520709                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.778901                       # Inst execution rate
+system.cpu2.iew.wb_sent                     278631802                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    277802604                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                216492114                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                355079818                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.791186                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609648                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.772297                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609700                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9397385                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         363071                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           345314                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    152442881                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.785612                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.660258                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        9642578                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         364981                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           357554                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    154160156                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.768058                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.650606                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     94319401     61.87%     61.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4425348      2.90%     64.77% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1302226      0.85%     65.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24740165     16.23%     81.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       979797      0.64%     82.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       733746      0.48%     82.98% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       423992      0.28%     83.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23324047     15.30%     98.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2194159      1.44%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     95860610     62.18%     62.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4461430      2.89%     65.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1337416      0.87%     65.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24820120     16.10%     82.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      1009976      0.66%     82.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       732580      0.48%     83.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       443548      0.29%     83.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23352402     15.15%     98.61% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2142074      1.39%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    152442881                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           138052587                       # Number of instructions committed
-system.cpu2.commit.committedOps             272203766                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    154160156                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           138237412                       # Number of instructions committed
+system.cpu2.commit.committedOps             272564120                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8933213                       # Number of memory references committed
-system.cpu2.commit.loads                      5693121                       # Number of loads committed
-system.cpu2.commit.membars                     162094                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27859693                       # Number of branches committed
+system.cpu2.commit.refs                       8893065                       # Number of memory references committed
+system.cpu2.commit.loads                      5655324                       # Number of loads committed
+system.cpu2.commit.membars                     162767                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27901240                       # Number of branches committed
 system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                248852946                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              461863                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        49962      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       263110099     96.66%     96.68% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          57933      0.02%     96.70% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           52599      0.02%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5693065      2.09%     98.81% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3240092      1.19%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                249166189                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              462772                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        50638      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       263510022     96.68%     96.70% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          58397      0.02%     96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           52041      0.02%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.74% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5655265      2.07%     98.81% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3237741      1.19%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        272203766                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2194159                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   431819572                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  564614589                       # The number of ROB writes
-system.cpu2.timesIdled                         120593                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                         967149                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4904349916                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  138052587                       # Number of Instructions Simulated
-system.cpu2.committedOps                    272203766                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.121422                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.121422                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.891725                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.891725                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               371027158                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              222252306                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72988                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                141449053                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               108603776                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               90794642                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                144161                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3553347                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3553347                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57679                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              10959                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1698                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1698                       # Transaction distribution
+system.cpu2.commit.op_class_0::total        272564120                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2142074                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   434194585                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  565865422                       # The number of ROB writes
+system.cpu2.timesIdled                         127222                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1142514                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4899644826                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  138237412                       # Number of Instructions Simulated
+system.cpu2.committedOps                    272564120                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.133898                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.133898                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.881913                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.881913                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               371610814                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              222643670                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73073                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                141701796                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               108796323                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               90941344                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                144983                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3552121                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3552121                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57703                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57703                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1657                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1657                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
@@ -1153,22 +1151,22 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7082616                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1098                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7080216                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1182                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27854                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7126806                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95246                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95246                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3396                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3396                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7225448                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7124404                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3314                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3314                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7222962                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
@@ -1177,425 +1175,437 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3541308                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2196                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3540108                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2364                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13970                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13927                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3569512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027768                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027768                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6604072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2741680                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3568437                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6628                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6628                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6602825                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2786496                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              6074000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              5677000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            141309000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            140109000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              285000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              441000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            10492000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            11327000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy                4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           155889253                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           104116682                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           301765000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           300127000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            31644993                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            23084000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1151000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1172000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47568                       # number of replacements
-system.iocache.tags.tagsinuse                0.079964                       # Cycle average of tags in use
+system.iocache.tags.replacements                47567                       # number of replacements
+system.iocache.tags.tagsinuse                0.081431                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47584                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47583                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000587823009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.079964                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.004998                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.004998                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000591236509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.081431                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005089                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005089                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428607                       # Number of tag accesses
-system.iocache.tags.data_accesses              428607                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          903                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          903                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               903                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          903                       # number of overall misses
-system.iocache.overall_misses::total              903                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128377230                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    128377230                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   5164742030                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   5164742030                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    128377230                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    128377230                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    128377230                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    128377230                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          903                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             903                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          903                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            903                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428598                       # Number of tag accesses
+system.iocache.tags.data_accesses              428598                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          902                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              902                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          902                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               902                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          902                       # number of overall misses
+system.iocache.overall_misses::total              902                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    121586746                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    121586746                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2354972936                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2354972936                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    121586746                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    121586746                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    121586746                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    121586746                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          902                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            902                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          902                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             902                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          902                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            902                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142167.475083                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 142167.475083                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 110546.704409                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 110546.704409                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142167.475083                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 142167.475083                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142167.475083                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 142167.475083                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         17612                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 134796.835920                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 134796.835920                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 50406.098801                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 50406.098801                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134796.835920                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 134796.835920                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134796.835920                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 134796.835920                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           552                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 2632                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.691489                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs           12                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          801                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          801                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        28264                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        28264                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          801                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          801                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          801                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          801                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     86423212                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     86423212                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   3695010034                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   3695010034                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     86423212                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     86423212                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     86423212                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     86423212                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.887043                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.887043                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.604966                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.604966                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.887043                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.887043                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.887043                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.887043                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 107894.147316                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130732.027809                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130732.027809                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 107894.147316                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 107894.147316                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          746                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          746                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        19960                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        19960                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          746                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          746                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          746                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          746                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     84286746                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     84286746                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1356972936                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1356972936                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     84286746                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     84286746                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     84286746                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     84286746                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.827051                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.827051                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.427226                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.427226                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.827051                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.827051                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.827051                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.827051                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 112984.914209                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67984.616032                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67984.616032                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 112984.914209                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 112984.914209                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   105369                       # number of replacements
-system.l2c.tags.tagsinuse                64830.626845                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3705679                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169446                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.869380                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   105904                       # number of replacements
+system.l2c.tags.tagsinuse                64832.216142                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4698304                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   170185                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    27.607039                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50858.096780                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134526                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1601.427587                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5289.246768                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000914                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      232.896636                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1549.888722                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     7.632040                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1227.720144                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4063.582728                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.776033                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   50894.263020                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.125303                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1602.122983                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5170.967993                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      244.936624                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1566.576743                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.469260                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker     0.003420                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1245.636306                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     4101.114491                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.776585                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.024436                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.080708                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.inst       0.003554                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000116                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.018734                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::total           0.989237                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         4057                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8155                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51563                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.977737                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33969935                       # Number of tag accesses
-system.l2c.tags.data_accesses                33969935                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        19552                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10769                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu0.data             476755                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        13141                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.inst             168208                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             219838                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        66288                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        13297                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             401625                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             617193                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2301274                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.024446                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data       0.023904                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::3         7407                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53037                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.980850                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 41908906                       # Number of tag accesses
+system.l2c.tags.data_accesses                41908906                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu0.itb.walker        10333                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                 134678                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1546428                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1546428                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             105                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              96                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 248                       # number of UpgradeReq hits
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-system.l2c.demand_hits::cpu0.itb.walker         10771                       # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.data             532742                       # number of overall hits
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-system.l2c.overall_hits::cpu1.itb.walker         7558                       # number of overall hits
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-system.l2c.overall_hits::cpu1.data             255391                       # number of overall hits
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-system.l2c.overall_hits::total                2460172                       # number of overall hits
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+system.l2c.Writeback_hits::total              1548927                       # number of Writeback hits
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+system.l2c.ReadCleanReq_hits::total            867184                       # number of ReadCleanReq hits
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 system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
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 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1546428                       # number of Writeback accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000464                       # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.841150                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.843854                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.864789                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.851675                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu1.data     0.430195                       # miss rate for ReadExReq accesses
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-system.l2c.overall_avg_miss_latency::total 39728.623871                       # average overall miss latency
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.816667                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.867982                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.848161                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.020927                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.014295                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.015528                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.017098                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.031287                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.017501                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.022130                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.024697                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000484                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.020927                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.131175                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.014295                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.102858                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000567                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.000063                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.015528                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.073730                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.067602                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000484                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.020927                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.131175                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.014295                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.102858                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000567                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.000063                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.015528                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.073730                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.067602                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 93435.897436                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        97000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 83133.333333                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20436.734694                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12548.076923                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  8520.629371                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75026.853312                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79287.622495                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 39051.016130                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80531.009410                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84915.112930                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 49616.605900                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83759.866735                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86329.823563                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 46226.980792                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80531.009410                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 76191.374479                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 93435.897436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker        97000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 84915.112930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 81098.216572                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 41280.375653                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80531.009410                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 76191.374479                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 93435.897436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker        97000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 84915.112930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81098.216572                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 41280.375653                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1604,206 +1614,218 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               97053                       # number of writebacks
-system.l2c.writebacks::total                    97053                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2825                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4632                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           35                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         5224                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        13983                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           26700                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          254                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          614                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          868                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        26842                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        35344                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         62186                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2825                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        31474                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           35                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         5224                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        49327                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            88886                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2825                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        31474                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu2.data        49327                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           88886                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data       186614                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data       205311                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total       391925                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3448                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         3872                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         7320                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data       190062                       # number of overall MSHR uncacheable misses
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-system.l2c.overall_mshr_uncacheable_misses::total       399245                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        70000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    193782500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    330037250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2632999                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    385025750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data   1049073500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1960621999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5213239                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10949612                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     16162851                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1688636313                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2360590135                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4049226448                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        70000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    193782500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   2018673563                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu2.inst    385025750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3409663635                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6009848447                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        70000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    193782500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   2018673563                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu2.data   3409663635                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6009848447                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27827045500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30156785500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  57983831000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    554838500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    711575000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1266413500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28381884000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30868360500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59250244500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000076                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.016517                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020635                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000528                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.012840                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.022154                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.011365                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.843854                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.864789                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.519139                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.430195                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.344148                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.214415                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000076                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.016517                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.109717                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000528                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012840                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.067214                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.033676                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000076                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.016517                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.109717                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000528                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012840                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.067214                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.033676                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68595.575221                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71251.565199                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73703.244640                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 75024.923121                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 73431.535543                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20524.562992                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17833.244300                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18620.796083                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62910.226995                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66788.992050                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 65114.759721                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68595.575221                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64137.814164                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73703.244640                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69123.677398                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 67612.992451                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68595.575221                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64137.814164                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 67612.992451                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060                       # average overall mshr uncacheable latency
+system.l2c.writebacks::writebacks               97557                       # number of writebacks
+system.l2c.writebacks::total                    97557                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           39                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::total              40                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks           51                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total           51                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          245                       # number of UpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::total          817                       # number of UpgradeReq MSHR misses
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+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2338                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         6597                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         8935                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         3902                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        14056                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        17958                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2338                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        29262                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           39                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         6597                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        54670                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            92907                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2338                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        29262                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           39                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         6597                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        54670                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           92907                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data       185834                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data       205183                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total       391017                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3059                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4433                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total         7492                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data       188893                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data       209616                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       398509                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3254000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        87000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total      3341000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5679500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     11921500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     17601000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1649081000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2814047500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4463128500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    164901500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    494215000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    659116500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    287811000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1073015000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1360826000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    164901500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1936892000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3254000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        87000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    494215000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3887062500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6486412000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    164901500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1936892000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3254000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        87000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    494215000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3887062500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6486412000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28249472000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30682332500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58931804500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    512257000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    827881000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1340138000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28761729000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31510213500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60271942500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000567                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000063                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000297                       # mshr miss rate for ReadReq accesses
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.816667                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.867982                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.484579                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.412177                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.381987                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.226656                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014295                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.015528                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010127                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.017501                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.022130                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.013311                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014295                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.102858                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000567                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000063                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015528                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.073730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034964                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014295                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.102858                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000567                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000063                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015528                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.073730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034964                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        87000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total        83525                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23181.632653                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20841.783217                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21543.451652                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65026.853312                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69287.622495                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 67649.809016                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70531.009410                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74915.112930                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73767.935087                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73759.866735                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76338.574274                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75778.260385                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70531.009410                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66191.374479                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        87000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74915.112930                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.466435                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69816.181773                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70531.009410                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66191.374479                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        87000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74915.112930                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.466435                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69816.181773                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152014.550620                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149536.426020                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150714.174831                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167458.973521                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186754.116851                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178875.867592                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152264.663063                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150323.512995                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 151243.616832                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5117226                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5117226                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13905                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13905                       # Transaction distribution
-system.membus.trans_dist::Writeback            143720                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1707                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1707                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130847                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130847                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1698                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1698                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3396                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3396                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7126806                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037388                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       457961                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10622155                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141555                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141555                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10767106                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3569512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6074773                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17637504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27281789                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6011648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6011648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33300229                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              820                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5455844                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.000311                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.017639                       # Request fanout histogram
+system.membus.trans_dist::ReadReq             5067078                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5116429                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13886                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13886                       # Transaction distribution
+system.membus.trans_dist::Writeback            144224                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8915                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1691                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1691                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130923                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130923                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         49352                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1657                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1657                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            1                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3314                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3314                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124404                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037524                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       467564                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            2                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10629494                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       142133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10774941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6628                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6628                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568437                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6075045                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17691840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27335322                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3025024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3025024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                30366974                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              812                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5464824                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.000303                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.017410                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5454146     99.97%     99.97% # Request fanout histogram
-system.membus.snoop_fanout::2                    1698      0.03%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5463167     99.97%     99.97% # Request fanout histogram
+system.membus.snoop_fanout::2                    1657      0.03%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             5455844                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           234105000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5464824                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           233042000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           304102500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           304115000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2302000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2344000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           670380805                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           525464887                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1151000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            1172000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1321113701                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1340471277                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           32422007                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           38659394                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1817,50 +1839,54 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            7449528                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7448995                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13907                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13907                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1546428                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        28278                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1672                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1672                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           290026                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          290026                       # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq            1151                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1743864                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14988008                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73882                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       225048                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17030802                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55802432                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213393597                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       274152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       823488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270293669                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           74263                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9350095                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.022573                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.148538                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5232649                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7464311                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13888                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13888                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          1628034                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          977588                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1686                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1686                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           291075                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          291075                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        882303                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1349887                       # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq            1172                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            1                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        19960                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2645849                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15085510                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        77708                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       228805                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18037872                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56466048                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213762586                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       290440                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       837080                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              271356154                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          159100                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         10426288                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.028740                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.167075                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9139035     97.74%     97.74% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 211060      2.26%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10126637     97.13%     97.13% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 299651      2.87%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9350095                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2511915480                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           402000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           10426288                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2853173500                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           328500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         868906655                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         883247245                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1944011740                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1934319786                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          26208491                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          28757491                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          98848126                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         101435667                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index df256055e..1f83c039b 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061296                       # Number of seconds simulated
-sim_ticks                                 61295518500                       # Number of ticks simulated
-final_tick                                61295518500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061280                       # Number of seconds simulated
+sim_ticks                                 61279840500                       # Number of ticks simulated
+final_tick                                61279840500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 265745                       # Simulator instruction rate (inst/s)
-host_op_rate                                   267069                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              179784475                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 446692                       # Number of bytes of host memory used
-host_seconds                                   340.94                       # Real time elapsed on the host
+host_inst_rate                                 263178                       # Simulator instruction rate (inst/s)
+host_op_rate                                   264489                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              178002192                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 447788                       # Number of bytes of host memory used
+host_seconds                                   344.26                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           49536                       # Nu
 system.physmem.num_reads::cpu.inst                774                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14800                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               808150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15453006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16261156                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          808150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             808150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              808150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15453006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16261156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               808357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15456959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16265316                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          808357                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             808357                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              808357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15456959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16265316                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                         15574                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61295424000                       # Total gap between requests
+system.physmem.totGap                     61279747000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     15453                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     15454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       110                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1527                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      651.693517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     447.533847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     399.021267                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            238     15.59%     15.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          181     11.85%     27.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           84      5.50%     32.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           68      4.45%     37.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      4.65%     42.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           87      5.70%     47.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           52      3.41%     51.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           56      3.67%     54.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          690     45.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1527                       # Bytes accessed per row activation
-system.physmem.totQLat                       75432750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 367445250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1531                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      650.032658                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     444.829113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     399.661041                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            243     15.87%     15.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          186     12.15%     28.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           73      4.77%     32.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           65      4.25%     37.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           75      4.90%     41.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          100      6.53%     48.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           43      2.81%     51.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           51      3.33%     54.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          695     45.40%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1531                       # Bytes accessed per row activation
+system.physmem.totQLat                       71795500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 363808000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4843.51                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        4609.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23593.51                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          16.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23359.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          16.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       16.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       16.27                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14042                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14039                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.16                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3935753.44                       # Average gap between requests
-system.physmem.pageHitRate                      90.16                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6282360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3427875                       # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap                      3934746.82                       # Average gap between requests
+system.physmem.pageHitRate                      90.14                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6259680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3415500                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                  63772800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4003384320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2494246185                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34588236750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41159350290                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.511167                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57530940500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2046720000                       # Time in different power states
+system.physmem_0.refreshEnergy             4002367200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2491685460                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34581139500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41148640140                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.507037                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57518843500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2046200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1716061500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1713017750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5261760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2871000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  57509400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5314680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2899875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  57517200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4003384320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2575259145                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34517172750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41161458375                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.545560                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57412676250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2046720000                       # Time in different power states
+system.physmem_1.refreshEnergy             4002367200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2548940535                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34530915750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41147955240                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.495861                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57435989500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2046200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1834237500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1796249000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20766617                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17069689                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                20766613                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17069686                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            765538                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8958723                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8857106                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups              8958713                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8857097                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.865720                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   62714                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.865730                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   62715                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,67 +377,67 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        122591037                       # number of cpu cycles simulated
+system.cpu.numCycles                        122559681                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2197459                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2197712                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.353059                       # CPI: cycles per instruction
-system.cpu.ipc                               0.739066                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109335027                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13256010                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.352713                       # CPI: cycles per instruction
+system.cpu.ipc                               0.739255                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109336366                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13223315                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            946108                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3616.919530                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26267744                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3616.962336                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26267632                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            950204                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.644321                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20526719250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3616.919530                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.883037                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883037                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             27.644203                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20520732500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3616.962336                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.883047                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.883047                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          255                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2247                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          254                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2248                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         1594                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55463926                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55463926                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21598657                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21598657                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660805                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660805                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55463928                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55463928                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21598652                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21598652                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660698                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660698                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26259462                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26259462                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26259970                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26259970                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       914937                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        914937                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74176                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74176                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      26259350                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26259350                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26259858                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26259858                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       914943                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        914943                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74283                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74283                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       989113                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         989113                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       989117                       # number of overall misses
-system.cpu.dcache.overall_misses::total        989117                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11917910744                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11917910744                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2566961500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2566961500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14484872244                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14484872244                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14484872244                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14484872244                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22513594                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22513594                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       989226                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         989226                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       989230                       # number of overall misses
+system.cpu.dcache.overall_misses::total        989230                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11918923000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11918923000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2541568000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2541568000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14460491000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14460491000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14460491000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14460491000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22513595                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22513595                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27248575                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27248575                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27249087                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27249087                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040639                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040639                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015666                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015666                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     27248576                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27248576                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27249088                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27249088                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040640                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040640                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015688                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015688                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036300                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036300                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036299                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036299                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14644.304790                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14644.245569                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036304                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036304                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036303                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036303                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14617.985172                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14617.926064                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -478,14 +478,14 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       943289                       # number of writebacks
 system.cpu.dcache.writebacks::total            943289                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11503                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11503                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27409                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27409                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        38912                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38912                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        38912                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38912                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11509                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11509                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27516                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27516                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39025                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39025                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903434                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       903434                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46767                       # number of WriteReq MSHR misses
@@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       950201
 system.cpu.dcache.demand_mshr_misses::total       950201                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950204                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950204                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10412555256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10412555256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1464079000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1464079000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       155500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       155500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11876634256                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11876634256                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11876789756                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11876789756                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865211000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865211000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1480610000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1480610000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12345821000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12345821000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12345977500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12345977500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040128                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040128                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009877                       # mshr miss rate for WriteReq accesses
@@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034872
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034871                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           690.424253                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27792420                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           690.428077                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27792848                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34653.890274                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34654.423940                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   690.424253                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.337121                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.337121                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   690.428077                       # Average occupied blocks per requestor
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 system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55587246                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55587246                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27792420                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27792420                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27792420                       # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::cpu.inst     27792420                       # number of overall hits
-system.cpu.icache.overall_hits::total        27792420                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          55588102                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst     27792848                       # number of ReadReq hits
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 system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     60382998                       # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::cpu.inst     60382998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     60382998                       # number of demand (read+write) miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst     27793222                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_accesses::cpu.inst     27793650                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total     27793650                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75290.521197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75290.521197                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74313.591022                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74313.591022                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          802
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     58841002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     58841002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     58841002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     58841002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     58841002                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     58841002                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     58797500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     58797500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     58797500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     58797500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     58797500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     58797500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918                       # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10245.234608                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831338                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10246.423743                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.717940                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.889696                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9355.355364                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.450791                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   215.428453                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.285503                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  9356.530979                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.454442                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   215.438322                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.285539                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020583                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006574                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.312660                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
@@ -632,78 +632,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1095                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13876                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15216684                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15216684                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           26                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       903175                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903201                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         15238060                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15238060                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks       943289                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       943289                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        32223                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        32223                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           26                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           26                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903175                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       903175                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           26                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       935398                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          935424                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           26                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       935398                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         935424                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          776                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          262                       # number of ReadReq misses
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 system.cpu.l2cache.ReadExReq_misses::cpu.data        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          776                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14806                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          776                       # number of overall misses
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 system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     57766000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21545250                       # number of ReadReq miss cycles
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 system.cpu.l2cache.Writeback_accesses::total       943289                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        46767                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        46767                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       950204                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data       950204                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       951006                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.967581                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001148                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.310989                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.310989                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967581                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967581                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000290                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967581                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015582                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.016385                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967581                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015582                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016385                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -712,93 +718,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            6                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          774                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          256                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1030                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14544                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          774                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          774                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          256                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          256                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          774                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14800                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     47928250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17945750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     65874000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    891746250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    891746250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     47928250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    909692000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    957620250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     47928250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    909692000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    957620250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001139                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    921208000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    921208000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49433000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49433000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18805000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18805000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    940013000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    989446000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49433000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    940013000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    989446000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.310989                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.310989                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000283                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016376                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         904239                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        904239                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       943289                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2672                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46767                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46767                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1604                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843697                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2845301                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       903437                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1607                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846366                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2847973                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121183552                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          121234880                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1894295                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1897118                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1894295    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1897118    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1894295                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1890436500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1897118                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1891848000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1372498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1203998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1428685244                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1425308994                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                1030                       # Transaction distribution
 system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1030                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
@@ -814,9 +827,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21690500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            21740500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82133750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82134000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index cb0d7cfc4..37d15d84b 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,117 +1,117 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058203                       # Number of seconds simulated
-sim_ticks                                 58203290500                       # Number of ticks simulated
-final_tick                                58203290500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058174                       # Number of seconds simulated
+sim_ticks                                 58174017500                       # Number of ticks simulated
+final_tick                                58174017500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   132567                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               84750962                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 445160                       # Number of bytes of host memory used
-host_seconds                                   686.76                       # Real time elapsed on the host
+host_inst_rate                                 129950                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130597                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               83449704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 446256                       # Number of bytes of host memory used
+host_seconds                                   697.11                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             48256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       930624                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1023424                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        25536                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             25536                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                696                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                754                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14541                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15991                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             399                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  399                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               765318                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               829094                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15989199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17583611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          765318                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             765318                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            438738                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 438738                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            438738                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              765318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              829094                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15989199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18022349                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15991                       # Number of read requests accepted
-system.physmem.writeReqs                          399                       # Number of write requests accepted
-system.physmem.readBursts                       15991                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        399                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1010944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     12480                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     24064                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1023424                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  25536                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      195                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       3                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1015                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst             44480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             49984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       930560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1025024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        26560                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             26560                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                695                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                781                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 16016                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             415                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  415                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               764603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               859215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15996145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17619962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          764603                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             764603                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            456561                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 456561                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            456561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              764603                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              859215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15996145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18076524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         16016                       # Number of read requests accepted
+system.physmem.writeReqs                          415                       # Number of write requests accepted
+system.physmem.readBursts                       16016                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        415                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1011776                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     13248                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     25088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1025024                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  26560                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      207                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                1014                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 876                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 963                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1023                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 957                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1139                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1118                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1101                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1044                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1144                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1126                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1093                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1040                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                939                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                905                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                898                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                928                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                921                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  32                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                903                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                912                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                888                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                938                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                925                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  43                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  16                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   9                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  45                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  72                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                  35                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                  36                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  10                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  44                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  74                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                  25                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                  45                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                 13                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  5                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 37                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 47                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                 27                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                 10                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  5                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                 11                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 32                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 48                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                 32                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58203132500                       # Total gap between requests
+system.physmem.totGap                     58173860500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15991                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   16016                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    399                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10953                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       519                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       309                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       305                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       289                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       304                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        62                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    415                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     10954                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       522                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       347                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       287                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       308                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
@@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       23                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                       22                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       22                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -197,94 +197,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1905                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      542.975328                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     308.892213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     434.261771                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            566     29.71%     29.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          241     12.65%     42.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           93      4.88%     47.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           55      2.89%     50.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           58      3.04%     53.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           46      2.41%     55.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           56      2.94%     58.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           43      2.26%     60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          747     39.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1905                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            21                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       751.047619                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       33.268614                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3285.704681                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511              20     95.24%     95.24% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      4.76%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              21                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            21                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.904762                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.888741                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.768424                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  2      9.52%      9.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 18     85.71%     95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      4.76%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              21                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      171453784                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 467628784                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     78980000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10854.25                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1930                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      536.107772                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     304.077638                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     432.159932                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            590     30.57%     30.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          221     11.45%     42.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           97      5.03%     47.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           69      3.58%     50.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      3.68%     54.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           49      2.54%     56.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           51      2.64%     59.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           42      2.18%     61.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          740     38.34%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1930                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            22                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       717.636364                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       31.597036                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3209.686449                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511              21     95.45%     95.45% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      4.55%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              22                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            22                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.818182                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.808292                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.588490                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  2      9.09%      9.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 20     90.91%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              22                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      169690298                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 466109048                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     79045000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10733.78                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29604.25                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.37                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.41                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29483.78                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          17.39                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.43                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       17.62                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.75                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14158                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       107                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.63                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  27.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3551136.82                       # Average gap between requests
-system.physmem.pageHitRate                      88.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7854840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4285875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  64662000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1354320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3801486000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2465906355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32758411500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39103960890                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.860748                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54486158959                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1943500000                       # Time in different power states
+system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        17.30                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14150                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       110                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  26.83                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3540494.22                       # Average gap between requests
+system.physmem.pageHitRate                      87.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7832160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4273500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  64506000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1289520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2476215945                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32730681000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39084249885                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.881619                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54439969881                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1772833541                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1788917619                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6546960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3572250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58468800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                  1082160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3801486000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2423272635                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32795809500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39090238305                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.624974                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54548877915                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1943500000                       # Time in different power states
+system.physmem_1.actEnergy                    6667920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3638250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  58507800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                  1146960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2448182205                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32755263750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39072858645                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.685955                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54482617084                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1710114585                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1747288416                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28259243                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23281231                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            837964                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11853879                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11785418                       # Number of BTB hits
+system.cpu.branchPred.lookups                28257086                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23279263                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            837830                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11842064                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11784394                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.422459                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75772                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 89                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.513007                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   75760                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -403,128 +402,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116406582                       # number of cpu cycles simulated
+system.cpu.numCycles                        116348036                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             748963                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134993544                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28259243                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11861190                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114762985                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679231                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  934                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          807                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32304048                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   578                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116353304                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165458                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             748817                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134985012                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28257086                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11860154                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114705506                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1679063                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1007                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          831                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32301197                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   575                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116295692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.165959                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.319053                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58781536     50.52%     50.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13944543     11.98%     62.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9221339      7.93%     70.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34405886     29.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58725363     50.50%     50.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13942075     11.99%     62.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9230802      7.94%     70.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34397452     29.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116353304                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242763                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.159673                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8844047                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64088450                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33032847                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9560591                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827369                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101287                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12347                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114434695                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1995559                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827369                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15306268                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49839660                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109196                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35408210                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14862601                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110902627                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1415209                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11132813                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1143128                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1515839                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 570040                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129962079                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483289738                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119478423                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               422                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116295692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242867                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.160183                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8839821                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64036145                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33034290                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9558144                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 827292                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4101248                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114428571                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1996975                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 827292                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15280810                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49891272                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109349                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35424705                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14762264                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110897410                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1415598                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11131669                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1144033                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1526935                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 476507                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129954934                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483266147                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119472382                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               420                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22649160                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 22642015                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts               4363                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           4358                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21571738                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26814245                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5349583                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            611820                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           348925                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109694682                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8246                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101389793                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1073874                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18661898                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41702987                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             28                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116353304                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871396                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.988581                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                  21506426                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26812625                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5349337                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            517439                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           253975                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109689181                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8247                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 101387653                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1074699                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18656398                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41685630                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             29                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116295692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871809                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.989320                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54657362     46.98%     46.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31448211     27.03%     74.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            21997386     18.91%     92.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7054887      6.06%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1195141      1.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 317      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54655211     47.00%     47.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31361654     26.97%     73.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22008607     18.92%     92.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7072409      6.08%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1197497      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 314      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116353304                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116295692                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9796132     48.71%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     50      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                12      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9605412     47.76%     96.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                708293      3.52%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9793566     48.69%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     50      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9616917     47.81%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                703878      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71985396     71.00%     71.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10710      0.01%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71983899     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10709      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
@@ -546,90 +545,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              56      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              53      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            123      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24344165     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049339      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24343332     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5049532      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101389793                       # Type of FU issued
-system.cpu.iq.rate                           0.870997                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20109899                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198342                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340316208                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128365476                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99625945                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 455                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                608                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          113                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121499455                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     237                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           282715                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              101387653                       # Type of FU issued
+system.cpu.iq.rate                           0.871417                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20114424                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198391                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340259668                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128354519                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99625011                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 453                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                612                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121501841                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     236                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           290489                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4338334                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1512                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         1293                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       604739                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4336714                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1516                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         1340                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       604493                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7563                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130432                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7566                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130818                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827369                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8116840                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                661308                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109715594                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 827292                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8117300                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                684188                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109710095                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26814245                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5349583                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4358                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178503                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                319361                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           1293                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436568                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412973                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849541                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100128175                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23807340                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1261618                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26812625                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5349337                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4359                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 178987                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                342189                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           1340                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         436578                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412874                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               849452                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100126762                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23806670                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1260891                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12666                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28725211                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624854                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917871                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860159                       # Inst execution rate
-system.cpu.iew.wb_sent                       99711063                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99626058                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59706030                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95562635                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12667                       # number of nop insts executed
+system.cpu.iew.exec_refs                     28724538                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20624131                       # Number of branches executed
+system.cpu.iew.exec_stores                    4917868                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860580                       # Inst execution rate
+system.cpu.iew.wb_sent                       99709725                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99625125                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59703453                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95545682                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.855846                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624784                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.856268                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624868                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        17389920                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        17384546                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            825718                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113660326                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801103                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.737104                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            825591                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    113603530                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801504                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.738080                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77212273     67.93%     67.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18641375     16.40%     84.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7152706      6.29%     90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3462873      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1652643      1.45%     95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       524647      0.46%     95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       723706      0.64%     96.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       178634      0.16%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4111469      3.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77180399     67.94%     67.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18615023     16.39%     84.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7150693      6.29%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3466326      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1641860      1.45%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       544762      0.48%     95.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       704352      0.62%     96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       180030      0.16%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4120085      3.63%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113660326                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    113603530                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -675,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4111469                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217986682                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219580711                       # The number of ROB writes
-system.cpu.timesIdled                             588                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           53278                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4120085                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217915896                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219569120                       # The number of ROB writes
+system.cpu.timesIdled                             587                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           52344                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284986                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284986                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778219                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778219                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108112805                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58701882                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369068913                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58692415                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28415527                       # number of misc regfile reads
+system.cpu.cpi                               1.284339                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284339                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778610                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778610                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108111439                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58700930                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       95                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 369063438                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58693153                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28414947                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5469565                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.787779                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18297385                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470077                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.344996                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35255000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.787779                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999586                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999586                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5470195                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.789215                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18252015                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5470707                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.336317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35049500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.789215                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999588                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999588                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          341                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          343                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61924887                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61924887                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13934133                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13934133                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4354955                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4354955                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61908703                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61908703                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13889937                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13889937                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353797                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353797                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18289088                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18289088                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18289610                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18289610                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9549988                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9549988                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       380026                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       380026                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18243734                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18243734                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18244256                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18244256                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9585777                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9585777                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381184                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381184                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9930014                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9930014                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9930021                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9930021                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88444420972                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88444420972                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3962617493                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3962617493                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       297000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       297000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92407038465                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92407038465                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92407038465                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92407038465                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23484121                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23484121                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9966961                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9966961                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9966968                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9966968                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88717689000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88717689000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3954782792                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3954782792                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  92672471792                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92672471792                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92672471792                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92672471792                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23475714                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23475714                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -755,302 +754,298 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28219102                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28219102                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28219631                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28219631                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.406657                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.406657                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080259                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080259                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28210695                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28210695                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28211224                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28211224                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408327                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408327                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080504                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080504                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.351890                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.351890                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.351883                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.351883                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9261.207550                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9261.207550                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10427.227329                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10427.227329                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        19800                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        19800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9305.831640                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9305.831640                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9305.825080                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9305.825080                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       306116                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        36058                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            120736                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            2278                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.535416                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    15.828797                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353304                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353304                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353298                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353298                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9255.138003                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9255.138003                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9297.966731                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9297.966731                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9297.960201                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9297.960201                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       330068                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        99317                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121445                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12837                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717839                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.736777                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5437967                       # number of writebacks
-system.cpu.dcache.writebacks::total           5437967                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4312992                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4312992                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       146947                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       146947                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5436552                       # number of writebacks
+system.cpu.dcache.writebacks::total           5436552                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337556                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4337556                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158702                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158702                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4459939                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4459939                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4459939                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4459939                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5236996                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5236996                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       233079                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       233079                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4496258                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4496258                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4496258                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4496258                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248221                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248221                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222482                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222482                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470079                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470079                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  40520727758                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  40520727758                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2294964437                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2294964437                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       213000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       213000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42815692195                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  42815692195                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42815905195                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  42815905195                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223002                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223002                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049225                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049225                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      5470703                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5470703                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5470707                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5470707                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43246268500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43246268500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2278267197                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2278267197                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45524535697                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45524535697                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45524750197                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45524750197                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223560                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223560                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193843                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193843                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193839                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193839                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7737.399028                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7737.399028                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9846.294334                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9846.294334                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53250                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53250                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7827.258711                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7827.258711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7827.291927                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7827.291927                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193923                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193920                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193920                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8240.176719                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8240.176719                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8321.514748                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8321.514748                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8321.547873                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8321.547873                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               449                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.262881                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32302878                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               908                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35575.856828                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               451                       # number of replacements
+system.cpu.icache.tags.tagsinuse           428.509106                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32300030                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               910                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35494.538462                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.262881                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836451                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836451                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   428.509106                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836932                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836932                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          332                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64608978                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64608978                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32302878                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32302878                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32302878                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32302878                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32302878                       # number of overall hits
-system.cpu.icache.overall_hits::total        32302878                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1157                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1157                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1157                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1157                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1157                       # number of overall misses
-system.cpu.icache.overall_misses::total          1157                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62067238                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62067238                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62067238                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62067238                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62067238                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62067238                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32304035                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32304035                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32304035                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32304035                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32304035                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32304035                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          64603278                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64603278                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32300030                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32300030                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32300030                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32300030                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32300030                       # number of overall hits
+system.cpu.icache.overall_hits::total        32300030                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1154                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1154                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1154                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1154                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1154                       # number of overall misses
+system.cpu.icache.overall_misses::total          1154                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     61388483                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     61388483                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total     61388483                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     61388483                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     61388483                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32301184                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32301184                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::cpu.inst     32301184                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32301184                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53644.976664                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53644.976664                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53644.976664                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53644.976664                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53644.976664                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53644.976664                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        18268                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          134                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               226                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53196.259099                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53196.259099                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53196.259099                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53196.259099                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        19635                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               227                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    80.831858                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    26.800000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    86.497797                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          249                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          249                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          249                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          249                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          249                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          249                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          908                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          908                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          908                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          908                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49773732                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     49773732                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49773732                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     49773732                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49773732                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     49773732                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          244                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          244                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          244                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          244                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          910                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          910                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          910                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50524487                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     50524487                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50524487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     50524487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50524487                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     50524487                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54816.885463                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54816.885463                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54816.885463                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4492873                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5289387                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       687833                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4525641                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5296015                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       665258                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14073797                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              562                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        12069.997275                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           10652240                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15999                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           665.806613                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074393                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              580                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        12072.245633                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           10689052                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            16020                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           667.231710                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11108.777118                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   571.857159                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   208.039641                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   181.323358                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.678026                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034903                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.012698                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.011067                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.736694                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          237                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          190                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          976                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1058                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13088                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.014465                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.927734                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        174792474                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       174792474                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          211                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      5236401                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        5236612                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      5437967                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      5437967                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       232700                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       232700                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          211                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5469101                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5469312                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          211                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5469101                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5469312                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          697                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          467                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1164                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 11065.307975                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   570.003280                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   229.604220                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   207.330158                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.675373                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034790                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.014014                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.012654                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.736831                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          262                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            8                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          220                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          972                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1056                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13076                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015991                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.926392                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.ReadExReq_misses::cpu.data          509                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          509                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          697                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst          697                       # number of overall misses
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+system.cpu.l2cache.overall_avg_miss_latency::total 67120.200827                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1059,144 +1054,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          399                       # number of writebacks
-system.cpu.l2cache.writebacks::total              399                       # number of writebacks
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43944500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     25180500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     25180500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43944500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     51230000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     95174500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43944500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     51230000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    860658985                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    955833485                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001454                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001454                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.766520                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000138                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000265                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.766520                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000138                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001501                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001501                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.763736                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000270                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.003962                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55837.951807                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58621.068407                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41027.438918                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        13751                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        13751                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74866.542773                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74866.542773                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64393.246684                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62419.148276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64393.246684                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42458.355492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.003967                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 42541.593841                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76616.176471                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76616.176471                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63229.496403                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 57098.639456                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 57098.639456                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        5237776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       5237776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      5437967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        22114                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       233209                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       233209                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1816                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16378127                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16379943                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698114944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          698173056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       22116                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     10931068                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.002023                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.044933                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       5245099                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      5436967                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        31344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        22118                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       226518                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       226518                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          910                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244189                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2259                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408706                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16410965                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58240                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698064576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          698122816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       22698                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     10964961                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.002070                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.045451                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           10908954     99.80%     99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              22114      0.20%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           10942263     99.79%     99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              22698      0.21%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       10931068                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10892444998                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization         18.7                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy         3000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1495005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       10964961                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10907683500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1366996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8205165681                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8206064991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               15652                       # Transaction distribution
-system.membus.trans_dist::ReadResp              15652                       # Transaction distribution
-system.membus.trans_dist::Writeback               399                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               339                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              339                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32385                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32385                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1048960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1048960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              15676                       # Transaction distribution
+system.membus.trans_dist::Writeback               415                       # Transaction distribution
+system.membus.trans_dist::CleanEvict              117                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         15676                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32564                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  32564                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1051584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1051584                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16392                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16548                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16392    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16548    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16392                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            27168735                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16548                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            27912645                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           83645045                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           83778508                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index b81c12b39..86fbc3533 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.361489                       # Number of seconds simulated
-sim_ticks                                361488530500                       # Number of ticks simulated
-final_tick                               361488530500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                361488535500                       # Number of ticks simulated
+final_tick                               361488535500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1163469                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1163517                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1724927568                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425840                       # Number of bytes of host memory used
-host_seconds                                   209.57                       # Real time elapsed on the host
+host_inst_rate                                1224088                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1224138                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1814798992                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 426288                       # Number of bytes of host memory used
+host_seconds                                   199.19                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data             2606821                       # To
 system.physmem.bw_total::total                2762444                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        722977061                       # number of cpu cycles simulated
+system.cpu.numCycles                        722977071                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   243825150                       # Number of instructions committed
@@ -50,7 +50,7 @@ system.cpu.num_mem_refs                     105711441                       # nu
 system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               722977060.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               722977070.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
@@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  244431613                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            935475                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3562.469045                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3562.469039                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           104186699                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            110.887521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle      134366266000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3562.469045                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle      134366268500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3562.469039                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.869743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.869743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       939567
 system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10274449500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10274449500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1148937000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1148937000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        88000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        88000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11423386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11423386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11423386500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11423386500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10720878000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10720878000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1172292000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1172292000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        90000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        90000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11893170000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11893170000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11893170000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11893170000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
@@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        22000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        22000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        22500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        22500                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                25                       # number of replacements
-system.cpu.icache.tags.tagsinuse           725.412975                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           725.412974                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               882                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          277120.880952                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   725.412975                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   725.412974                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.354206                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.354206                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          857                       # Occupied blocks per task id
@@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst          882                       # n
 system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
 system.cpu.icache.overall_misses::total           882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     48384500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     48384500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     48384500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     48384500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     48384500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     48384500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     48389500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     48389500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     48389500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     48389500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     48389500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     48389500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    244421499                       # number of demand (read+write) accesses
@@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54857.709751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54857.709751                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54863.378685                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54863.378685                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -284,34 +284,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          882
 system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47061500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     47061500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47061500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     47061500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47061500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     47061500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47507500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     47507500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47507500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     47507500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47507500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     47507500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9730.625210                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1813290                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         9730.625133                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1813523                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15586                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           116.340947                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           116.355896                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8847.670164                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.635590                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   144.319456                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  8847.670093                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.635586                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   144.319455                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.270009                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.022541                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004404                       # Average percentage of cache occupancy
@@ -323,78 +323,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          150
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13986                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475647                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15068052                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15068052                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       892700                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         892703                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         15069916                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15069916                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks       935266                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       935266                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        32147                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        32147                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            3                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       892700                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       892700                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       924847                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          924850                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       924847                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         924850                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          879                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          157                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1036                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14567                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14567                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          879                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          879                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          157                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          157                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          879                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14724                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total         15603                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          879                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15603                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46148000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      8242500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     54390500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    764767500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    764767500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     46148000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     46150500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     46150500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8242500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      8242500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     46150500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data    773010000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    819158000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     46148000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total    819160500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     46150500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    773010000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    819158000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          882                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       892857                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       893739                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::total    819160500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks       935266                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       935266                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        46714                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          882                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          882                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       892857                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       892857                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          882                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       939571                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       940453                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          882                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       939571                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       940453                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996599                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000176                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001159                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311834                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996599                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996599                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000176                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000176                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996599                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015671                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.016591                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996599                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015671                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016591                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -403,84 +409,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          879                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          157                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1036                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          879                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          879                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          157                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          157                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          879                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14724                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          879                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14724                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35599500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6358500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     41958000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    589963500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    589963500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    596322000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    631921500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35599500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    596322000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    631921500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000176                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001159                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    619097500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    619097500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     37360500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     37360500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6672500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6672500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     37360500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    625770000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    663130500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     37360500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    625770000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    663130500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311834                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000176                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000176                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015671                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016591                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015671                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         893739                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        893739                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       935266                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          233                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46714                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46714                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1764                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2814408                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2816172                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          882                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       892857                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1789                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2814616                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2816405                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    119989568                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          120046016                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1875719                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1875953                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1875719    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1875953    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1875719                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1873125500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1875953                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1873242500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1323000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1409356500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                1036                       # Transaction distribution
 system.membus.trans_dist::ReadResp               1036                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14567                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14567                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1036                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31206                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  31206                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       998592                       # Cumulative packet size per connected master and slave (bytes)
@@ -496,9 +508,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15603                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15603500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            15606000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           78015500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           78018000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 1d5681a17..6f4514f73 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,79 +1,79 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.062108                       # Number of seconds simulated
-sim_ticks                                 62108139000                       # Number of ticks simulated
-final_tick                                62108139000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.062104                       # Number of seconds simulated
+sim_ticks                                 62103992500                       # Number of ticks simulated
+final_tick                                62103992500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114338                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201331                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44948395                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455560                       # Number of bytes of host memory used
-host_seconds                                  1381.77                       # Real time elapsed on the host
+host_inst_rate                                 108853                       # Simulator instruction rate (inst/s)
+host_op_rate                                   191673                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42789284                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 455804                       # Number of bytes of host memory used
+host_seconds                                  1451.39                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             64960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1886080                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1951040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        13952                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             13952                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1015                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29470                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30485                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             218                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  218                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1045918                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             30367679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                31413596                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1045918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1045918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            224640                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 224640                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            224640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1045918                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            30367679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               31638237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30485                       # Number of read requests accepted
-system.physmem.writeReqs                          218                       # Number of write requests accepted
-system.physmem.readBursts                       30485                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        218                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1943936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     12736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1951040                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  13952                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             64832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1883648                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1948480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        64832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           64832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        11776                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             11776                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1013                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29432                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30445                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             184                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  184                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1043926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             30330546                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                31374472                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1043926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1043926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            189617                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 189617                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            189617                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1043926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            30330546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               31564090                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30446                       # Number of read requests accepted
+system.physmem.writeReqs                          184                       # Number of write requests accepted
+system.physmem.readBursts                       30446                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        184                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1943488                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5056                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     10368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1948544                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  11776                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       79                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1926                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2065                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2030                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1931                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2028                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1903                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1964                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1862                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1927                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2069                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1929                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1959                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1865                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               1795                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1937                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               1796                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               1819                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  14                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  89                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  33                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  21                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  13                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  25                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  94                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   8                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                  13                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
 system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
 system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
@@ -82,25 +82,25 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     62107943500                       # Total gap between requests
+system.physmem.totGap                     62103972000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30485                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30446                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    218                       # Write request sizes (log2)
+system.physmem.writePktSize::6                    184                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                     29885                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       375                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       384                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        75                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,225 +193,221 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2733                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      715.170143                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     514.587482                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     389.057467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            358     13.10%     13.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          248      9.07%     22.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          120      4.39%     26.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          119      4.35%     30.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          123      4.50%     35.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           99      3.62%     39.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           98      3.59%     42.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           77      2.82%     45.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1491     54.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2733                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            11                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2756.545455                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       17.211839                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     9104.288367                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023             10     90.91%     90.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1      9.09%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              11                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            11                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.090909                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.068275                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.943880                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1      9.09%      9.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  8     72.73%     81.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      9.09%     90.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      9.09%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              11                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      137229500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 706742000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4517.99                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         2720                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      718.117647                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     516.851204                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     389.329010                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            349     12.83%     12.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          252      9.26%     22.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          126      4.63%     26.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          106      3.90%     30.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          106      3.90%     34.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          118      4.34%     38.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           88      3.24%     42.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           74      2.72%     44.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1501     55.18%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2720                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3367.333333                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       25.147360                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    10062.626521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  9    100.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      131808750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 701190000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151835000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4340.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23267.99                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          31.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.21                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       31.41                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.22                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23090.53                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          31.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       31.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.24                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.79                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27693                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       139                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  63.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2022862.38                       # Average gap between requests
-system.physmem.pageHitRate                      90.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   10893960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    5944125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 122226000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1134000                       # Energy for write commands per rank (pJ)
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        13.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27697                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       108                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   91.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.70                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2027553.77                       # Average gap between requests
+system.physmem.pageHitRate                      91.01                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   10848600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    5919375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 122421000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   997920                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             4056274560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2882954835                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34733126250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41812553730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.273290                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57766447750                       # Time in different power states
+system.physmem_0.actBackEnergy             2874471525                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34740567750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41811500730                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.256335                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57777967000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      2073760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2264083750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2251676750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9699480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5292375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 114270000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    9714600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5300625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 114371400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             4056274560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3028786200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34605195750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41819570205                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.386420                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57553191500                       # Time in different power states
+system.physmem_1.actBackEnergy             3081237030                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34559194500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41826144555                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.492132                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57475856750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      2073760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2477594500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2554341750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37389273                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          37389273                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            796060                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             21398380                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21281300                       # Number of BTB hits
+system.cpu.branchPred.lookups                37407153                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          37407153                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            797525                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             21397569                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21291133                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.452856                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5538224                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               5409                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.502579                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5522199                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5378                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        124216279                       # number of cpu cycles simulated
+system.cpu.numCycles                        124207986                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28231712                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      201414270                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37389273                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           26819524                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      95072949                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1663625                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  802                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13794                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  27828273                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                190340                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          124151097                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.859474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.368729                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28243826                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      201531916                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37407153                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           26813332                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      95053081                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1666271                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                          3                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                  874                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         14570                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines                  27854872                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                208775                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          124145503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.860655                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.369153                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 63239379     50.94%     50.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3665567      2.95%     53.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3524262      2.84%     56.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5966051      4.81%     61.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7629037      6.14%     67.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5460577      4.40%     72.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3340077      2.69%     74.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2074079      1.67%     76.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 29252068     23.56%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 63227150     50.93%     50.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3664165      2.95%     53.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3505505      2.82%     56.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5966108      4.81%     61.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7642313      6.16%     67.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5450974      4.39%     72.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3347715      2.70%     74.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2079081      1.67%     76.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29262492     23.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            124151097                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.301001                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.621480                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13268959                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63731322                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  36520631                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9798373                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 831812                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              334996047                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 831812                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18591577                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8853243                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          16711                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  40784813                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              55072941                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              328614087                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2150                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 765426                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48317500                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4996682                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           330544508                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             872885571                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        537662987                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               823                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            124145503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.301165                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.622536                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 13298609                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63688691                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  36532978                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9792090                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 833135                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              335053232                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 833135                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18606460                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8830273                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          16174                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  40807487                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              55051974                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              328692220                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2265                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 765831                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               48323645                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4961410                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           330669691                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             873156420                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        537756143                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               567                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 51331761                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                491                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            491                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  66256508                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106310670                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            36525048                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          49788623                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8449867                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  325445308                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1768                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 307970327                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             51339                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        47254612                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     68858955                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1323                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     124151097                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.480609                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.128122                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 51456944                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            481                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  66169497                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            106330183                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            36531613                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          49817317                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8395275                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  325507363                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2500                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 308019505                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             50533                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        47317399                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     68952386                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2055                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     124145503                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.481117                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.143684                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30600533     24.65%     24.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19593175     15.78%     40.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16755552     13.50%     53.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17045170     13.73%     67.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            15962727     12.86%     80.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12649852     10.19%     90.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5781799      4.66%     95.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4158736      3.35%     98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1603553      1.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30872061     24.87%     24.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19525697     15.73%     40.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            16787256     13.52%     54.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17357634     13.98%     68.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            14846406     11.96%     80.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12689504     10.22%     90.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6302474      5.08%     95.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3917362      3.16%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1847109      1.49%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       124151097                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       124145503                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  316480      7.51%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3709774     87.98%     95.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                190338      4.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  329941      8.31%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3456308     87.04%     95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                184474      4.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             175386232     56.95%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11196      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   347      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  45      0.00%     56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             33338      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             175410718     56.95%     56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11212      0.00%     56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   340      0.00%     56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  38      0.00%     56.96% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.96% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.96% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.96% # Type of FU issued
@@ -437,84 +433,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.96% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.96% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.96% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             98505322     31.99%     88.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34033845     11.05%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             98529790     31.99%     88.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34034069     11.05%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              307970327                       # Type of FU issued
-system.cpu.iq.rate                           2.479307                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4216592                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013692                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          744358969                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         372741153                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    305973250                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 713                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1268                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          215                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              312153240                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     339                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58265174                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              308019505                       # Type of FU issued
+system.cpu.iq.rate                           2.479869                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3970723                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012891                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          744205245                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         372866875                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    306008038                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 524                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                864                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          168                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              311956642                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     248                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         58273942                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     15531285                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        58585                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41983                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      5085296                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     15550798                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        67136                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        41716                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5091861                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3668                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        124310                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3678                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        142532                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 831812                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5699246                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3054980                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           325447076                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            123578                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106310670                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             36525048                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                476                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2754                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3058247                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41983                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         401587                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       444043                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               845630                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             306900581                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              98149248                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1069746                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 833135                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5706209                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3030570                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           325509863                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            125935                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             106330183                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             36531613                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                471                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2800                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3033928                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          41716                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         402612                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       445047                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               847659                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             306958421                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              98183223                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1061084                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    131968833                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31535132                       # Number of branches executed
-system.cpu.iew.exec_stores                   33819585                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.470695                       # Inst execution rate
-system.cpu.iew.wb_sent                      306301702                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     305973465                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 231572201                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 336082865                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    132003276                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31537655                       # Number of branches executed
+system.cpu.iew.exec_stores                   33820053                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.471326                       # Inst execution rate
+system.cpu.iew.wb_sent                      306335531                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     306008206                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 231609196                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 336109097                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.463232                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.689033                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.463676                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.689089                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        47355755                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        47420049                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            796864                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117707358                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.363425                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.086682                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            798401                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    117693042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.363712                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.086908                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     53343112     45.32%     45.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     15934290     13.54%     58.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11043478      9.38%     68.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8763951      7.45%     75.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1880549      1.60%     77.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1728612      1.47%     78.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       852753      0.72%     79.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       687313      0.58%     80.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23473300     19.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     53351319     45.33%     45.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     15952359     13.55%     58.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     10962553      9.31%     68.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8763534      7.45%     75.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1923790      1.63%     77.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1729278      1.47%     78.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       853123      0.72%     79.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       692579      0.59%     80.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23464507     19.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117707358                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117693042                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -560,324 +556,330 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23473300                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    419782277                       # The number of ROB reads
-system.cpu.rob.rob_writes                   657549499                       # The number of ROB writes
-system.cpu.timesIdled                             568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           65182                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              23464507                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    419841048                       # The number of ROB reads
+system.cpu.rob.rob_writes                   657686557                       # The number of ROB writes
+system.cpu.timesIdled                             566                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           62483                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.786236                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.786236                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.271883                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.271883                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                493639930                       # number of integer regfile reads
-system.cpu.int_regfile_writes               240886983                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       187                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      111                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107695799                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64567771                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               196286158                       # number of misc regfile reads
+system.cpu.cpi                               0.786183                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.786183                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.271968                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.271968                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                493729388                       # number of integer regfile reads
+system.cpu.int_regfile_writes               240917610                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       146                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107705980                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 64576396                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               196329384                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2072438                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.873358                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68418587                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076534                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.948455                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       19755616250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.873358                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993133                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993133                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2072430                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.090496                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            68424035                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076526                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             32.951206                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       19739908500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.090496                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993186                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993186                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          606                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          595                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3373                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         144472022                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        144472022                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     37072750                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37072750                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345837                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345837                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68418587                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68418587                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68418587                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68418587                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2685242                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2685242                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93915                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93915                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2779157                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2779157                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2779157                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2779157                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32132974500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32132974500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2979596244                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2979596244                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35112570744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35112570744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35112570744                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35112570744                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39757992                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39757992                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         144493228                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        144493228                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     37078222                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37078222                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345813                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345813                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68424035                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68424035                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68424035                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68424035                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2690377                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2690377                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93939                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93939                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2784316                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2784316                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2784316                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2784316                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32316565000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32316565000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2955969494                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2955969494                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35272534494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35272534494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35272534494                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35272534494                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     39768599                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     39768599                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     71197744                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     71197744                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     71197744                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     71197744                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.067540                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.067540                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002987                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002987                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.039034                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.039034                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039034                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039034                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11966.509722                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11966.509722                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31726.521259                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31726.521259                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12634.252309                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12634.252309                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12634.252309                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12634.252309                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       199012                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     71208351                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     71208351                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     71208351                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     71208351                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.067651                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.067651                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002988                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002988                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.039101                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.039101                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039101                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039101                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12668.294293                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12668.294293                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       221313                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             39951                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43094                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     4.981402                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.135587                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066723                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066723                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       690734                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       690734                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11889                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        11889                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       702623                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       702623                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       702623                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       702623                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994508                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994508                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82026                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82026                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076534                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076534                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076534                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076534                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23036962750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23036962750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2767409747                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2767409747                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25804372497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25804372497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25804372497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  25804372497                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050166                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050166                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029166                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029166                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029166                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029166                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11550.198219                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11550.198219                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33738.201875                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33738.201875                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12426.655425                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12426.655425                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12426.655425                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12426.655425                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2066711                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066711                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       695911                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       695911                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11877                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11877                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       707788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       707788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       707788                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       707788                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994466                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994466                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82062                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82062                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076528                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076528                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076528                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076528                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24203306500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24203306500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2798613994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2798613994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27001920494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27001920494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27001920494                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27001920494                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050152                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050152                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002610                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002610                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029161                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029161                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029161                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029161                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                61                       # number of replacements
-system.cpu.icache.tags.tagsinuse           828.295860                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27826925                       # Total number of references to valid blocks.
+system.cpu.icache.tags.replacements                64                       # number of replacements
+system.cpu.icache.tags.tagsinuse           833.320748                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27853507                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              1032                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          26964.074612                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          26989.832364                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   828.295860                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.404441                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.404441                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          971                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   833.320748                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.406895                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.406895                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          968                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          873                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.474121                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55657578                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55657578                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27826925                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27826925                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27826925                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27826925                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27826925                       # number of overall hits
-system.cpu.icache.overall_hits::total        27826925                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1348                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1348                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1348                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1348                       # number of overall misses
-system.cpu.icache.overall_misses::total          1348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    101838000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    101838000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    101838000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    101838000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    101838000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    101838000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27828273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27828273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27828273                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27828273                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27828273                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27828273                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75547.477745                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75547.477745                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75547.477745                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75547.477745                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75547.477745                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75547.477745                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          460                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          876                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.472656                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55710776                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55710776                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27853507                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27853507                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27853507                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27853507                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27853507                       # number of overall hits
+system.cpu.icache.overall_hits::total        27853507                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1365                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1365                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1365                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1365                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1365                       # number of overall misses
+system.cpu.icache.overall_misses::total          1365                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     98783500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     98783500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     98783500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     98783500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     98783500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     98783500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27854872                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27854872                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27854872                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27854872                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27854872                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27854872                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000049                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000049                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000049                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000049                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000049                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72368.864469                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72368.864469                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72368.864469                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72368.864469                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72368.864469                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72368.864469                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          217                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    65.714286                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    72.333333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          316                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          316                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          316                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          316                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          316                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          316                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          333                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          333                       # number of ReadReq MSHR hits
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 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1032                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         1032                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         1032                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         1032                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         1032                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         1032                       # number of overall MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.806202                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              538                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20666.246528                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4029584                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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 system.cpu.l2cache.demand_accesses::cpu.inst         1032                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.inst         1032                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.981589                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75414.116486                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75414.116486                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76271.167048                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76271.167048                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75414.116486                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.127646                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73149.083623                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75414.116486                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.127646                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73149.083623                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -886,107 +888,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          218                       # number of writebacks
-system.cpu.l2cache.writebacks::total              218                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1015                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          467                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1482                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        29003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1015                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29470                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30485                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1015                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29470                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30485                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     65734750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     28861750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     94596500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1765566500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1765566500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65734750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1794428250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1860163000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65734750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1794428250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1860163000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983527                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000234                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000743                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983527                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014192                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014673                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983527                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014192                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014673                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64763.300493                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61802.462527                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63830.296896                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60875.306003                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60875.306003                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64763.300493                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60889.998303                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61018.960144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64763.300493                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60889.998303                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61018.960144                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          184                       # number of writebacks
+system.cpu.l2cache.writebacks::total              184                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            7                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            7                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28996                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        28996                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1013                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1013                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          437                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          437                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1013                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29433                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30446                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1013                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29433                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30446                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1827412000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1827412000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     66264500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     66264500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28980500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28980500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66264500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856392500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1922657000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66264500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856392500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1922657000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353213                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353213                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.981589                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000219                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000219                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014174                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014655                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014174                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014655                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63022.899710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63022.899710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65414.116486                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66316.933638                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66316.933638                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63071.807155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63149.740524                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63071.807155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63149.740524                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1995500                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1995500                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066723                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82066                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82066                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2064                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219791                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6221855                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp       1995466                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6085                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82092                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82092                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994436                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2128                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225475                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6227603                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        66048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265168448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265234496                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4144289                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265167168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265233216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         495                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4150549                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.000119                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010920                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4144289    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4150054     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                495      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4144289                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4138867500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        4150549                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4141738000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1740500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1548000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3121586499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3114789000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          5.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                1482                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1482                       # Transaction distribution
-system.membus.trans_dist::Writeback               218                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             29003                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            29003                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61188                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61188                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61188                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1964992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1964992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1964992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               1448                       # Transaction distribution
+system.membus.trans_dist::Writeback               184                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               34                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28996                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28996                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1450                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61108                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61108                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61108                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1960192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1960192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1960192                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30703                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30664                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30703    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30664    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30703                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42842500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30664                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            42854000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          160650000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          160427250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 02993075a..d40f8a71c 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.365989                       # Number of seconds simulated
-sim_ticks                                365989065500                       # Number of ticks simulated
-final_tick                               365989065500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                365988859500                       # Number of ticks simulated
+final_tick                               365988859500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 678113                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1194048                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1570885616                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 451452                       # Number of bytes of host memory used
-host_seconds                                   232.98                       # Real time elapsed on the host
+host_inst_rate                                 643347                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1132831                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1490347920                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451472                       # Number of bytes of host memory used
+host_seconds                                   245.57                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1871744                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1923136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1871424                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1922816                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        51392                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           51392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks         6400                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              6400                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks         6528                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6528                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                803                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30049                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             100                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  100                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               140419                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5114207                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 5254627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          140419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             140419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             17487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  17487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             17487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              140419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5114207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5272114                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data              29241                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30044                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             102                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  102                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               140420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5113336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5253756                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          140420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             140420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             17837                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  17837                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             17837                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              140420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5113336                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5271592                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        731978131                       # number of cpu cycles simulated
+system.cpu.numCycles                        731977719                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   157988548                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                     122219137                       # nu
 system.cpu.num_load_insts                    90779385                       # Number of load instructions
 system.cpu.num_store_insts                   31439752                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               731978130.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               731977718.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
@@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  278192465                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           2062733                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.488607                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4076.488591                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           120152370                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             58.133677                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle      126079702000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.488607                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle      126079705500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.488591                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995236                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995236                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data      2066829                       # n
 system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  25498684000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  25498684000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2598456000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2598456000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  28097140000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28097140000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  28097140000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28097140000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25498474000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25498474000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2598457000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2598457000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  28096931000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  28096931000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  28096931000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  28096931000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     90779447                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     90779447                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
@@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_miss_rate::total     0.016911                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13594.322510                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13594.322510                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13594.221389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13594.221389                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -172,8 +172,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2062484                       # number of writebacks
-system.cpu.dcache.writebacks::total           2062484                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      2062482                       # number of writebacks
+system.cpu.dcache.writebacks::total           2062482                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1960720                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1960720                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       106109                       # number of WriteReq MSHR misses
@@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2066829
 system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22557604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  22557604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2439292500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2439292500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24996896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24996896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24996896500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24996896500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23537754000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23537754000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2492348000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2492348000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26030102000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26030102000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26030102000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26030102000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
@@ -198,22 +198,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_mshr_miss_rate::total     0.016911                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                24                       # number of replacements
-system.cpu.icache.tags.tagsinuse           665.632506                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           665.632473                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           217695356                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               808                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          269424.945545                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   665.632506                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   665.632473                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.325016                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.325016                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
@@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst          808                       # n
 system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
 system.cpu.icache.overall_misses::total           808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44230500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44230500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44230500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44230500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44230500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44230500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44233500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44233500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44233500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44233500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44233500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44233500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    217696164                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    217696164                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    217696164                       # number of demand (read+write) accesses
@@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54740.717822                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54740.717822                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54744.430693                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54744.430693                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -273,117 +273,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          808
 system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43018500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     43018500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43018500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     43018500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43018500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     43018500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43425500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     43425500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43425500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     43425500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43425500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     43425500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              318                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20041.899592                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3992419                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30026                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.965397                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              313                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20041.891909                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3992697                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30021                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.996802                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   557.646380                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   153.900219                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_percent::cpu.data     0.004697                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27875                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses         33177103                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33177103                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1960498                       # number of ReadReq hits
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-system.cpu.l2cache.Writeback_hits::writebacks      2062484                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2062484                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         33179282                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33179282                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2062482                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2062482                       # number of Writeback hits
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42158000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     11655000                       # number of ReadReq miss cycles
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 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1523791000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993812                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993812                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014150                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805                       # average ReadReq miss latency
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 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -392,107 +398,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          100                       # number of writebacks
-system.cpu.l2cache.writebacks::total              100                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          803                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          803                       # number of ReadCleanReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.inst          803                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.inst          803                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.273530                       # mshr miss rate for ReadExReq accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993812                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993812                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1961528                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       1961528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2062484                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2062584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          486                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       106109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       106109                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6196142                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6197758                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          808                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1960720                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6196391                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6198031                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    264276032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          264327744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4130121                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    264275904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          264327616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         313                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4130707                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.000076                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.008704                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4130121    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4130394     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                313      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4130121                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4127544500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        4130707                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4127679000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1212000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3100243500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                1025                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1025                       # Transaction distribution
-system.membus.trans_dist::Writeback               100                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1020                       # Transaction distribution
+system.membus.trans_dist::Writeback               102                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               14                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             29024                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            29024                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        60198                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        60198                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  60198                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1929536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1929536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1929536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          1020                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        60204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        60204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  60204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1929344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1929344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1929344                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30149                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30160                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30149    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30160    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30149                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30585000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30160                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30601000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          150276500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          150253000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index c17d6c2b8..721b096f0 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.413311                       # Number of seconds simulated
-sim_ticks                                413311471500                       # Number of ticks simulated
-final_tick                               413311471500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.412968                       # Number of seconds simulated
+sim_ticks                                412968287500                       # Number of ticks simulated
+final_tick                               412968287500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 320750                       # Simulator instruction rate (inst/s)
-host_op_rate                                   320750                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              216651718                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298932                       # Number of bytes of host memory used
-host_seconds                                  1907.72                       # Real time elapsed on the host
+host_inst_rate                                 309752                       # Simulator instruction rate (inst/s)
+host_op_rate                                   309752                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              209049423                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299216                       # Number of bytes of host memory used
+host_seconds                                  1975.46                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            170944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24150272                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24321216                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       170944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          170944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18724096                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18724096                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2671                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             377348                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                380019                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292564                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292564                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               413596                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58431168                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58844764                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          413596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             413596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45302628                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45302628                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45302628                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              413596                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58431168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104147392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        380019                       # Number of read requests accepted
-system.physmem.writeReqs                       292564                       # Number of write requests accepted
-system.physmem.readBursts                      380019                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292564                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24298816                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22400                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18722432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24321216                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18724096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      350                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            171008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24125568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24296576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       171008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          171008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18781376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18781376                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2672                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             376962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                379634                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293459                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293459                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               414095                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58419905                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                58833999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          414095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             414095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45478979                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45478979                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45478979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              414095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58419905                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104312978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        379634                       # Number of read requests accepted
+system.physmem.writeReqs                       293459                       # Number of write requests accepted
+system.physmem.readBursts                      379634                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293459                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24275200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21376                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18779968                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24296576                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18781376                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      334                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23743                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23222                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23516                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24520                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25462                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23584                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23675                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23980                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23177                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23949                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24669                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22747                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23729                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24425                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22797                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22474                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               17756                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               17433                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17901                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18770                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               19442                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18538                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18680                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18573                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18350                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18834                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19126                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17963                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18227                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18693                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17147                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17105                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23720                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23189                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23443                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24493                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25427                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23582                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23638                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23957                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23144                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23961                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24713                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22767                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23721                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24378                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22727                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22440                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               17784                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               17460                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17942                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18842                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               19508                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18590                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18730                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18662                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18408                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18932                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19251                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18034                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18264                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18730                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17177                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17123                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    413311383000                       # Total gap between requests
+system.physmem.totGap                    412968199500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  380019                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  379634                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292564                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    378271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1381                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293459                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    377911                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1373                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,47 +144,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    17007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17473                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17472                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -193,128 +193,125 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       142426                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.052266                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.083619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.600685                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          51194     35.94%     35.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38668     27.15%     63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13205      9.27%     72.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8199      5.76%     78.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5653      3.97%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3753      2.64%     84.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3030      2.13%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2604      1.83%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16120     11.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         142426                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17258                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.998378                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      228.944233                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17248     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            4      0.02%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       142181                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.814019                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.682339                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.904056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50781     35.72%     35.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38739     27.25%     62.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13305      9.36%     72.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8117      5.71%     78.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5703      4.01%     82.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3753      2.64%     84.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3029      2.13%     86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2502      1.76%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16252     11.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         142181                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17324                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.893847                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      236.830288                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17315     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17258                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17258                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.950863                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.879940                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.817078                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17053     98.81%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             148      0.86%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              32      0.19%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               8      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               6      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17258                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4042656250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11161450000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1898345000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10647.84                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17324                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17324                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.938178                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.866265                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.087562                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           17274     99.71%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              36      0.21%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39               4      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               3      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::328-335             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17324                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4037980750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11149855750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1896500000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10645.88                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29397.84                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.79                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.30                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       58.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.30                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29395.88                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          58.78                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.48                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       58.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.48                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.81                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.55                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314442                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215335                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.82                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                       614513.57                       # Average gap between requests
-system.physmem.pageHitRate                      78.81                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  549347400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  299743125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1495252200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                953162640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26995381920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62649847125                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           193029983250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             285972717660                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.908567                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   320566103500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13801320000                       # Time in different power states
+system.physmem.avgWrQLen                        20.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314187                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216366                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                       613538.10                       # Average gap between requests
+system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  547268400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  298608750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1493302200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                955858320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26973005280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62129952405                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           193280474250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             285678469605                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.770048                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   320991140250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13789880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78943046000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78186381000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  527378040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  287755875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1466010000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                942483600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26995381920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59502215925                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           195791063250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             285512288610                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.794563                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   325183887500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13801320000                       # Time in different power states
+system.physmem_1.actEnergy                  527582160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  287867250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1465152000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                945535680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26973005280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            59078125665                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           195957550500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             285234818535                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              690.695650                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   325462585000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13789880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     74324788750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     73715009750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               124207419                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87899229                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6403012                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71682632                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67406446                       # Number of BTB hits
+system.cpu.branchPred.lookups               124207922                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87898525                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6402854                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71417252                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67405039                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.034558                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15055625                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1126618                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.382012                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15056477                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126637                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149439695                       # DTB read hits
-system.cpu.dtb.read_misses                     564071                       # DTB read misses
+system.cpu.dtb.read_hits                    149440392                       # DTB read hits
+system.cpu.dtb.read_misses                     563754                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                150003766                       # DTB read accesses
-system.cpu.dtb.write_hits                    57327469                       # DTB write hits
-system.cpu.dtb.write_misses                     66798                       # DTB write misses
+system.cpu.dtb.read_accesses                150004146                       # DTB read accesses
+system.cpu.dtb.write_hits                    57327101                       # DTB write hits
+system.cpu.dtb.write_misses                     66835                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57394267                       # DTB write accesses
-system.cpu.dtb.data_hits                    206767164                       # DTB hits
-system.cpu.dtb.data_misses                     630869                       # DTB misses
+system.cpu.dtb.write_accesses                57393936                       # DTB write accesses
+system.cpu.dtb.data_hits                    206767493                       # DTB hits
+system.cpu.dtb.data_misses                     630589                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207398033                       # DTB accesses
-system.cpu.itb.fetch_hits                   226566802                       # ITB hits
+system.cpu.dtb.data_accesses                207398082                       # DTB accesses
+system.cpu.itb.fetch_hits                   226564860                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               226566850                       # ITB accesses
+system.cpu.itb.fetch_accesses               226564908                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -328,82 +325,82 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        826622943                       # number of cpu cycles simulated
+system.cpu.numCycles                        825936575                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13262321                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13262650                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.350908                       # CPI: cycles per instruction
-system.cpu.ipc                               0.740243                       # IPC: instructions per cycle
-system.cpu.tickCycles                       740977624                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        85645319                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           2535493                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.640549                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202664153                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539589                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.801949                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1642835250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.640549                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997959                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997959                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.349787                       # CPI: cycles per instruction
+system.cpu.ipc                               0.740858                       # IPC: instructions per cycle
+system.cpu.tickCycles                       740975160                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        84961415                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           2535462                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.659006                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202664910                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539558                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.803222                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1636438500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.659006                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997964                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          828                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          830                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3144                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414772189                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414772189                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146997943                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146997943                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     55666210                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666210                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     202664153                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202664153                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    202664153                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202664153                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1908323                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908323                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1543824                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543824                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3452147                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3452147                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3452147                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3452147                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37798959500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37798959500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  48016494500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  48016494500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  85815454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  85815454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  85815454000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  85815454000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    148906266                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148906266                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         414773666                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414773666                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146998717                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146998717                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     55666193                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666193                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     202664910                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202664910                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    202664910                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202664910                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1908303                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908303                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1543841                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543841                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3452144                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452144                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3452144                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452144                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37694000500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37694000500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  47697864000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  47697864000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  85391864500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  85391864500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  85391864500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  85391864500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    148907020                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148907020                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206116300                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206116300                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206116300                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206116300                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012816                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012816                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    206117054                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206117054                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206117054                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206117054                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012815                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012815                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026985                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016749                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016749                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.016749                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.016749                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.422276                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.422276                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31102.311209                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31102.311209                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24858.574678                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24858.574678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24858.574678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24858.574678                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016748                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016748                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016748                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016748                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19752.628644                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19752.628644                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30895.580568                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30895.580568                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.892970                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24735.892970                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.892970                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24735.892970                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -412,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2340079                       # number of writebacks
-system.cpu.dcache.writebacks::total           2340079                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143534                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143534                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769024                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769024                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       912558                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       912558                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       912558                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       912558                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764789                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764789                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774800                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       774800                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2539589                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539589                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2539589                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539589                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32332751000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  32332751000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23008045000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23008045000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55340796000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  55340796000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55340796000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  55340796000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      2339794                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339794                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143529                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143529                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769057                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769057                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       912586                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       912586                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       912586                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       912586                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764774                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764774                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774784                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       774784                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2539558                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539558                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2539558                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539558                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33188844000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33188844000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23330038500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23330038500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56518882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56518882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56518882500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56518882500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011852                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011852                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
@@ -446,69 +443,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012321
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012321                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012321                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012321                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18321.029313                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18321.029313                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29695.463345                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29695.463345                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21791.241024                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21791.241024                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21791.241024                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21791.241024                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18806.285677                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18806.285677                       # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22255.401334                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22255.401334                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3154                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1117.871500                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226561819                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4983                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45466.951435                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3160                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1117.196292                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226559871                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4989                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45411.880337                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1117.871500                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545836                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1588                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         453138587                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        453138587                       # Number of data accesses
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-system.cpu.icache.overall_misses::cpu.inst         4983                       # number of overall misses
-system.cpu.icache.overall_misses::total          4983                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    247079500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    247079500                       # number of ReadReq miss cycles
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49584.487257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49584.487257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49584.487257                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49584.487257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49584.487257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49584.487257                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48778.813389                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48778.813389                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48778.813389                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48778.813389                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48778.813389                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48778.813389                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -517,123 +514,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4983                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47862.933976                       # average ReadReq mshr miss latency
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           347308                       # number of replacements
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.536022                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.096924                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.098162                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265534                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265534                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.536022                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.148586                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149345                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.536022                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.148586                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149345                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78333.021340                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80828.718239                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80790.274630                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78767.432800                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78767.432800                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78333.021340                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79700.033523                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79690.425347                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78333.021340                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79700.033523                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79690.425347                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses         41822837                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41822837                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2339794                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2339794                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       571874                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571874                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2317                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         2317                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590722                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1590722                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2317                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2162596                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164913                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2317                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2162596                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164913                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206263                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206263                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2672                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2672                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       170699                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       170699                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2672                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       376962                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        379634                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2672                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       376962                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       379634                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16205579000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16205579000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    206542500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    206542500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13758959500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  13758959500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    206542500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  29964538500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30171081000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    206542500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  29964538500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30171081000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2339794                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2339794                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       778137                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       778137                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4989                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4989                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761421                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1761421                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4989                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2539558                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.data      2539558                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544547                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265073                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265073                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.535578                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.535578                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.096910                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.096910                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.535578                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.148436                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.149195                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.535578                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.148436                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.149195                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78567.552106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78567.552106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77298.839820                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77298.839820                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80603.632710                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80603.632710                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77298.839820                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79489.546692                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79474.127712                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77298.839820                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79489.546692                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79474.127712                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -642,105 +645,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292564                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292564                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2671                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       170726                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       173397                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206622                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206622                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2671                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       377348                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       380019                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2671                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       377348                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       380019                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    175804500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  11663055250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11838859750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13690980000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13690980000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    175804500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25354035250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  25529839750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    175804500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25354035250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  25529839750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.536022                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.096924                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098162                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265534                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265534                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.536022                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148586                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149345                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.536022                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148586                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149345                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65819.730438                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68314.464405                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68276.035629                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66260.998345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66260.998345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65819.730438                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67190.061296                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67180.429794                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65819.730438                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67190.061296                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67180.429794                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293459                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293459                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          739                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          739                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206263                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206263                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2672                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2672                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       170699                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       170699                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2672                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       376962                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       379634                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.data       376962                       # number of overall MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14142949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14142949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    179822500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    179822500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12051969500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12051969500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    179822500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26194918500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26374741000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    179822500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26194918500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26374741000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265073                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265073                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.535578                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.096910                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.096910                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148436                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149195                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148436                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68567.552106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68567.552106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67298.839820                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70603.632710                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70603.632710                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69489.546692                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.127712                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69489.546692                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69474.127712                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1766434                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1766434                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2340079                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       778138                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       778138                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9966                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7419257                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7429223                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       318912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312298752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312617664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4884651                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1766410                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2633253                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       252293                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       778137                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       778137                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4989                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761421                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13138                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7614578                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7627716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       319296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312278528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312597824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      346924                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5430093                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.063889                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.244555                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4884651    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5083169     93.61%     93.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             346924      6.39%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4884651                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4782404500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5430093                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4881378500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8026500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7483500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3891673000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3809337000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              173397                       # Transaction distribution
-system.membus.trans_dist::ReadResp             173397                       # Transaction distribution
-system.membus.trans_dist::Writeback            292564                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206622                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206622                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052602                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1052602                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43045312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43045312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             173371                       # Transaction distribution
+system.membus.trans_dist::Writeback            293459                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            51814                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206263                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206263                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        173371                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1104541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43077952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43077952                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            672583                       # Request fanout histogram
+system.membus.snoop_fanout::samples            724907                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  672583    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  724907    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              672583                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1984973000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              724907                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2020096000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2011061250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2009057000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 41f3b60e2..9049068c3 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.366030                       # Number of seconds simulated
-sim_ticks                                366029674500                       # Number of ticks simulated
-final_tick                               366029674500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.365934                       # Number of seconds simulated
+sim_ticks                                365934171500                       # Number of ticks simulated
+final_tick                               365934171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 241467                       # Simulator instruction rate (inst/s)
-host_op_rate                                   261540                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              174471263                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317880                       # Number of bytes of host memory used
-host_seconds                                  2097.94                       # Real time elapsed on the host
+host_inst_rate                                 236242                       # Simulator instruction rate (inst/s)
+host_op_rate                                   255881                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              170651382                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317968                       # Number of bytes of host memory used
+host_seconds                                  2144.34                       # Real time elapsed on the host
 sim_insts                                   506582156                       # Number of instructions simulated
 sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9008192                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9229632                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6182144                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6182144                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3460                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140753                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                144213                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96596                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96596                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               604978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24610551                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25215529                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          604978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             604978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          16889734                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               16889734                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          16889734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              604978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24610551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42105264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        144213                       # Number of read requests accepted
-system.physmem.writeReqs                        96596                       # Number of write requests accepted
-system.physmem.readBursts                      144213                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      96596                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9221696                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7936                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6180992                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9229632                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6182144                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      124                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            218560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8996480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9215040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       218560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          218560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6186432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6186432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140570                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                143985                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96663                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96663                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               597266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24584968                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25182234                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          597266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             597266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          16905860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               16905860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          16905860                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              597266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24584968                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42088095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        143985                       # Number of read requests accepted
+system.physmem.writeReqs                        96663                       # Number of write requests accepted
+system.physmem.readBursts                      143985                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      96663                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9208192                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6184704                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9215040                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6186432                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9409                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9017                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8952                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8679                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9335                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8992                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8932                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8655                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                9455                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9348                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8942                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8103                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8564                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8678                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8771                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9482                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9373                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9523                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8716                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9077                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6225                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6098                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6004                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5808                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6164                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6178                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6016                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5497                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5725                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5821                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6450                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6306                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6280                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5998                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6047                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8940                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8097                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8569                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8673                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8766                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9474                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9347                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8717                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9061                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6192                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6097                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6005                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5812                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6185                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6187                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5496                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5731                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5829                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6464                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6313                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6284                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6001                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6058                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    366029646000                       # Total gap between requests
+system.physmem.totGap                    365934145500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  144213                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  143985                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96596                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143718                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  96663                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       334                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5679                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5606                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
@@ -193,112 +193,107 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65352                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.682213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.342104                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.346143                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24838     38.01%     38.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18259     27.94%     65.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6996     10.71%     76.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7952     12.17%     88.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2091      3.20%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1098      1.68%     93.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          757      1.16%     94.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          602      0.92%     95.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2759      4.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65352                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5574                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.850018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      381.983730                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5570     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65249                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.897316                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.545884                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.443874                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24707     37.87%     37.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18339     28.11%     65.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7015     10.75%     76.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7835     12.01%     88.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2110      3.23%     91.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1145      1.75%     93.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          725      1.11%     94.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          601      0.92%     95.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2772      4.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65249                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5581                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.778176                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      381.924168                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5576     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5574                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5574                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.326516                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.224346                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.427330                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2648     47.51%     47.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2778     49.84%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              56      1.00%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              28      0.50%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              12      0.22%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              10      0.18%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               6      0.11%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               9      0.16%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               4      0.07%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               7      0.13%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               2      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               4      0.07%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               2      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65               1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::70-71               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-81               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5574                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1545997750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4247666500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    720445000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10729.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5581                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5581                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.315176                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.217549                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.442698                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2634     47.20%     47.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2799     50.15%     97.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              58      1.04%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              24      0.43%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              19      0.34%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               9      0.16%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               9      0.16%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               3      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               4      0.07%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               3      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               4      0.07%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-73               1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::74-75               2      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-93               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5581                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1559327000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4257039500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    719390000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10837.84                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29479.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          16.89                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.22                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       16.89                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29587.84                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          16.90                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       16.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.60                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110923                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64387                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.66                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1519999.86                       # Average gap between requests
-system.physmem.pageHitRate                      72.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  248708880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135704250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 560640600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                310761360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23906897040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47751629445                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           177727049250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             250641390825                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.767505                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   295355626000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12222340000                       # Time in different power states
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110804                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64456                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.01                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1520619.93                       # Average gap between requests
+system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  248300640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135481500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 559572000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                310819680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47511748935                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           177881418000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             250548135075                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.687479                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   295615195000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12219220000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     58446120250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     58096250000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  245064960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133716000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562816800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                314753040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23906897040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            47056905180                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           178336456500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             250556609520                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.535877                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   296372694500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12222340000                       # Time in different power states
+system.physmem_1.actEnergy                  244785240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  133563375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 562356600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                315174240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            46698412230                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           178594871250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             250449957255                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.419183                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   296806540250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12219220000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57429294500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     56906569250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               132485545                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98435425                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6553959                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68727443                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64816198                       # Number of BTB hits
+system.cpu.branchPred.lookups               132492243                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98438822                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6555205                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68897926                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64816869                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.309049                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                10006764                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              17617                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.076662                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                10008233                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              17907                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -417,98 +412,98 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        732059349                       # number of cpu cycles simulated
+system.cpu.numCycles                        731868343                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506582156                       # Number of instructions committed
 system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13911652                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13915585                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.445095                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691996                       # IPC: instructions per cycle
-system.cpu.tickCycles                       695000552                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        37058797                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1139856                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.933719                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171285318                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1143952                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.731211                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4900143250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.933719                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993880                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993880                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.444718                       # CPI: cycles per instruction
+system.cpu.ipc                               0.692177                       # IPC: instructions per cycle
+system.cpu.tickCycles                       695013398                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36854945                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1139741                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.950270                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171285752                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1143837                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.746644                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4896340500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.950270                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993884                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993884                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          552                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          549                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3503                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346825504                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346825504                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114766819                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114766819                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53538648                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538648                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2769                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2769                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         346825855                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346825855                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114767186                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114767186                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53538711                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538711                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2773                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2773                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168305467                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168305467                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168308236                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168308236                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       854784                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        854784                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       700658                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700658                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1555442                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1555442                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1555458                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1555458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14034932732                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14034932732                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22036201250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22036201250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  36071133982                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  36071133982                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  36071133982                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  36071133982                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115621603                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115621603                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168305897                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168305897                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168308670                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168308670                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       854648                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854648                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       700595                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700595                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           14                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           14                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1555243                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1555243                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1555257                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1555257                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14022869000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14022869000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21909880500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21909880500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35932749500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35932749500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35932749500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35932749500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115621834                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115621834                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2785                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2785                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2787                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169860909                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169860909                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169863694                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169863694                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007393                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007393                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005745                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005745                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009157                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009157                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009157                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009157                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23190.279022                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23190.040478                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    169861140                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169861140                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169863927                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169863927                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007392                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005023                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005023                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009156                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009156                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009156                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009156                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23104.266986                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23104.059008                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -517,111 +512,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1068580                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068580                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        67006                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        67006                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344497                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344497                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       411503                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411503                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       411503                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411503                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787778                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       787778                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356161                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356161                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           13                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1143939                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1143939                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1143952                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1143952                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11938933765                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11938933765                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10970217000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10970217000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1208500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1208500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22909150765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22909150765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22910359265                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22910359265                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1068492                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068492                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66944                       # number of ReadReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total       411418                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       411418                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411418                       # number of overall MSHR hits
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+system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1143825                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1143825                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      1143837                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12336256500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12336256500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11129164500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11129164500                       # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1374500                       # number of SoftPFReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total  23465421000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total  23466795500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004668                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004668                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15155.200786                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15155.200786                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30801.286497                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30801.286497                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 92961.538462                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92961.538462                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20026.549287                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20026.549287                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20027.378129                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20027.378129                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004306                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004306                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006734                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006734                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179                       # average WriteReq mshr miss latency
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+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667                       # average SoftPFReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17693                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1189.692945                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           200785966                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19565                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10262.507846                       # Average number of references to valid blocks.
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 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1189.692945                       # Average occupied blocks per requestor
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-system.cpu.icache.tags.occ_percent::total     0.580905                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1410                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         401630627                       # Number of tag accesses
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
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 system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25165.844416                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25165.844416                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25165.844416                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25165.844416                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25165.844416                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25165.844416                       # average overall miss latency
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+system.cpu.icache.ReadReq_avg_miss_latency::total 24980.937292                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24980.937292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24980.937292                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -630,122 +625,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.176949                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.123054                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123960                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.176949                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.123054                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123960                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78836.727325                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82660.384577                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 82354.837965                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78624.853824                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78624.853824                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78836.727325                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79767.615864                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79745.271441                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78836.727325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79767.615864                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79745.271441                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4931                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25867                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19026681                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19026681                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1068492                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1068492                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       255561                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       255561                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16150                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        16150                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747691                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       747691                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        16150                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1003252                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1019402                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        16150                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1003252                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1019402                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       100813                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100813                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3417                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3417                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39772                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        39772                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3417                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       140585                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        144002                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3417                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       140585                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       144002                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7914075500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7914075500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    270270000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    270270000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3286332500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3286332500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    270270000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11200408000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11470678000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    270270000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11200408000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11470678000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      1068492                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1068492                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       356374                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356374                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19567                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        19567                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       787463                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       787463                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        19567                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1143837                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.inst        19567                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1143837                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1163404                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282885                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.282885                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.174631                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.174631                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050506                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050506                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.174631                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.122906                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123776                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.174631                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.122906                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123776                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78502.529436                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78502.529436                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79095.697981                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79095.697981                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82629.299507                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82629.299507                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79656.379773                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79656.379773                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -754,114 +755,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96596                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96596                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        96663                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96663                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           15                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39847                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        43307                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100906                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100906                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3460                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       140753                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       144213                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3460                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       140753                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       144213                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    229496250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2794594500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3024090750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6671817000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6671817000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    229496250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9466411500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9695907750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    229496250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9466411500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9695907750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053657                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283115                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283115                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123946                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123041                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123946                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536                       # average overall mshr miss latency
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1183                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1183                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100813                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100813                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3415                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3415                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39757                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39757                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3415                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       140570                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       143985                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3415                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       140570                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       143985                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6905945500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6905945500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    235984000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    235984000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2887628500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2887628500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    235984000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9793574000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10029558000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    235984000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9793574000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10029558000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282885                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282885                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.174529                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050487                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050487                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123762                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123762                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         807103                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        807103                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1068580                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356414                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356414                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39130                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356484                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3395614                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141602048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          142854208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2232097                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        807030                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1165155                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        98658                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356374                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356374                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        19567                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       787463                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56593                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3422797                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3479390                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141589056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          142841344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      111231                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2432071                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.045735                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.208910                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            2232097    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2320840     95.43%     95.43% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             111231      4.57%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2232097                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2184628500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        2432071                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2228912000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      30040746                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      29351498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1744732235                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1715762985                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               43307                       # Transaction distribution
-system.membus.trans_dist::ReadResp              43307                       # Transaction distribution
-system.membus.trans_dist::Writeback             96596                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100906                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100906                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       385022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 385022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15411776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15411776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              43172                       # Transaction distribution
+system.membus.trans_dist::Writeback             96663                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            13165                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100813                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100813                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         43172                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397798                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 397798                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15401472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15401472                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            240809                       # Request fanout histogram
+system.membus.snoop_fanout::samples            253813                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  240809    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253813    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              240809                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           679106500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              253813                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           683218000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          765494750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          764295250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 12498d68b..7cef0aacd 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233457                       # Number of seconds simulated
-sim_ticks                                233457400500                       # Number of ticks simulated
-final_tick                               233457400500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.233283                       # Number of seconds simulated
+sim_ticks                                233282768000                       # Number of ticks simulated
+final_tick                               233282768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140578                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152296                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64957541                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319412                       # Number of bytes of host memory used
-host_seconds                                  3594.00                       # Real time elapsed on the host
+host_inst_rate                                 136250                       # Simulator instruction rate (inst/s)
+host_op_rate                                   147606                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               62910352                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320784                       # Number of bytes of host memory used
+host_seconds                                  3708.18                       # Real time elapsed on the host
 sim_insts                                   505237724                       # Number of instructions simulated
 sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            691264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9218304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16465984                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26375552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       691264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          691264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18705216                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18705216                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10801                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144036                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257281                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                412118                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292269                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292269                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2960986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39486022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70531000                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               112978008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2960986                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2960986                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80122609                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80122609                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80122609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2960986                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39486022                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70531000                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              193100617                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        412118                       # Number of read requests accepted
-system.physmem.writeReqs                       292269                       # Number of write requests accepted
-system.physmem.readBursts                      412118                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292269                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26236672                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    138880                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18703040                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26375552                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18705216                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2170                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            683136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9221056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16463744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             26367936                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       683136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          683136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18705728                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18705728                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10674                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144079                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257246                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                411999                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292277                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292277                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2928360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39527377                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70574197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               113029935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2928360                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2928360                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80184782                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80184782                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80184782                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2928360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39527377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70574197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              193214717                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        411999                       # Number of read requests accepted
+system.physmem.writeReqs                       292277                       # Number of write requests accepted
+system.physmem.readBursts                      411999                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292277                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26229824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    138112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18703872                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26367936                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18705728                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2158                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26483                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25520                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25375                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24791                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27157                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               26569                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25228                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24398                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25772                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24727                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25014                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25991                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26422                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25825                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25184                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25492                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18766                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18282                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18016                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18022                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18772                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18348                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               17902                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17779                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18029                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17785                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18061                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18677                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18741                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18309                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18406                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18340                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26728                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25477                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25253                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24678                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27151                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               26546                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25195                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24195                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25840                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24882                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24886                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26093                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26302                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26067                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24895                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25653                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18973                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18287                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17868                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17935                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18795                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18319                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17931                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17655                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18179                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17927                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              17987                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18662                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18697                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18344                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18231                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18458                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233457328000                       # Total gap between requests
+system.physmem.totGap                    233282750000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  412118                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  411999                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292269                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    312558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7441                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6251                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4463                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292277                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    312898                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7330                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5273                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4418                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       40                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    19851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    18588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    13204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17443                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    18185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17613                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
@@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       306919                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      146.415804                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.989110                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     182.052610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         184181     60.01%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        81968     26.71%     86.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        16622      5.42%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7343      2.39%     94.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4784      1.56%     96.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2292      0.75%     96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1776      0.58%     97.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1536      0.50%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6417      2.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         306919                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17350                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.626628                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      116.525366                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           17349     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       306889                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      146.413224                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.997180                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     182.093051                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         184151     60.01%     60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        82036     26.73%     86.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        16582      5.40%     92.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7394      2.41%     94.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4756      1.55%     96.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2254      0.73%     96.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1661      0.54%     97.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1625      0.53%     97.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6430      2.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         306889                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17312                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.673001                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      116.829793                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           17311     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17350                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17350                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.843516                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.802727                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.214220                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10753     61.98%     61.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                289      1.67%     63.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5387     31.05%     94.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                614      3.54%     98.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                106      0.61%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 63      0.36%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 46      0.27%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 45      0.26%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 29      0.17%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 12      0.07%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  6      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17350                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9548241731                       # Total ticks spent queuing
-system.physmem.totMemAccLat               17234766731                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2049740000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23291.35                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17312                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17312                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.881238                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.838780                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.240848                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              10485     60.56%     60.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                306      1.77%     62.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5502     31.78%     94.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                671      3.88%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                134      0.77%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 74      0.43%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 42      0.24%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 45      0.26%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 29      0.17%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 14      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  9      0.05%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17312                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9036310212                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16720828962                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2049205000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22048.33                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42041.35                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         112.38                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      112.98                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40798.33                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         112.44                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.18                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      113.03                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.18                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.50                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.88                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.73                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     299652                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95604                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  32.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                       331433.33                       # Average gap between requests
+system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.78                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     299552                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95641                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  32.72                       # Row buffer hit rate for writes
+system.physmem.avgGap                       331237.68                       # Average gap between requests
 system.physmem.pageHitRate                      56.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1157927400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  631805625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1602907800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                945308880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            75190255245                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            74116872000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             168893231430                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              723.449687                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   122769601530                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7795580000                       # Time in different power states
+system.physmem_0.actEnergy                 1156763160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  631170375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1600435200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                944401680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15236457600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            74473770375                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            74637909000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             168680907390                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              723.094931                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   123643637069                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7789600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    102890225970                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    101845250931                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1162259280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  634169250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1594382400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                948263760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74130386985                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75046581000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             168764197155                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              722.896972                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   124323822632                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7795580000                       # Time in different power states
+system.physmem_1.actEnergy                 1163007720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  634577625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1595802000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                949158000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15236457600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            74040443550                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75018020250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             168637466745                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              722.908711                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   124281047938                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7789600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    101336607368                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    101208398062                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175097732                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131341907                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7444118                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90491460                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83879546                       # Number of BTB hits
+system.cpu.branchPred.lookups               175089811                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131337021                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7444155                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90376647                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83876100                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.693328                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12111412                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104155                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.807271                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12110019                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104160                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -410,129 +411,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        466914802                       # number of cpu cycles simulated
+system.cpu.numCycles                        466565537                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7831702                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      731836126                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175097732                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           95990958                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     450721779                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14940955                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 5640                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           179                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13551                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236729658                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34605                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          466043328                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.700638                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.179812                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7838065                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      731795546                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   175089811                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95986119                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     450385778                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14940817                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           243                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        14677                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 236716672                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 34578                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          465715008                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.701748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.179403                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 94098707     20.19%     20.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132700679     28.47%     48.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57861600     12.42%     61.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181382342     38.92%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 93791115     20.14%     20.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132693411     28.49%     48.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57855471     12.42%     61.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                181375011     38.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            466043328                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.375010                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.567387                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32400238                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             117626282                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 286962359                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22072426                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6982023                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24050963                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496269                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              715816443                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29997814                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6982023                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63475472                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                54498348                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40339589                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276580199                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24167697                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686605984                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13334781                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9429797                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2386503                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1670701                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1903283                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831017415                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3019232506                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        723934620                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            465715008                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.375274                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.568473                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32367511                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             117249871                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 287084329                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22031549                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6981748                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             24050134                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                496459                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              715800999                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              30008433                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6981748                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63425626                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                54212557                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40336788                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276681526                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24076763                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              686589929                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13340569                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9410638                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2384158                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1669115                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1841927                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           831018421                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3019159141                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        723918647                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                176893664                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544707                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1534925                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42378773                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143528821                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67986057                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12870746                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11400164                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668175203                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2978333                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610240343                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5850286                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123802591                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319329527                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            701                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     466043328                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.309407                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.101734                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                176894670                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1544698                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1534992                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  42289780                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            143526215                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67981217                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12855514                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11197113                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  668159255                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2978326                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 610231748                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5860169                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       123786636                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    319274742                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            694                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     465715008                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.310312                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101358                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           148928880     31.96%     31.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101192205     21.71%     53.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145640431     31.25%     84.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63360456     13.60%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6920872      1.49%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 484      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           148574576     31.90%     31.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           101171602     21.72%     53.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145766544     31.30%     84.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63282576     13.59%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6919220      1.49%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 490      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       466043328                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       465715008                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71964986     53.01%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44551194     32.82%     85.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19229314     14.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71921517     52.96%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44556516     32.81%     85.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19328890     14.23%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413153889     67.70%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               351748      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413144323     67.70%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               351745      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
@@ -560,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134217118     21.99%     89.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62517585     10.24%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            134209580     21.99%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62526097     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610240343                       # Type of FU issued
-system.cpu.iq.rate                           1.306963                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135745524                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222446                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1828119531                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         794984388                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    594979068                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              610231748                       # Type of FU issued
+system.cpu.iq.rate                           1.307923                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135806953                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222550                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1827845333                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         794952356                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594966802                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              745985690                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              746038524                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7282878                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          7273046                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27644065                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25657                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        28996                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11125580                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27641459                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25471                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        28891                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11120740                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       225352                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         19393                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225190                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22470                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6982023                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                23078591                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                913703                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672641346                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6981748                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                23001930                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                919984                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           672625014                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143528821                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67986057                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1489791                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 257861                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                519542                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          28996                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3822175                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3731272                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7553447                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599393385                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129576774                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10846958                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             143526215                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67981217                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1489784                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 258650                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                525178                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          28891                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3821630                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3731398                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7553028                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             599382547                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129570228                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10849201                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487810                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190521112                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131377011                       # Number of branches executed
-system.cpu.iew.exec_stores                   60944338                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.283732                       # Inst execution rate
-system.cpu.iew.wb_sent                      596274130                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     594979084                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349911288                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570684699                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1487433                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190523509                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131370037                       # Number of branches executed
+system.cpu.iew.exec_stores                   60953281                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.284670                       # Inst execution rate
+system.cpu.iew.wb_sent                      596261681                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594966818                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349901968                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 570648646                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.274278                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613143                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.275205                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.613165                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110037784                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       110016162                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6955664                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    448925828                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.222239                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.888253                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6955495                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    448601420                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.223123                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.887905                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    219983984     49.00%     49.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116251312     25.90%     74.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43736792      9.74%     84.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23204110      5.17%     89.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11645207      2.59%     92.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7768175      1.73%     94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8255090      1.84%     95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4243904      0.95%     96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13837254      3.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    219539851     48.94%     48.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116349885     25.94%     74.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43748468      9.75%     84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23302371      5.19%     89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11552802      2.58%     92.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7777273      1.73%     94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8275373      1.84%     95.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4252092      0.95%     96.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13803305      3.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    448925828                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    448601420                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
 system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -683,380 +684,386 @@ system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13837254                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1093814049                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334612597                       # The number of ROB writes
-system.cpu.timesIdled                           13893                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          871474                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13803305                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1093501968                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1334565325                       # The number of ROB writes
+system.cpu.timesIdled                           13884                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          850529                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
 system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.924149                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.924149                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.082077                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.082077                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611066187                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328122868                       # number of integer regfile writes
+system.cpu.cpi                               0.923457                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.923457                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.082887                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.082887                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                611072880                       # number of integer regfile reads
+system.cpu.int_regfile_writes               328111730                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170174557                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376546263                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217961585                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2170116632                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376537008                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217962216                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2821455                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.631544                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169406374                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2821967                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.031309                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         498452500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.631544                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999280                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999280                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2820796                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.631791                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           169351038                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2821308                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             60.025718                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         498038000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.631791                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999281                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999281                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356233951                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356233951                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114665404                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114665404                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51761034                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51761034                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         356237372                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        356237372                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114646487                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114646487                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51724617                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51724617                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488559                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488559                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166426438                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166426438                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166429221                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166429221                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4821321                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4821321                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2478272                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2478272                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     166371104                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        166371104                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    166373887                       # number of overall hits
+system.cpu.dcache.overall_hits::total       166373887                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4842277                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4842277                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2514689                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2514689                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7299593                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7299593                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7299605                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7299605                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  56428314397                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  56428314397                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18848897160                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18848897160                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1043750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      1043750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  75277211557                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  75277211557                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  75277211557                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  75277211557                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119486725                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119486725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      7356966                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7356966                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7356978                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7356978                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  56244825000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  56244825000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18846227941                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18846227941                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1242500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1242500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  75091052941                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  75091052941                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  75091052941                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  75091052941                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119488764                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119488764                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173726031                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173726031                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173728826                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173728826                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040350                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040350                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045691                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.045691                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    173728070                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173728070                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173730865                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173730865                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040525                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040525                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046363                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046363                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042018                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042018                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042017                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042017                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11703.911521                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11703.911521                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7605.661187                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7605.661187                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15814.393939                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15814.393939                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10312.521747                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10312.521747                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10312.504794                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10312.504794                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           28                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       711137                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          220355                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.333333                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     3.227233                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042348                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042348                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042347                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042347                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7494.456746                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7494.456746                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10206.796245                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10206.779596                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       911242                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221024                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.122819                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2352760                       # number of writebacks
-system.cpu.dcache.writebacks::total           2352760                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2518936                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2518936                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1958671                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1958671                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2356243                       # number of writebacks
+system.cpu.dcache.writebacks::total           2356243                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2540565                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2540565                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995076                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1995076                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4477607                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4477607                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4477607                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4477607                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2302385                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2302385                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519601                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519601                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4535641                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4535641                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4535641                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4535641                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301712                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2301712                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519613                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519613                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2821986                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2821986                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2821996                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2821996                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27643726875                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27643726875                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4325979851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4325979851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       667500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       667500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31969706726                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  31969706726                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31970374226                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31970374226                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019269                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019269                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2821325                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2821325                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2821335                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2821335                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28710026000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28710026000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4575255494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4575255494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       657000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       657000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33285281494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33285281494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  33285938494                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  33285938494                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019263                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019263                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009580                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009580                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016244                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.016244                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12006.561403                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12006.561403                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8325.580303                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8325.580303                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        66750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        66750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11328.797069                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11328.797069                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11328.993459                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11328.993459                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016240                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016240                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8805.121300                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8805.121300                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        65700                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        65700                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73478                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.210203                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236647479                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73990                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3198.371118                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      115019212250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.210203                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910567                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910567                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             73477                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.193561                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           236634038                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             73989                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3198.232683                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      114977932500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.193561                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910534                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910534                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4           16                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473533098                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473533098                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236647479                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236647479                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236647479                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236647479                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236647479                       # number of overall hits
-system.cpu.icache.overall_hits::total       236647479                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        82060                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         82060                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        82060                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          82060                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        82060                       # number of overall misses
-system.cpu.icache.overall_misses::total         82060                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1575366023                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1575366023                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1575366023                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1575366023                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1575366023                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1575366023                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236729539                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236729539                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236729539                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236729539                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236729539                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236729539                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000347                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000347                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000347                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000347                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000347                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000347                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19197.733646                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19197.733646                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19197.733646                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19197.733646                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       189178                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           92                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6697                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         473507120                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        473507120                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    236634038                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       236634038                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     236634038                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        236634038                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    236634038                       # number of overall hits
+system.cpu.icache.overall_hits::total       236634038                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        82514                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         82514                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        82514                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          82514                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        82514                       # number of overall misses
+system.cpu.icache.overall_misses::total         82514                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1544948153                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1544948153                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1544948153                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1544948153                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1544948153                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1544948153                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    236716552                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    236716552                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    236716552                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    236716552                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    236716552                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    236716552                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000349                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000349                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000349                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000349                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000349                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000349                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18723.466963                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18723.466963                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       193180                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              6947                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.248171                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           23                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    27.807687                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    23.750000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8039                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         8039                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         8039                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         8039                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         8039                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         8039                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74021                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        74021                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        74021                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        74021                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        74021                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        74021                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1246042756                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1246042756                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1246042756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1246042756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1246042756                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1246042756                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8497                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         8497                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         8497                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         8497                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         8497                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         8497                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74017                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        74017                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        74017                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        74017                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        74017                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        74017                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1266772756                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1266772756                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1266772756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1266772756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1266772756                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1266772756                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16833.638508                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8513000                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8515433                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          981                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8510429                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8512950                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         1055                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743879                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           401084                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15418.862546                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4557178                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           417421                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.917462                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      34596581000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8463.110256                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   474.072074                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4920.608759                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1561.071458                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.516547                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.028935                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300330                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.095280                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.941093                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         1053                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15284                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfSpanPage       742850                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           400878                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15418.113154                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5066482                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           417216                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.143547                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      34592827000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  8451.219479                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   476.205325                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4934.937237                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1555.751112                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.515822                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.029065                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.301205                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.094956                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.941047                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         1092                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15246                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           24                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          767                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1548                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10003                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3375                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.064270                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.932861                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         84919237                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        84919237                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        63177                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      2155522                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2218699                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2352760                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2352760                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           27                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           27                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       516754                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       516754                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        63177                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2672276                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2735453                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        63177                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2672276                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2735453                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        10810                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       144544                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       155354                       # number of ReadReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           37                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          235                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          819                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1560                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9946                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3385                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.066650                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.930542                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         93192221                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        93192221                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2356243                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2356243                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           25                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           25                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       516767                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       516767                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        63301                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        63301                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2154697                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      2154697                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        63301                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2671464                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2734765                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        63301                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2671464                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2734765                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         5147                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         5147                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        10810                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       149691                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        160501                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        10810                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       149691                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       160501                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    797246429                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11231476587                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  12028723016                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    470778109                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    470778109                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    797246429                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11702254696                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12499501125                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    797246429                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11702254696                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12499501125                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        73987                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      2300066                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2374053                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2352760                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2352760                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           29                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           29                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       521901                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       521901                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        73987                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2821967                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2895954                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        73987                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2821967                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2895954                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.146107                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.062843                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.065438                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.068966                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.068966                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009862                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.009862                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.146107                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.053045                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.055422                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.146107                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.053045                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.055422                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73750.825994                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77702.821196                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77427.829448                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91466.506509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91466.506509                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77878.026461                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77878.026461                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    460413000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    460413000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    779781500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    779781500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11147875000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  11147875000                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::total  12388069500                       # number of overall miss cycles
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+system.cpu.l2cache.Writeback_accesses::total      2356243                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           27                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           27                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.074074                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.074074                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009972                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009972                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.144396                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.062905                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.062905                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.144396                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.053112                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.055444                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.144396                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.053112                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88455.907781                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88455.907781                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72992.745483                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72992.745483                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77073.783696                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77073.783696                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72992.745483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77469.154587                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77171.251565                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72992.745483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77469.154587                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77171.251565                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1065,141 +1072,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292269                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292269                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         4161                       # number of ReadReq MSHR hits
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-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1493                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1493                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks       292277                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292277                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1529                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1529                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            8                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
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+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4235                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5654                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5654                       # number of overall MSHR hits
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 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3654                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   9683951989                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18994026058                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        28002                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        28002                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.061034                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063682                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  19117391245                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  19117391245                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        33000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        33000                       # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    715179500                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10269035500                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total  30101606245                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.068966                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.068966                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007001                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007001                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.053467                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.074074                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.074074                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007043                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007043                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.144288                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.144288                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.061063                       # mshr miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::total     0.053451                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.051069                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.148473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68982.369582                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68715.208586                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69036.048362                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78076.288451                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78076.288451                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68936.117955                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69000.061925                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.148406                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2374087                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2374086                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2352760                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       317092                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       521901                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       521901                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       148007                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7996752                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8144759                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4735104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331182528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          335917632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      317126                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5565869                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.056971                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.231787                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       2373352                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2648520                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       622852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       320716                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       521972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       521972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        74017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299336                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220623                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440541                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8661164                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4734912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331363264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          336098176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      721627                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6511219                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.110823                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.313913                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5248777     94.30%     94.30% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             317092      5.70%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5789625     88.92%     88.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             721594     11.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5565869                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4977148500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     112866029                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6511219                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5251055500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     111049948                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4256213768                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4231992466                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              408465                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408465                       # Transaction distribution
-system.membus.trans_dist::Writeback            292269                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408324                       # Transaction distribution
+system.membus.trans_dist::Writeback            292277                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           103036                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3653                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3653                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1116511                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1116511                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45080768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45080768                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              3675                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3675                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        408324                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1219317                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1219317                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45073664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45073664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            704390                       # Request fanout histogram
+system.membus.snoop_fanout::samples            807315                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  704390    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  807315    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              704390                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2099926272                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              807315                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2175050688                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2178828981                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2177979128                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 5ab6bd474..7568a8b98 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.707538                       # Number of seconds simulated
-sim_ticks                                707538047500                       # Number of ticks simulated
-final_tick                               707538047500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.707533                       # Number of seconds simulated
+sim_ticks                                707533448500                       # Number of ticks simulated
+final_tick                               707533448500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 813114                       # Simulator instruction rate (inst/s)
-host_op_rate                                   880566                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1139256199                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308656                       # Number of bytes of host memory used
-host_seconds                                   621.05                       # Real time elapsed on the host
+host_inst_rate                                1147583                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1242781                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1607870578                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316160                       # Number of bytes of host memory used
+host_seconds                                   440.04                       # Real time elapsed on the host
 sim_insts                                   504986854                       # Number of instructions simulated
 sim_ops                                     546878105                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            177216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8952320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9129536                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       177216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          177216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6140992                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6140992                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2769                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139880                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                142649                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           95953                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                95953                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               250469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12652775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                12903244                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          250469                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             250469                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8679381                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8679381                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8679381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              250469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12652775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               21582625                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            175360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8946752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9122112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       175360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          175360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6146048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6146048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2740                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139793                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                142533                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96032                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96032                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               247847                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12644988                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                12892835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          247847                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             247847                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8686583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8686583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8686583                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              247847                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12644988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21579418                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1415076095                       # number of cpu cycles simulated
+system.cpu.numCycles                       1415066897                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   504986854                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     172745235                       # nu
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1415076094.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1415066896.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         121548302                       # Number of branches fetched
@@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  548695379                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           1134822                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4065.318385                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4065.318183                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       11716394000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318385                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle       11716394500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318183                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data      1138917                       # n
 system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11818699500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11818699500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8868772000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8868772000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20687471500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20687471500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20687471500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20687471500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11817723000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11817723000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8866220000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8866220000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20683943000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20683943000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20683943000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20683943000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18164.160777                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18164.144829                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18161.062659                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18161.046713                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1064905                       # number of writebacks
-system.cpu.dcache.writebacks::total           1064905                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1064880                       # number of writebacks
+system.cpu.dcache.writebacks::total           1064880                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782657                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       782657                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
@@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1138917
 system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10644714000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10644714000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8334382000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8334382000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18979096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18979096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18979149500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18979149500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11035066000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11035066000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8509960000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8509960000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19545026000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  19545026000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19545080000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  19545080000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
@@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
-system.cpu.icache.tags.tagsinuse           983.372130                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           983.369510                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516599856                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             11521                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          44839.845152                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   983.372130                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.480162                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.480162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   983.369510                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.480161                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.480161                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
@@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst        11521                       # n
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    266251500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    266251500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    266251500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    266251500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    266251500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    266251500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    265181000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    265181000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    265181000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    265181000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    265181000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    265181000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    516611377                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    516611377                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    516611377                       # number of demand (read+write) accesses
@@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000022
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23110.103290                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23110.103290                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23017.186008                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23017.186008                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -415,116 +415,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11521
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    248970000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    248970000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    248970000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    248970000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    248970000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    248970000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    253660000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    253660000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    253660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    253660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    253660000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    253660000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           109895                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27249.388101                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1668833                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           141072                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            11.829654                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     338494305500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.672992                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3574.725951                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.713714                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008779                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.831585                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           109779                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27249.065072                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1743796                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           140956                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.371208                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     338493397000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.705162                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3616.355202                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.712433                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008780                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.110362                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.831575                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3656                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3657                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27180                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18220084                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18220084                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8752                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       743572                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         752324                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1064905                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1064905                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       255466                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255466                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8752                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       999038                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1007790                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8752                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       999038                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1007790                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2769                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        39086                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        41855                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       100794                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100794                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2769                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       139880                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        142649                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2769                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       139880                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       142649                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    145553000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2054549000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2200102000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5295729000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5295729000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    145553000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7350278000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7495831000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    145553000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7350278000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7495831000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       794179                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1064905                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1064905                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.tag_accesses         18829920                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18829920                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1064880                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1064880                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       255527                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8781                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8781                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       743598                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       743598                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8781                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       999125                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1007906                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8781                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       999125                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1007906                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       100733                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100733                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2740                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2740                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39060                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        39060                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2740                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       139793                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        142533                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2740                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       139793                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       142533                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5292536500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5292536500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    144147000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    144147000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2053299500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2053299500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    144147000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   7345836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   7489983000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    144147000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   7345836000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   7489983000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      1064880                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1064880                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       356260                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11521                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        11521                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       782658                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       782658                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        11521                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      1138918                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total      1150439                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.240344                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049940                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.052702                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282923                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.282923                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.240344                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.122818                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123995                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.240344                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.122818                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123995                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.185988                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.831397                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.185988                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026022                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.185988                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026022                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.282751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.237827                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.237827                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.049907                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.049907                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.237827                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.122742                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123894                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.237827                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.122742                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123894                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -533,105 +539,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        95953                       # number of writebacks
-system.cpu.l2cache.writebacks::total            95953                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2769                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39086                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        41855                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100794                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100794                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2769                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       139880                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       142649                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2769                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       139880                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       142649                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112178000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1583383500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1695561500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4082164000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4082164000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112178000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5665547500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5777725500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112178000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5665547500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5777725500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049940                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.052702                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282923                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282923                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122818                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123995                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122818                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123995                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        96032                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96032                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          792                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          792                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100733                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100733                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2740                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2740                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39060                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39060                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2740                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       139793                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       142533                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2740                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       139793                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       142533                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4285206500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4285206500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    116747000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    116747000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1662699500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1662699500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    116747000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5947906000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   6064653000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    116747000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5947906000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   6064653000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.237827                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.049907                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.049907                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122742                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123894                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122742                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123894                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         794179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        794179                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1064905                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1160912                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        90016                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       356260                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       356260                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23042                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3342741                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3365783                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11521                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       782658                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32793                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3409234                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3442027                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       737344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141044672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          141782016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2215344                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141043072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          141780416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      109779                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2404828                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.045649                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.208724                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            2215344    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2295049     95.44%     95.44% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             109779      4.56%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2215344                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2172577000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        2404828                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2212404500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      17281500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1708377000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               41855                       # Transaction distribution
-system.membus.trans_dist::ReadResp              41855                       # Transaction distribution
-system.membus.trans_dist::Writeback             95953                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100794                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100794                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       381251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 381251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15270528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15270528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              41800                       # Transaction distribution
+system.membus.trans_dist::Writeback             96032                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            12399                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100733                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100733                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         41800                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393497                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 393497                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15268160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15268160                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            238603                       # Request fanout histogram
+system.membus.snoop_fanout::samples            251058                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  238603    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  251058    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              238603                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           638238328                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              251058                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           643796820                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          719562500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          719009492                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 3384a1591..2dc4a1c77 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.417996                       # Number of seconds simulated
-sim_ticks                                417996021500                       # Number of ticks simulated
-final_tick                               417996021500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.417249                       # Number of seconds simulated
+sim_ticks                                417248608500                       # Number of ticks simulated
+final_tick                               417248608500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  98610                       # Simulator instruction rate (inst/s)
-host_op_rate                                   182341                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49848381                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 430328                       # Number of bytes of host memory used
-host_seconds                                  8385.35                       # Real time elapsed on the host
+host_inst_rate                                  95567                       # Simulator instruction rate (inst/s)
+host_op_rate                                   176715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48224052                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 428536                       # Number of bytes of host memory used
+host_seconds                                  8652.29                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            227200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24536320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24763520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       227200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          227200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18818240                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18818240                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3550                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             383380                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                386930                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          294035                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               294035                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               543546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58699889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59243435                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          543546                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             543546                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45020141                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45020141                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45020141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              543546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58699889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104263576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        386930                       # Number of read requests accepted
-system.physmem.writeReqs                       294035                       # Number of write requests accepted
-system.physmem.readBursts                      386930                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     294035                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24740928                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18817024                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24763520                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18818240                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      353                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            222784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24527040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24749824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       222784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          222784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18883520                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18883520                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3481                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             383235                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386716                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          295055                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               295055                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               533936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58782796                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                59316732                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          533936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             533936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45257239                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45257239                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45257239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              533936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58782796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104573971                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386716                       # Number of read requests accepted
+system.physmem.writeReqs                       295055                       # Number of write requests accepted
+system.physmem.readBursts                      386716                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     295055                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24729280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18881664                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24749824                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18883520                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      321                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         195133                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24110                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26511                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24689                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24586                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23301                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23773                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24463                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24300                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23625                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23952                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24787                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24070                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23353                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22981                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24097                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23979                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18543                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19847                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18947                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18939                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18047                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18457                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18996                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18981                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18548                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18168                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18839                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17728                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17372                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16973                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17820                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17811                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         188421                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24059                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26427                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24735                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24592                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23512                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23783                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24571                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24367                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23708                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23929                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24776                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24016                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23246                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22935                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23871                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23868                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18618                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19926                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18978                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               19008                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18159                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18511                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19142                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19088                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18666                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18203                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18897                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17760                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17400                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16992                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17815                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17863                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    417995980500                       # Total gap between requests
+system.physmem.totGap                    417248585500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  386930                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386716                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 294035                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    381501                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       352                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        43                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 295055                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381306                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4710                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       331                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,48 +144,48 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6571                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                    16924                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17825                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17679                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
@@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147449                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      295.402912                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.387317                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.474139                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54872     37.21%     37.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        39881     27.05%     64.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13729      9.31%     73.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7544      5.12%     78.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5538      3.76%     82.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3897      2.64%     85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3110      2.11%     87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2694      1.83%     89.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16184     10.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147449                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17448                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.155834                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      209.387263                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17435     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            8      0.05%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       147457                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      295.740616                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.463963                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.226581                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54784     37.15%     37.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40098     27.19%     64.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13706      9.29%     73.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7465      5.06%     78.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5444      3.69%     82.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3767      2.55%     84.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3056      2.07%     87.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2830      1.92%     88.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16307     11.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         147457                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17513                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.062525                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      217.476315                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17502     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17448                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17448                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.850986                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.777295                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.658929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17245     98.84%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             147      0.84%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              24      0.14%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              10      0.06%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               5      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               3      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               3      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17513                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17513                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.846114                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.774956                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.557273                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17320     98.90%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             139      0.79%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.18%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               5      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.02%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::88-91               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::236-239             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17448                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4282714250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11531033000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1932885000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11078.55                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::212-215             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17513                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4300099500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11545005750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1931975000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11128.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29828.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          59.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       59.24                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29878.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          59.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.25                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       59.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.26                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.81                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     318033                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215097                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.15                       # Row buffer hit rate for writes
-system.physmem.avgGap                       613828.88                       # Average gap between requests
-system.physmem.pageHitRate                      78.33                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  567967680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  309903000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1526584800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                976607280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            27301026480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63862686000                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           194773803000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             289318578240                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.167087                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   323459791500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13957580000                       # Time in different power states
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     318002                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215948                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.30                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.19                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612006.94                       # Average gap between requests
+system.physmem.pageHitRate                      78.35                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  569698920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  310847625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1529026200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                981072000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            27252204720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63410789430                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           194721715500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             288775354395                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.105150                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   323379971500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13932620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     80574068000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     79931501500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  546278040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  298068375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1488138600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                928098000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            27301026480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61813739205                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           196571124750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             288946473450                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.276862                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   326467583000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13957580000                       # Time in different power states
+system.physmem_1.actEnergy                  544690440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  297202125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1484246400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                930262320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            27252204720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61581182625                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           196326633750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             288416422380                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              691.244901                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   326066613500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13932620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     77566206500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     77244604500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               230262495                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         230262495                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9742888                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131521089                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               128797905                       # Number of BTB hits
+system.cpu.branchPred.lookups               230038764                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         230038764                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9737010                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            131438605                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               128726788                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.929470                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27751403                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1472504                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.936818                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                27748214                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1467706                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        835992044                       # number of cpu cycles simulated
+system.cpu.numCycles                        834497218                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          185232757                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1269385486                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   230262495                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          156549308                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     639500926                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                20224879                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        485                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles               100878                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        834249                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles         1640                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 179526470                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2741098                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       7                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          835783416                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.825648                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.381813                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          185109509                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1269285801                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   230038764                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          156475002                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     638168020                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                20207441                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        514                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                99542                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        817516                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         1330                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           56                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 179424674                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2717056                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          834300207                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.829871                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.382747                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                428043161     51.21%     51.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 33828750      4.05%     55.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 32944896      3.94%     59.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 33232373      3.98%     63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 27262474      3.26%     66.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 27644327      3.31%     69.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 36950250      4.42%     74.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 33776724      4.04%     78.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                182100461     21.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                426804407     51.16%     51.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 33711236      4.04%     55.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 32817404      3.93%     59.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33341418      4.00%     63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 27188546      3.26%     66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 27662073      3.32%     69.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 36987842      4.43%     74.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 33698291      4.04%     78.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                182088990     21.83%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            835783416                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.275436                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.518418                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                127710765                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             376117098                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 240273770                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              81569344                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10112439                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2225700133                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               10112439                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                159685424                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               160601450                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          42674                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 285796855                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             219544574                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2175664077                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                185857                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              136149821                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24262583                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               49140413                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2279803570                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5502723498                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3499975195                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             67752                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            834300207                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.275662                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.521019                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                127532754                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             374895763                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 240450543                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              81317427                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10103720                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2225154931                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               10103720                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                159590885                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               159861387                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          39705                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 285625371                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             219079139                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2175033402                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                169320                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              136042771                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               24241877                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               48673196                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2279253847                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5500789642                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3498971898                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             55892                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                665762716                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3202                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           3008                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 414696821                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            528426075                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           209872279                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         239265917                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         72168406                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2101339198                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               25266                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1827025844                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            429417                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       572375763                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    974716036                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          24714                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     835783416                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.186004                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.072692                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                665212993                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               3161                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2925                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 415266866                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            528334914                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           209874644                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         239338770                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         72144908                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2101019043                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               25133                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1826920514                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            398452                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       572055475                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    973771254                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          24581                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     834300207                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.189764                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.073153                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           256113706     30.64%     30.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           125601677     15.03%     45.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119268677     14.27%     59.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           111065913     13.29%     73.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            92467369     11.06%     84.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            61706105      7.38%     91.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            43038473      5.15%     96.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            19113733      2.29%     99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7407763      0.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           254789239     30.54%     30.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           125577373     15.05%     45.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           119153367     14.28%     59.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           111141032     13.32%     73.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            92244378     11.06%     84.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            61717114      7.40%     91.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            43107761      5.17%     96.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            19155881      2.30%     99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7414062      0.89%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       835783416                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       834300207                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11312018     42.37%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12328079     46.18%     88.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3055344     11.45%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11334405     42.48%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12275528     46.01%     88.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3069676     11.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2717945      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1211291441     66.30%     66.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               390219      0.02%     66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3881058      0.21%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 119      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2718617      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1211210104     66.30%     66.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               389740      0.02%     66.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3881078      0.21%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 127      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 36      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 409      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   2      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 27      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                 416      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.68% # Type of FU issued
@@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.68% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            435052343     23.81%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           173692274      9.51%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            435004125     23.81%     90.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           173716278      9.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1827025844                       # Type of FU issued
-system.cpu.iq.rate                           2.185458                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26695441                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014611                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4516927324                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2674001021                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1796885315                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               32638                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              71794                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         7253                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1850988135                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   15205                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        185719617                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1826920514                       # Type of FU issued
+system.cpu.iq.rate                           2.189247                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    26679609                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014604                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4515187521                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2673359658                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1796857140                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               31775                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              70770                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         6885                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1850866868                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   14638                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        185770181                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    144326663                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       210089                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       386690                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     60712093                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    144235066                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       213448                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       384677                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     60714458                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19150                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1058                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19450                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           994                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10112439                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               107482997                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6407343                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2101364464                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            396756                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             528428820                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            209872279                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               7401                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1872023                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3639843                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         386690                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5742846                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4583278                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10326124                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1805593119                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             428868135                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          21432725                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               10103720                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               107027275                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6171947                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2101044176                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            397040                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             528337223                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            209874644                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               7154                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1885059                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3390398                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         384677                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5738634                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4563911                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10302545                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1805509782                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             428792858                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          21410732                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    598999412                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                171793179                       # Number of branches executed
-system.cpu.iew.exec_stores                  170131277                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.159821                       # Inst execution rate
-system.cpu.iew.wb_sent                     1802187162                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1796892568                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1367992688                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2090178306                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    598991015                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                171766085                       # Number of branches executed
+system.cpu.iew.exec_stores                  170198157                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.163590                       # Inst execution rate
+system.cpu.iew.wb_sent                     1802110409                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1796864025                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1368049337                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2090115063                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.149413                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.654486                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.153229                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.654533                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       572454923                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       572135204                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9832210                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    758082487                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.016916                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.546878                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9825001                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    756651956                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.020729                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.548081                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    289327383     38.17%     38.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    175257093     23.12%     61.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     57420140      7.57%     68.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86252758     11.38%     80.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     27155131      3.58%     83.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27117110      3.58%     87.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9822533      1.30%     88.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8850930      1.17%     89.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     76879409     10.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    287953386     38.06%     38.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    175292333     23.17%     61.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57344837      7.58%     68.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     86221937     11.40%     80.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     27113369      3.58%     83.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27107052      3.58%     87.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9811804      1.30%     88.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8976581      1.19%     89.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     76830657     10.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    758082487                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    756651956                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -577,338 +579,344 @@ system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              76879409                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2782646702                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4280772798                       # The number of ROB writes
-system.cpu.timesIdled                            2318                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          208628                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              76830657                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2780945204                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4280083493                       # The number of ROB writes
+system.cpu.timesIdled                            2292                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          197011                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.011023                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.011023                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.989097                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.989097                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2762036439                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1465125360                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      7563                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      476                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 600921582                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                409666959                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               990189445                       # number of misc regfile reads
+system.cpu.cpi                               1.009216                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.009216                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.990869                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.990869                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2762017076                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1465005269                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      7183                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      481                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 600929280                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                409654003                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               990121594                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2534281                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.998981                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           387677401                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2538377                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            152.726487                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1688557250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.998981                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998047                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998047                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2534273                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.021333                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           387553004                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2538369                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            152.677961                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1679458500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.021333                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998052                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          873                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3167                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3168                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         784481905                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        784481905                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    239023256                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       239023256                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148173502                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148173502                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     387196758                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        387196758                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    387196758                       # number of overall hits
-system.cpu.dcache.overall_hits::total       387196758                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2788306                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2788306                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       986700                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       986700                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3775006                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3775006                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3775006                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3775006                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  60089695608                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  60089695608                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  31307364104                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  31307364104                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  91397059712                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  91397059712                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  91397059712                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  91397059712                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    241811562                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    241811562                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         784232137                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        784232137                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    238902536                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       238902536                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148180257                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148180257                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     387082793                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        387082793                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    387082793                       # number of overall hits
+system.cpu.dcache.overall_hits::total       387082793                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2784146                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2784146                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       979945                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       979945                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3764091                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3764091                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3764091                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3764091                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  59451413500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  59451413500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  30841040499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  30841040499                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  90292453999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  90292453999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  90292453999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  90292453999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    241686682                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    241686682                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    390971764                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    390971764                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    390971764                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    390971764                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011531                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011531                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006615                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006615                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009655                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009655                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009655                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009655                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24211.103164                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24211.103164                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        10735                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           46                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1081                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.930620                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     9.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    390846884                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    390846884                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    390846884                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    390846884                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011520                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011520                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006570                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006570                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009631                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009631                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23987.850984                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23987.850984                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        10871                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           28                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1128                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.637411                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets            7                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2332980                       # number of writebacks
-system.cpu.dcache.writebacks::total           2332980                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1021252                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1021252                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18400                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18400                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1039652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1039652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1039652                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1039652                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767054                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1767054                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       968300                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       968300                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2735354                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2735354                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2735354                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2735354                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32779677502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  32779677502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29519299643                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  29519299643                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62298977145                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  62298977145                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62298977145                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  62298977145                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007308                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007308                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006492                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006492                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006996                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006996                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006996                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006996                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2332718                       # number of writebacks
+system.cpu.dcache.writebacks::total           2332718                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1016180                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1016180                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19269                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        19269                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1035449                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1035449                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1035449                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1035449                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767966                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1767966                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       960676                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       960676                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2728642                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2728642                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2728642                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2728642                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33608501500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33608501500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29628930000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  29628930000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63237431500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  63237431500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63237431500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  63237431500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007315                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007315                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006441                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006441                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006981                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006981                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006981                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006981                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30841.751017                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23175.422609                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23175.422609                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23175.422609                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23175.422609                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              7107                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1054.726418                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           179314504                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8709                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          20589.562981                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6996                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1051.094157                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           179219973                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8606                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          20825.002673                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1054.726418                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.515003                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.515003                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1602                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1051.094157                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.513230                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.513230                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1610                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          330                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1149                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.782227                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         359258778                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        359258778                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    179317997                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       179317997                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     179317997                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        179317997                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    179317997                       # number of overall hits
-system.cpu.icache.overall_hits::total       179317997                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       208472                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        208472                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       208472                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         208472                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       208472                       # number of overall misses
-system.cpu.icache.overall_misses::total        208472                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1336227738                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1336227738                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1336227738                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1336227738                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1336227738                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1336227738                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    179526469                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    179526469                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    179526469                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    179526469                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    179526469                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    179526469                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001161                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001161                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001161                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001161                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001161                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001161                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6409.626895                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6409.626895                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6409.626895                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6409.626895                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6409.626895                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6409.626895                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1217                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          319                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1167                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.786133                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         359048380                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        359048380                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    179223042                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       179223042                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     179223042                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        179223042                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    179223042                       # number of overall hits
+system.cpu.icache.overall_hits::total       179223042                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       201632                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        201632                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       201632                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         201632                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       201632                       # number of overall misses
+system.cpu.icache.overall_misses::total        201632                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1282836497                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1282836497                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1282836497                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1282836497                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1282836497                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1282836497                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    179424674                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    179424674                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    179424674                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    179424674                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    179424674                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    179424674                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001124                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001124                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001124                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001124                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001124                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001124                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6362.266391                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6362.266391                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6362.266391                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6362.266391                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6362.266391                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6362.266391                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          972                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    81.133333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    60.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2630                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2630                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2630                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2630                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2630                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2630                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       205842                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       205842                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       205842                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       205842                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       205842                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       205842                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    900667759                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    900667759                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    900667759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    900667759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    900667759                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    900667759                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001147                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001147                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001147                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001147                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001147                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001147                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4375.529576                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4375.529576                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4375.529576                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4375.529576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4375.529576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4375.529576                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2599                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2599                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2599                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2599                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2599                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2599                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       199033                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       199033                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       199033                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       199033                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       199033                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       199033                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    971187998                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    971187998                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    971187998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    971187998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    971187998                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    971187998                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001109                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001109                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001109                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001109                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001109                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001109                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4879.532530                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4879.532530                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4879.532530                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  4879.532530                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4879.532530                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  4879.532530                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           354249                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29619.496841                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3704141                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           386604                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.581228                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     197893481000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   254.372713                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8282.624354                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.643387                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007763                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.252766                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.903915                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          245                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13370                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18660                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41777056                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41777056                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         5192                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1590453                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1595645                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2332980                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2332980                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1881                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1881                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564507                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564507                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         5192                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2154960                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2160152                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         5192                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2154960                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2160152                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3552                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       176400                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       179952                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       195096                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       195096                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       207017                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       207017                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3552                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       383417                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        386969                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3552                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       383417                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       386969                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    294540500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  14275679000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  14570219500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13220077                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     13220077                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16430030463                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16430030463                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    294540500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30705709463                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  31000249963                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    294540500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30705709463                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  31000249963                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         8744                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1766853                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1775597                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2332980                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2332980                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       196977                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       196977                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771524                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771524                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8744                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2538377                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2547121                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8744                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2538377                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2547121                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.406221                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099839                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.101347                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990451                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990451                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268322                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268322                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.406221                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.151048                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151924                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.406221                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.151048                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151924                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    67.761907                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    67.761907                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           354039                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29616.478826                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3899597                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           386397                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.092203                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     197715227000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20954.813586                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   251.117391                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8410.547849                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.639490                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007663                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.256670                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.903823                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32358                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13367                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18661                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987488                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43296958                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43296958                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2332718                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2332718                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1894                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1894                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       564156                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       564156                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5160                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         5160                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590936                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1590936                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         5160                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2155092                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2160252                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         5160                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2155092                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2160252                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       188379                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       188379                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206660                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206660                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3483                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3483                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176617                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       176617                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3483                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       383277                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        386760                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3483                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       383277                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       386760                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13128500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     13128500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16382009500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16382009500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    282985000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    282985000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14212128500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  14212128500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    282985000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30594138000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30877123000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    282985000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30594138000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30877123000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2332718                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2332718                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       190273                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       190273                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       770816                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       770816                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8643                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8643                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1767553                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1767553                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8643                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2538369                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2547012                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8643                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2538369                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2547012                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990046                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990046                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268105                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.268105                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.402985                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.402985                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099922                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099922                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.402985                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150993                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151849                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.402985                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150993                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151849                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    69.691951                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    69.691951                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79270.345011                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79270.345011                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81247.487798                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81247.487798                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80468.632691                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80468.632691                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81247.487798                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79822.525223                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79835.357845                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81247.487798                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79822.525223                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79835.357845                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -917,125 +925,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       294035                       # number of writebacks
-system.cpu.l2cache.writebacks::total           294035                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks       295055                       # number of writebacks
+system.cpu.l2cache.writebacks::total           295055                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3551                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       176400                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       179951                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       195096                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       195096                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       207017                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       207017                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3551                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       383417                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       386968                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3551                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       383417                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       386968                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    250130000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  12068381000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  12318511000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3521803787                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3521803787                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13841306537                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13841306537                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    250130000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25909687537                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26159817537                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    250130000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25909687537                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26159817537                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.406107                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099839                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101347                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990451                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990451                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268322                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268322                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.406107                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151048                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151924                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.406107                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151048                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151924                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575                       # average overall mshr miss latency
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1999                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1999                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       188379                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       188379                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206660                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206660                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3482                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3482                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176617                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176617                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3482                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       383277                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386759                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3482                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       383277                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386759                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3964257964                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3964257964                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14315409500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14315409500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    248098000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    248098000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12445958500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12445958500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    248098000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26761368000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27009466000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    248098000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26761368000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27009466000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990046                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990046                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268105                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268105                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.402869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.402869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099922                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099922                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.402869                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150993                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151848                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.402869                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150993                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151848                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1972695                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1972693                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2332980                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       196977                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       196977                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771524                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       214584                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7803688                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8018272                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       559488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311766848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312326336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      197098                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5274176                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1966585                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2627773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       256159                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       190273                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       190273                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       770816                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       770816                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       199033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1767553                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       214213                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7980639                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8194852                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       553088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311749568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312302656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      544429                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5822983                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.060800                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.238964                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5274176    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5468944     93.92%     93.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             354039      6.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5274176                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4998685151                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5822983                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5095186894                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     309293990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     298551493                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3989146355                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              179950                       # Transaction distribution
-system.membus.trans_dist::ReadResp             179949                       # Transaction distribution
-system.membus.trans_dist::Writeback            294035                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           195133                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          195133                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206980                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206980                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1458160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1458160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1458160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43581696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43581696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43581696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    3902690569                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             180098                       # Transaction distribution
+system.membus.trans_dist::Writeback            295055                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57423                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           188421                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          188421                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206618                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206618                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        180098                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1502752                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1502752                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1502752                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43633344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43633344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43633344                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            876098                       # Request fanout histogram
+system.membus.snoop_fanout::samples            927615                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  876098    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  927615    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              876098                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2246796268                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              927615                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2233739536                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2437948408                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2422494891                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index d2da1780a..7244d6f89 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.647873                       # Number of seconds simulated
-sim_ticks                                1647872738500                       # Number of ticks simulated
-final_tick                               1647872738500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.647861                       # Number of seconds simulated
+sim_ticks                                1647861059500                       # Number of ticks simulated
+final_tick                               1647861059500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 720688                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1332632                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1436248802                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323576                       # Number of bytes of host memory used
-host_seconds                                  1147.35                       # Real time elapsed on the host
+host_inst_rate                                 708384                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1309882                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1411719986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323600                       # Number of bytes of host memory used
+host_seconds                                  1167.27                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24272448                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24393152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       120704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          120704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18706304                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18706304                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1886                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             379257                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                381143                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292286                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292286                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                73248                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             14729565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14802813                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           73248                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              73248                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11351789                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11351789                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11351789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               73248                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            14729565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               26154602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            120384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24254848                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24375232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       120384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          120384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18763136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18763136                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1881                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             378982                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380863                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293174                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293174                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                73055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14718989                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14792043                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           73055                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              73055                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11386358                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11386358                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11386358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               73055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            14718989                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               26178401                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       3295745477                       # number of cpu cycles simulated
+system.cpu.numCycles                       3295722119                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   826877110                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                     533262343                       # nu
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               3295745476.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               3295722118.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
@@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           2514362                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4086.415780                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4086.415711                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           530743930                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            210.741624                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        8211725000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4086.415780                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle        8211725500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4086.415711                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data      2518458                       # n
 system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29704183000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29704183000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18964598500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18964598500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  48668781500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  48668781500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  48668781500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  48668781500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29707934500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29707934500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18949311500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18949311500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  48657246000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  48657246000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  48657246000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  48657246000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    384102186                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    384102186                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
@@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_miss_rate::total     0.004723                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.004723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19324.833489                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19324.833489                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19320.253107                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19320.253107                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2323523                       # number of writebacks
-system.cpu.dcache.writebacks::total           2323523                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      2323227                       # number of writebacks
+system.cpu.dcache.writebacks::total           2323227                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
@@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2518458
 system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27113062000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27113062000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17778032500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17778032500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  44891094500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  44891094500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  44891094500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  44891094500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27980520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27980520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18158267500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18158267500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46138788000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  46138788000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46138788000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  46138788000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
@@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_mshr_miss_rate::total     0.004723                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.004723                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1253                       # number of replacements
-system.cpu.icache.tags.tagsinuse           881.356484                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           881.348726                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068344251                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              2814                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          379653.251955                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   881.356484                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.430350                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.430350                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   881.348726                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.430346                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.430346                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1561                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
@@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst         2814                       # n
 system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
 system.cpu.icache.overall_misses::total          2814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    115798500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    115798500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    115798500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    115798500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    115798500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    115798500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    115655000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    115655000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    115655000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    115655000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    115655000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    115655000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1068347065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1068347065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1068347065                       # number of demand (read+write) accesses
@@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000003
 system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41150.852878                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41150.852878                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41099.857854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41099.857854                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -276,116 +276,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         2814
 system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    111577500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    111577500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    111577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    111577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    111577500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    111577500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    112841000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    112841000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    112841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    112841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    112841000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    112841000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           348459                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29286.402293                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3655011                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           380814                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.597890                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     755936423000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.758524                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8105.344842                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.642129                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004265                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.247355                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.893750                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.tagsinuse        29285.938694                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3846845                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           380537                       # Sample count of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle     755943397500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.data  8218.320163                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8220                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        24069                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39930218                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39930218                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::total        1555776                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2323523                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2323523                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       584353                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     99019500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   9059744000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10851282000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10851282000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  19911026000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.Writeback_accesses::total      2323523                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.tag_accesses         41466677                       # Number of tag accesses
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 system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst         2814                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      2518458                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.670220                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099898                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.100826                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.261289                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.261289                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.670220                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150591                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151171                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.670220                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150591                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151171                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.260829                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.260829                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.668443                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.668443                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099950                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099950                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.668443                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150482                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151060                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.668443                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150482                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151060                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -394,107 +400,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292286                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292286                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1886                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       172566                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       174452                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206691                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206691                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1886                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       379257                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       381143                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1886                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       379257                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       381143                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     76387000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6988941000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7065328000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8370987500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8370987500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     76387000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15359928500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15436315500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     76387000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15359928500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15436315500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099898                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.100826                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.261289                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.261289                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150591                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151171                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151171                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293174                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293174                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          275                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          275                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206327                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206327                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1881                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1881                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       172655                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       172655                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1881                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       378982                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       380863                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1881                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       378982                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       380863                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8768903000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8768903000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     80007000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     80007000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7337878500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7337878500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     80007000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16106781500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  16186788500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     80007000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16106781500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  16186788500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.260829                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.260829                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.668443                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099950                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099950                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150482                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151060                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150482                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151060                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1730228                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       1730228                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2323523                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2616401                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       247396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       791044                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       791044                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         5628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7360439                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7366067                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         2814                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1727414                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         6881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7551278                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7558159                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       180096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    309886784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          310066880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4844795                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    309867840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          310047936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      348182                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5385069                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.064657                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.245920                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4844795    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5036887     93.53%     93.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             348182      6.47%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4844795                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4745920500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5385069                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4841670500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       4221000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3777687000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              174452                       # Transaction distribution
-system.membus.trans_dist::ReadResp             174452                       # Transaction distribution
-system.membus.trans_dist::Writeback            292286                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206691                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206691                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1054572                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1054572                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1054572                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43099456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43099456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43099456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             174536                       # Transaction distribution
+system.membus.trans_dist::Writeback            293174                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            53553                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206327                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206327                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174536                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1108453                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1108453                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1108453                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43138368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43138368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43138368                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            673429                       # Request fanout histogram
+system.membus.snoop_fanout::samples            727623                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  673429    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  727623    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              673429                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1860874000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              727623                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1900350576                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1905729000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1904342076                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 5e6582f7a..1a7177e69 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.226051                       # Number of seconds simulated
-sim_ticks                                226051212500                       # Number of ticks simulated
-final_tick                               226051212500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.226045                       # Number of seconds simulated
+sim_ticks                                226044973500                       # Number of ticks simulated
+final_tick                               226044973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 313509                       # Simulator instruction rate (inst/s)
-host_op_rate                                   313509                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              177766322                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302576                       # Number of bytes of host memory used
-host_seconds                                  1271.62                       # Real time elapsed on the host
+host_inst_rate                                 304016                       # Simulator instruction rate (inst/s)
+host_op_rate                                   304016                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              172378586                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302856                       # Number of bytes of host memory used
+host_seconds                                  1311.33                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          249344                       # Nu
 system.physmem.num_reads::cpu.inst               3896                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7874                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1103042                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1126258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2229300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1103042                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1103042                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1103042                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1126258                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2229300                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1103073                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1126289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2229362                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1103073                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1103073                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1103073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1126289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2229362                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7874                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7874                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    226051111000                       # Total gap between requests
+system.physmem.totGap                    226044886000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6818                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        82                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6812                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1564                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      321.964194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     193.457187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.645688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            541     34.59%     34.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          357     22.83%     57.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          194     12.40%     69.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          101      6.46%     76.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           65      4.16%     80.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           55      3.52%     83.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           35      2.24%     86.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           34      2.17%     88.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          182     11.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1564                       # Bytes accessed per row activation
-system.physmem.totQLat                       54215500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 201853000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1551                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      323.878788                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     193.961760                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.450478                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            540     34.82%     34.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          341     21.99%     56.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          198     12.77%     69.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          105      6.77%     76.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           68      4.38%     80.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           43      2.77%     83.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      2.13%     85.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           36      2.32%     87.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          187     12.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1551                       # Bytes accessed per row activation
+system.physmem.totQLat                       53691750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 201329250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39370000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6885.38                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6818.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25635.38                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25568.87                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.23                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6308                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6316                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.11                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.21                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28708548.51                       # Average gap between requests
-system.physmem.pageHitRate                      80.11                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6872040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3749625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  34327800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28707757.94                       # Average gap between requests
+system.physmem.pageHitRate                      80.21                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6811560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3716625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  34210800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14764513920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5850636750                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           130498264500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             151158364635                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.692398                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   217093450250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7548320000                       # Time in different power states
+system.physmem_0.refreshEnergy            14764005360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5854324365                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           130490358000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             151153426710                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.693587                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   217080502500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7548060000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1408913500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1414335000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4951800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2701875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  27042600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4914000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2681250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  27011400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14764513920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5592917520                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           130724334000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             151116461715                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.507029                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   217471574500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7548320000                       # Time in different power states
+system.physmem_1.refreshEnergy            14764005360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5569701705                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           130740027000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             151108340715                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.494129                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   217498306250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7548060000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1030789250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       997097750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                46270925                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26727379                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1017826                       # Number of conditional branches incorrect
+system.cpu.branchPred.lookups                46270920                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26727376                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1017825                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups             25620092                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21360644                       # Number of BTB hits
+system.cpu.branchPred.BTBHits                21360645                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.374580                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8341960                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             83.374584                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8341957                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95612151                       # DTB read hits
+system.cpu.dtb.read_hits                     95612152                       # DTB read hits
 system.cpu.dtb.read_misses                        116                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95612267                       # DTB read accesses
-system.cpu.dtb.write_hits                    73605971                       # DTB write hits
+system.cpu.dtb.read_accesses                 95612268                       # DTB read accesses
+system.cpu.dtb.write_hits                    73605970                       # DTB write hits
 system.cpu.dtb.write_misses                       858                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73606829                       # DTB write accesses
+system.cpu.dtb.write_accesses                73606828                       # DTB write accesses
 system.cpu.dtb.data_hits                    169218122                       # DTB hits
 system.cpu.dtb.data_misses                        974                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_accesses                169219096                       # DTB accesses
-system.cpu.itb.fetch_hits                    98739643                       # ITB hits
+system.cpu.itb.fetch_hits                    98739640                       # ITB hits
 system.cpu.itb.fetch_misses                      1232                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98740875                       # ITB accesses
+system.cpu.itb.fetch_accesses                98740872                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,67 +293,67 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        452102425                       # number of cpu cycles simulated
+system.cpu.numCycles                        452089947                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4488157                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4488161                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.134042                       # CPI: cycles per instruction
-system.cpu.ipc                               0.881802                       # IPC: instructions per cycle
-system.cpu.tickCycles                       448265843                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3836582                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.134011                       # CPI: cycles per instruction
+system.cpu.ipc                               0.881826                       # IPC: instructions per cycle
+system.cpu.tickCycles                       448265885                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3824062                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.681680                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168032891                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.715048                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168032888                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40344.031453                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40344.030732                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.681680                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803633                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803633                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.715048                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803641                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803641                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336084169                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336084169                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94518092                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94518092                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73514799                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514799                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     168032891                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168032891                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168032891                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168032891                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         336084171                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336084171                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     94518093                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94518093                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73514795                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514795                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     168032888                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168032888                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168032888                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168032888                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1180                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1180                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5931                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5931                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         7111                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7111                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7111                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7111                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     88098000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     88098000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    432683750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    432683750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    520781750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    520781750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    520781750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    520781750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94519272                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94519272                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         5935                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5935                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         7115                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7115                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7115                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7115                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     87916000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     87916000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    428863500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    428863500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    516779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    516779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    516779500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    516779500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94519273                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94519273                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168040002                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168040002                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168040002                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168040002                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168040003                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168040003                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168040003                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168040003                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
@@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73236.077907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73236.077907                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72632.396346                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72632.396346                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks          654                       # nu
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          211                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2735                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2735                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2946                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2946                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2946                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2946                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2739                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2739                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2950                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2950                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3196                       # number of WriteReq MSHR misses
@@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     69978250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     69978250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    238524000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    238524000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    308502250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    308502250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    308502250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    308502250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     71088500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     71088500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    239432500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    239432500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    310521000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    310521000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    310521000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    310521000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              3197                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1918.668517                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98734468                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1918.682192                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            98734465                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              5175                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          19079.124251                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          19079.123671                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1918.668517                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.936850                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.936850                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1918.682192                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.936857                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.936857                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1281                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         197484461                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        197484461                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98734468                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98734468                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98734468                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98734468                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98734468                       # number of overall hits
-system.cpu.icache.overall_hits::total        98734468                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         197484455                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        197484455                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     98734465                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        98734465                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      98734465                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         98734465                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     98734465                       # number of overall hits
+system.cpu.icache.overall_hits::total        98734465                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         5175                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          5175                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         5175                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           5175                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         5175                       # number of overall misses
 system.cpu.icache.overall_misses::total          5175                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    322926000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    322926000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    322926000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    322926000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    322926000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    322926000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98739643                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98739643                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98739643                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98739643                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98739643                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98739643                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    319209000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    319209000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    319209000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    319209000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    319209000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    319209000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     98739640                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     98739640                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     98739640                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     98739640                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     98739640                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     98739640                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62401.159420                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62401.159420                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61682.898551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61682.898551                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -488,116 +488,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         5175
 system.cpu.icache.demand_mshr_misses::total         5175                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         5175                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         5175                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    313513500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    313513500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    313513500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    313513500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    313513500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    313513500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    314034000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    314034000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    314034000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    314034000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.tags.tagsinuse         4426.539250                       # Cycle average of tags in use
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses            88424                       # Number of tag accesses
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-system.cpu.l2cache.overall_avg_miss_latency::total 75850.742951                       # average overall miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81046.967895                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75164.527721                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 75580.010160                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -606,84 +612,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.demand_mshr_misses::cpu.inst         3896                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           6142                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          6142                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         3314                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10350                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19334                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         5175                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13547                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             22648                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331200                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             639616                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9994                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13308                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               9994    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13308    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9994                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5651000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13308                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7308000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8587500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7762500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7035750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6247999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4737                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3137                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3137                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4737                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15748                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  15748                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       503936                       # Cumulative packet size per connected master and slave (bytes)
@@ -699,9 +711,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7874                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9179500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9183500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           41811750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           41813250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 1cb945d89..be9d713b1 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,57 +1,57 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.069793                       # Number of seconds simulated
-sim_ticks                                 69793219500                       # Number of ticks simulated
-final_tick                                69793219500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.069809                       # Number of seconds simulated
+sim_ticks                                 69809049000                       # Number of ticks simulated
+final_tick                                69809049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 237836                       # Simulator instruction rate (inst/s)
-host_op_rate                                   237836                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44197170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232228                       # Number of bytes of host memory used
-host_seconds                                  1579.13                       # Real time elapsed on the host
+host_inst_rate                                 246384                       # Simulator instruction rate (inst/s)
+host_op_rate                                   246384                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45796096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304152                       # Number of bytes of host memory used
+host_seconds                                  1524.35                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               477248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221440                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3460                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3997                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7457                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3172801                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3665227                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6838028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3172801                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3172801                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3172801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3665227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6838028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7457                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            221504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255680                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               477184                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221504                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3461                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3995                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7456                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3172998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3662562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6835561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3172998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3172998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3172998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3662562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6835561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7456                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7457                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7456                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   477248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   477184                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    477248                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    477184                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 527                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 657                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 455                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 602                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 655                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 454                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 455                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 515                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 522                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 438                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 525                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 439                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 407                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                338                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     69793123000                       # Total gap between requests
+system.physmem.totGap                     69808953500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7457                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7456                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1915                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       898                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4273                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1892                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       906                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       323                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1360                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      348.047059                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     208.039838                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     346.646558                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            428     31.47%     31.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          327     24.04%     55.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          157     11.54%     67.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           92      6.76%     73.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           56      4.12%     77.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           39      2.87%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.43%     83.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           25      1.84%     85.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          203     14.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1360                       # Bytes accessed per row activation
-system.physmem.totQLat                       67335750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 207154500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37285000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9029.87                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1355                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      349.142435                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     207.457712                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.186854                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            436     32.18%     32.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          321     23.69%     55.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          135      9.96%     65.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          103      7.60%     73.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      4.13%     77.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           42      3.10%     80.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           37      2.73%     83.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      2.07%     85.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          197     14.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1355                       # Bytes accessed per row activation
+system.physmem.totQLat                       63176250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 202976250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8473.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27779.87                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27223.21                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.84                       # Average system read bandwidth in MiByte/s
@@ -214,72 +214,72 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6086                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6090                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.68                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9359410.35                       # Average gap between requests
-system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                      9362788.83                       # Average gap between requests
+system.physmem.pageHitRate                      81.68                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                    5828760                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                    3180375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32377800                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                  32370000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4558223280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2111779035                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            40020613500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              46732002750                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.624038                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    66577889000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2330380000                       # Time in different power states
+system.physmem_0.refreshEnergy             4559240400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2097349200                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            40042614750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              46740583485                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.597578                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    66614495250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2330900000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       882777000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       861488750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4430160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2417250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25272000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4399920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2400750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  25256400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4558223280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2013356565                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            40106949000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              46710648255                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.318049                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    66719394750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2330380000                       # Time in different power states
+system.physmem_1.refreshEnergy             4559240400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1988059680                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            40138482750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              46717839900                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.271757                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    66771998750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2330900000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       738657750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       701106250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                51259743                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          29683169                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233682                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             26552604                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23664767                       # Number of BTB hits
+system.cpu.branchPred.lookups                51296431                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          29722668                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1234399                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             27069453                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23684308                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.124091                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9366329                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                317                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             87.494594                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9353372                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                312                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    103795078                       # DTB read hits
-system.cpu.dtb.read_misses                      91880                       # DTB read misses
-system.cpu.dtb.read_acv                         49322                       # DTB read access violations
-system.cpu.dtb.read_accesses                103886958                       # DTB read accesses
-system.cpu.dtb.write_hits                    79431295                       # DTB write hits
-system.cpu.dtb.write_misses                      1540                       # DTB write misses
+system.cpu.dtb.read_hits                    103786850                       # DTB read hits
+system.cpu.dtb.read_misses                      91978                       # DTB read misses
+system.cpu.dtb.read_acv                         49358                       # DTB read access violations
+system.cpu.dtb.read_accesses                103878828                       # DTB read accesses
+system.cpu.dtb.write_hits                    79421845                       # DTB write hits
+system.cpu.dtb.write_misses                      1562                       # DTB write misses
 system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                79432835                       # DTB write accesses
-system.cpu.dtb.data_hits                    183226373                       # DTB hits
-system.cpu.dtb.data_misses                      93420                       # DTB misses
-system.cpu.dtb.data_acv                         49324                       # DTB access violations
-system.cpu.dtb.data_accesses                183319793                       # DTB accesses
-system.cpu.itb.fetch_hits                    51424924                       # ITB hits
-system.cpu.itb.fetch_misses                       367                       # ITB misses
+system.cpu.dtb.write_accesses                79423407                       # DTB write accesses
+system.cpu.dtb.data_hits                    183208695                       # DTB hits
+system.cpu.dtb.data_misses                      93540                       # DTB misses
+system.cpu.dtb.data_acv                         49360                       # DTB access violations
+system.cpu.dtb.data_accesses                183302235                       # DTB accesses
+system.cpu.itb.fetch_hits                    51432488                       # ITB hits
+system.cpu.itb.fetch_misses                       372                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                51425291                       # ITB accesses
+system.cpu.itb.fetch_accesses                51432860                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,106 +293,106 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        139586442                       # number of cpu cycles simulated
+system.cpu.numCycles                        139618100                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           52218190                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      457878359                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    51259743                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33031096                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      85762697                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2573496                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           52215637                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      458041697                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    51296431                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33037680                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      85803922                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2575582                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13442                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           10                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  51424924                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                558112                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          139281263                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.287437                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.344389                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles                  177                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13927                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           49                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  51432488                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                569689                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          139321507                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.287660                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.344182                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58400466     41.93%     41.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4519538      3.24%     45.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7300185      5.24%     50.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5568881      4.00%     54.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11993718      8.61%     63.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  8035210      5.77%     68.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5954127      4.27%     73.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1896980      1.36%     74.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35612158     25.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58400173     41.92%     41.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4522566      3.25%     45.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  7306043      5.24%     50.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5576459      4.00%     54.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 12017776      8.63%     63.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  8032548      5.77%     68.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5948759      4.27%     73.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1886194      1.35%     74.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35630989     25.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            139281263                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367226                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.280250                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45296559                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              16238717                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  71951122                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4512320                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1282545                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9579038                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4257                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              452073358                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 14179                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1282545                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 47196926                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5664651                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         519192                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  74460720                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10157229                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              448418638                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                439172                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2532304                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2861217                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3565763                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           292805975                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             590541853                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        420605547                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         169936305                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            139321507                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367405                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.280676                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45279858                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              16277373                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  71952167                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4528520                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1283589                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9590263                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4245                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              452242919                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 14142                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1283589                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 47190225                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5719256                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         519758                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  74463142                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10145537                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              448534058                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                439648                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2541243                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2902301                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3500431                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           292850852                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             590664412                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        420646005                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         170018406                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 33273646                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37923                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                 33318523                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37911                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            320                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  15988914                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106425467                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            81691000                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12462225                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9670397                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  415046688                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 308                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 407272286                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            487219                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        39472187                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     18379010                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             93                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     139281263                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.924100                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.223091                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                  16086321                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            106433302                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            81699514                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12490023                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9782021                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  415154479                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 307                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 407277518                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            483889                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        39579977                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     18549388                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             92                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     139321507                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.923293                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.222373                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24058662     17.27%     17.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19633951     14.10%     31.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22674806     16.28%     47.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18925755     13.59%     61.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19544360     14.03%     75.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            14234748     10.22%     85.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9653364      6.93%     92.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6204842      4.45%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4350775      3.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24043039     17.26%     17.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19688824     14.13%     31.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22672553     16.27%     47.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18939258     13.59%     61.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19545668     14.03%     75.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            14219061     10.21%     85.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9684319      6.95%     92.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6188357      4.44%     96.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4340428      3.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       139281263                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       139321507                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  264805      1.33%      1.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  265122      1.33%      1.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      1.33% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                148480      0.74%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 91560      0.46%      2.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  2226      0.01%      2.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3500111     17.53%     20.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1672568      8.38%     28.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                151057      0.76%      2.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 93335      0.47%      2.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  3062      0.02%      2.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3506383     17.53%     20.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1668666      8.34%     28.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.44% # attempts to use FU when none available
@@ -414,118 +414,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.44% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9323721     46.69%     75.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4965817     24.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9341831     46.71%     75.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4968318     24.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             153389569     37.66%     37.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128191      0.52%     38.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             153385991     37.66%     37.67% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128232      0.52%     38.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            37431648      9.19%     47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7537641      1.85%     49.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2804878      0.69%     49.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16758896      4.11%     54.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1606846      0.39%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            105464958     25.90%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            80116078     19.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            37448194      9.19%     47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7543709      1.85%     49.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2805732      0.69%     49.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16759263      4.11%     54.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1610357      0.40%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            105461195     25.89%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            80101264     19.67%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              407272286                       # Type of FU issued
-system.cpu.iq.rate                           2.917707                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19969288                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.049032                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          626696170                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         266819247                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    237458259                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           347586172                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          187775636                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    163387975                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              246426590                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               180781403                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19964423                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              407277518                       # Type of FU issued
+system.cpu.iq.rate                           2.917083                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    19997775                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.049101                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          626671270                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         266840013                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237433052                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           347686937                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          187970906                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    163426789                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              246404368                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               180837344                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19931279                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11670980                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       165408                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        76048                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8170271                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     11678815                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       164981                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        76480                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8178785                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       382447                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3767                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       381276                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3827                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1282545                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 4525606                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 90420                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           440059104                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            152527                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106425467                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             81691000                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                308                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   7009                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 82356                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          76048                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1000879                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       421168                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1422047                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             403473304                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             103936308                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3798982                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1283589                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4537578                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                127300                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           440164979                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            164208                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             106433302                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             81699514                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                307                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   6586                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                117247                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          76480                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1004792                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       416739                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1421531                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             403496390                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             103928218                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3781128                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      25012108                       # number of nop insts executed
-system.cpu.iew.exec_refs                    183369178                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46997600                       # Number of branches executed
-system.cpu.iew.exec_stores                   79432870                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.890491                       # Inst execution rate
-system.cpu.iew.wb_sent                      401684713                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     400846234                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 198095133                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 284050882                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      25010193                       # number of nop insts executed
+system.cpu.iew.exec_refs                    183351660                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 47000418                       # Number of branches executed
+system.cpu.iew.exec_stores                   79423442                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.890001                       # Inst execution rate
+system.cpu.iew.wb_sent                      401708524                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     400859841                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 198115569                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 284128842                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.871670                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.697393                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.871117                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.697274                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        41395670                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        41501718                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1229479                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    133482933                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.986633                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.212859                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1230197                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    133512631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.985969                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.212275                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     48683097     36.47%     36.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18109981     13.57%     50.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      9618460      7.21%     57.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8715508      6.53%     63.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6449297      4.83%     68.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4412968      3.31%     71.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5003390      3.75%     75.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2633066      1.97%     77.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     29857166     22.37%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     48674660     36.46%     36.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18127731     13.58%     50.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      9648746      7.23%     57.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8719124      6.53%     63.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6443109      4.83%     68.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4416607      3.31%     71.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5004547      3.75%     75.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2625621      1.97%     77.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29852486     22.36%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    133482933                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    133512631                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,127 +571,127 @@ system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              29857166                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    543683043                       # The number of ROB reads
-system.cpu.rob.rob_writes                   885930772                       # The number of ROB writes
-system.cpu.timesIdled                            3165                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          305179                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              29852486                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    543823469                       # The number of ROB reads
+system.cpu.rob.rob_writes                   886153369                       # The number of ROB writes
+system.cpu.timesIdled                            3159                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          296593                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.371661                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.371661                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.690625                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.690625                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                403591803                       # number of integer regfile reads
-system.cpu.int_regfile_writes               172078772                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 157997982                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                105636085                       # number of floating regfile writes
+system.cpu.cpi                               0.371745                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.371745                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.690015                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.690015                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                403553331                       # number of integer regfile reads
+system.cpu.int_regfile_writes               172072539                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 158043337                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                105673333                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements               806                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3297.136243                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           156944357                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4209                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37287.801616                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               795                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3296.035456                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           156970312                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4197                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37400.598523                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3297.136243                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.804965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.804965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3403                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  3296.035456                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.804696                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.804696                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3119                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.830811                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         313935887                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        313935887                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     83443297                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        83443297                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501051                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501051                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     156944348                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        156944348                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    156944348                       # number of overall hits
-system.cpu.dcache.overall_hits::total       156944348                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1804                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1804                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19678                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19678                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21482                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21482                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21482                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21482                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    122640500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    122640500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1228413709                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1228413709                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1351054209                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1351054209                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1351054209                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1351054209                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     83445101                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     83445101                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3116                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         313987939                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        313987939                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     83469338                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        83469338                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73500964                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73500964                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     156970302                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        156970302                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    156970302                       # number of overall hits
+system.cpu.dcache.overall_hits::total       156970302                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1794                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1794                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19765                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19765                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21559                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21559                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21559                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21559                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    128871000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    128871000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1185279954                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1185279954                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1314150954                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1314150954                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1314150954                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1314150954                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     83471132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     83471132                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            9                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            9                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    156965830                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    156965830                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    156965830                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    156965830                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           10                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           10                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    156991861                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    156991861                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    156991861                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    156991861                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000269                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000137                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000137                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000137                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000137                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62892.384741                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62892.384741                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        51314                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          108                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               737                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60956.025511                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60956.025511                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        49421                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           88                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               747                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.625509                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          108                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.159304                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           88                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          682                       # number of writebacks
-system.cpu.dcache.writebacks::total               682                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          803                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          803                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16470                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16470                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17273                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17273                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17273                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17273                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1001                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1001                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3208                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3208                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4209                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4209                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4209                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4209                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     72824500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     72824500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    253362750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    253362750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    326187250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    326187250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    326187250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    326187250                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          671                       # number of writebacks
+system.cpu.dcache.writebacks::total               671                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          799                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          799                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16563                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16563                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17362                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17362                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17362                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17362                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          995                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          995                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4197                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4197                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4197                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4197                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76593500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     76593500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    246844000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    246844000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    323437500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    323437500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    323437500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    323437500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -700,198 +700,204 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76978.391960                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76978.391960                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77090.568395                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77090.568395                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77063.974267                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77063.974267                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77063.974267                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77063.974267                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2160                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1831.206745                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            51419247                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4087                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12581.171275                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2157                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1832.216020                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            51426803                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4084                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12592.263222                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1831.206745                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894144                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894144                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1832.216020                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894637                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894637                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          289                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1348                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1347                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         102853935                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        102853935                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     51419247                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        51419247                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      51419247                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         51419247                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     51419247                       # number of overall hits
-system.cpu.icache.overall_hits::total        51419247                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5677                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5677                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5677                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5677                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5677                       # number of overall misses
-system.cpu.icache.overall_misses::total          5677                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    373029250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    373029250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    373029250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    373029250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    373029250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    373029250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     51424924                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     51424924                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     51424924                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     51424924                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     51424924                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     51424924                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000110                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000110                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000110                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000110                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000110                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000110                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65708.869121                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65708.869121                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65708.869121                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65708.869121                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65708.869121                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65708.869121                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          290                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         102869060                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        102869060                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     51426803                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        51426803                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total         51426803                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     51426803                       # number of overall hits
+system.cpu.icache.overall_hits::total        51426803                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5685                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5685                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total           5685                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5685                       # number of overall misses
+system.cpu.icache.overall_misses::total          5685                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    368406498                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    368406498                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    368406498                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    368406498                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    368406498                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    368406498                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     51432488                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     51432488                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     51432488                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     51432488                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     51432488                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000111                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000111                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000111                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000111                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000111                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000111                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64803.253826                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64803.253826                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64803.253826                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64803.253826                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64803.253826                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64803.253826                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          546                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    68.250000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1590                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1590                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1590                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1590                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1590                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1590                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4087                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4087                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4087                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4087                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4087                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4087                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    274156250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    274156250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    274156250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    274156250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    274156250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    274156250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1601                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4084                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    275253499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    275253499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    275253499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    275253499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    275253499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    275253499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67080.070957                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67080.070957                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67080.070957                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67080.070957                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67080.070957                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67080.070957                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67398.016405                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67398.016405                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67398.016405                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4023.366871                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                875                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4863                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.179930                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4020.332980                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3138                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4861                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.645546                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.059378                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2982.142231                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   669.165262                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   372.062557                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2982.230615                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   666.039808                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011354                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.091008                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020421                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122783                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4863                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.091010                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020326                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122691                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4861                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          529                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4051                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148407                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            79895                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           79895                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          627                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          134                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            761                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          682                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          682                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           78                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           78                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          627                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          212                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             839                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          627                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          212                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            839                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3460                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          867                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4327                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         3130                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3130                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3460                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3997                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7457                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3460                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3997                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7457                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    263476500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     70328000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    333804500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    249238250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    249238250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    263476500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    319566250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    583042750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    263476500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    319566250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    583042750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4087                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1001                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5088                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          682                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          682                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3208                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst         4087                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4209                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8296                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data         4209                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8296                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.846587                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.866134                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.850432                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.975686                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.975686                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.846587                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.949632                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.898867                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.846587                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.949632                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.898867                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76149.277457                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81116.493656                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77144.557430                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79628.833866                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79628.833866                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76149.277457                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79951.526145                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78187.307228                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76149.277457                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79951.526145                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78187.307228                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          530                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4047                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148346                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            97927                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           97927                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks          671                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          671                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           71                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           71                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          623                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          623                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          131                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          131                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          623                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          202                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             825                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          623                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          202                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            825                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3131                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3131                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3461                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3461                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          864                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          864                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3461                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3995                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7456                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3461                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3995                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7456                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    241202500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    241202500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262576000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    262576000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     73634500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     73634500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    262576000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    314837000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    577413000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    262576000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    314837000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    577413000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks          671                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          671                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4084                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4084                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          995                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          995                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4084                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4197                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8281                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4084                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4197                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8281                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.977826                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.977826                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.847453                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.847453                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.868342                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.868342                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.847453                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.951870                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.900374                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.847453                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.951870                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.900374                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77036.889173                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77036.889173                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.090436                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.090436                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85225.115741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85225.115741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.090436                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78807.759700                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77442.730687                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.090436                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78807.759700                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77442.730687                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -900,102 +906,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          867                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4327                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3460                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3997                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7457                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3460                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3997                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7457                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    220205500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     59518000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    279723500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    210540750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    210540750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    220205500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    270058750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    490264250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    220205500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    270058750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    490264250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.846587                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.866134                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.850432                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.975686                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.975686                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.846587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.949632                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.898867                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.846587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.949632                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.898867                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3131                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3131                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3461                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3461                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          864                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          864                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3461                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3995                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7456                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3461                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3995                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7456                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    209892500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    209892500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    227966000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    227966000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     64994500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     64994500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    227966000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    274887000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    502853000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    227966000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    274887000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    502853000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.977826                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.977826                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.847453                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.868342                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.868342                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.951870                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.900374                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.951870                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.900374                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           5088                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5088                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3208                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8174                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9100                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17274                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       261568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       313024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             574592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp          5079                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          671                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2281                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4084                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          995                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10325                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9189                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19514                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       261376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       311552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             572928                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         8978                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        11233                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               8978    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11233    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           8978                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5171000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          11233                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        6287500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6830250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6126000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6882750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6295500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4327                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4327                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3130                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3130                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14914                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14914                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       477248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  477248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4325                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3131                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3131                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4325                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       477184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  477184                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7457                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7456                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7457    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7456    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7457                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9341500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7456                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9215500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39310250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39331250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 97440304f..8c86953a0 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.567335                       # Number of seconds simulated
-sim_ticks                                567335093500                       # Number of ticks simulated
-final_tick                               567335093500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                567335097500                       # Number of ticks simulated
+final_tick                               567335097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1360508                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1360508                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1936123010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299124                       # Number of bytes of host memory used
-host_seconds                                   293.03                       # Real time elapsed on the host
+host_inst_rate                                1293186                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1293186                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1840317995                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300812                       # Number of bytes of host memory used
+host_seconds                                   308.28                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -63,7 +63,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                       1134670187                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134670195                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664609                       # Number of instructions committed
@@ -82,7 +82,7 @@ system.cpu.num_mem_refs                     168275276                       # nu
 system.cpu.num_load_insts                    94754511                       # Number of load instructions
 system.cpu.num_store_insts                   73520765                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1134670187                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1134670195                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587535                       # Number of branches fetched
@@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  398664665                       # Class of executed instruction
 system.cpu.dcache.tags.replacements               764                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3288.930570                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3288.930558                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          40527.713873                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3288.930570                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  3288.930558                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.802962                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.802962                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
@@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     45659000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     45659000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    168787000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    168787000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    214446000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    214446000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    214446000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    214446000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     46134000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     46134000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    170388000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    170388000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    216522000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    216522000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    216522000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    216522000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1795.138960                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1795.138955                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           398660993                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3673                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          108538.250204                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1795.138960                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1795.138955                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.876533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.876533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1904                       # Occupied blocks per task id
@@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst         3673                       # n
 system.cpu.icache.demand_misses::total           3673                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3673                       # number of overall misses
 system.cpu.icache.overall_misses::total          3673                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    182359500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    182359500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    182359500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    182359500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    182359500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    182359500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    182363500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    182363500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    182363500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    182363500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    182363500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    182363500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    398664666                       # number of demand (read+write) accesses
@@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000009
 system.cpu.icache.demand_miss_rate::total     0.000009                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49648.652328                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49648.652328                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49649.741356                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49649.741356                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3673
 system.cpu.icache.demand_mshr_misses::total         3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3673                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3673                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    176850000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    176850000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    176850000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    176850000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    176850000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    176850000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    178690500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    178690500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    178690500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    178690500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    178690500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    178690500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3772.485298                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                677                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3772.485272                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2561                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4566                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.148270                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.560885                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.540220                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2770.469918                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   630.475159                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.540218                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2770.469899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   630.475155                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011339                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019241                       # Average percentage of cache occupancy
@@ -337,78 +337,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2           75
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          497                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3787                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.139343                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            75560                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           75560                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          468                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            591                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses            90632                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           90632                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks          649                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          649                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          468                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          468                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          123                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          123                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst          468                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          183                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total             651                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst          468                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          183                       # number of overall hits
 system.cpu.l2cache.overall_hits::total            651                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3205                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          827                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4032                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3142                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3142                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3205                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3205                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          827                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          827                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         3205                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         3969                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          7174                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         3205                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7174                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    168263000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     43417500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    211680500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    164955000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    164955000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    168263000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    168265000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    168265000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     43417500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     43417500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    168265000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data    208372500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    376635500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    168263000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total    376637500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    168265000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    208372500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    376635500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         3673                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          950                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         4623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::total    376637500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks          649                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          649                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         3673                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         3673                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          950                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          950                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         3673                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4152                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total         7825                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         3673                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4152                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total         7825                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.872584                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.870526                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.872161                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981262                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.872584                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.872584                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.870526                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.870526                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.872584                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955925                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.916805                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.872584                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916805                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3205                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          827                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4032                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3142                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3142                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3205                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3205                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          827                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          827                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         3205                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         3969                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         7174                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3205                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7174                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    129802500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     33493500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    163296000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    127251000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    127251000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    129802500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    160744500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    290547000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    129802500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    160744500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    290547000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.870526                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.872161                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133535000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133535000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    136215000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    136215000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     35147500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     35147500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    136215000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    168682500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    304897500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    136215000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168682500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    304897500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981262                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981262                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.872584                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.870526                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.870526                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.916805                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.916805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           4623                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          4623                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         1884                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         7346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8953                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             16299                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         3673                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          950                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9115                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9068                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             18183                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       235072                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       307264                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             542336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         8474                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        10358                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               8474    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              10358    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           8474                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        4886000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          10358                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        5828000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       5509500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6228000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4032                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4032                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3142                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3142                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4032                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14348                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  14348                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       459136                       # Cumulative packet size per connected master and slave (bytes)
@@ -510,9 +522,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7174                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7174500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7176500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35870500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           35872500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 572510825..454441ad4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.216140                       # Number of seconds simulated
-sim_ticks                                216139917000                       # Number of ticks simulated
-final_tick                               216139917000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.216071                       # Number of seconds simulated
+sim_ticks                                216071083000                       # Number of ticks simulated
+final_tick                               216071083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173188                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              137097336                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323040                       # Number of bytes of host memory used
-host_seconds                                  1576.54                       # Real time elapsed on the host
+host_inst_rate                                 173126                       # Simulator instruction rate (inst/s)
+host_op_rate                                   207857                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              137004908                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323124                       # Number of bytes of host memory used
+host_seconds                                  1577.10                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            219136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            219072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485504                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219136                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3424                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               485440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219072                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3423                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7586                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1013862                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1232387                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2246249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1013862                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1013862                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1013862                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1232387                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2246249                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7586                       # Number of read requests accepted
+system.physmem.num_reads::total                  7585                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1013889                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1232779                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2246668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1013889                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1013889                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1013889                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1232779                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2246668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7585                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7586                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7585                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485440                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485504                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485440                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11                428                       # Pe
 system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                541                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    216139680500                       # Total gap between requests
+system.physmem.totGap                    216070847500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7586                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7585                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6624                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       901                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1523                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      318.319107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.795582                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.243204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            551     36.18%     36.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          346     22.72%     58.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          176     11.56%     70.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           81      5.32%     75.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           75      4.92%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           50      3.28%     83.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      2.10%     86.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      1.84%     87.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     12.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1523                       # Bytes accessed per row activation
-system.physmem.totQLat                       53007250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 195244750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37930000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6987.51                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1505                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      321.445847                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.975712                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.801659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            552     36.68%     36.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          337     22.39%     59.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          156     10.37%     69.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           81      5.38%     74.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           75      4.98%     79.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           59      3.92%     83.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           41      2.72%     86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           29      1.93%     88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          175     11.63%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1505                       # Bytes accessed per row activation
+system.physmem.totQLat                       52368250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194587000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37925000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6904.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25737.51                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25654.19                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6060                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6074                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.88                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.08                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28491916.75                       # Average gap between requests
-system.physmem.pageHitRate                      79.88                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5004720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2730750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  30022200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28486598.22                       # Average gap between requests
+system.physmem.pageHitRate                      80.08                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5050080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2755500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29959800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14117117040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5648540400                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           124728404250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             144531819360                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.699173                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   207494790250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7217340000                       # Time in different power states
+system.physmem_0.refreshEnergy            14112540000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5672899350                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           124664991000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             144488195730                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.714152                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   207389955000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7215000000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1426657250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1464485500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6509160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3551625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  29062800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6320160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3448500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28992600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14117117040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5781551040                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           124611728250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             144549519915                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.781068                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   207298156250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7217340000                       # Time in different power states
+system.physmem_1.refreshEnergy            14112540000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5762856465                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           124586081250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             144500238975                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.769890                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   207255387750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7215000000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1623563250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1598323500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                33139216                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17107199                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1560655                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17520877                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15610870                       # Number of BTB hits
+system.cpu.branchPred.lookups                33111389                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17094855                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1552605                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17374125                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15590921                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.098679                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6611023                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             89.736439                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6603992                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,69 +377,69 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        432279834                       # number of cpu cycles simulated
+system.cpu.numCycles                        432142166                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037857                       # Number of instructions committed
 system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4207498                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4177938                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.583223                       # CPI: cycles per instruction
-system.cpu.ipc                               0.631623                       # IPC: instructions per cycle
-system.cpu.tickCycles                       428628441                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3651393                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.582719                       # CPI: cycles per instruction
+system.cpu.ipc                               0.631824                       # IPC: instructions per cycle
+system.cpu.tickCycles                       428506724                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3635442                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.737950                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168771151                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3085.759854                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168767138                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37413.245622                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37412.356019                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.737950                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.759854                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753359                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753359                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337561379                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337561379                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86638362                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86638362                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82047459                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047459                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         337553367                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337553367                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86634356                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86634356                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82047452                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047452                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data        63540                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total         63540                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168685821                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168685821                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168749361                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168749361                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     168681808                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168681808                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168745348                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168745348                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5218                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5218                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5225                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5225                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         7277                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7277                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7283                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7283                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    136967456                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    136967456                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    400451000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    400451000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    537418456                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    537418456                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    537418456                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    537418456                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86640421                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86640421                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         7284                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7284                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7290                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    134727000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    134727000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    395694000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    395694000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    530421000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    530421000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    530421000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    530421000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86636415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86636415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data        63546                       # number of SoftPFReq accesses(hits+misses)
@@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168693098                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168693098                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168756644                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168756644                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168689092                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168689092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168752638                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168752638                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
@@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73851.649856                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73790.808183                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72820.016474                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72760.082305                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks         1010                       # nu
 system.cpu.dcache.writebacks::total              1010                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          422                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          422                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2348                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2348                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2770                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2770                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2770                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2770                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2355                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2355                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2777                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2777                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2777                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2777                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1637                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total         1637                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
@@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4507
 system.cpu.dcache.demand_mshr_misses::total         4507                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    108888792                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    108888792                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220256750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    220256750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       320750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       320750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329145542                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    329145542                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329466292                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    329466292                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    108637000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    108637000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220584500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    220584500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       322000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       322000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329221500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    329221500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329543500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    329543500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        80500                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        80500                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36928                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.841098                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            73108223                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38865                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1881.081256                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             36911                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1924.852805                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            73041980                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38848                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1880.199238                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.841098                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939864                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.852805                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939870                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939870                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          274                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1488                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146333043                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146333043                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     73108223                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        73108223                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      73108223                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         73108223                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     73108223                       # number of overall hits
-system.cpu.icache.overall_hits::total        73108223                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38866                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38866                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38866                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38866                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38866                       # number of overall misses
-system.cpu.icache.overall_misses::total         38866                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    728130248                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    728130248                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    728130248                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    728130248                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    728130248                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    728130248                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     73147089                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     73147089                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     73147089                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     73147089                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     73147089                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     73147089                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000531                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000531                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000531                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000531                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000531                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000531                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18734.375753                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18734.375753                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146200506                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146200506                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     73041980                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        73041980                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      73041980                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         73041980                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     73041980                       # number of overall hits
+system.cpu.icache.overall_hits::total        73041980                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38849                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38849                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38849                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38849                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38849                       # number of overall misses
+system.cpu.icache.overall_misses::total         38849                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    726693000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    726693000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    726693000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    726693000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    726693000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    726693000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     73080829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     73080829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     73080829                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     73080829                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     73080829                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     73080829                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000532                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000532                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000532                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000532                       # miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18705.578007                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18705.578007                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18705.578007                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18705.578007                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18705.578007                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18705.578007                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,123 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38866                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38866                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        38866                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        38866                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        38866                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        38866                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    668381252                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    668381252                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total    668381252                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    668381252                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    668381252                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000531                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 17705.603748                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4199.211257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              35810                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5648                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.340297                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4199.240994                       # Cycle average of tags in use
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+system.cpu.l2cache.tags.sampled_refs             5647                       # Sample count of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.787736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.125698                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.297823                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1252                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172363                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           363614                       # Number of tag accesses
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 system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_avg_miss_latency::total 75647.463626                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75219.416058                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75996.194101                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75647.463626                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -716,111 +722,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           42                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           42                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           42                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           42                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4732                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3424                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1308                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1308                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3423                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7586                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3424                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7585                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3423                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7586                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    214398750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     85427750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    299826500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    181482250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    181482250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    214398750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    266910000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    481308750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    214398750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    266910000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    481308750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116819                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total         7585                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    187536500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    187536500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223262000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223262000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     87309500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     87309500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    274846000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    498108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    274846000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    498108000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088110                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797075                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.174885                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.174931                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.174885                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.174931                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          40507                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         40506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40489                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        22221                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77731                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10032                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             87763                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2487360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        38849                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq         1641                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        99690                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10260                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            109950                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2486272                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2840704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2839616                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        44387                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        81625                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              44387    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              81625    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          44387                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       23203500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          81625                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       41822500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      59023248                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      58272998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7574708                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6787458                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4732                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4732                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4731                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15172                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15172                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          4731                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15170                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15170                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485440                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7586                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7585                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7586    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7585    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7586                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8848500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7585                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8844500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40266750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40248250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 94f7097ff..8a385b77d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.112557                       # Number of seconds simulated
-sim_ticks                                112556618500                       # Number of ticks simulated
-final_tick                               112556618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.112686                       # Number of seconds simulated
+sim_ticks                                112686104500                       # Number of ticks simulated
+final_tick                               112686104500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125639                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150843                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               51793233                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 327772                       # Number of bytes of host memory used
-host_seconds                                  2173.19                       # Real time elapsed on the host
+host_inst_rate                                 125538                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150722                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51811162                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 327864                       # Number of bytes of host memory used
+host_seconds                                  2174.94                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            187072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            117696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       162752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               467520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            112896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       167936                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               467904                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       187072                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          187072                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               2923                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1839                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2543                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7305                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1662026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1045660                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1445957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4153643                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1662026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1662026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1662026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1045660                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1445957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4153643                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7305                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data               1764                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2624                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7311                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1660116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1001863                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1490299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4152278                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1660116                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1660116                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1660116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1001863                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1490299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4152278                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7311                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7305                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7311                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   467520                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   467904                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    467520                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    467904                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -51,16 +51,16 @@ system.physmem.perBankRdBursts::2                 601                       # Pe
 system.physmem.perBankRdBursts::3                 520                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 346                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 146                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 247                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 153                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                315                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                411                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                547                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                678                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                615                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                555                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                542                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    112556460000                       # Total gap between requests
+system.physmem.totGap                    112685946000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7305                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7311                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,22 +94,22 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4013                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1460                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       289                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       237                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       168                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       137                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       186                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        52                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3986                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1457                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       235                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       200                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       198                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        66                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1395                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      333.121147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     192.861490                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     347.787983                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            501     35.91%     35.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          324     23.23%     59.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          138      9.89%     69.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           72      5.16%     74.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           60      4.30%     78.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           40      2.87%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           25      1.79%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           33      2.37%     85.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          202     14.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1395                       # Bytes accessed per row activation
-system.physmem.totQLat                      103629565                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 240598315                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36525000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14186.11                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1367                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      340.646672                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     198.022122                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     348.529599                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            486     35.55%     35.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          298     21.80%     57.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          139     10.17%     67.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           76      5.56%     73.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           63      4.61%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           51      3.73%     81.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           27      1.98%     83.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           26      1.90%     85.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          201     14.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1367                       # Bytes accessed per row activation
+system.physmem.totQLat                      102208518                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 239289768                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36555000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13980.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32936.11                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  32730.10                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.15                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.15                       # Average system read bandwidth in MiByte/s
@@ -218,51 +218,51 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.37                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.49                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5900                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5935                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.77                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.18                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15408139.63                       # Average gap between requests
-system.physmem.pageHitRate                      80.77                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4800600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2619375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  28509000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     15413205.58                       # Average gap between requests
+system.physmem.pageHitRate                      81.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4815720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2627625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  28657200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             7351234800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3210095790                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            64714428750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              75311688315                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.136839                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   107655127862                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3758300000                       # Time in different power states
+system.physmem_0.refreshEnergy             7359880320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3231673425                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            64774920750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              75402575040                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.157389                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   107755851914                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3762720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1137230638                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1164613086                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5692680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3106125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28033200                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5496120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2998875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28064400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             7351234800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3321763065                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            64616466750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              75326296620                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.266714                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   107490739638                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3758300000                       # Time in different power states
+system.physmem_1.refreshEnergy             7359880320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3295137510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            64719250500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              75410827725                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.230627                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   107661884129                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3762720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1301464112                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1258279621                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37745745                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20165036                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746193                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18664433                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17299757                       # Number of BTB hits
+system.cpu.branchPred.lookups                37742989                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20164516                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1746156                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18663196                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                17299233                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.688361                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7225644                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3815                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.691697                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7223653                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3816                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,129 +381,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        225113238                       # number of cpu cycles simulated
+system.cpu.numCycles                        225372210                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12251417                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334051298                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37745745                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24525401                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     210778013                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3510671                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1214                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         2374                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89095174                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 21831                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          224788353                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.802613                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228565                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12439138                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      334051202                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37742989                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24522886                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     210855691                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3510707                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1284                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles         2593                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  89092155                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 21708                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          225054059                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.800470                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.229417                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 51103569     22.73%     22.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42898008     19.08%     41.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30051948     13.37%     55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100734828     44.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 51374086     22.83%     22.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42891136     19.06%     41.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 30054592     13.35%     55.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                100734245     44.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            224788353                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.167674                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.483926                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 27670582                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63851253                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108576447                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23069494                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620577                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880022                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135197                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363530011                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6168132                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620577                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 44985380                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                17900890                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         342489                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113387887                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46551130                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355747905                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2899336                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6599141                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 195125                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7751977                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21225499                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2892433                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403402217                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2533894130                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350207887                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194891394                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            225054059                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.167470                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.482220                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 27837229                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63912010                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 108618315                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              23065911                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1620594                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6880048                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                135198                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              363546099                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               6169805                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1620594                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45200014                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                17874059                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         342377                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 113380979                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46636036                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355768136                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               2890465                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               6610669                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 177931                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7803674                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               21223053                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          2890533                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           403406015                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2534023592                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        350247327                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         194894263                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31172166                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              17015                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          17024                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55319848                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92416628                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88482470                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1658909                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1843123                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353235356                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               28024                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346405014                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2300418                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25451778                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73600174                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           5904                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     224788353                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.541027                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.099686                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 31175964                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              17016                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          17025                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  55505783                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             92416404                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            88498336                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1661010                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1846418                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  353252226                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               28026                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 346438238                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2301579                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        25468650                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     73725461                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           5906                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     225054059                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.539356                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.099855                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40435382     17.99%     17.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78271933     34.82%     52.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            61035531     27.15%     79.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34789384     15.48%     95.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9595504      4.27%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              651863      0.29%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                8756      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            40665072     18.07%     18.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            78300215     34.79%     52.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            60997700     27.10%     79.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34882254     15.50%     95.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9557051      4.25%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              642945      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                8822      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       224788353                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       225054059                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9471637      7.62%      7.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7328      0.01%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            257062      0.21%      7.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            126985      0.10%      7.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             92941      0.07%      8.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             68002      0.05%      8.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           719490      0.58%      8.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           316341      0.25%      8.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        682827      0.55%      9.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53603507     43.13%     52.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              58947270     47.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9490410      7.63%      7.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7314      0.01%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            255762      0.21%      7.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            126866      0.10%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             93218      0.07%      8.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             68015      0.05%      8.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           721741      0.58%      8.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           297231      0.24%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        683043      0.55%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               53642366     43.14%     52.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              58960700     47.42%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110656004     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148356      0.62%     32.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             110655140     31.94%     31.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148362      0.62%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
@@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798499      1.96%     34.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8668326      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332485      0.96%     37.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1592467      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20930113      6.04%     44.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7182308      2.07%     46.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148959      2.06%     48.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6798396      1.96%     34.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8668155      2.50%     37.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3332481      0.96%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1592458      0.46%     38.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20930094      6.04%     44.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7182326      2.07%     46.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148962      2.06%     48.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91886991     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85885220     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             91923219     26.53%     75.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85883359     24.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346405014                       # Type of FU issued
-system.cpu.iq.rate                           1.538803                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124293390                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.358809                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          756692141                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251708637                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223263072                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287500048                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127016707                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117424886                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303165485                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167532919                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5066153                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              346438238                       # Type of FU issued
+system.cpu.iq.rate                           1.537183                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   124346666                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.358929                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          757024395                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         251740362                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    223260150                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           287554385                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          127018791                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    117424955                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              303230405                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               167554499                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5064919                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6684353                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13689                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10190                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6106853                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6684129                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13573                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        10255                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6122719                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       154467                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        567717                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       155303                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        607776                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620577                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2121612                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                331103                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353264247                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                1620594                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2118849                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                332046                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           353281117                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92416628                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88482470                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              16991                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8045                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                337585                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10190                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220609                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439082                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659691                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342414524                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90667106                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3990490                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              92416404                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             88498336                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              16993                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   8049                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                338505                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          10255                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1220656                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       439058                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1659714                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             342448377                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              90703712                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3989861                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           867                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175256113                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31752933                       # Number of branches executed
-system.cpu.iew.exec_stores                   84589007                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.521077                       # Inst execution rate
-system.cpu.iew.wb_sent                      340946411                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340687958                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153730891                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266895127                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           865                       # number of nop insts executed
+system.cpu.iew.exec_refs                    175291126                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31752707                       # Number of branches executed
+system.cpu.iew.exec_stores                   84587414                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.519479                       # Inst execution rate
+system.cpu.iew.wb_sent                      340943800                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     340685105                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 153662327                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 266738216                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.513407                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.575997                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.511655                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.576079                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23077429                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23082519                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1611435                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    221063225                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.482889                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.052142                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1611397                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    221328864                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.481109                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.050764                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87359166     39.52%     39.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70369846     31.83%     71.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20804571      9.41%     80.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13442893      6.08%     86.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8809424      3.99%     90.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4514904      2.04%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2991184      1.35%     94.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2424669      1.10%     95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10346568      4.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     87530154     39.55%     39.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     70479011     31.84%     71.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20814829      9.40%     80.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13433176      6.07%     86.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8801116      3.98%     90.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4514131      2.04%     92.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2986629      1.35%     94.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2449420      1.11%     95.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10320398      4.66%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    221063225                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    221328864                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
 system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -654,154 +654,154 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10346568                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    561603777                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705508335                       # The number of ROB writes
-system.cpu.timesIdled                           50687                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          324885                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10320398                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    561900676                       # The number of ROB reads
+system.cpu.rob.rob_writes                   705518580                       # The number of ROB writes
+system.cpu.timesIdled                           50864                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          318151                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.824478                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.824478                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.212888                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.212888                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331301011                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136940115                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187107432                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132177980                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297030870                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80242369                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1182848919                       # number of misc regfile reads
+system.cpu.cpi                               0.825427                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.825427                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.211495                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.211495                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                331331443                       # number of integer regfile reads
+system.cpu.int_regfile_writes               136939322                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 187108010                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132178699                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1297132712                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80241070                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1183128145                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1533856                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.842901                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163689178                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1534368                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.681825                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          84489000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.842901                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999693                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999693                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1533845                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.844014                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           163642665                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1534357                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            106.652275                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          82317000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.844014                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999695                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999695                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336633512                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336633512                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82631334                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82631334                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80965560                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80965560                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70478                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70478                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         336636785                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336636785                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82609327                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82609327                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80941037                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80941037                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        70495                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         70495                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163596894                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163596894                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163667372                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163667372                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2773234                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2773234                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1087139                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1087139                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     163550364                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        163550364                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    163620859                       # number of overall hits
+system.cpu.dcache.overall_hits::total       163620859                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2796866                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2796866                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1111662                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1111662                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3860373                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3860373                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3860391                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3860391                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  22353219965                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  22353219965                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8921439031                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8921439031                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       189750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  31274658996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  31274658996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  31274658996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  31274658996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85404568                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85404568                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      3908528                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3908528                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3908546                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3908546                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  22404027000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  22404027000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8967503998                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8967503998                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       189000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  31371530998                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  31371530998                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  31371530998                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  31371530998                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     85406193                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     85406193                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70496                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70496                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        70513                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        70513                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167457267                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167457267                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167527763                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167527763                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032472                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032472                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013249                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013249                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    167458892                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167458892                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167529405                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167529405                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032748                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032748                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013548                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013548                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000255                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.000255                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000458                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023053                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023053                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8060.343976                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  8060.343976                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8206.346227                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8206.346227                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37950                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37950                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  8101.460402                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  8101.460402                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  8101.422627                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  8101.422627                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023340                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023340                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023331                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023331                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8010.404145                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  8010.404145                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8066.754102                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8066.754102                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37800                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37800                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  8026.431178                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  8026.431178                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  8026.394214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  8026.394214                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       920181                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1059827                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          117395                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          134751                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.838332                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.865077                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       966341                       # number of writebacks
-system.cpu.dcache.writebacks::total            966341                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1459520                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1459520                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       866494                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       866494                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       966339                       # number of writebacks
+system.cpu.dcache.writebacks::total            966339                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1483173                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1483173                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891007                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       891007                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2326014                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2326014                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2326014                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2326014                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313714                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1313714                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220645                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       220645                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      2374180                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2374180                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2374180                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2374180                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313693                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1313693                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220655                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       220655                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1534359                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1534359                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1534370                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1534370                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9970454284                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9970454284                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1720952041                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1720952041                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       709000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       709000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11691406325                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11691406325                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11692115325                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11692115325                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      1534348                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1534348                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1534359                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1534359                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10622731000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10622731000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1827670779                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1827670779                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       681000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       681000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12450401779                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12450401779                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12451082779                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12451082779                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
@@ -812,368 +812,381 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009163
 system.cpu.dcache.demand_mshr_miss_rate::total     0.009163                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009159                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7589.516656                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7589.516656                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7799.642145                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7799.642145                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7619.733273                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7619.733273                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7620.140726                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7620.140726                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8086.159399                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8086.159399                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8282.933897                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8282.933897                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8114.457593                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8114.457593                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8114.843253                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8114.843253                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715712                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.827844                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88374047                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716224                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.388838                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         326692250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.827844                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999664                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999664                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            715634                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.830268                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            88370349                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            716146                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            123.397113                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         324802500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.830268                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999668                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999668                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          245                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178906541                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178906541                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88374047                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88374047                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88374047                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88374047                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88374047                       # number of overall hits
-system.cpu.icache.overall_hits::total        88374047                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       721111                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        721111                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       721111                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         721111                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       721111                       # number of overall misses
-system.cpu.icache.overall_misses::total        721111                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   5974650710                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   5974650710                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   5974650710                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   5974650710                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   5974650710                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   5974650710                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     89095158                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     89095158                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     89095158                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     89095158                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     89095158                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     89095158                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008094                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.008094                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.008094                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.008094                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.008094                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.008094                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8285.341244                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8285.341244                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8285.341244                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8285.341244                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8285.341244                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8285.341244                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        59670                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2032                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         178900425                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        178900425                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     88370349                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        88370349                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      88370349                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         88370349                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     88370349                       # number of overall hits
+system.cpu.icache.overall_hits::total        88370349                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       721790                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        721790                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       721790                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         721790                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       721790                       # number of overall misses
+system.cpu.icache.overall_misses::total        721790                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   5973224944                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   5973224944                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   5973224944                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   5973224944                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   5973224944                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   5973224944                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     89092139                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     89092139                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     89092139                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     89092139                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     89092139                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     89092139                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008102                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008102                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008102                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008102                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008102                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008102                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8275.571765                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8275.571765                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8275.571765                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8275.571765                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8275.571765                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8275.571765                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        62134                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2178                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.365157                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    31.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.528007                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4886                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4886                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4886                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4886                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716225                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       716225                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       716225                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       716225                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       716225                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       716225                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5193352944                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   5193352944                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5193352944                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   5193352944                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5193352944                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   5193352944                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.008039                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.008039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7251.007636                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7251.007636                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7251.007636                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5643                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         5643                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         5643                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         5643                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716147                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       716147                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       716147                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       716147                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       716147                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       716147                       # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total   5549831453                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5549831453                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   5549831453                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5549831453                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   5549831453                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008038                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.008038                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.008038                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7749.570204                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7749.570204                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7749.570204                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       405309                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       405577                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          209                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       404667                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       404963                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          238                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        27975                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        28037                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5974.758413                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2806551                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             7279                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           385.568210                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5979.453401                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3840411                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             7285                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           527.166918                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2575.130596                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.592596                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   609.586326                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   109.448896                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.157173                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163610                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.037206                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006680                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.364670                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          497                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6782                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  2575.206017                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.661219                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   617.502494                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   106.083671                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.157178                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163615                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006475                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.364957                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         6791                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          115                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          112                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          127                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5741                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030334                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.413940                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         51684404                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        51684404                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       712384                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1312658                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2025042                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       966341                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       966341                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          772                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5749                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.414490                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         68225284                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        68225284                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       966339                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       966339                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219788                       # number of ReadExReq hits
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-system.cpu.l2cache.overall_hits::cpu.inst       712384                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1532446                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2244830                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2935                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1067                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4002                       # number of ReadReq misses
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       712305                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       712305                       # number of ReadCleanReq hits
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+system.cpu.l2cache.overall_hits::cpu.data      1532503                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2244808                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          855                       # number of ReadExReq misses
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-system.cpu.l2cache.demand_misses::cpu.data         1922                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          4857                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data         1922                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         4857                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    201263959                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     77652750                       # number of ReadReq miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data    139235498                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total      2029044                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       966341                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       966341                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.overall_misses::total         4790                       # number of overall misses
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total     76381000                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data    133463000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    332753000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       966339                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       966339                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_accesses::total       220643                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data      1534368                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2249687                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000812                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001972                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       715241                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       715241                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1313704                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1313704                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       715241                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1534357                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2249598                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       715241                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1534357                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2249598                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003875                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003875                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004103                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.001253                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.002159                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004103                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.001253                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.002159                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68573.750937                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72776.710403                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69694.330085                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        23499                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        23499                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72026.605848                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72026.605848                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.750937                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72443.027055                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70104.891291                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.750937                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72443.027055                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70104.891291                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs          704                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004105                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004105                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000805                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000805                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004105                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.001208                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.002129                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004105                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.001208                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.002129                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        23000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        23000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71621.079046                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71621.079046                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67878.065395                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67878.065395                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72262.062441                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72262.062441                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67878.065395                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71986.515642                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69468.267223                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67878.065395                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71986.515642                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69468.267223                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                2                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          352                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           33                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           50                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           50                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           83                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           95                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           83                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           95                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2923                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1034                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3957                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        30254                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        30254                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           57                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           57                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           90                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          103                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           90                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          103                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        30350                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        30350                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          805                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          805                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          740                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          740                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2923                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2923                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1024                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1024                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2923                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1839                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4762                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1764                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4687                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2923                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1839                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        30254                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        35016                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    175790791                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     67094500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    242885291                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    178618011                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    178618011                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        14001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        14001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     52729252                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     52729252                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    175790791                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    119823752                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    295614543                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    175790791                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    119823752                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    178618011                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    474232554                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000787                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001950                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1764                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        30350                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        35037                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    188993302                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    188993302                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        17000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        17000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50613500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50613500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    181139000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    181139000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     68370000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     68370000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    181139000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    118983500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    300122500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    181139000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    118983500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    188993302                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    489115802                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003648                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003648                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001199                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.002117                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001199                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003354                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003354                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000779                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000779                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001150                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.002083                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001150                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.015565                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5903.946949                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  5903.946949                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5903.946949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.015575                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  6227.126919                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  6227.126919                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        17000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        17000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  6227.126919                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2029950                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2029950                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       966341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        31609                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2029851                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       966339                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1033895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        31761                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       220643                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       220643                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1431544                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4035081                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5466625                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45780416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    160045376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205825792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       32515                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3248545                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.009730                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.098161                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       220653                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       220653                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       716147                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313704                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2122577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4377763                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6500340                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45775424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    160044544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205819968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       32667                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4531746                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.007009                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.083423                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3216936     99.03%     99.03% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              31609      0.97%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4499985     99.30%     99.30% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              31761      0.70%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3248545                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2574809000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1075177011                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4531746                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3216331500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1074485469                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2301798469                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2301553965                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                6500                       # Transaction distribution
-system.membus.trans_dist::ReadResp               6500                       # Transaction distribution
+system.membus.trans_dist::ReadResp               6571                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               805                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              805                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14612                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14612                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       467520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  467520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               740                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              740                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          6571                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14624                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14624                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       467904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  467904                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7306                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7312                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7306    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7312    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7306                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9226230                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7312                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9348857                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           38266679                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           38261400                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index cfbe2044c..b10e642ea 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.517235                       # Number of seconds simulated
-sim_ticks                                517235405500                       # Number of ticks simulated
-final_tick                               517235405500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                517235407500                       # Number of ticks simulated
+final_tick                               517235407500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 520716                       # Simulator instruction rate (inst/s)
-host_op_rate                                   625139                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              987510163                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313820                       # Number of bytes of host memory used
-host_seconds                                   523.78                       # Real time elapsed on the host
+host_inst_rate                                 785915                       # Simulator instruction rate (inst/s)
+host_op_rate                                   943520                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1490444540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321320                       # Number of bytes of host memory used
+host_seconds                                   347.03                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,7 +147,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1034470811                       # number of cpu cycles simulated
+system.cpu.numCycles                       1034470815                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   272739286                       # Number of instructions committed
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs                     168107847                       # nu
 system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1034470810.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1034470814.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          30563503                       # Number of branches fetched
@@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812214                       # Class of executed instruction
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.445034                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3078.445031                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445034                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445031                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
@@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data         4479                       #
 system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data     78396000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     78396000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    157422500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    157422500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235818500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235818500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235818500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235818500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    157423500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    157423500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    235819500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235819500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    235819500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235819500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data     0.000027
 system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52685.098302                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52649.810225                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52685.321716                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52650.033490                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4475
 system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75951500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75951500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    153114500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    153114500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       160500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       160500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    229066000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    229066000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    229226500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    229226500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76753000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     76753000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    154551500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    154551500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       162000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       162000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    231304500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    231304500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    231466500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    231466500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1766.007655                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1766.007653                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          22344.725373                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007655                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007653                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.862308                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.862308                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
@@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst        15603                       # n
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    312482000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    312482000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    312482000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    312482000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    312482000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    312482000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    312483000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    312483000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    312483000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    312483000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    312483000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    312483000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    348660353                       # number of demand (read+write) accesses
@@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000045
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.046081                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20027.046081                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.046081                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20027.046081                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.046081                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20027.046081                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20027.110171                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20027.110171                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15603
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    289077500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    289077500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    289077500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    289077500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    289077500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    289077500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    296880000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    296880000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    296880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    296880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    296880000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    296880000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18527.046081                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18527.046081                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18527.046081                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3487.765010                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              13310                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3487.764994                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              19775                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4882                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.726342                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.050594                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   341.623059                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.427162                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   738.714789                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   341.623058                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.427152                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   738.714783                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.010426                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073469                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.022544                       # Average percentage of cache occupancy
@@ -453,78 +453,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2           26
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1232                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           176386                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          176386                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12995                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          238                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          13233                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses           228106                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          228106                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks          998                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          998                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12995                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        12995                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          238                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          238                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst        12995                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          254                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total           13249                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst        12995                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          254                       # number of overall hits
 system.cpu.l2cache.overall_hits::total          13249                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2608                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1368                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3976                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         2856                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         2856                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2608                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2608                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1368                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1368                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2608                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         4224                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          6832                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2608                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4224                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    137027000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     72007000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    209034000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    150074500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    150074500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    137027000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    222081500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    359108500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    137027000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    222081500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    359108500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        15603                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1606                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        17209                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    150075000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    150075000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    137027500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    137027500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     72007000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     72007000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    137027500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    222082000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    359109500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    137027500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    222082000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    359109500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks          998                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          998                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15603                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        15603                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1606                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total         1606                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        15603                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4478                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total        20081                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        15603                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4478                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total        20081                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.167147                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.851806                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.231042                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994429                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.167147                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.167147                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.851806                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.851806                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167147                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.943278                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.340222                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167147                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.943278                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.027607                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.695906                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.027607                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.112689                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.027607                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.112689                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -533,84 +539,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2608                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1368                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3976                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2856                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2608                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2608                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1368                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1368                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2608                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         4224                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         6832                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2608                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4224                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    105625000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     55404000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    161029000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115668000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115668000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    105625000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    171072000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    276697000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    105625000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    171072000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    276697000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851806                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.231042                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    121515000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    121515000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    110947500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    110947500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     58327000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     58327000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110947500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    179842000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    290789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110947500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    179842000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    290789500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.167147                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.851806                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.851806                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          998                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6465                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2872                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31206                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9954                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             41160                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        15603                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq         1606                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        37418                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10207                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             47625                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       998592                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       350464                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total            1349056                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        21079                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        35209                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              21079    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              35209    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          21079                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       11537500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          35209                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       18602500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6717000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3976                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2856                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3976                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        13664                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  13664                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       437248                       # Cumulative packet size per connected master and slave (bytes)
@@ -626,9 +638,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                6833                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7260500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7261500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           34587500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           34588500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index efccfaef5..f751a40d2 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.561049                       # Number of seconds simulated
-sim_ticks                                561048999000                       # Number of ticks simulated
-final_tick                               561048999000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.560940                       # Number of seconds simulated
+sim_ticks                                560939897000                       # Number of ticks simulated
+final_tick                               560939897000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 327042                       # Simulator instruction rate (inst/s)
-host_op_rate                                   327042                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              197554566                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305844                       # Number of bytes of host memory used
-host_seconds                                  2839.97                       # Real time elapsed on the host
+host_inst_rate                                 309766                       # Simulator instruction rate (inst/s)
+host_op_rate                                   309766                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              187082277                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305868                       # Number of bytes of host memory used
+host_seconds                                  2998.36                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            186944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18470400                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18657344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       186944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            186880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18514240                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18701120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       186880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          186880                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2921                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291521                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2920                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289285                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292205                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               333204                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             32921189                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33254393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          333204                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             333204                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7606665                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7606665                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7606665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              333204                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            32921189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40861059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291521                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               333155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33005746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33338902                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          333155                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             333155                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7608145                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7608145                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7608145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              333155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33005746                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40947046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292205                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      291521                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292205                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18639104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18240                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266496                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18657344                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18680832                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18701120                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      285                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               17937                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18285                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18301                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18253                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18160                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18247                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18325                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18297                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18227                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18224                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18215                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18384                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18260                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18042                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              17980                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18099                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18030                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18359                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18394                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18343                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18248                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18243                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18313                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18291                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18223                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18225                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18213                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18377                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18256                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18128                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18060                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18185                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4188                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4185                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    561048916000                       # Total gap between requests
+system.physmem.totGap                    560939815000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291521                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292205                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,7 +97,7 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290732                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291384                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       475                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        29                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,117 +193,119 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       105209                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      217.703657                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     140.847395                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     266.018983                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          39852     37.88%     37.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43676     41.51%     79.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8737      8.30%     87.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          846      0.80%     88.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1608      1.53%     90.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1088      1.03%     91.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          546      0.52%     91.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          586      0.56%     92.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8270      7.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         105209                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4041                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.193764                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.202156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      784.629260                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4034     99.83%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            5      0.12%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4041                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4041                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.496907                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.475096                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.865198                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3038     75.18%     75.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1001     24.77%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4041                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2859634000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8320309000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1456180000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9818.96                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       103977                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      220.682651                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.922946                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     267.989820                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          38271     36.81%     36.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43979     42.30%     79.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8888      8.55%     87.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          756      0.73%     88.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1408      1.35%     89.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1167      1.12%     90.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          628      0.60%     91.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          577      0.55%     92.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8303      7.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         103977                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.413929                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.545155                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      755.096124                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            3      0.07%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.463571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.442765                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.845366                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3112     76.86%     76.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                934     23.07%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2918754250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8391654250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459440000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9999.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28568.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          33.22                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.60                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       33.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28749.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          33.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.61                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       33.34                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        7.61                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202235                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50448                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.65                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1566283.22                       # Average gap between requests
-system.physmem.pageHitRate                      70.60                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  396718560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  216463500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1137021600                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.25                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202534                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52030                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.39                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1562994.07                       # Average gap between requests
+system.physmem.pageHitRate                      70.99                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  391812120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  213786375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1140274200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            36644799360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           109036341675                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           240981860250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             388629643425                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.687306                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   400213963500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18734560000                       # Time in different power states
+system.physmem_0.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           109227211875                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           240749028000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             388576230570                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.726692                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   399826633250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18730920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142097780250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    142379745750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  398601000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  217490625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1134307200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215544240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            36644799360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           109322809425                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           240730572750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             388664124600                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.748765                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   399791677000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18734560000                       # Time in different power states
+system.physmem_1.actEnergy                  394193520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  215085750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136148000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215524800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           109501586505                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           240508346250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             388608564345                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.784339                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   399420466000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18730920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    142520871000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    142786637000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               125749073                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          81144364                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12157127                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103970968                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83513050                       # Number of BTB hits
+system.cpu.branchPred.lookups               125749081                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          81144339                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12157133                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            103971313                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83513402                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.323432                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18691036                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               9451                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.323504                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691072                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9449                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237538495                       # DTB read hits
+system.cpu.dtb.read_hits                    237538494                       # DTB read hits
 system.cpu.dtb.read_misses                     198467                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237736962                       # DTB read accesses
-system.cpu.dtb.write_hits                    98305062                       # DTB write hits
-system.cpu.dtb.write_misses                      7206                       # DTB write misses
+system.cpu.dtb.read_accesses                237736961                       # DTB read accesses
+system.cpu.dtb.write_hits                    98305022                       # DTB write hits
+system.cpu.dtb.write_misses                      7216                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312268                       # DTB write accesses
-system.cpu.dtb.data_hits                    335843557                       # DTB hits
-system.cpu.dtb.data_misses                     205673                       # DTB misses
+system.cpu.dtb.write_accesses                98312238                       # DTB write accesses
+system.cpu.dtb.data_hits                    335843516                       # DTB hits
+system.cpu.dtb.data_misses                     205683                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336049230                       # DTB accesses
-system.cpu.itb.fetch_hits                   316986664                       # ITB hits
+system.cpu.dtb.data_accesses                336049199                       # DTB accesses
+system.cpu.itb.fetch_hits                   316987000                       # ITB hits
 system.cpu.itb.fetch_misses                       120                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               316986784                       # ITB accesses
+system.cpu.itb.fetch_accesses               316987120                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -317,67 +319,67 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1122097998                       # number of cpu cycles simulated
+system.cpu.numCycles                       1121879794                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      30863568                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      30863449                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.208130                       # CPI: cycles per instruction
-system.cpu.ipc                               0.827726                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1059712720                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        62385278                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.207895                       # CPI: cycles per instruction
+system.cpu.ipc                               0.827887                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1059714780                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        62165014                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            776532                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.688853                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322867255                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4092.723334                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           322867251                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780628                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.599378                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         907886250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.688853                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999192                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999192                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            413.599373                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         899878500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.723334                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999200                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999200                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          952                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         1242                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1642                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648213290                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648213290                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    224703202                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224703202                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164053                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164053                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     322867255                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322867255                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    322867255                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322867255                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         648213288                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        648213288                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    224703201                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       224703201                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164050                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164050                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     322867251                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        322867251                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    322867251                       # number of overall hits
+system.cpu.dcache.overall_hits::total       322867251                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711929                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137147                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137147                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       849076                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849076                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       849076                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849076                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24858122500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24858122500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10112031250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10112031250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34970153750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34970153750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34970153750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34970153750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    225415131                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225415131                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137150                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137150                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       849079                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849079                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       849079                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849079                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24888612000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24888612000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9943107500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9943107500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34831719500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34831719500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34831719500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34831719500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    225415130                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    225415130                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    323716331                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323716331                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323716331                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323716331                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    323716330                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    323716330                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    323716330                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    323716330                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
@@ -386,14 +388,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002623
 system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002623                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41186.129098                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41186.129098                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41022.943095                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41022.943095                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -402,16 +404,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91489                       # number of writebacks
-system.cpu.dcache.writebacks::total             91489                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88848                       # number of writebacks
+system.cpu.dcache.writebacks::total             88848                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          312                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          312                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68136                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68136                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68448                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68448                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68448                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68448                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68139                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68139                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68451                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68451                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68451                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68451                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711617                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711617                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
@@ -420,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780628
 system.cpu.dcache.demand_mshr_misses::total       780628                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780628                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780628                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23712269000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23712269000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5006644750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5006644750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28718913750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28718913750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28718913750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28718913750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24170012500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24170012500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4987370000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4987370000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29157382500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29157382500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29157382500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29157382500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -436,24 +438,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002411
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002411                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33321.673035                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33321.673035                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72548.503137                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72548.503137                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36789.499928                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33964.917224                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33964.917224                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72269.203460                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72269.203460                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37351.187121                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37351.187121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37351.187121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37351.187121                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             10608                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1686.311703                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           316974313                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12350                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25665.936275                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             10610                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1686.330189                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           316974647                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12352                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25661.807562                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1686.311703                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.823394                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.823394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1686.330189                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.823403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.823403                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
@@ -461,44 +463,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2            2
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         633985678                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        633985678                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    316974313                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       316974313                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     316974313                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        316974313                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    316974313                       # number of overall hits
-system.cpu.icache.overall_hits::total       316974313                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12351                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12351                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12351                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12351                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12351                       # number of overall misses
-system.cpu.icache.overall_misses::total         12351                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    355440500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    355440500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    355440500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    355440500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    355440500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    355440500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    316986664                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    316986664                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    316986664                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    316986664                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    316986664                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    316986664                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         633986352                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        633986352                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    316974647                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       316974647                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     316974647                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        316974647                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    316974647                       # number of overall hits
+system.cpu.icache.overall_hits::total       316974647                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12353                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12353                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12353                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12353                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12353                       # number of overall misses
+system.cpu.icache.overall_misses::total         12353                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    352286000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    352286000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    352286000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    352286000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    352286000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    352286000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    316987000                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    316987000                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    316987000                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    316987000                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    316987000                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    316987000                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28778.277063                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28778.277063                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28778.277063                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28778.277063                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28778.277063                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28778.277063                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28518.254675                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28518.254675                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28518.254675                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28518.254675                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28518.254675                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28518.254675                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -507,123 +509,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12351                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12351                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12351                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12351                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    335642500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    335642500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    335642500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    335642500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    335642500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    335642500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12353                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    339934000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    339934000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27175.329933                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27175.329933                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27175.329933                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27175.329933                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27175.329933                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27175.329933                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258742                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32592.002895                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             523848                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291478                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.797213                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259426                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32593.023927                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1218366                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             4.170173                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2882.733111                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    84.797304                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29624.472480                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.087974                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002588                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.904067                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994629                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2589.520333                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.281926                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.079026                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          272                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2658                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29475                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses          7436233                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7436233                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::total         499091                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        91489                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        91489                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         13002157                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13002157                       # Number of data accesses
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+system.cpu.l2cache.Writeback_hits::total        88848                       # number of Writeback hits
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-system.cpu.l2cache.Writeback_accesses::writebacks        91489                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        91489                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69011                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.overall_accesses::cpu.data       780628                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       792979                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.236580                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311902                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.369702                       # miss rate for demand accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76758.384668                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80463.102881                       # average ReadReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78904.889986                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78883.375011                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76758.384668                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78904.889986                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78883.375011                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.440243                       # average ReadExReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76128.038343                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76128.038343                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80705.693047                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80705.693047                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76128.038343                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78909.374838                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78881.571563                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76128.038343                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78909.374838                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78881.571563                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -634,103 +642,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2922                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221955                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       224877                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          453                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          453                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2922                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288600                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291522                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2922                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288600                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291522                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    187662000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  15084314000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15271976000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4079380750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4079380750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    187662000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19163694750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  19351356750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    187662000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19163694750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19351356750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.236580                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311902                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.310617                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2921                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2921                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222640                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222640                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2921                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289285                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292206                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2921                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289285                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292206                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4192533000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4192533000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193170000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193170000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15741915500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15741915500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193170000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19934448500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20127618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193170000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19934448500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20127618500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.236580                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.369702                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.367629                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.236580                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369702                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.367629                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64223.819302                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67961.136266                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67912.574430                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61210.604697                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61210.604697                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64223.819302                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66402.268711                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66380.433552                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64223.819302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66402.268711                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66380.433552                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.236461                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312865                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312865                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368491                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368491                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         723968                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        723967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723969                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       891037                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24701                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652745                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1677446                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55815488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56605888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       884468                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       711617                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35315                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337788                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2373103                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55646464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56436992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259426                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1839549                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.141027                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.348049                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             884468    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1580123     85.90%     85.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             259426     14.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         884468                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      533723000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      19161500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1839549                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      878909500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      18528000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1222147750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1170942000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              224876                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224876                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225560                       # Transaction distribution
 system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191116                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649725                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 649725                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22925056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22925056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225560                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22968832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22968832                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            358204                       # Request fanout histogram
+system.membus.snoop_fanout::samples            550004                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  358204    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  550004    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              358204                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           732288500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1552393250                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              550004                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918579000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1556120750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 887940ec1..7d418bd2e 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.279669                       # Number of seconds simulated
-sim_ticks                                279668927000                       # Number of ticks simulated
-final_tick                               279668927000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.279557                       # Number of seconds simulated
+sim_ticks                                279556845500                       # Number of ticks simulated
+final_tick                               279556845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 172383                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57230702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232716                       # Number of bytes of host memory used
-host_seconds                                  4886.69                       # Real time elapsed on the host
+host_inst_rate                                 180071                       # Simulator instruction rate (inst/s)
+host_op_rate                                   180071                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59759118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307148                       # Number of bytes of host memory used
+host_seconds                                  4678.06                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            176256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18476288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18652544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       176256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          176256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            176320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18520448                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18696768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       176320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          176320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2754                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288692                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291446                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2755                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289382                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292137                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               630231                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             66064858                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                66695089                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          630231                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             630231                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15259872                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15259872                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15259872                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              630231                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            66064858                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               81954961                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291446                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               630713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             66249310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                66880022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          630713                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             630713                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          15265990                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               15265990                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          15265990                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              630713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            66249310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               82146012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292137                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      291446                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292137                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18633664                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18880                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4265984                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18652544                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18678144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18624                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4265920                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18696768                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      295                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      291                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               17911                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18258                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18306                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18250                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18158                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18224                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18321                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18307                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18228                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18015                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18332                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18407                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18336                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18230                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18323                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18299                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               18222                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18213                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18209                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              18393                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18247                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18043                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              17966                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18104                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18246                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18127                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18048                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18184                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6                4262                       # Pe
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4180                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4149                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    279668837500                       # Total gap between requests
+system.physmem.totGap                    279556756000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291446                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292137                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,13 +97,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    215531                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47086                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       198                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    215113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47042                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29481                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2144                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4458                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4969                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -193,117 +193,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       100388                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      228.091007                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     146.320458                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     278.791024                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          35777     35.64%     35.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        42525     42.36%     78.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        10061     10.02%     88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          470      0.47%     88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          508      0.51%     89.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          391      0.39%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          492      0.49%     89.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1510      1.50%     91.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8654      8.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         100388                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4044                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        69.235658                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.129419                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      756.508896                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4037     99.83%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            5      0.12%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4044                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4044                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.482690                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.461191                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.859365                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3072     75.96%     75.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                964     23.84%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  8      0.20%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4044                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3601508250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9060589500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1455755000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12369.90                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        99332                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      230.959771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     149.026626                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.596004                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          34426     34.66%     34.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        42079     42.36%     77.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        10100     10.17%     87.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          831      0.84%     88.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1119      1.13%     89.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          640      0.64%     89.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          198      0.20%     89.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1366      1.38%     91.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8573      8.63%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          99332                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4052                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        69.011846                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.507282                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      732.804018                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4044     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            5      0.12%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4052                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.449901                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.429330                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.841533                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3145     77.62%     77.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                903     22.29%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4052                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3589265250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9061377750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12298.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31119.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          66.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          15.25                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       66.70                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       15.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31048.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          66.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          15.26                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       66.88                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       15.27                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.64                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.52                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     206952                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50458                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   71.08                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                       780916.48                       # Average gap between requests
-system.physmem.pageHitRate                      71.94                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  378650160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  206604750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1136467800                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.19                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     207190                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51966                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   70.99                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.93                       # Row buffer hit rate for writes
+system.physmem.avgGap                       779100.26                       # Average gap between requests
+system.physmem.pageHitRate                      72.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  374756760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  204480375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1139564400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            18266458080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            79892908290                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            97718574000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             197816101560                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.327829                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   162042939000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      9338680000                       # Time in different power states
+system.physmem_0.refreshEnergy            18258829680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80335161315                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            97260556500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             197789787510                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              707.529215                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   161282435500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      9334780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    108285182250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    108932951500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  380207520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  207454500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1134088800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215492400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            18266458080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80233432560                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            97419868500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             197857002360                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              707.474077                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   161543146250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      9338680000                       # Time in different power states
+system.physmem_1.actEnergy                  375943680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  205128000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1135750200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215485920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            18258829680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80056140615                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            97505311500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             197752589595                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              707.396151                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   161684152500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      9334780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    108784975000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    108531075000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               192995150                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         125739221                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11883936                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            145375032                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               127081867                       # Number of BTB hits
+system.cpu.branchPred.lookups               192642813                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         125666016                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11886398                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            146763457                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               126951211                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.416570                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                29018342                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                151                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             86.500559                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                29013974                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                143                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    244533779                       # DTB read hits
-system.cpu.dtb.read_misses                     309591                       # DTB read misses
+system.cpu.dtb.read_hits                    244534581                       # DTB read hits
+system.cpu.dtb.read_misses                     309538                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                244843370                       # DTB read accesses
-system.cpu.dtb.write_hits                   135671849                       # DTB write hits
-system.cpu.dtb.write_misses                     31346                       # DTB write misses
+system.cpu.dtb.read_accesses                244844119                       # DTB read accesses
+system.cpu.dtb.write_hits                   135677576                       # DTB write hits
+system.cpu.dtb.write_misses                     31395                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               135703195                       # DTB write accesses
-system.cpu.dtb.data_hits                    380205628                       # DTB hits
-system.cpu.dtb.data_misses                     340937                       # DTB misses
+system.cpu.dtb.write_accesses               135708971                       # DTB write accesses
+system.cpu.dtb.data_hits                    380212157                       # DTB hits
+system.cpu.dtb.data_misses                     340933                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                380546565                       # DTB accesses
-system.cpu.itb.fetch_hits                   197011138                       # ITB hits
-system.cpu.itb.fetch_misses                       297                       # ITB misses
+system.cpu.dtb.data_accesses                380553090                       # DTB accesses
+system.cpu.itb.fetch_hits                   197116758                       # ITB hits
+system.cpu.itb.fetch_misses                       277                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               197011435                       # ITB accesses
+system.cpu.itb.fetch_accesses               197117035                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -317,238 +320,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                        559337855                       # number of cpu cycles simulated
+system.cpu.numCycles                        559113692                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          202154435                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1649182914                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   192995150                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          156100209                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     344813807                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                24235896                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6519                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           26                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 197011138                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7083229                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          559092875                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.949748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.175515                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          202267120                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1648589560                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   192642813                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155965185                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     344477338                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                24241354                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  146                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          6562                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 197116758                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               7079440                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          558871871                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.949852                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.174628                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                239653225     42.86%     42.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30449692      5.45%     48.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22058642      3.95%     52.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 36467190      6.52%     58.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 68017058     12.17%     70.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 21431579      3.83%     74.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19299153      3.45%     78.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3537365      0.63%     78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                118178971     21.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                239606568     42.87%     42.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30232310      5.41%     48.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 22062681      3.95%     52.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 36416175      6.52%     58.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 68096392     12.18%     70.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 21641580      3.87%     74.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 19299985      3.45%     78.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3539455      0.63%     78.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                117976725     21.11%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            559092875                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.345042                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.948456                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                168803167                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              91739479                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 273671215                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12767829                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               12111185                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             15522167                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  6976                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1584668893                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 25197                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               12111185                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                176688622                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                61751221                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14050                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 278532777                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29995020                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1538585292                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  9438                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2658750                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               20386888                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7267964                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1027382191                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1769248125                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1729530138                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          39717986                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            558871871                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.344550                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.948577                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                168941255                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              91534254                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 273571884                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              12710570                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               12113908                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             15306458                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  6991                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1583914254                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25227                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               12113908                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                176800339                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                61738556                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14140                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 278402636                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29802292                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1538072104                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  9577                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2573672                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               20322038                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7208635                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1027250775                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1768837330                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1729119220                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          39718109                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                388415033                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1375                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            100                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9495582                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            372551032                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           175434243                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          40723012                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11258595                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1304972518                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  89                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1016009395                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           8790765                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       462590577                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    427723515                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             52                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     559092875                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.817246                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.904787                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                388283617                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1370                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             93                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   9395851                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            372336921                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           175495034                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          40680070                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11286315                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1304559063                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  83                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1015639240                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           8789930                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       462177116                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    427685030                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     558871871                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.817302                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.903889                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           200119998     35.79%     35.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            93029621     16.64%     52.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            91384631     16.35%     68.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            59843024     10.70%     79.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            56522593     10.11%     89.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            29852885      5.34%     94.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            17077557      3.05%     97.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7239227      1.29%     99.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4023339      0.72%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           199951896     35.78%     35.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            92994240     16.64%     52.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            91399550     16.35%     68.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            59708328     10.68%     79.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            56828177     10.17%     89.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            29755879      5.32%     94.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            17031836      3.05%     98.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             7177923      1.28%     99.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4024042      0.72%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       559092875                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       558871871                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2463450     10.43%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               15566876     65.90%     76.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5592414     23.67%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2464205     10.45%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               15633751     66.29%     76.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5485030     23.26%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             579702610     57.06%     57.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7931      0.00%     57.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13180646      1.30%     58.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826544      0.38%     58.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             3339801      0.33%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            277022873     27.27%     86.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           138927710     13.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             579358124     57.04%     57.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7924      0.00%     57.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13180764      1.30%     58.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826542      0.38%     58.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             3339800      0.33%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            276992447     27.27%     86.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           138932359     13.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1016009395                       # Type of FU issued
-system.cpu.iq.rate                           1.816450                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23622740                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023251                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2552720615                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1726519951                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    940123896                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            70804555                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           41088367                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34423394                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1003270759                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                36360100                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         50476055                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1015639240                       # Type of FU issued
+system.cpu.iq.rate                           1.816516                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23582986                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023220                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2551718253                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1725674688                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    939925074                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            70805014                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           41106869                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34423614                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1002860612                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                36360338                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         50469534                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    135040435                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      1174528                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        45615                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     77133043                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    134826324                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      1160001                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        45767                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     77193834                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2509                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4123                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2684                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4171                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               12111185                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                60760024                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                216464                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1479434002                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             17901                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             372551032                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            175434243                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 87                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  21559                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                205996                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          45615                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       11877701                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        16644                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11894345                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             976302878                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             244843546                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          39706517                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               12113908                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                60768232                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                187260                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1479124792                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             20793                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             372336921                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            175495034                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 81                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  15841                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                182755                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          45767                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       11880363                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        16467                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11896830                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             976089984                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             244844291                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          39549256                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     174461395                       # number of nop insts executed
-system.cpu.iew.exec_refs                    380547191                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                129259483                       # Number of branches executed
-system.cpu.iew.exec_stores                  135703645                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.745462                       # Inst execution rate
-system.cpu.iew.wb_sent                      975066188                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     974547290                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 556173359                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 831980820                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     174565646                       # number of nop insts executed
+system.cpu.iew.exec_refs                    380553668                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                129052167                       # Number of branches executed
+system.cpu.iew.exec_stores                  135709377                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.745781                       # Inst execution rate
+system.cpu.iew.wb_sent                      974867255                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     974348688                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 556190036                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 832343662                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.742323                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.668493                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.742666                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.668222                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       543601549                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       543293982                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          11877174                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    486379014                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.909185                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.596644                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          11879630                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    486147412                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.910095                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.597279                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    208258289     42.82%     42.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    102386957     21.05%     63.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     51676822     10.62%     74.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     25636051      5.27%     79.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     21554637      4.43%     84.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      9250657      1.90%     86.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10396507      2.14%     88.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6664753      1.37%     89.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     50554341     10.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    208054375     42.80%     42.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    102342395     21.05%     63.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51700065     10.63%     74.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     25702081      5.29%     79.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     21547094      4.43%     84.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      9129205      1.88%     86.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10401484      2.14%     88.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6670149      1.37%     89.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     50600564     10.41%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    486379014                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    486147412                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -594,345 +597,335 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              50554341                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1905392712                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3017093514                       # The number of ROB writes
-system.cpu.timesIdled                            3164                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          244980                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              50600564                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1904807320                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3016488956                       # The number of ROB writes
+system.cpu.timesIdled                            3196                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          241821                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.663995                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.663995                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.506034                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.506034                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1237178642                       # number of integer regfile reads
-system.cpu.int_regfile_writes               705781417                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36689419                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24410667                       # number of floating regfile writes
+system.cpu.cpi                               0.663729                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.663729                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.506638                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.506638                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237184723                       # number of integer regfile reads
+system.cpu.int_regfile_writes               705784215                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36689750                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24410793                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            777209                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.895157                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           289903947                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            781305                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            371.050930                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         374093250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.895157                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999242                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999242                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            777216                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.910211                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           289913128                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            781312                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            371.059357                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         371553500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.910211                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999246                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999246                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2495                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2498                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4          253                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         585486411                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        585486411                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    192496951                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       192496951                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97406971                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97406971                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           25                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           25                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     289903922                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        289903922                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    289903922                       # number of overall hits
-system.cpu.dcache.overall_hits::total       289903922                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1554376                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1554376                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       894229                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       894229                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2448605                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2448605                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2448605                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2448605                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  84529453750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  84529453750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  62304618080                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  62304618080                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       100250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       100250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 146834071830                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 146834071830                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 146834071830                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 146834071830                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    194051327                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    194051327                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         585500596                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        585500596                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    192503314                       # number of ReadReq hits
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 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           26                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           26                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    292352527                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    292352527                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    292352527                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    292352527                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008010                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008010                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009097                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009097                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038462                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038462                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008376                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008376                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008376                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008376                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       100250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       100250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59966.418361                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59966.418361                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        21964                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        69527                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               343                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           24                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008014                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008014                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009068                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009068                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008368                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008368                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008368                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008368                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59477.321953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59477.321953                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        22265                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        67906                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               347                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets             515                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.034985                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   135.003883                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.164265                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   131.856311                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91524                       # number of writebacks
-system.cpu.dcache.writebacks::total             91524                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       841911                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       841911                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       825390                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       825390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1667301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1667301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1667301                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1667301                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712465                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712465                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68839                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        68839                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       781304                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       781304                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       781304                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       781304                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23794966500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23794966500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5675142998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5675142998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        98250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        98250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29470109498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29470109498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29470109498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29470109498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003672                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003672                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks        88850                       # number of writebacks
+system.cpu.dcache.writebacks::total             88850                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842619                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       842619                       # number of ReadReq MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total       712485                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68827                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68827                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       781312                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       781312                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       781312                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       781312                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24145312000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24145312000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5651970498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5651970498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29797282498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29797282498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29797282498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29797282498                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003671                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003671                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.038462                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.038462                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002672                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002672                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002672                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002672                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        98250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        98250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4665                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1651.262169                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           197002801                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6374                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30907.248353                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4695                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1651.888032                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           197108400                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6404                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          30778.950656                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1651.262169                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.806280                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.806280                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1651.888032                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.806586                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.806586                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1709                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1547                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024     0.834473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         394028650                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        394028650                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    197002801                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       197002801                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     197002801                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        197002801                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    197002801                       # number of overall hits
-system.cpu.icache.overall_hits::total       197002801                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8337                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8337                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8337                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8337                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8337                       # number of overall misses
-system.cpu.icache.overall_misses::total          8337                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    359956749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    359956749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    359956749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    359956749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    359956749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    359956749                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    197011138                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::cpu.inst    197011138                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    197011138                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         394239920                       # Number of tag accesses
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43175.812522                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43175.812522                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          938                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42453.996052                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42453.996052                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          620                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    62.533333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    56.363636                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1962                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1962                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1962                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1962                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1962                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1962                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6375                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6375                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6375                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6375                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6375                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6375                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    264410499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    264410499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    264410499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    264410499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    264410499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    264410499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1953                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_latency::total    268250499                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total    268250499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41476.156706                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41476.156706                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41476.156706                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41476.156706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41476.156706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41476.156706                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41881.420609                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 41881.420609                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41881.420609                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258668                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32630.441536                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             518837                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291405                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.780467                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259359                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32631.025486                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1208176                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292097                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.136215                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2805.006533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    68.921998                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29756.513005                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.085602                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002103                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.908097                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995802                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32737                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  2513.776004                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    69.329948                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30047.919535                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.076714                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002116                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          160                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          531                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26536                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999054                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          7393876                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7393876                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3620                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       490402                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         494022                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        91524                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        91524                       # number of Writeback hits
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+system.cpu.l2cache.overall_avg_miss_latency::total 81036.564911                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -943,103 +936,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
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+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          405                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66628                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66628                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312644                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312644                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.430289                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370380                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.370867                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.430289                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370380                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.370867                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72928.415981                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72928.415981                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69939.404935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70484.312291                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70484.312291                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71047.048538                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71036.599142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71047.048538                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71036.599142                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         718841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        718840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        68839                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        68839                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12749                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1654134                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1666883                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       407936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55861056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56268992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       879204                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        718889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155533                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       885737                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6405                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712485                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17504                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339840                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2357344                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       409856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55690368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56100224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259359                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1828987                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.141805                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.348850                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             879204    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1569628     85.82%     85.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             259359     14.18%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         879204                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      531126000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10103500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1828987                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      873664000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       9606000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1213595000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1171968000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              224818                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224818                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225509                       # Transaction distribution
 system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191067                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66628                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66628                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 649575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22920256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22920256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225509                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842024                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842024                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22964480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22964480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            358129                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549887                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  358129    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549887    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              358129                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           682357500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1548216750                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              549887                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           853984000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1551628500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index eff48cf7e..07561ac8e 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.286250                       # Number of seconds simulated
-sim_ticks                                1286249817500                       # Number of ticks simulated
-final_tick                               1286249817500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.286279                       # Number of seconds simulated
+sim_ticks                                1286278511500                       # Number of ticks simulated
+final_tick                               1286278511500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1412500                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1412500                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1956550284                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303116                       # Number of bytes of host memory used
-host_seconds                                   657.41                       # Real time elapsed on the host
+host_inst_rate                                1355944                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1355944                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1878251411                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303804                       # Number of bytes of host memory used
+host_seconds                                   684.83                       # Real time elapsed on the host
 sim_insts                                   928587629                       # Number of instructions simulated
 sim_ops                                     928587629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18465664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18603456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18509184                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18646976                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       137792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          137792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               2153                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288526                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                290679                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289206                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291359                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               107127                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             14356203                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14463330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          107127                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107127                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3317950                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3317950                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3317950                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              107127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            14356203                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17781280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107125                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14389717                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14496842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107125                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107125                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3317876                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3317876                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3317876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107125                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            14389717                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17814717                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       2572499635                       # number of cpu cycles simulated
+system.cpu.numCycles                       2572557023                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928587629                       # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs                     336013318                       # nu
 system.cpu.num_load_insts                   237705247                       # Number of load instructions
 system.cpu.num_store_insts                   98308071                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 2572499635                       # Number of busy cycles
+system.cpu.num_busy_cycles                 2572557023                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         123111018                       # Number of branches fetched
@@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  928789150                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            776432                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.261321                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4094.261358                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           335031269                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780528                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            429.236708                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1046537000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.261321                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle        1046537500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.261358                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999576                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999576                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data       780528                       # n
 system.cpu.dcache.demand_misses::total         780528                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       780528                       # number of overall misses
 system.cpu.dcache.overall_misses::total        780528                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18568558000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18568558000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3696398000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3696398000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22264956000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22264956000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22264956000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22264956000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18597166000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18597166000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3696410000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3696410000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22293576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22293576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22293576000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22293576000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    237510597                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    237510597                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002324
 system.cpu.dcache.demand_miss_rate::total     0.002324                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002324                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002324                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28525.505811                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28525.505811                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28562.173298                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28562.173298                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91660                       # number of writebacks
-system.cpu.dcache.writebacks::total             91660                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        89031                       # number of writebacks
+system.cpu.dcache.writebacks::total             89031                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711514                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711514                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69014                       # number of WriteReq MSHR misses
@@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780528
 system.cpu.dcache.demand_mshr_misses::total       780528                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780528                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780528                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17501287000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17501287000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3592877000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3592877000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21094164000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21094164000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21094164000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21094164000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17885652000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17885652000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3627396000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3627396000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21513048000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21513048000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21513048000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21513048000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002996                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002996                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -228,22 +228,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002324
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002324                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002324                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002324                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4618                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1474.486238                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1474.486224                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           928782983                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              6168                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          150580.898671                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1474.486238                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1474.486224                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.719964                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.719964                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1550                       # Occupied blocks per task id
@@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst         6168                       # n
 system.cpu.icache.demand_misses::total           6168                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         6168                       # number of overall misses
 system.cpu.icache.overall_misses::total          6168                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    170610500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    170610500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    170610500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    170610500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    170610500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    170610500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    170684500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    170684500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    170684500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    170684500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    170684500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    170684500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    928789151                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    928789151                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    928789151                       # number of demand (read+write) accesses
@@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000007
 system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27660.586900                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27660.586900                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27672.584306                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27672.584306                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,38 +304,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         6168
 system.cpu.icache.demand_mshr_misses::total         6168                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         6168                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         6168                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    161358500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    161358500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    161358500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    161358500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    161358500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    161358500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    164516500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    164516500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    164516500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    164516500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    164516500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    164516500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000007                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           257900                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32657.894008                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             518578                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           290634                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.784299                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258580                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32657.927159                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1207050                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291314                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.143467                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2768.249705                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.156527                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.084480                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001531                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.910629                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996640                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2486.879631                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.811890                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.075894                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001520                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.919227                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996641                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
@@ -343,78 +343,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          117
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1144                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31198                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          7386496                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7386496                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4015                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       489636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         493651                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        91660                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        91660                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         12902296                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12902296                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks        89031                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        89031                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4015                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         4015                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488956                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       488956                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         4015                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       492002                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          496017                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       491322                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.inst         4015                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       492002                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         496017                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2153                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       221878                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       224031                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::cpu.data       491322                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         495337                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66648                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66648                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2153                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2153                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222558                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222558                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2153                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       288526                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        290679                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289206                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst         2153                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       288526                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       290679                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    113033000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11648595000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  11761628000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3499020000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3499020000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    113033000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15147615000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  15260648000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    113033000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15147615000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15260648000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6168                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       711514                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       717682                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        91660                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        91660                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data       289206                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       291359                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3499032000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3499032000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    113105000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    113105000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11684343000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  11684343000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    113105000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  15183375000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15296480000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    113105000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  15183375000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15296480000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks        89031                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        89031                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69014                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69014                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6168                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         6168                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711514                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       711514                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         6168                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       780528                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       786696                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         6168                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       780528                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       786696                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.349060                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311839                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.312159                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965717                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.965717                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.349060                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.349060                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312795                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312795                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.349060                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.369655                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.369493                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370526                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.370358                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.349060                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.369655                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.369493                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370526                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.370358                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -425,103 +431,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2153                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221878                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       224031                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          238                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          238                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66648                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66648                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2153                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2153                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222558                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222558                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288526                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       290679                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289206                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291359                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2153                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288526                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       290679                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     87196500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8986059000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9073255500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2699244000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2699244000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     87196500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11685303000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11772499500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     87196500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11685303000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11772499500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311839                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.312159                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289206                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291359                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2832552000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2832552000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     91575000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     91575000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9458763000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9458763000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     91575000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12291315000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12382890000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     91575000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12291315000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12382890000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965717                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965717                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.349060                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312795                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312795                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.369655                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.369493                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370526                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.370358                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369655                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.369493                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370526                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.370358                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         717682                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        717682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91660                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155714                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       883916                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69014                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69014                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12336                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652716                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1665052                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6168                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       711514                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        16954                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337488                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2354442                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       394752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55820032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56214784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       878356                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55651776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56046528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258580                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1826326                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.141585                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.348624                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             878356    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1567746     85.84%     85.84% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             258580     14.16%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         878356                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      530838000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1826326                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      872904000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       9252000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1170792000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              224031                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224031                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224711                       # Transaction distribution
 system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190417                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66648                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66648                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       648041                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 648041                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22871168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22871168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        224711                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839818                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839818                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22914688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22914688                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            357362                       # Request fanout histogram
+system.membus.snoop_fanout::samples            548514                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  357362    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  548514    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              357362                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           636219000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1453395500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              548514                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           815261292                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1456808792                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 5b9278fb0..cc0a8b561 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.541773                       # Number of seconds simulated
-sim_ticks                                541773299500                       # Number of ticks simulated
-final_tick                               541773299500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.541068                       # Number of seconds simulated
+sim_ticks                                541067717500                       # Number of ticks simulated
+final_tick                               541067717500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180126                       # Simulator instruction rate (inst/s)
-host_op_rate                                   221759                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              152324877                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323140                       # Number of bytes of host memory used
-host_seconds                                  3556.70                       # Real time elapsed on the host
+host_inst_rate                                 180313                       # Simulator instruction rate (inst/s)
+host_op_rate                                   221989                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152283805                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322972                       # Number of bytes of host memory used
+host_seconds                                  3553.02                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            164800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18429120                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18593920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       164800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          164800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            164736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18470272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18635008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       164736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          164736                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2575                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             287955                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                290530                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2574                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288598                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291172                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               304186                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             34016294                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34320481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          304186                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             304186                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7808196                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7808196                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7808196                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              304186                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            34016294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42128676                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        290530                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               304465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             34136710                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34441175                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          304465                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             304465                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7818378                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7818378                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7818378                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              304465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            34136710                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42259553                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291172                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      290530                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291172                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18574272                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228608                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18593920                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18613824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228224                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18635008                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      307                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18288                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18136                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18223                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18182                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18272                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18313                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18098                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17913                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               17942                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               17963                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18020                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18117                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18146                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18079                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18260                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4100                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4225                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18127                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18214                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18173                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18274                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18402                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18180                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17989                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18022                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18061                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18102                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18198                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18215                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18265                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18078                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18259                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4092                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    541773205000                       # Total gap between requests
+system.physmem.totGap                    541067624000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  290530                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291172                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    289832                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       376                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290452                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       372                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,96 +193,94 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       112123                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      203.355529                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     132.415015                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     254.574164                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          47170     42.07%     42.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43612     38.90%     80.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9039      8.06%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1917      1.71%     90.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          483      0.43%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          738      0.66%     91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          730      0.65%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          502      0.45%     92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7932      7.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         112123                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4009                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.524570                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.058155                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      507.570273                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4006     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       110882                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      205.996862                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     134.129754                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.860056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45611     41.13%     41.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43911     39.60%     80.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9208      8.30%     89.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1504      1.36%     90.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          772      0.70%     91.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          428      0.39%     91.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          846      0.76%     92.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          594      0.54%     92.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8008      7.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         110882                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.509335                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.234035                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.719748                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4009                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4009                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.480918                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.459590                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.855706                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3046     75.98%     75.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                961     23.97%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4009                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2883248250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8324929500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1451115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9934.60                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.446602                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.426400                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.833021                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3120     77.67%     77.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                897     22.33%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3065169000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8518437750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454205000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10538.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28684.60                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          34.28                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29288.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          34.40                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.81                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       34.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.81                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       34.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194064                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50094                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   66.87                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1519154.99                       # Average gap between requests
-system.physmem.pageHitRate                      68.52                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  423874080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  231280500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1134198000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215622000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35385604800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           107588305125                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           230684814750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             375663699255                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.403859                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   383052702750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18090800000                       # Time in different power states
+system.physmem.avgWrQLen                        28.63                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     194425                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51597                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   66.85                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1514450.20                       # Average gap between requests
+system.physmem.pageHitRate                      68.93                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  420041160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  229189125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1135976400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           108869403780                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           229140586500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             375350562645                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              693.723181                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   380482098250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18067400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    140624192250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    142518050750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  423692640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  231181500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1129104600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212524560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35385604800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           107075040930                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           231135046500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             375592195530                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              693.271876                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   383804077000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18090800000                       # Time in different power states
+system.physmem_1.actEnergy                  418226760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  228199125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1132497600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212576400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           107776907010                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           230098917000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             375207158295                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              693.458141                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   382081982750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18067400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    139874284500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    140917403500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               156119313                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         106151666                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12881666                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90098747                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                82494804                       # Number of BTB hits
+system.cpu.branchPred.lookups               157565509                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         107229273                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12892751                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             98103751                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                81778311                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.560434                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19276925                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1327                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.359005                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19318729                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1315                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -401,69 +399,69 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1083546599                       # number of cpu cycles simulated
+system.cpu.numCycles                       1082135435                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      23911488                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      23942424                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.691310                       # CPI: cycles per instruction
-system.cpu.ipc                               0.591258                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1025165387                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        58381212                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            778275                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.437677                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378454072                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782371                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.727122                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         802618250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.437677                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999130                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999130                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.689108                       # CPI: cycles per instruction
+system.cpu.ipc                               0.592029                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1024380125                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        57755310                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778330                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.458630                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378454621                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782426                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.693820                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         795587500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.458630                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999135                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999135                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          963                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1345                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1346                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1586                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759393811                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759393811                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249625343                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249625343                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128813766                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128813766                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         759395078                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759395078                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249625893                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249625893                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3485                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3485                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378439109                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378439109                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378442594                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378442594                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713796                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713796                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137711                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137711                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     378439658                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378439658                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378443143                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378443143                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       713852                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713852                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       851507                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851507                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851648                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851648                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24839025218                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24839025218                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10202615750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10202615750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35041640968                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35041640968                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35041640968                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35041640968                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250339139                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250339139                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       851564                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851564                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       851705                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851705                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24973506500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24973506500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10064105500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10064105500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35037612000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35037612000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35037612000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35037612000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250339745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250339745                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         3626                       # number of SoftPFReq accesses(hits+misses)
@@ -472,12 +470,12 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739
 system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379290616                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379290616                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379294242                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379294242                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002851                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    379291222                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379291222                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379294848                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379294848                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038886                       # miss rate for SoftPFReq accesses
@@ -486,14 +484,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002245
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002245                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34798.493152                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34798.493152                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74087.151716                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74087.151716                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41152.499002                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41152.499002                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41145.685739                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41145.685739                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41145.013176                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41138.201607                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -502,36 +500,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
-system.cpu.dcache.writebacks::total             91420                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          886                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          886                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68389                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68389                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        69275                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69275                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        69275                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69275                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712910                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712910                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks        88940                       # number of writebacks
+system.cpu.dcache.writebacks::total             88940                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          887                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          887                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total        69277                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        69277                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69277                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712965                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712965                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782232                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782232                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782371                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782371                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23683196777                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23683196777                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5051765250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5051765250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1719000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1719000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28734962027                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28734962027                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28736681027                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28736681027                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       782287                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782287                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782426                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782426                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24245308500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24245308500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5047418500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5047418500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29292727000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29292727000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29294515000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29294515000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -542,69 +540,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33220.458090                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33220.458090                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72873.910880                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72873.910880                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36734.577500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36734.577500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36730.248216                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36730.248216                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             23596                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1712.059457                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           290105857                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25347                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11445.372510                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             23593                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1712.048816                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           288484492                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             25344                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11382.752999                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1712.059457                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835967                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835967                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1712.048816                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835961                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835961                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1602                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1603                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         580287757                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        580287757                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    290105857                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       290105857                       # number of ReadReq hits
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-system.cpu.icache.overall_hits::total       290105857                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25348                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25348                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total          25348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25348                       # number of overall misses
-system.cpu.icache.overall_misses::total         25348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    499853745                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    499853745                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    499853745                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    499853745                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    499853745                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    499853745                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    290131205                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    290131205                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    290131205                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    290131205                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19719.652241                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19719.652241                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19719.652241                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19719.652241                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19719.652241                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19719.652241                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         577045018                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        577045018                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    288484492                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total         25345                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    499936000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst    288509837                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::cpu.inst    288509837                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    288509837                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000088                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000088                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000088                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000088                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000088                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000088                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19725.231801                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19725.231801                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -613,123 +611,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25348                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25348                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total        25348                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    460727755                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    460727755                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    460727755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    460727755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    460727755                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    460727755                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18176.098903                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18176.098903                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18176.098903                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18176.098903                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18176.098903                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18176.098903                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_latency::total    474592000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    474592000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    474592000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    474592000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    474592000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000088                       # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total     0.000088                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           257750                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32572.840203                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             539129                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2880.993603                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    89.456847                       # Average occupied blocks per requestor
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-system.cpu.l2cache.Writeback_hits::total        91420                       # number of Writeback hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,112 +744,124 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4248598000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4248598000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    171535500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    171535500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15799227000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15799227000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171535500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20047825000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20219360500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171535500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20047825000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20219360500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101625                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368054                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.359693                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101625                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368054                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.359693                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63562.888199                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67777.834619                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67729.457762                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62340.897399                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62340.897399                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63562.888199                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66529.956938                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66503.649352                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63562.888199                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66529.956938                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66503.649352                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101598                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312026                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312026                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.360465                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.360465                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         738397                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        738396                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        738448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155038                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       901935                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50695                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1656162                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1706857                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55922624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57544832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       899139                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        25345                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       713104                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        72953                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341169                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2414122                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55767424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57389440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258392                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1868086                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.138319                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.345235                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             899139    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1609694     86.17%     86.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             258392     13.83%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         899139                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      540989500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38573245                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1868086                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      893787000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      38017996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1224491973                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1173652972                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              224439                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224439                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225081                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190637                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 647158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22824192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225081                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839079                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839079                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22865280                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22865280                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            356628                       # Request fanout histogram
+system.membus.snoop_fanout::samples            547907                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  356628    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  547907    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              356628                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           731800000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1550863750                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              547907                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           916769500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1554235250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index bdaafd38c..95f0885fc 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,81 +1,81 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.409388                       # Number of seconds simulated
-sim_ticks                                409388416000                       # Number of ticks simulated
-final_tick                               409388416000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.410927                       # Number of seconds simulated
+sim_ticks                                410926760000                       # Number of ticks simulated
+final_tick                               410926760000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93306                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114872                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59624294                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320320                       # Number of bytes of host memory used
-host_seconds                                  6866.13                       # Real time elapsed on the host
+host_inst_rate                                  92513                       # Simulator instruction rate (inst/s)
+host_op_rate                                   113896                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59339858                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320156                       # Number of bytes of host memory used
+host_seconds                                  6924.97                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            226560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7024000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12938624                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             20189184                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       226560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          226560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4245888                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4245888                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3540                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             109750                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       202166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                315456                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66342                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66342                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               553411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17157300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     31604763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                49315475                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          553411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             553411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          10371295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               10371295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          10371295                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              553411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17157300                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     31604763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59686769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        315456                       # Number of read requests accepted
-system.physmem.writeReqs                        66342                       # Number of write requests accepted
-system.physmem.readBursts                      315456                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66342                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 20169600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4238784                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  20189184                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4245888                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      306                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      81                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             19                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19899                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19575                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               19715                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               19833                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19635                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20130                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19631                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19419                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19547                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19463                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19540                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19765                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19604                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              19959                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19457                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              19978                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4260                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4107                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4142                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4156                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4244                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst            227008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7012480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12950080                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             20189568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       227008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          227008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4245632                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4245632                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3547                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             109570                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       202345                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                315462                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66338                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66338                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               552429                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17065036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     31514326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                49131792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          552429                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             552429                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          10331846                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               10331846                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          10331846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              552429                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17065036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     31514326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               59463638                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        315462                       # Number of read requests accepted
+system.physmem.writeReqs                        66338                       # Number of write requests accepted
+system.physmem.readBursts                      315462                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66338                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 20169664                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4239360                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  20189568                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4245632                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      69                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               19798                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19540                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               19718                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               19803                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19742                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20227                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19591                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19445                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19492                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19431                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19416                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19789                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19620                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              20020                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19553                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19966                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4272                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4105                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4143                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4154                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
@@ -83,38 +83,38 @@ system.physmem.perBankWrBursts::11               4097                       # Pe
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4150                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4151                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    409388361500                       # Total gap between requests
+system.physmem.totGap                    410926705500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  315456                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  315462                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66342                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    122394                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    117234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6795                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6485                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7459                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8460                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      8297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     10473                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     3291                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2480                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1879                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1340                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66338                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    125674                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    115954                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14051                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6709                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6515                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7602                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8811                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      9422                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      8719                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4043                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1569                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      985                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,165 +148,167 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4978                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       136710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      178.527277                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     128.653997                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     198.191580                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54126     39.59%     39.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        57414     42.00%     81.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14737     10.78%     92.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1353      0.99%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1490      1.09%     94.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1455      1.06%     95.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1216      0.89%     96.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1169      0.86%     97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3750      2.74%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         136710                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4038                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        65.701585                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.708310                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      449.952316                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3996     98.96%     98.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023           21      0.52%     99.48% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            8      0.20%     99.68% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            4      0.10%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-4607            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-5119            1      0.02%     99.88% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       136743                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      178.487469                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     128.645908                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     198.261259                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54158     39.61%     39.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        57478     42.03%     81.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        14696     10.75%     92.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1431      1.05%     93.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1373      1.00%     94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1481      1.08%     95.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1196      0.87%     96.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1150      0.84%     97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3780      2.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         136743                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4027                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        66.735038                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.718214                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      464.978559                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            3992     99.13%     99.13% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023           15      0.37%     99.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            4      0.10%     99.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            3      0.07%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            4      0.10%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            2      0.05%     99.88% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-5631            1      0.02%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9728-10239            1      0.02%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-14847            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15872-16383            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4038                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4038                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.401932                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.368431                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.138933                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3429     84.92%     84.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  6      0.15%     85.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                436     10.80%     95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 81      2.01%     97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 33      0.82%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 20      0.50%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 10      0.25%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  9      0.22%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.05%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  6      0.15%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  2      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  2      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4038                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9474850817                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15383913317                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1575750000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       30064.58                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::8192-8703            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13824-14335            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            2      0.05%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4027                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4027                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.448969                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.407245                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.299266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3382     83.98%     83.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     84.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                453     11.25%     95.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                103      2.56%     97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 20      0.50%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 19      0.47%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 10      0.25%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.27%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  8      0.20%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  5      0.12%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.07%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.10%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4027                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8985315314                       # Total ticks spent queuing
+system.physmem.totMemAccLat               14894396564                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1575755000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28511.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  48814.58                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          49.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          10.35                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       49.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       10.37                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47261.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          49.08                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          10.32                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       49.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       10.33                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.47                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.46                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     218195                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     26465                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.24                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1072264.29                       # Average gap between requests
-system.physmem.pageHitRate                      64.15                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  518729400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  283036875                       # Energy for precharge commands per rank (pJ)
+system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.12                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     218304                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     26331                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.27                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1076287.86                       # Average gap between requests
+system.physmem.pageHitRate                      64.14                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  518260680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  282781125                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1231058400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216470880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96374211480                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           161092645500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             286455220215                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              699.719632                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   267357262270                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13670280000                       # Time in different power states
+system.physmem_0.writeEnergy                216522720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26839254000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            96516777600                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           161887922250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             287492576775                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              699.632177                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   268678979341                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13721500000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    128358277730                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    128519138159                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  514722600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  280850625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1226721600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96210213075                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           161236503750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             286420785330                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              699.635519                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   267597865087                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13670280000                       # Time in different power states
+system.physmem_1.actEnergy                  515334960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  281184750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1226448600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212712480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26839254000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            96027774030                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           162316872750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             287419581570                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              699.454538                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   269400106911                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13721500000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    128117581163                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    127799659089                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               233960267                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         161822378                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514618                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            121575807                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               108259798                       # Number of BTB hits
+system.cpu.branchPred.lookups               233961600                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         161823435                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15514478                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            121576875                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               108260850                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.047156                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25036830                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300193                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.047239                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25036809                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1300056                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -425,129 +427,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        818776833                       # number of cpu cycles simulated
+system.cpu.numCycles                        821853521                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           84080281                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200690651                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   233960267                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133296628                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     718834157                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31063665                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2157                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           85352108                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1200709266                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   233961600                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133297659                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     720636600                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31063377                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2846                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3294                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 370702196                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652814                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          818451752                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.833525                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.163546                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3322                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 370706156                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                652600                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          821526595                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.826688                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.166658                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                136786252     16.71%     16.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                223134631     27.26%     43.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 98075133     11.98%     55.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                360455736     44.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                139803220     17.02%     17.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                223204281     27.17%     44.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 98088574     11.94%     56.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                360430520     43.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            818451752                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.285744                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.466444                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                119992574                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             159648734                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484662553                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38629739                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518152                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             25181029                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13828                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248127732                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39967182                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518152                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                177000175                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                78889127                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         210704                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464955834                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              81877760                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190635501                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              25549976                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24948594                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2267380                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41534187                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1694237                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1225376861                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5812387733                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358166990                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876517                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            821526595                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.284676                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.460977                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                121268240                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             161448420                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 484660246                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              38631680                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15518009                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             25181996                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13829                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1248138563                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              39966565                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15518009                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                178275276                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                80711720                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         210548                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 464319817                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              82491225                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1190650018                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              25545971                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              24926226                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2267555                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               41530027                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1673344                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1225393242                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5812447453                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1358179782                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          40876479                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                350598631                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7265                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                350615012                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               7270                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108139973                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            366113111                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236095933                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1592417                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5322589                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1168545131                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12357                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017136914                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18518110                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       379832530                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1032101126                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            203                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     818451752                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.242757                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.084999                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                 108779302                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            366116842                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           236096763                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1776884                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5334939                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1168558899                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12359                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1017090766                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          18380245                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       379846300                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1032153355                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            205                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     821526595                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.238050                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.084805                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           260802028     31.87%     31.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227738086     27.83%     59.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           216482422     26.45%     86.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            97282889     11.89%     98.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16146318      1.97%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                   9      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           263868507     32.12%     32.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           227113166     27.65%     59.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           217783209     26.51%     86.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            96635677     11.76%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16126029      1.96%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                   7      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       818451752                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       821526595                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                64511713     19.12%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18146      0.01%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              155540667     46.10%     65.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116678907     34.58%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                63875827     18.90%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              157407577     46.57%     65.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite             116033793     34.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456370990     44.87%     44.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5195830      0.51%     45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             456370958     44.87%     44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5195826      0.51%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
@@ -569,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550148      0.25%     46.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478993      1.13%     47.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322128333     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215587418     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478994      1.13%     47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            322082825     31.67%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           215586812     21.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017136914                       # Type of FU issued
-system.cpu.iq.rate                           1.242264                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   337386322                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.331702                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3146752970                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1504842539                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934271199                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61877042                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565869                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     26152443                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1320712886                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33810350                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9960171                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1017090766                       # Type of FU issued
+system.cpu.iq.rate                           1.237557                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   337972229                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.332293                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3150183586                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1504870139                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    934273978                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            61877015                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           43565815                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     26152444                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1321252671                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                33810324                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          9960626                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    113872173                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1090                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18393                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107115437                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    113875904                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1099                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18399                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    107116267                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065797                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22350                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2065816                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         20694                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518152                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35325436                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 42128                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1168563042                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               15518009                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35327000                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 41213                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1168576814                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             366113111                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236095933                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6617                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    102                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 45749                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18393                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437385                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784510                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.iewDispLoadInsts             366116842                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            236096763                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6619                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    114                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 44806                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18399                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15437241                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3784654                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts             19221895                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974751184                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303297622                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42385730                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             974751722                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             303298002                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          42339044                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          5554                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497765238                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150613469                       # Number of branches executed
-system.cpu.iew.exec_stores                  194467616                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.190497                       # Inst execution rate
-system.cpu.iew.wb_sent                      963723937                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960423642                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536680583                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893282195                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          5556                       # number of nop insts executed
+system.cpu.iew.exec_refs                    497764632                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                150613642                       # Number of branches executed
+system.cpu.iew.exec_stores                  194466630                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.186041                       # Inst execution rate
+system.cpu.iew.wb_sent                      963724701                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     960426422                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 536047355                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 893284415                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.172998                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.600796                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.168610                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.600086                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       357407209                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       357420349                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500938                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    767631497                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.027485                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.786864                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15500799                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    770704967                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.023388                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.776993                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    430923455     56.14%     56.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    172477669     22.47%     78.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     73566542      9.58%     88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     31624094      4.12%     92.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8540357      1.11%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14250532      1.86%     95.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7269334      0.95%     96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6619169      0.86%     97.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22360345      2.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    432077450     56.06%     56.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    174390434     22.63%     78.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     72936884      9.46%     88.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     32898197      4.27%     92.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8538905      1.11%     93.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14258273      1.85%     95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7269904      0.94%     96.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5974492      0.78%     97.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22360428      2.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    767631497                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    770704967                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -698,383 +700,389 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22360345                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1891399680                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343098733                       # The number of ROB writes
-system.cpu.timesIdled                          647345                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          325081                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              22360428                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1894486207                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2343126387                       # The number of ROB writes
+system.cpu.timesIdled                          647317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          326926                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.278042                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.278042                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.782447                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.782447                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995806519                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567906159                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  31889841                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 22959492                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794435468                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384898950                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715817595                       # number of misc regfile reads
+system.cpu.cpi                               1.282845                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.282845                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.779518                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.779518                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                995802121                       # number of integer regfile reads
+system.cpu.int_regfile_writes               567908278                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  31889840                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 22959495                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                3794438886                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                384898194                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               715817246                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           2756184                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.932971                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414226712                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           511.933712                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           414215984                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.262021                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         257775000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.932971                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            150.258129                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         256316000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.933712                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999871                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999871                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          224                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839343984                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839343984                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286295259                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286295259                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127916705                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127916705                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3174                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3174                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         839346446                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        839346446                       # Number of data accesses
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 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414211964                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414211964                       # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total       414215138                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3031608                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3031608                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1034772                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1034772                       # number of WriteReq misses
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 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4066380                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4066380                       # number of demand (read+write) misses
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-system.cpu.dcache.ReadReq_miss_latency::cpu.data  35305181420                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  35305181420                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9981703626                       # number of WriteReq miss cycles
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-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       189500                       # number of LoadLockedReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total  45286885046                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45286885046                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45286885046                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289326867                       # number of ReadReq accesses(hits+misses)
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 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3821                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3821                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
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 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418278344                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418278344                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418282165                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418282165                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010478                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.010478                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008025                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008025                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169327                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.169327                       # miss rate for SoftPFReq accesses
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010488                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.010488                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008094                       # miss rate for WriteReq accesses
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+system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009722                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009722                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009723                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9646.283071                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9646.283071                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11136.904334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11135.132628                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009750                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009750                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009752                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009752                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9493.442396                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9493.442396                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11068.834844                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11067.081827                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       343566                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       326278                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            5188                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4869                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    66.223207                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    67.011296                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       735673                       # number of writebacks
-system.cpu.dcache.writebacks::total            735673                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       996399                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       996399                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       313907                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       313907                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       735190                       # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999322                       # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total       322910                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1310306                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1310306                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1310306                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1310306                       # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total      2035209                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720865                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       720865                       # number of WriteReq MSHR misses
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 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756074                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756074                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2756715                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2756715                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23118028700                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23118028700                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5596519781                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5596519781                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5770003                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5770003                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28714548481                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28714548481                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28720318484                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28720318484                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756071                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756071                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2756712                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2756712                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24098858500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24098858500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5945182850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5945182850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      6199500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      6199500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  30044041350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  30044041350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  30050240850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  30050240850                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.167757                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.167757                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168551                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168551                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7763.617017                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7763.617017                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9001.564743                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9001.564743                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8247.313082                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8247.313082                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9671.606864                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9671.606864                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10901.040412                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10901.040412                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10900.754540                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10900.754540                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169974                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.005918                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           365528009                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5170484                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.695124                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         247768250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.005918                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998058                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           5169094                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.159465                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           365531814                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           5169604                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.707894                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         246618500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.159465                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998358                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998358                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         746574831                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        746574831                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    365528032                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       365528032                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     365528032                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        365528032                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    365528032                       # number of overall hits
-system.cpu.icache.overall_hits::total       365528032                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5174132                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5174132                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5174132                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5174132                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5174132                       # number of overall misses
-system.cpu.icache.overall_misses::total       5174132                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41647443196                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41647443196                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41647443196                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41647443196                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41647443196                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41647443196                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    370702164                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    370702164                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    370702164                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    370702164                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    370702164                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    370702164                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         746581864                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        746581864                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    365531869                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total       365531869                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      5174253                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       5174253                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst      5174253                       # number of overall misses
+system.cpu.icache.overall_misses::total       5174253                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  41642635922                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::cpu.inst  41642635922                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  41642635922                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  41642635922                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  41642635922                       # number of overall miss cycles
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+system.cpu.icache.ReadReq_accesses::total    370706122                       # number of ReadReq accesses(hits+misses)
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013958                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.013958                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.013958                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.013958                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.013958                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.013958                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8049.165193                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8049.165193                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8049.165193                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8049.165193                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8049.165193                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8049.165193                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        75254                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          145                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3130                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8048.047887                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8048.047887                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8048.047887                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8048.047887                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8048.047887                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8048.047887                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        80330                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          136                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3828                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    24.042812                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           29                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.984848                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    27.200000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3628                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3628                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3628                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3628                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3628                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3628                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170504                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5170504                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5170504                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5170504                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5170504                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5170504                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36431387686                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  36431387686                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36431387686                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  36431387686                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36431387686                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  36431387686                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013948                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013948                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013948                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7046.003192                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7046.003192                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7046.003192                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7046.003192                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7046.003192                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7046.003192                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4632                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4632                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4632                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         4632                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4632                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169621                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      5169621                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      5169621                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      5169621                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total      5169621                       # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total  39011263436                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39011263436                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  39011263436                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39011263436                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  39011263436                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013945                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013945                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013945                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7546.252121                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7546.252121                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7546.252121                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1347095                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1354943                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         6866                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1349196                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1355261                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         5306                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4789921                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           299165                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16361.556320                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7824806                       # Total number of references to valid blocks.
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 system.cpu.l2cache.demand_accesses::cpu.data      2756696                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data      2756696                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      7927182                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.000687                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.053854                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015707                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003965                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003965                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000687                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.040809                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.040809                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014640                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535                       # average ReadReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73634.971910                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77983.689884                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77983.689884                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73634.971910                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73634.971910                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77879.899551                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77749.012628                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1083,141 +1091,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66342                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66342                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         1287                       # number of ReadReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         2747                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         2761                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         2747                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         2761                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3540                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       108352                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       111892                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202242                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       202242                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           19                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           19                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1398                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1398                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3540                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       109750                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       113290                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3540                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       109750                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202242                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       315532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    229882786                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7609765250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7839648036                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17078829649                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       262019                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       262019                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114010508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114010508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    229882786                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7723775758                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   7953658544                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    229882786                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7723775758                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  25032488193                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.000685                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.053222                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015527                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.writebacks::writebacks        66338                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66338                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1216                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1216                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         1112                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         1112                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         2328                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         2341                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         2328                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         2341                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         8918                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         8918                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202421                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       202421                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1394                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1394                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3547                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3547                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       108176                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       108176                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3547                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       109570                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       113117                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3547                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       109570                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202421                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       315538                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17045778133                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17045778133                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       268500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       268500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    123342500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    123342500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    239801000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    239801000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7820358000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7820358000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    239801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7943700500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8183501500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    239801000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7943700500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17045778133                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  25229279633                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001939                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001939                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000685                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014291                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000685                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001934                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001934                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.053136                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.053136                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039747                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014271                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039747                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.039804                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.039809                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7206354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7206353                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       735673                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       248887                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           19                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           19                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10340989                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6249103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16590092                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330911040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223511616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          554422656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      248905                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      8911779                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.027928                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.164766                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7205469                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       801528                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6778838                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       266094                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169621                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035849                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15507443                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626416                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          23133859                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330854720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223480704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          554335424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      565266                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     16416862                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.034431                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.182334                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            8662892     97.21%     97.21% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             248887      2.79%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           15851611     96.56%     96.56% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             565251      3.44%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        8911779                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5067119000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7756292749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       16416862                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     8660995500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    7754456946                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4138723116                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4135063976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              314058                       # Transaction distribution
-system.membus.trans_dist::ReadResp             314058                       # Transaction distribution
-system.membus.trans_dist::Writeback             66342                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               19                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              19                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1398                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1398                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       697292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 697292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24435072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                24435072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             314068                       # Transaction distribution
+system.membus.trans_dist::Writeback             66338                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           232219                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1394                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1394                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        314068                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       929513                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 929513                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24435200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                24435200                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            381817                       # Request fanout histogram
+system.membus.snoop_fanout::samples            614035                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  381817    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  614035    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              381817                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           746606366                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              614035                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           967133123                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1648197495                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1648308021                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 4a7e6f230..627fd964a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.043695                       # Number of seconds simulated
-sim_ticks                                1043695078500                       # Number of ticks simulated
-final_tick                               1043695078500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.043722                       # Number of seconds simulated
+sim_ticks                                1043722398500                       # Number of ticks simulated
+final_tick                               1043722398500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 624059                       # Simulator instruction rate (inst/s)
-host_op_rate                                   766694                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1018706197                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313408                       # Number of bytes of host memory used
-host_seconds                                  1024.53                       # Real time elapsed on the host
+host_inst_rate                                 921530                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1132156                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1504334297                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320916                       # Number of bytes of host memory used
+host_seconds                                   693.81                       # Real time elapsed on the host
 sim_insts                                   639366787                       # Number of instructions simulated
 sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            113216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18428352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18541568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18469760                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18582976                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       113216                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          113216                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               1769                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             287943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                289712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288590                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290359                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               108476                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17656835                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17765311                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108476                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108476                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4053168                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4053168                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4053168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108476                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17656835                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               21818480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108473                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17696046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17804520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108473                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108473                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4053062                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4053062                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4053062                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17696046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21857582                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       2087390157                       # number of cpu cycles simulated
+system.cpu.numCycles                       2087444797                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   639366787                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     381221435                       # nu
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               2087390156.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               2087444796.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         137364860                       # Number of branches fetched
@@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  788730744                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            778046                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4093.640584                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4093.640641                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         996415000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640584                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         996416500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640641                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data       782004                       # n
 system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
 system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582740000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18582740000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677152000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3677152000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22259892000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22259892000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22259892000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22259892000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18609964000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18609964000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677169000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3677169000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22287133000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22287133000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22287133000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22287133000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28465.189436                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28460.130692                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28500.024297                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28494.959362                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91561                       # number of writebacks
-system.cpu.dcache.writebacks::total             91561                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        89072                       # number of writebacks
+system.cpu.dcache.writebacks::total             89072                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
@@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782003
 system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17513680000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17513680000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3573167500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3573167500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21086847500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21086847500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21088530000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21088530000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17897244000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17897244000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3607846000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3607846000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1752000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1752000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21505090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21505090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21506842000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21506842000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1391.464501                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1391.464534                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           643367692                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             10208                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          63025.831897                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464501                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464534                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.679426                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.679426                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
@@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst        10208                       # n
 system.cpu.icache.demand_misses::total          10208                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        10208                       # number of overall misses
 system.cpu.icache.overall_misses::total         10208                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    207074000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    207074000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    207074000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    207074000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    207074000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    207074000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    207153000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    207153000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    207153000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    207153000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    207153000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    207153000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    643377900                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    643377900                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    643377900                       # number of demand (read+write) accesses
@@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000016
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20285.462382                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20285.462382                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20293.201411                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20293.201411                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,38 +419,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        10208
 system.cpu.icache.demand_mshr_misses::total        10208                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        10208                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        10208                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    191762000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    191762000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    191762000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    191762000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    191762000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    191762000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    196945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    196945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    196945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    196945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    196945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    196945000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18785.462382                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18785.462382                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18785.462382                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           256932                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32626.698157                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             524746                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           289675                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.811499                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257579                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32626.732272                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1218059                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290322                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.195545                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2792.505444                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.076488                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.116225                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.085221                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.908970                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995688                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2506.606006                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    48.754528                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.076496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001488                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.917705                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995689                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32743                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
@@ -458,78 +458,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          149
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1441                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        30967                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          7430286                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7430286                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8439                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       490969                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         499408                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        91561                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        91561                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         12984085                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12984085                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks        89072                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        89072                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         3230                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3230                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8439                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8439                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490322                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       490322                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         8439                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       494199                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          502638                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.inst         8439                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       494199                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         502638                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1769                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       221850                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       223619                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::cpu.data       493552                       # number of overall hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1769                       # number of ReadCleanReq misses
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+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222497                       # number of ReadSharedReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst         1769                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       287943                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        289712                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       288590                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst         1769                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       287943                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       289712                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     92944500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11647369000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  11740313500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3469929500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3469929500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     92944500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15117298500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  15210243000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  15117298500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15210243000                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total       723027                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        91561                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        91561                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3469946000                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     93021000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     93021000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11681386500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  11681386500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     93021000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  15151332500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data  15151332500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15244353500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks        89072                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        89072                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69323                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69323                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst        10208                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       782142                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       792350                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        10208                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       782142                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       792350                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.173295                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311229                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.309282                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953407                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953407                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.173295                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.173295                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312137                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312137                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.173295                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368147                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.365636                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.173295                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368147                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.365636                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.700961                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099842                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.700961                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010617                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.700961                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010617                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368974                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.366453                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -540,103 +546,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1769                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221850                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       223619                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          184                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          184                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1769                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1769                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222497                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222497                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         1769                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       287943                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       289712                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288590                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290359                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1769                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       287943                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       289712                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     71648500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8984925000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9056573500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2676766500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2676766500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71648500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11661691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11733340000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71648500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11661691500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11733340000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311229                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.309282                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288590                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290359                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2809016000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2809016000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     75331000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     75331000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9456416500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9456416500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     75331000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12265432500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12340763500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     75331000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12265432500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12340763500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953407                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.173295                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312137                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312137                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368147                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.365636                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368974                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.366453                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368147                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.365636                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368974                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.366453                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         723027                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        723027                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91561                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155170                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       888114                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69323                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69323                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20416                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1655845                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1676261                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        10208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712819                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        29168                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341237                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2370405                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       653312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55916992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56570304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       883911                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55757696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56411008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      257579                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1836744                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.140237                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.347233                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             883911    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1579165     85.98%     85.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             257579     14.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         883911                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      533516500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1836744                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      878654500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      15312000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1173213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              223619                       # Transaction distribution
-system.membus.trans_dist::ReadResp             223619                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224266                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190085                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       645522                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 645522                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22771840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22771840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        224266                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       836901                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 836901                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22813248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22813248                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            355811                       # Request fanout histogram
+system.membus.snoop_fanout::samples            546599                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  355811    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  546599    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              355811                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           632634000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              546599                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           811365948                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1448919000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1452169448                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index bd4df05db..dfd14c576 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.059732                       # Number of seconds simulated
-sim_ticks                                 59731559000                       # Number of ticks simulated
-final_tick                                59731559000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.059580                       # Number of seconds simulated
+sim_ticks                                 59579614000                       # Number of ticks simulated
+final_tick                                59579614000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330143                       # Simulator instruction rate (inst/s)
-host_op_rate                                   330143                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              222980587                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304704                       # Number of bytes of host memory used
-host_seconds                                   267.88                       # Real time elapsed on the host
+host_inst_rate                                 321432                       # Simulator instruction rate (inst/s)
+host_op_rate                                   321432                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              216544599                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304972                       # Number of bytes of host memory used
+host_seconds                                   275.14                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            516416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10147392                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10663808                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       516416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          516416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7298880                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7298880                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8069                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158553                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166622                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114045                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114045                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8645614                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            169883261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               178528874                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8645614                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8645614                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         122194701                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              122194701                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         122194701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8645614                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           169883261                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              300723576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166622                       # Number of read requests accepted
-system.physmem.writeReqs                       114045                       # Number of write requests accepted
-system.physmem.readBursts                      166622                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114045                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10663168                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       640                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7297280                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10663808                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7298880                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       10                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            500672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10147648                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10648320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       500672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          500672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7320576                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7320576                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7823                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166380                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114384                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114384                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8403411                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            170320808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               178724219                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8403411                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8403411                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         122870484                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              122870484                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         122870484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8403411                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           170320808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301594703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166380                       # Number of read requests accepted
+system.physmem.writeReqs                       114384                       # Number of write requests accepted
+system.physmem.readBursts                      166380                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114384                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10648064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7319040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10648320                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7320576                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        4                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10463                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10512                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10314                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10093                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10430                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10428                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9849                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10305                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10593                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10642                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10591                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10451                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10284                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10088                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10415                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10418                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9828                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10277                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10580                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10645                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10557                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10259                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10303                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10653                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10528                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10649                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7087                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7261                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7256                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7125                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7091                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7094                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10298                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10623                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10516                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10631                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7162                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7274                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7295                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6999                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7182                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6834                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7222                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6994                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7111                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6965                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7289                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7283                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6990                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7296                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7306                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     59731532000                       # Total gap between requests
+system.physmem.totGap                     59579590000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166622                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166380                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114045                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    165035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1551                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114384                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    164758                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1592                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6985                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      762                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -193,121 +193,122 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54759                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      327.975602                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.612520                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.469121                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19499     35.61%     35.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11959     21.84%     57.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5687     10.39%     67.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3574      6.53%     74.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2717      4.96%     79.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2083      3.80%     83.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1679      3.07%     86.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1528      2.79%     88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6033     11.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54759                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7017                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.742625                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      348.245058                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7015     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7017                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7017                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.249109                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.233383                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.749815                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6248     89.04%     89.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 18      0.26%     89.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                569      8.11%     97.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                155      2.21%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 21      0.30%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.bytesPerActivate::samples        54737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      328.220838                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.100573                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.685535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19472     35.57%     35.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11861     21.67%     57.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5645     10.31%     67.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3680      6.72%     74.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2860      5.22%     79.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2018      3.69%     83.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1694      3.09%     86.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1489      2.72%     89.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6018     10.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54737                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7040                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.631676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.376134                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7037     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7040                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7040                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.244318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.229045                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.737232                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6278     89.18%     89.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.23%     89.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                578      8.21%     97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                145      2.06%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 15      0.21%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  3      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  2      0.03%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7017                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1993187750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5117162750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    833060000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11963.05                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7040                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2004219750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5123769750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    831880000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12046.33                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30713.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         178.52                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         122.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      178.53                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      122.19                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30796.33                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         178.72                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         122.84                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      178.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      122.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.35                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.39                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.95                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           2.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.40                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144646                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81220                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.12                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144447                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81540                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   86.82                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                       212819.93                       # Average gap between requests
-system.physmem.pageHitRate                      80.48                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  199621800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  108920625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 642564000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                367681680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3901163760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12761553015                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24642806250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42624311130                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              713.633365                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    40844346250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1994460000                       # Time in different power states
+system.physmem.writeRowHitRate                  71.29                       # Row buffer hit rate for writes
+system.physmem.avgGap                       212205.23                       # Average gap between requests
+system.physmem.pageHitRate                      80.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  199372320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  108784500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 641464200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368938800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3890992560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            12501731340                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24777284250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42488567970                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              713.220229                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    41071172000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1989260000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16889792000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16512675000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  214235280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116894250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 656728800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370960560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3901163760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13264546950                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24201582750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42726112350                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              715.337777                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40104532750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1994460000                       # Time in different power states
+system.physmem_1.actEnergy                  214189920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116869500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 655792800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                371790000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3890992560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13114227690                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24240006750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42603869220                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              715.155695                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40171909250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1989260000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17629849250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17411703250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14669488                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9491497                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            392361                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10408467                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6389552                       # Number of BTB hits
+system.cpu.branchPred.lookups                14668515                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9490335                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            391198                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9984003                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6387554                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.388022                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1708748                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              85394                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             63.977885                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1708558                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              85259                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20569996                       # DTB read hits
-system.cpu.dtb.read_misses                      97344                       # DTB read misses
+system.cpu.dtb.read_hits                     20570256                       # DTB read hits
+system.cpu.dtb.read_misses                      97321                       # DTB read misses
 system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20667340                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665866                       # DTB write hits
-system.cpu.dtb.write_misses                      9405                       # DTB write misses
+system.cpu.dtb.read_accesses                 20667577                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665734                       # DTB write hits
+system.cpu.dtb.write_misses                      9406                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14675271                       # DTB write accesses
-system.cpu.dtb.data_hits                     35235862                       # DTB hits
-system.cpu.dtb.data_misses                     106749                       # DTB misses
+system.cpu.dtb.write_accesses                14675140                       # DTB write accesses
+system.cpu.dtb.data_hits                     35235990                       # DTB hits
+system.cpu.dtb.data_misses                     106727                       # DTB misses
 system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35342611                       # DTB accesses
-system.cpu.itb.fetch_hits                    25629903                       # ITB hits
-system.cpu.itb.fetch_misses                      5247                       # ITB misses
+system.cpu.dtb.data_accesses                 35342717                       # DTB accesses
+system.cpu.itb.fetch_hits                    25623202                       # ITB hits
+system.cpu.itb.fetch_misses                      5252                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25635150                       # ITB accesses
+system.cpu.itb.fetch_accesses                25628454                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -321,81 +322,81 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        119463118                       # number of cpu cycles simulated
+system.cpu.numCycles                        119159228                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1109771                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1111760                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.350811                       # CPI: cycles per instruction
-system.cpu.ipc                               0.740296                       # IPC: instructions per cycle
-system.cpu.tickCycles                        91541167                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        27921951                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            200768                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.577182                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34616116                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204864                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.971200                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         693853250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.577182                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993793                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993793                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.347375                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742184                       # IPC: instructions per cycle
+system.cpu.tickCycles                        91522395                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        27636833                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            200775                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.716592                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34616548                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204871                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.967536                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         688117500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.716592                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993827                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993827                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          679                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3369                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3359                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70176158                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70176158                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20282855                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20282855                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333261                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333261                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34616116                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34616116                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34616116                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34616116                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89415                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89415                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280116                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280116                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       369531                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369531                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       369531                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369531                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4791422750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4791422750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21873540250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21873540250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  26664963000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  26664963000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  26664963000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  26664963000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20372270                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20372270                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70177059                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70177059                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20283298                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20283298                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333250                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333250                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34616548                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34616548                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34616548                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34616548                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89419                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89419                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280127                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280127                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       369546                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369546                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       369546                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369546                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4766015000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4766015000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21725113500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21725113500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  26491128500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  26491128500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  26491128500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  26491128500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20372717                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20372717                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34985647                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34985647                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34985647                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34985647                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     34986094                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34986094                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34986094                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34986094                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004389                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53586.341777                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53586.341777                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78087.436098                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 78087.436098                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72158.933892                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72158.933892                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72158.933892                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72158.933892                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010563                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010563                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010563                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010563                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71685.604769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71685.604769                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -404,32 +405,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168537                       # number of writebacks
-system.cpu.dcache.writebacks::total            168537                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28116                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28116                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136551                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136551                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       164667                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164667                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       164667                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164667                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61299                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61299                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143565                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143565                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       204864                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204864                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       204864                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204864                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2648121500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2648121500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10930365250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10930365250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13578486750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13578486750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13578486750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13578486750                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       168451                       # number of writebacks
+system.cpu.dcache.writebacks::total            168451                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136563                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136563                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164675                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164675                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       164675                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164675                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61307                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61307                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143564                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143564                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       204871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204871                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204871                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2678080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2678080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10985374000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10985374000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13663454000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13663454000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13663454000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13663454000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
@@ -438,68 +439,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43200.076673                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43200.076673                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76135.306307                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76135.306307                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66280.492180                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66280.492180                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66280.492180                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66280.492180                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43683.103071                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43683.103071                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76519.001978                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76519.001978                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66692.962889                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66692.962889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66692.962889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66692.962889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            152979                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1932.259039                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25474875                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            155027                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            164.325408                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42450985250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1932.259039                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943486                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943486                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            153439                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1932.585595                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25467714                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            155487                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            163.793205                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42332946500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1932.585595                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.943645                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.943645                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1044                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1043                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51414833                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51414833                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25474875                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25474875                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25474875                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25474875                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25474875                       # number of overall hits
-system.cpu.icache.overall_hits::total        25474875                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       155028                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        155028                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       155028                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         155028                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       155028                       # number of overall misses
-system.cpu.icache.overall_misses::total        155028                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2574589242                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2574589242                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2574589242                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2574589242                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2574589242                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2574589242                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25629903                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25629903                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25629903                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25629903                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25629903                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25629903                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006049                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006049                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006049                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006049                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006049                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16607.253154                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16607.253154                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16607.253154                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16607.253154                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16607.253154                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16607.253154                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51401891                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51401891                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25467714                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25467714                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25467714                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25467714                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25467714                       # number of overall hits
+system.cpu.icache.overall_hits::total        25467714                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       155488                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        155488                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       155488                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         155488                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       155488                       # number of overall misses
+system.cpu.icache.overall_misses::total        155488                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2558679500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2558679500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2558679500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2558679500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2558679500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2558679500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25623202                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25623202                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25623202                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25623202                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25623202                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25623202                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006068                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006068                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006068                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006068                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006068                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006068                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16455.800448                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16455.800448                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16455.800448                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16455.800448                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16455.800448                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16455.800448                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -508,123 +510,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155028                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       155028                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       155028                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       155028                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       155028                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       155028                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2338939258                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2338939258                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2338939258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2338939258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2338939258                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2338939258                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006049                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15087.205266                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15087.205266                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15087.205266                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15087.205266                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15087.205266                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15087.205266                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155488                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst       155488                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2403192500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2403192500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2403192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2403192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2403192500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2403192500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006068                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006068                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006068                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006068                       # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total     0.006068                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15455.806879                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15455.806879                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15455.806879                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132696                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30421.451198                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             219829                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164772                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.334141                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132455                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30425.611503                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             404125                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164531                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.456224                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26160.561062                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2366.479179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1894.410957                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.798357                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072219                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.057813                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.928389                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 25960.344438                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2481.956505                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1983.310560                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.792247                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32076                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11640                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19278                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          937                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11867                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19026                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          126                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4535770                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4535770                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       146958                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        33627                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         180585                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168537                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168537                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12684                       # number of ReadExReq hits
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+system.cpu.l2cache.overall_avg_miss_latency::total 81071.537615                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -633,105 +641,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114045                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114045                       # number of writebacks
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130882                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130882                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773936                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.461709                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773936                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.461709                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         216326                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        216325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168537                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143566                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143566                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       310055                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578265                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            888320                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9921728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23897664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           33819392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       528429                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        216793                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       282835                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       203834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       155488                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61306                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       464414                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610517                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1074931                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9951168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23892608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           33843776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      132455                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       847028                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.156376                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.363212                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             528429    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             714573     84.36%     84.36% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             132455     15.64%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         528429                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      432751500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     234095242                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         847028                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      525737500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     233232496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     343202250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               35740                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35740                       # Transaction distribution
-system.membus.trans_dist::Writeback            114045                       # Transaction distribution
+system.cpu.toL2Bus.respLayer1.occupancy     307309993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp              35498                       # Transaction distribution
+system.membus.trans_dist::Writeback            114384                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16134                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130882                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130882                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447289                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 447289                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17962688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17962688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         35498                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 463278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17968896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17968896                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            280667                       # Request fanout histogram
+system.membus.snoop_fanout::samples            296898                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  280667    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  296898    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              280667                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           816993000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              296898                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           824886500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          879772000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          878487500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 9afa0da2d..2061356b3 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022578                       # Number of seconds simulated
-sim_ticks                                 22578120000                       # Number of ticks simulated
-final_tick                                22578120000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022637                       # Number of seconds simulated
+sim_ticks                                 22637068500                       # Number of ticks simulated
+final_tick                                22637068500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210348                       # Simulator instruction rate (inst/s)
-host_op_rate                                   210348                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59670380                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234940                       # Number of bytes of host memory used
-host_seconds                                   378.38                       # Real time elapsed on the host
+host_inst_rate                                 222882                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222882                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63391012                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306268                       # Number of bytes of host memory used
+host_seconds                                   357.10                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            487616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10151104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10638720                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       487616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          487616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7296832                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7296832                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7619                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166230                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114013                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114013                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             21596838                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            449599169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               471196007                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        21596838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           21596838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         323181558                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              323181558                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         323181558                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            21596838                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           449599169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              794377566                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166230                       # Number of read requests accepted
-system.physmem.writeReqs                       114013                       # Number of write requests accepted
-system.physmem.readBursts                      166230                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114013                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10638144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7294912                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10638720                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7296832                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            472384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10153088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10625472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       472384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          472384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7318784                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7318784                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7381                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158642                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166023                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114356                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114356                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             20867720                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            448516026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               469383746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        20867720                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           20867720                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         323309708                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              323309708                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         323309708                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            20867720                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           448516026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              792693453                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166023                       # Number of read requests accepted
+system.physmem.writeReqs                       114356                       # Number of write requests accepted
+system.physmem.readBursts                      166023                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114356                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10625216                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7317504                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10625472                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7318784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        4                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10435                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10460                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10318                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10427                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10469                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10285                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10413                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10396                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9837                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10308                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10587                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10644                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10547                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10270                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10618                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10481                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10621                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7083                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7171                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6772                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7083                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6939                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6988                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7288                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10410                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10383                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9823                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10285                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10562                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10635                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10512                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10227                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10266                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10475                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10612                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7161                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7270                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7175                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6835                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6995                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6993                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7294                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22578086500                       # Total gap between requests
+system.physmem.totGap                     22637037500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166230                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166023                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114013                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     52462                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     43160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32153                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114356                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     52265                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     42988                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     38514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32235                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1941                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     3478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7835                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9963                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,121 +193,123 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52260                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      343.127440                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.641716                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     343.309325                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18423     35.25%     35.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10477     20.05%     55.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5934     11.35%     66.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2978      5.70%     72.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2855      5.46%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1509      2.89%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2072      3.96%     84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          924      1.77%     86.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7088     13.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52260                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6982                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.804927                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      342.249057                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6981     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52301                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      343.050573                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     202.162039                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.313279                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18282     34.96%     34.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10576     20.22%     55.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5922     11.32%     66.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2988      5.71%     72.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3062      5.85%     78.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1483      2.84%     80.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1989      3.80%     84.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1021      1.95%     86.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6978     13.34%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52301                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6994                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.736917                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.159441                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6991     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6982                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6982                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.325265                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.299310                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.979398                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6150     88.08%     88.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 25      0.36%     88.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                468      6.70%     95.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                181      2.59%     97.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 78      1.12%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 46      0.66%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 19      0.27%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.14%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  4      0.06%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6982                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5742111500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8858755250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34545.04                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6994                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6994                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.347727                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.319415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.025091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6123     87.55%     87.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 26      0.37%     87.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                468      6.69%     94.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                194      2.77%     97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 92      1.32%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 55      0.79%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 18      0.26%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 10      0.14%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.09%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6994                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5783499750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8896356000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    830095000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34836.37                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53295.04                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         471.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         323.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      471.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      323.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53586.37                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         469.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         323.25                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      469.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      323.31                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.21                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.68                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.52                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     146222                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81709                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.97                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                        80566.10                       # Average gap between requests
+system.physmem.busUtil                           6.19                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.67                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.53                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.92                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145949                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82096                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.91                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                        80737.28                       # Average gap between requests
 system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  190685880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  104044875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 641035200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                367584480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1474315440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6555814245                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7792863750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              17126343870                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              758.721685                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12883309000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       753740000                       # Time in different power states
+system.physmem_0.actEnergy                  190852200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  104135625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 640543800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368925840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1478383920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             6748287570                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             7661408250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              17192537205                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              759.557739                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    12661521500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       755820000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8935594000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9217738000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  204104880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  111366750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654919200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370701360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1474315440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6889050495                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7500532500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              17204990625                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              762.206905                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12395641000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       753740000                       # Time in different power states
+system.physmem_1.actEnergy                  204354360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  111502875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654108000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                371764080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1478383920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             6845140260                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             7576424250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              17241677745                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              761.730174                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    12521267250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       755820000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9423231500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9357815250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16619938                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10751763                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            361573                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10694449                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7373128                       # Number of BTB hits
+system.cpu.branchPred.lookups                16666171                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10777513                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            373740                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11097684                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7405754                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             68.943505                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1990233                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3119                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             66.732428                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1996658                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               2898                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22587975                       # DTB read hits
-system.cpu.dtb.read_misses                     226213                       # DTB read misses
-system.cpu.dtb.read_acv                            17                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22814188                       # DTB read accesses
-system.cpu.dtb.write_hits                    15866557                       # DTB write hits
-system.cpu.dtb.write_misses                     44947                       # DTB write misses
-system.cpu.dtb.write_acv                            1                       # DTB write access violations
-system.cpu.dtb.write_accesses                15911504                       # DTB write accesses
-system.cpu.dtb.data_hits                     38454532                       # DTB hits
-system.cpu.dtb.data_misses                     271160                       # DTB misses
-system.cpu.dtb.data_acv                            18                       # DTB access violations
-system.cpu.dtb.data_accesses                 38725692                       # DTB accesses
-system.cpu.itb.fetch_hits                    13913083                       # ITB hits
-system.cpu.itb.fetch_misses                     32600                       # ITB misses
+system.cpu.dtb.read_hits                     22620977                       # DTB read hits
+system.cpu.dtb.read_misses                     226849                       # DTB read misses
+system.cpu.dtb.read_acv                            27                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22847826                       # DTB read accesses
+system.cpu.dtb.write_hits                    15870488                       # DTB write hits
+system.cpu.dtb.write_misses                     45057                       # DTB write misses
+system.cpu.dtb.write_acv                            4                       # DTB write access violations
+system.cpu.dtb.write_accesses                15915545                       # DTB write accesses
+system.cpu.dtb.data_hits                     38491465                       # DTB hits
+system.cpu.dtb.data_misses                     271906                       # DTB misses
+system.cpu.dtb.data_acv                            31                       # DTB access violations
+system.cpu.dtb.data_accesses                 38763371                       # DTB accesses
+system.cpu.itb.fetch_hits                    13971550                       # ITB hits
+system.cpu.itb.fetch_misses                     35700                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13945683                       # ITB accesses
+system.cpu.itb.fetch_accesses                14007250                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -321,101 +323,101 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         45156244                       # number of cpu cycles simulated
+system.cpu.numCycles                         45274140                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15767330                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      106100961                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16619938                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9363361                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27775290                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  962592                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        208                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 5030                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        339291                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           71                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13913083                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                207051                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           44368516                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.391357                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.125574                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15840684                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      106412182                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16666171                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9402412                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27820247                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  987192                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        787                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5202                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        343767                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          103                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13971550                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                209132                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples           44504386                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.391049                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.126296                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24640012     55.53%     55.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1537852      3.47%     59.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1401576      3.16%     62.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1522530      3.43%     65.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4244947      9.57%     75.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1845094      4.16%     79.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   677475      1.53%     80.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1069981      2.41%     83.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7429049     16.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24724412     55.56%     55.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1545163      3.47%     59.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1406842      3.16%     62.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1520478      3.42%     65.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4242713      9.53%     75.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1851895      4.16%     79.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   685374      1.54%     80.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1070742      2.41%     83.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7456767     16.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44368516                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.368054                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.349641                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15099347                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9823247                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18465046                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                597969                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 382907                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3741515                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                100209                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              104016227                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                314595                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 382907                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15487504                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 6707215                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          96849                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18654699                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3039342                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102867556                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  4643                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 101006                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 348263                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                2491758                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            61906530                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             124122948                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        123794647                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            328300                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44504386                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.368117                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.350397                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15190182                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9797968                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18517517                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                603822                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 394897                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3753615                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                100898                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              104278713                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                316536                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 394897                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15562376                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4515044                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          96153                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18732590                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5203326                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              103086111                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  6702                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  93508                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 341438                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4700364                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            62061981                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             124384146                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        124055114                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            329031                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9359649                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5745                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5793                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2522683                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23265731                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16453437                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1244012                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           539260                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   91299347                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5639                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  89055311                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             77552                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11713229                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4714239                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1056                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44368516                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.007174                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.246117                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9515100                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5718                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5766                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2349661                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23316234                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16465365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1246740                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           545757                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   91441079                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5553                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  89167924                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             83024                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11854875                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4801848                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            970                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44504386                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.003576                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.243462                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17795444     40.11%     40.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5774110     13.01%     53.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5077311     11.44%     64.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4396727      9.91%     74.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4357066      9.82%     84.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2650893      5.97%     90.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1948119      4.39%     94.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1385813      3.12%     97.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              983033      2.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17850579     40.11%     40.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5788896     13.01%     53.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5155949     11.59%     64.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4393297      9.87%     74.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4359248      9.80%     84.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2645472      5.94%     90.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1941559      4.36%     94.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1381555      3.10%     97.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              987831      2.22%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44368516                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44504386                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  243204      9.64%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      1      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  244058      9.64%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.64% # attempts to use FU when none available
@@ -443,118 +445,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.64% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1172094     46.45%     56.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1108166     43.91%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1174802     46.40%     56.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1112961     43.96%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49651741     55.75%     55.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                44157      0.05%     55.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121956      0.14%     55.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              121436      0.14%     56.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 54      0.00%     56.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39055      0.04%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23004684     25.83%     81.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16072139     18.05%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49705550     55.74%     55.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                44198      0.05%     55.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121960      0.14%     55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              121539      0.14%     56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 56      0.00%     56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39076      0.04%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23058691     25.86%     81.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            16076765     18.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               89055311                       # Type of FU issued
-system.cpu.iq.rate                           1.972159                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2523465                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028336                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          224465346                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         102605449                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87163804                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              614809                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             433844                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       300747                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               91271228                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  307548                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1661543                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               89167924                       # Type of FU issued
+system.cpu.iq.rate                           1.969511                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2531821                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028394                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          224839378                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         102887543                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87218101                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              615701                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             435266                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       300894                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               91391726                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  308019                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1669932                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2989093                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6317                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        21548                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1840060                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3039596                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6284                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        21688                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1851988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3023                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        186080                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3150                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        205518                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 382907                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1413856                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               4974138                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100829471                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            151929                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23265731                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16453437                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5565                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   4999                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               4957861                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          21548                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         151078                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       158072                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               309150                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              88275465                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22814985                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            779846                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 394897                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1352665                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2733681                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100982224                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            167502                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23316234                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16465365                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5553                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3853                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2732159                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          21688                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         162395                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       158558                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               320953                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              88354535                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22848688                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            813389                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9524485                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38726852                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15171568                       # Number of branches executed
-system.cpu.iew.exec_stores                   15911867                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.954889                       # Inst execution rate
-system.cpu.iew.wb_sent                       87882002                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87464551                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33900833                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44342613                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9535592                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38764588                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15181336                       # Number of branches executed
+system.cpu.iew.exec_stores                   15915900                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.951545                       # Inst execution rate
+system.cpu.iew.wb_sent                       87941007                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87518995                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33890392                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44346264                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.936931                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764520                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.933090                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764222                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         9282281                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         9432406                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            263184                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43000551                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.054408                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.876009                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            275041                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43112835                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.049057                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.870632                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21467431     49.92%     49.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6329802     14.72%     64.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2918642      6.79%     71.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1760390      4.09%     75.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1670777      3.89%     79.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1138707      2.65%     82.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1203989      2.80%     84.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       794665      1.85%     86.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5716148     13.29%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     21537439     49.96%     49.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6339258     14.70%     64.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2938097      6.81%     71.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1767481      4.10%     75.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1703049      3.95%     79.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1136594      2.64%     82.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1201073      2.79%     84.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       797579      1.85%     86.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5692265     13.20%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43000551                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43112835                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -600,343 +602,349 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5716148                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    133590014                       # The number of ROB reads
-system.cpu.rob.rob_writes                   196617452                       # The number of ROB writes
-system.cpu.timesIdled                           47547                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          787728                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5692265                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    133876306                       # The number of ROB reads
+system.cpu.rob.rob_writes                   196941310                       # The number of ROB writes
+system.cpu.timesIdled                           47582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          769754                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.567348                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.567348                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.762586                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.762586                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116851082                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57926468                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255690                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   241313                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38160                       # number of misc regfile reads
+system.cpu.cpi                               0.568830                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.568830                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.757996                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.757996                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116950893                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57974920                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255771                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   241359                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38164                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            201362                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.706489                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34086491                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205458                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.904910                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         231989000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.706489                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993825                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993825                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201397                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.850359                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34098493                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205493                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.935059                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         231077500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.850359                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993860                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993860                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2590                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1430                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2777                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1229                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          71020044                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         71020044                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20525035                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20525035                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13561393                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13561393                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           63                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           63                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34086428                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34086428                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34086428                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34086428                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       268817                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        268817                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1051984                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1051984                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses          71045365                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71045365                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20537317                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20537317                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13561115                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13561115                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      34098432                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34098432                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34098432                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34098432                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       269180                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        269180                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1052262                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1052262                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1320801                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1320801                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1320801                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1320801                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  17503667749                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  17503667749                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  89467046923                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  89467046923                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        99750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        99750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106970714672                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106970714672                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106970714672                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106970714672                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20793852                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20793852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      1321442                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1321442                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1321442                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1321442                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  17386725500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  17386725500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  89260696666                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  89260696666                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        99000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        99000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106647422166                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106647422166                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106647422166                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106647422166                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20806497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20806497                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           64                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           64                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35407229                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35407229                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35407229                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35407229                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012928                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012928                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071988                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071988                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.015625                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.015625                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037303                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037303                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037303                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037303                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        99750                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        99750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80989.274442                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80989.274442                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6831456                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           62                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           62                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35419874                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35419874                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35419874                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35419874                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012937                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012937                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072007                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.072007                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.016129                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.016129                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037308                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037308                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037308                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037308                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        99000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        99000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80705.337174                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80705.337174                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6894813                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             88055                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             88842                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.581693                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.607584                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168921                       # number of writebacks
-system.cpu.dcache.writebacks::total            168921                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       206754                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       206754                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908590                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       908590                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1115344                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1115344                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1115344                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1115344                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62063                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62063                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143394                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168840                       # number of writebacks
+system.cpu.dcache.writebacks::total            168840                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207085                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       207085                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908865                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       908865                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115950                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115950                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62095                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62095                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143397                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143397                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205457                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205457                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205457                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205457                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3191920501                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3191920501                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14187677704                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14187677704                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        97750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        97750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17379598205                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17379598205                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17379598205                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17379598205                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002985                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002985                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205492                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205492                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205492                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205492                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3215385000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3215385000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14267732202                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14267732202                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        98000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        98000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17483117202                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17483117202                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17483117202                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17483117202                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002984                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002984                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.015625                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005803                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005803                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005803                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005803                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        97750                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        97750                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.016129                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.016129                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005802                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005802                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005802                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005802                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51781.705451                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51781.705451                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99498.122011                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99498.122011                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        98000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        98000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85079.308207                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 85079.308207                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85079.308207                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 85079.308207                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             92948                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1916.254210                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13805160                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             94996                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            145.323593                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19026930250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1916.254210                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935671                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935671                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             93160                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1916.318628                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13863089                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             95208                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            145.608447                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       19085068500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1916.318628                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.935702                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.935702                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1478                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          379                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1486                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          371                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27921160                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27921160                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13805160                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13805160                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13805160                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13805160                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13805160                       # number of overall hits
-system.cpu.icache.overall_hits::total        13805160                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       107922                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        107922                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       107922                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         107922                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       107922                       # number of overall misses
-system.cpu.icache.overall_misses::total        107922                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2071977734                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2071977734                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2071977734                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2071977734                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2071977734                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2071977734                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13913082                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13913082                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13913082                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13913082                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13913082                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13913082                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007757                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007757                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007757                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007757                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007757                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007757                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19198.844851                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19198.844851                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19198.844851                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19198.844851                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19198.844851                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19198.844851                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          448                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          28038306                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         28038306                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13863089                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13863089                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13863089                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13863089                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13863089                       # number of overall hits
+system.cpu.icache.overall_hits::total        13863089                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       108460                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        108460                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       108460                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         108460                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       108460                       # number of overall misses
+system.cpu.icache.overall_misses::total        108460                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2048888998                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2048888998                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2048888998                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2048888998                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2048888998                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2048888998                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13971549                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13971549                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13971549                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13971549                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13971549                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13971549                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007763                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007763                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007763                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007763                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007763                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007763                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18890.733893                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18890.733893                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18890.733893                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18890.733893                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18890.733893                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18890.733893                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1159                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    44.800000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    82.785714                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12925                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12925                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12925                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12925                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12925                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12925                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        94997                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        94997                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        94997                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        94997                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        94997                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        94997                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1636224764                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1636224764                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1636224764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1636224764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1636224764                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1636224764                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006828                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006828                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006828                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17223.962483                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17223.962483                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17223.962483                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13251                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        13251                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        13251                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        13251                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        13251                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        13251                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        95209                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        95209                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        95209                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        95209                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        95209                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        95209                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1668176000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1668176000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1668176000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1668176000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1668176000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1668176000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006814                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006814                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17521.200727                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17521.200727                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17521.200727                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132323                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30601.222528                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             161333                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164386                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.981428                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132107                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30604.111406                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             285364                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164184                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.738074                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26658.229296                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2102.973655                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1840.019577                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.813545                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.056153                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933875                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32063                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2820                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28790                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          228                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           57                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978485                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4062789                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4062789                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        87377                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        34233                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         121610                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168921                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168921                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12614                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12614                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        87377                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46847                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          134224                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        87377                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46847                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         134224                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         7620                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        27830                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35450                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 26463.213686                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2221.858475                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1919.039245                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.807593                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.067806                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::total     0.933963                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32077                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3041                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28427                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          365                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           59                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978912                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          5069653                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         5069653                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       168840                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168840                       # number of Writeback hits
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+system.cpu.l2cache.ReadExReq_hits::total        12616                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        87827                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        87827                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34235                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        34235                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        87827                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46851                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.data        46851                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         134678                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       130781                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130781                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7620                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158611                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166231                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       158611                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166231                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    623216750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2766024500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3389241250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13898935250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13898935250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    623216750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16664959750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  17288176500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    623216750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16664959750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  17288176500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        94997                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        62063                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       157060                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168921                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168921                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143395                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143395                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        94997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205458                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       300455                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        94997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205458                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       300455                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.080213                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448415                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.225710                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912033                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912033                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.080213                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771987                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.553264                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.080213                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771987                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.553264                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81786.975066                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 99390.028746                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 95606.241185                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106276.410564                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106276.410564                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81786.975066                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105068.121063                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 104000.917398                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81786.975066                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105068.121063                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 104000.917398                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7382                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         7382                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27861                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27861                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7382                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158642                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166024                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7382                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158642                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166024                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13916068500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13916068500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    602620000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    602620000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2758143500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2758143500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    602620000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  16674212000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17276832000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    602620000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  16674212000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17276832000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       168840                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168840                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143397                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143397                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        95209                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        95209                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        62096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        95209                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205493                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.inst        95209                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205493                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       300702                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912020                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.912020                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.077535                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.077535                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448676                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448676                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.077535                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.772007                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.552121                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.077535                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.772007                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.552121                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106407.417744                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106407.417744                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81633.703603                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81633.703603                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98996.572269                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98996.572269                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81633.703603                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105105.911423                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 104062.256059                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81633.703603                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105105.911423                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 104062.256059                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -945,105 +953,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114013                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114013                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7620                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27830                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35450                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       114356                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114356                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2054                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         2054                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130781                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130781                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7620                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158611                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166231                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7620                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158611                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166231                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    527900750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2422370000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2950270750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12290499750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12290499750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    527900750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14712869750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15240770500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    527900750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14712869750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15240770500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448415                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.225710                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912033                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912033                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771987                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.553264                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771987                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.553264                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         7382                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         7382                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27861                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27861                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7382                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158642                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166024                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7382                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158642                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166024                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12608258500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12608258500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    528810000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    528810000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2479533500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2479533500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    528810000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15087792000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15616602000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    528810000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15087792000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  15616602000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912020                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912020                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.077535                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448676                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448676                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772007                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.552121                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772007                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.552121                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96407.417744                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96407.417744                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71635.058250                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88996.572269                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88996.572269                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95105.911423                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94062.316292                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95105.911423                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94062.316292                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         157060                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        157059                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168921                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143395                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       189993                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       579837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            769830                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6079744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23960256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           30040000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       469376                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        157304                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       283196                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       143468                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143397                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143397                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        95209                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        62096                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       283577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612383                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            895960                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6093312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23957312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           30050624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      132107                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       727366                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.181624                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.385534                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             469376    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             595259     81.84%     81.84% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             132107     18.16%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         469376                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      403609000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     143899236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         727366                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      466469500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     142819485                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     325469999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308243991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               35449                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35449                       # Transaction distribution
-system.membus.trans_dist::Writeback            114013                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35242                       # Transaction distribution
+system.membus.trans_dist::Writeback            114356                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15775                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130781                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130781                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446473                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 446473                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17935552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17935552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         35242                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 462177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17944256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17944256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            280243                       # Request fanout histogram
+system.membus.snoop_fanout::samples            296154                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  280243    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  296154    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              280243                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           786749500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          865056500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              296154                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           778878000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          857917500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index c3c27d986..a8d113a77 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.057148                       # Number of seconds simulated
-sim_ticks                                 57147901500                       # Number of ticks simulated
-final_tick                                57147901500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.057054                       # Number of seconds simulated
+sim_ticks                                 57053790500                       # Number of ticks simulated
+final_tick                                57053790500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 198372                       # Simulator instruction rate (inst/s)
-host_op_rate                                   253689                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              159860838                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323444                       # Number of bytes of host memory used
-host_seconds                                   357.49                       # Real time elapsed on the host
+host_inst_rate                                 195523                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250045                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              157305109                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323528                       # Number of bytes of host memory used
+host_seconds                                   362.70                       # Real time elapsed on the host
 sim_insts                                    70915128                       # Number of instructions simulated
 sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            324160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7923136                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8247296                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       324160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          324160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5372800                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5372800                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5065                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             123799                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128864                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83950                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83950                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5672299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            138642641                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               144314940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5672299                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5672299                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          94015701                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               94015701                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          94015701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5672299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           138642641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              238330641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128864                       # Number of read requests accepted
-system.physmem.writeReqs                        83950                       # Number of write requests accepted
-system.physmem.readBursts                      128864                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83950                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8246976                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst            319296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7924224                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8243520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       319296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          319296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5514240                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5514240                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4989                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128805                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86160                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86160                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5596403                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            138890404                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               144486807                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5596403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5596403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          96649845                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               96649845                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          96649845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5596403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           138890404                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              241136652                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128805                       # Number of read requests accepted
+system.physmem.writeReqs                        86160                       # Number of write requests accepted
+system.physmem.readBursts                      128805                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      86160                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8243200                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5370816                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8247296                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5372800                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   5512512                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8243520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5514240                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8158                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8145                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                8375                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8229                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8247                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8317                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8450                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8089                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7970                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8070                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7639                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7818                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               7830                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8318                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8434                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7957                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8058                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7633                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7816                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               7879                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8005                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5181                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5374                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5285                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5197                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5033                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5143                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5224                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               7996                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5393                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5463                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5328                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5352                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5550                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5247                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5102                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5289                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5270                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5703                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     57147867000                       # Total gap between requests
+system.physmem.totGap                     57053759500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128864                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128805                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83950                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116734                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12104                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  86160                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    116563                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12216                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      606                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5912                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,98 +193,97 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38410                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      354.471023                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.710692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.512328                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12078     31.44%     31.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8121     21.14%     52.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4196     10.92%     63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2833      7.38%     70.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2487      6.47%     77.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1687      4.39%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1308      3.41%     85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1147      2.99%     88.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4553     11.85%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38410                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5157                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.969750                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      360.703721                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5155     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      355.314336                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     216.053807                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.949103                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12175     31.45%     31.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8182     21.14%     52.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4142     10.70%     63.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2786      7.20%     70.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2727      7.05%     77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1625      4.20%     81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1301      3.36%     85.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1172      3.03%     88.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4597     11.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38707                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5298                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.311061                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      351.967739                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5296     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::25600-26623            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5157                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5157                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.272833                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.256213                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.766988                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4532     87.88%     87.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  8      0.16%     88.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                487      9.44%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                109      2.11%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 13      0.25%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.08%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  3      0.06%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5157                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1657207000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4073313250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    644295000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12860.62                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5298                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5297                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.259581                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.243681                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.749380                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4690     88.54%     88.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  4      0.08%     88.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                472      8.91%     97.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                106      2.00%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 18      0.34%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  5      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5297                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1693807750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4108807750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    644000000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13150.68                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31610.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         144.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          93.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      144.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       94.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31900.68                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         144.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          96.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      144.49                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       96.65                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.86                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.73                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.46                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112198                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62160                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                       268534.34                       # Average gap between requests
-system.physmem.pageHitRate                      81.93                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  150580080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82161750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 512592600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                272315520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3732321840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11751586830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            23977725000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40479283620                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              708.378781                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    39762160500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1908140000                       # Time in different power states
+system.physmem.avgWrQLen                        23.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112096                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64121                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.03                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.42                       # Row buffer hit rate for writes
+system.physmem.avgGap                       265409.53                       # Average gap between requests
+system.physmem.pageHitRate                      81.98                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  151956000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   82912500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 512405400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                278951040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11612859660                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24043349250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40408652970                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.301006                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    39871864500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1905020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15473270000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15273243000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  139769280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76263000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 492016200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                271479600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3732321840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11244014370                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24422958750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40378823040                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              706.620851                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40500942500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1908140000                       # Time in different power states
+system.physmem_1.actEnergy                  140638680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76737375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 491797800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                279151920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11026970910                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24557286750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40298802555                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.375499                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40728832250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1905020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14734649500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14416275250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14823153                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9921447                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            393425                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9508830                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6745421                       # Number of BTB hits
+system.cpu.branchPred.lookups                14816555                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9915062                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            392110                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9527196                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6742365                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.938496                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1716328                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             70.769668                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1716488                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -404,97 +403,97 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        114295803                       # number of cpu cycles simulated
+system.cpu.numCycles                        114107581                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915128                       # Number of instructions committed
 system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1165738                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1163698                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.611727                       # CPI: cycles per instruction
-system.cpu.ipc                               0.620453                       # IPC: instructions per cycle
-system.cpu.tickCycles                        95732462                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18563341                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156421                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.059654                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42628242                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160517                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.568395                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         829804250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.059654                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992934                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992934                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.609072                       # CPI: cycles per instruction
+system.cpu.ipc                               0.621476                       # IPC: instructions per cycle
+system.cpu.tickCycles                        95702284                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18405297                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156420                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.153595                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42625103                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160516                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.550493                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         823362500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.153595                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992957                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992957                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1142                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2909                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1109                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86023319                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86023319                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22869697                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22869697                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642191                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642191                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        84516                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         84516                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86018450                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86018450                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22867482                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22867482                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642183                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642183                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83600                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83600                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42511888                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42511888                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42596404                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42596404                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51738                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51738                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207710                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207710                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        43711                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        43711                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259448                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259448                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       303159                       # number of overall misses
-system.cpu.dcache.overall_misses::total        303159                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1479377187                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1479377187                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16921529000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16921529000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18400906187                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18400906187                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18400906187                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18400906187                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22921435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22921435                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42509665                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42509665                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42593265                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42593265                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51591                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51591                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207718                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207718                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44555                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44555                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259309                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259309                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       303864                       # number of overall misses
+system.cpu.dcache.overall_misses::total        303864                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1486882500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1486882500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16821632500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16821632500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18308515000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18308515000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18308515000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18308515000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22919073                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22919073                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128227                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128227                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128155                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128155                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42771336                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42771336                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42899563                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42899563                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002257                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002257                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     42768974                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42768974                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42897129                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42897129                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002251                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002251                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.340888                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.340888                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006066                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006066                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007067                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007067                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70923.291708                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60697.212311                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.347665                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.347665                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006063                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006063                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007084                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007084                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70605.011781                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60252.333281                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -503,110 +502,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128425                       # number of writebacks
-system.cpu.dcache.writebacks::total            128425                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22255                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22255                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100680                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100680                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122935                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122935                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122935                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122935                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29483                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29483                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107030                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107030                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        24004                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        24004                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136513                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136513                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160517                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160517                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    559151063                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    559151063                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8446390250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8446390250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1684744250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1684744250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9005541313                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9005541313                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10690285563                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10690285563                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001286                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001286                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       128380                       # number of writebacks
+system.cpu.dcache.writebacks::total            128380                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22097                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22097                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100690                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100690                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122787                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122787                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122787                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122787                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29494                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29494                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23994                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23994                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160516                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160516                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    572555000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    572555000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8494060500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8494060500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1717129000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1717129000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9066615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9066615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10783744500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10783744500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001287                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001287                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187199                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187199                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187226                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187226                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42924                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.595671                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24987535                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44966                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            555.698417                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             42980                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1852.974873                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24976744                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             45022                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            554.767536                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.595671                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904588                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904588                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1852.974873                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.904773                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.904773                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          915                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1006                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          914                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1007                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50109970                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50109970                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24987535                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24987535                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24987535                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24987535                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24987535                       # number of overall hits
-system.cpu.icache.overall_hits::total        24987535                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44967                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44967                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        44967                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          44967                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44967                       # number of overall misses
-system.cpu.icache.overall_misses::total         44967                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    940451988                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    940451988                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    940451988                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    940451988                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    940451988                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    940451988                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25032502                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25032502                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25032502                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25032502                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25032502                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25032502                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001796                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001796                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001796                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001796                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001796                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001796                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20914.270198                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20914.270198                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20914.270198                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20914.270198                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20914.270198                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20914.270198                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          50088556                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         50088556                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24976744                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24976744                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      24976744                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         24976744                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     24976744                       # number of overall hits
+system.cpu.icache.overall_hits::total        24976744                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        45023                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         45023                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        45023                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          45023                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        45023                       # number of overall misses
+system.cpu.icache.overall_misses::total         45023                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    929482000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    929482000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    929482000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    929482000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    929482000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    929482000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25021767                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25021767                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total     25021767                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001799                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001799                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001799                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001799                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001799                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001799                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20644.603869                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20644.603869                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20644.603869                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20644.603869                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -615,123 +614,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44967                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        44967                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        44967                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        44967                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        44967                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        44967                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    871086012                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    871086012                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    871086012                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    871086012                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    871086012                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    871086012                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001796                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001796                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001796                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001796                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001796                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001796                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19371.672827                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19371.672827                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19371.672827                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19371.672827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19371.672827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19371.672827                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 19644.626080                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95727                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29852.290925                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              99928                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126845                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.787796                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26729.758607                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1556.401717                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1566.130601                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12771                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::writebacks       128425                       # number of Writeback hits
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81901.523470                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81835.065419                       # average overall miss latency
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+system.cpu.l2cache.overall_accesses::cpu.data       160516                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       205539                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955647                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955647                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111054                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111054                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403810                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403810                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111054                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771761                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.627034                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111054                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771761                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.627034                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80988.981336                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80988.981336                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79326.300000                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79326.300000                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86772.697810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86772.697810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81893.769398                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81893.769398                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,114 +745,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83950                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83950                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           63                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.writebacks::writebacks        86160                       # number of writebacks
+system.cpu.l2cache.writebacks::total            86160                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           10                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           10                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           64                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           64                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           63                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5066                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21521                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26587                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102278                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102278                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         5066                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       123799                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128865                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         5066                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       123799                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128865                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    342787750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1580541000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1923328750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7010820250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7010820250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    342787750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8591361250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8934149000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    342787750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8591361250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8934149000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.112660                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.402359                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.270045                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955601                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955601                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.112660                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771252                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.627129                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.112660                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771252                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.627129                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144                       # average overall mshr miss latency
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1376                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1376                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102281                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102281                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4990                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4990                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21535                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21535                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4990                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       123816                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128806                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4990                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       123816                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       128806                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7260824000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7260824000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    346082000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    346082000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1654286500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1654286500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    346082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8915110500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9261192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    346082000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8915110500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9261192500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955647                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955647                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110832                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402614                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402614                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.626674                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.626674                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          98454                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         98453                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128425                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107030                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        89933                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449459                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            539392                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2877824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18492288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           21370112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       333909                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp         98510                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       214540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        72719                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        45023                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        53488                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129456                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473213                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            602669                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2881408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18489344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           21370752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       95667                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       500606                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.191102                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.393170                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             333909    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             404939     80.89%     80.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              95667     19.11%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         333909                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      295379500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      68407488                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         500606                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      330849500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      67538489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     268248937                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               26586                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26586                       # Transaction distribution
-system.membus.trans_dist::Writeback             83950                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102278                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102278                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 341678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13620096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy     240805936                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp              26524                       # Transaction distribution
+system.membus.trans_dist::Writeback             86160                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7518                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102281                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102281                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         26524                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       351288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 351288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13757760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13757760                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            212814                       # Request fanout histogram
+system.membus.snoop_fanout::samples            222483                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  212814    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  222483    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              212814                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           578378500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              222483                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           591579500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          680081000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          679724750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 3b7597919..54ac67971 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,118 +1,118 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033331                       # Number of seconds simulated
-sim_ticks                                 33330913000                       # Number of ticks simulated
-final_tick                                33330913000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033295                       # Number of seconds simulated
+sim_ticks                                 33294994000                       # Number of ticks simulated
+final_tick                                33294994000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 123947                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158514                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               58262578                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323704                       # Number of bytes of host memory used
-host_seconds                                   572.08                       # Real time elapsed on the host
+host_inst_rate                                 125667                       # Simulator instruction rate (inst/s)
+host_op_rate                                   160714                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59007684                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 325068                       # Number of bytes of host memory used
+host_seconds                                   564.25                       # Real time elapsed on the host
 sim_insts                                    70907630                       # Number of instructions simulated
 sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            583488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2505024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6203200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9291712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       583488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          583488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6256128                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6256128                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               9117                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              39141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                145183                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97752                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97752                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             17505911                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75156177                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    186109513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               278771602                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        17505911                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           17505911                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         187697469                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              187697469                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         187697469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            17505911                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75156177                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    186109513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              466469070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        145183                       # Number of read requests accepted
-system.physmem.writeReqs                        97752                       # Number of write requests accepted
-system.physmem.readBursts                      145183                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97752                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9284992                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6254720                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9291712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6256128                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            579648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2508288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6196352                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9284288                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       579648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          579648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6263808                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6263808                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               9057                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              39192                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96818                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                145067                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97872                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97872                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             17409464                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             75335289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    186104614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               278849367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        17409464                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           17409464                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         188130624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              188130624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         188130624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            17409464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            75335289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    186104614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              466979991                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        145067                       # Number of read requests accepted
+system.physmem.writeReqs                        97872                       # Number of write requests accepted
+system.physmem.readBursts                      145067                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97872                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9276928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6262080                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9284288                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6263808                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9145                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9372                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9233                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9500                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9743                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9700                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9083                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8995                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9233                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8567                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8856                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8704                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8629                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8694                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8697                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8927                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5993                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6233                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6131                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6188                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6147                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6290                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6056                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6014                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6000                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6152                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6228                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5920                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6078                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6086                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6193                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6021                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9133                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9402                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9189                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9501                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9688                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9749                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9050                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9017                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9142                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8554                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8859                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8689                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8621                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8707                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8654                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8997                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5994                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6239                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6113                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6223                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6099                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6360                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6100                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5988                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5999                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6164                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6223                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5911                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6098                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6094                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6156                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6084                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33330641500                       # Total gap between requests
+system.physmem.totGap                     33294791000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  145183                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  145067                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97752                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     41867                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     51877                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     18150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6097                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97872                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     42425                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     52688                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     16531                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9335                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6069                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                      5279                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4608                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4301                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                      3567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        88                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5913                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      175.273178                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     110.551570                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     239.030923                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52157     58.84%     58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22538     25.42%     84.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4461      5.03%     89.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1758      1.98%     91.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1068      1.20%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          785      0.89%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          713      0.80%     94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          748      0.84%     95.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4421      4.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88649                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5905                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.566130                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       21.054973                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      187.117675                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5904     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        88605                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      175.366717                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     110.599846                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     238.987527                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          52022     58.71%     58.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22627     25.54%     84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4475      5.05%     89.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1626      1.84%     91.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1127      1.27%     92.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          853      0.96%     93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          741      0.84%     94.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          771      0.87%     95.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4363      4.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88605                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.519032                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       21.016952                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      186.911555                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5905                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5905                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.550381                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.508750                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.243905                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4712     79.80%     79.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 29      0.49%     80.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                757     12.82%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                163      2.76%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                111      1.88%     97.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 62      1.05%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 43      0.73%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 20      0.34%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.10%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5905                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7425181339                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10145393839                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    725390000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       51180.62                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.553037                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.510340                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.264183                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4718     79.82%     79.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 30      0.51%     80.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                754     12.76%     93.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                178      3.01%     96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 93      1.57%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 63      1.07%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 39      0.66%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 18      0.30%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 13      0.22%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  4      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7210112096                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9927962096                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    724760000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       49741.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  69930.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         278.57                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         187.66                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      278.77                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      187.70                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  68491.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         278.63                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         188.08                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      278.85                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      188.13                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.64                       # Data bus utilization in percentage
+system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.63                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     117819                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36329                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  37.16                       # Row buffer hit rate for writes
-system.physmem.avgGap                       137199.83                       # Average gap between requests
-system.physmem.pageHitRate                      63.48                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  342679680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  186978000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 582769200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                317714400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11943657450                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             9518358000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25068793530                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              752.242445                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    15735797307                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1112800000                       # Time in different power states
+system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     117862                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     36326                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.31                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  37.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                       137050.00                       # Average gap between requests
+system.physmem.pageHitRate                      63.50                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  341636400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  186408750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 582823800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                318271680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11786161320                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             9637821000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25027725510                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.712810                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    15936534744                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1111760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16476833443                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16245984006                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  327053160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  178451625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 548121600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315264960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11265215805                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            10113486000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              24924229950                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.904367                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    16730540892                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1112800000                       # Time in different power states
+system.physmem_1.actEnergy                  328217400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179086875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 547723800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                315763920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11208088125                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            10144902750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              24898385430                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              747.828055                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    16783464024                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1111760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     15482244108                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     15399360476                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17205793                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11516695                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            648305                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9352037                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7676056                       # Number of BTB hits
+system.cpu.branchPred.lookups                17206050                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11517760                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            648066                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9347785                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7673761                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.078974                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1873350                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101557                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.091758                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1873139                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101558                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -410,95 +411,95 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         66661827                       # number of cpu cycles simulated
+system.cpu.numCycles                         66589989                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            4979954                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88191186                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17205793                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9549406                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60159688                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1322593                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 6446                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            25                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13285                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22768352                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 68999                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           65820694                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.695691                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.296532                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            5006781                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       88183966                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17206050                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9546900                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60089478                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1322083                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 6754                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            23                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        13752                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22762089                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 69210                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           65777829                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.696584                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.296287                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20039717     30.45%     30.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8265549     12.56%     43.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9200264     13.98%     56.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28315164     43.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20002417     30.41%     30.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8264821     12.56%     42.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9199012     13.98%     56.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 28311579     43.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             65820694                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258106                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.322964                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8562659                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              19557917                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31575920                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5632021                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 492177                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3179708                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171007                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101418024                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3051775                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 492177                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13320782                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5331170                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         788978                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32236803                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13650784                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99206458                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                984473                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3857341                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63915                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4307533                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5353775                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103928524                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457724306                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115417327                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total             65777829                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258388                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.324283                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8581179                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              19502182                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31574906                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5627602                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 491960                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3179377                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                170933                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              101404474                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3045182                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 491960                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13335070                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5313056                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         801397                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  32234531                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13601815                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               99199856                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                982546                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3844821                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62523                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4317608                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5297882                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103921297                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             457696388                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        115410759                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10299298                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18661                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18655                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12693692                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24322711                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21993814                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1396246                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2340033                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98168548                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.UndoneMaps                 10292071                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18651                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12693629                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24321623                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21992796                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1398027                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2340833                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   98163899                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded               34521                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94889336                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            694958                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7520484                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20257229                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                  94893533                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            694347                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7515835                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     20236855                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            735                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      65820694                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.441634                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150001                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples      65777829                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.442637                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.149664                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17560123     26.68%     26.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17422684     26.47%     53.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17103546     25.99%     79.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11678791     17.74%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2054563      3.12%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 987      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17511633     26.62%     26.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17428256     26.50%     53.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17102675     26.00%     79.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11682123     17.76%     96.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2052152      3.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 990      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        65820694                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        65777829                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6715459     22.40%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     39      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6715699     22.40%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     38      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
@@ -526,118 +527,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11205581     37.37%     59.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12062957     40.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11201748     37.36%     59.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              12068794     40.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49498174     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89865      0.09%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24060336     25.36%     77.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21240923     22.38%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49496640     52.16%     52.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                89875      0.09%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24065423     25.36%     77.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21241557     22.38%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94889336                       # Type of FU issued
-system.cpu.iq.rate                           1.423443                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29984036                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315990                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286278153                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105734805                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93465836                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total               94893533                       # Type of FU issued
+system.cpu.iq.rate                           1.425042                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29986279                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315999                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          286245314                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         105725496                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93465397                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124873254                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              124879694                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1363649                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          1364211                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1456449                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2030                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11752                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1438076                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1455361                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2068                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11748                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1437058                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       138616                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        176709                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       140354                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        182528                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 492177                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  621288                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                454814                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98212928                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 491960                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  620291                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                463716                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            98208276                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24322711                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21993814                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              24321623                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21992796                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts              18601                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1642                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                450257                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11752                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         303335                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221647                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               524982                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93971179                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23753264                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            918157                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   1628                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                459155                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11748                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         302696                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       221540                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               524236                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93976140                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23758122                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            917393                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9859                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44736876                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14252919                       # Number of branches executed
-system.cpu.iew.exec_stores                   20983612                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.409670                       # Inst execution rate
-system.cpu.iew.wb_sent                       93587571                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93465893                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44982416                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76564206                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9856                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44743070                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14251776                       # Number of branches executed
+system.cpu.iew.exec_stores                   20984948                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.411265                       # Inst execution rate
+system.cpu.iew.wb_sent                       93586994                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93465454                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44981756                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76565949                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.402090                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587512                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.403596                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.587490                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         6539953                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         6535729                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            479186                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     64761460                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.400341                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.165093                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            478985                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     64719651                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.401246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.164864                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31172018     48.13%     48.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16800427     25.94%     74.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4337432      6.70%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4161423      6.43%     87.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1935218      2.99%     90.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1264756      1.95%     92.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       739046      1.14%     93.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       579471      0.89%     94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3771669      5.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31116285     48.08%     48.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16809912     25.97%     74.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4342534      6.71%     80.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4161990      6.43%     87.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1938865      3.00%     90.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1263903      1.95%     92.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       739138      1.14%     93.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       578808      0.89%     94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3768216      5.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     64761460                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     64719651                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
 system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -683,379 +684,386 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3771669                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158192582                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195517129                       # The number of ROB writes
-system.cpu.timesIdled                           23763                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          841133                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3768216                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    158150002                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195507605                       # The number of ROB writes
+system.cpu.timesIdled                           23773                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          812160                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.940122                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.940122                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.063692                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.063692                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102266688                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56794481                       # number of integer regfile writes
+system.cpu.cpi                               0.939109                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.939109                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.064839                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.064839                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102273698                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56793498                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346084159                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38805382                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44209334                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 346096996                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38804962                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44209976                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485106                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.740457                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40427935                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485618                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.250487                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         152807000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.740457                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997540                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997540                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            485041                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.740827                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40418511                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            485553                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             83.242223                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         152851500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.740827                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997541                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997541                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84615616                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84615616                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21501539                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21501539                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18833357                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18833357                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        61715                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         61715                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15379                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15379                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84611501                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84611501                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21495962                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21495962                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18831064                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18831064                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60188                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60188                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15352                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15352                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40334896                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40334896                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40396611                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40396611                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       552871                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        552871                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1016544                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1016544                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        67128                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        67128                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          547                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          547                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1569415                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1569415                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1636543                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1636543                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9102953011                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9102953011                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14661434456                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14661434456                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23764387467                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23764387467                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23764387467                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23764387467                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22054410                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22054410                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40327026                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40327026                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40387214                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40387214                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       556411                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        556411                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1018837                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1018837                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68667                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68667                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          574                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          574                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1575248                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1575248                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1643915                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1643915                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8968261000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8968261000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14556255401                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14556255401                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      4964500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      4964500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23524516401                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23524516401                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23524516401                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23524516401                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22052373                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22052373                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128843                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128843                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128855                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128855                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41904311                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41904311                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42033154                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42033154                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025069                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025069                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051212                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051212                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.521006                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.521006                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034346                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034346                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037452                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037452                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.038935                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038935                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9348.263254                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9348.263254                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15142.194682                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14521.089557                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           25                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3013610                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          128472                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    23.457329                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41902274                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41902274                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42031129                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42031129                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025231                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025231                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051327                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051327                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532901                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.532901                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036042                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036042                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037593                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037593                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039112                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039112                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8648.954704                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8648.954704                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14933.849401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14310.056421                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           45                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3094334                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          130016                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.625000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    23.799640                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       264409                       # number of writebacks
-system.cpu.dcache.writebacks::total            264409                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       253375                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       253375                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868011                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       868011                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          547                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          547                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1121386                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1121386                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1121386                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1121386                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299496                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299496                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148533                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148533                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37600                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37600                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       448029                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       448029                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485629                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485629                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3035888114                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3035888114                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2279411901                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2279411901                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2033283784                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2033283784                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5315300015                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5315300015                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7348583799                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7348583799                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013580                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013580                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       256956                       # number of writebacks
+system.cpu.dcache.writebacks::total            256956                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256971                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       256971                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870307                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       870307                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          574                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          574                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1127278                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1127278                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1127278                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1127278                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299440                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       299440                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148530                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148530                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37596                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37596                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       447970                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       447970                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       485566                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       485566                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3182608500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3182608500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2345597960                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2345597960                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2017960000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2017960000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5528206460                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5528206460                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7546166460                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7546166460                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013579                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013579                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291828                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291828                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010692                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010692                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010691                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10628.534932                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10628.534932                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15792.082138                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15792.082138                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53674.859028                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53674.859028                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12340.572940                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322771                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.304013                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22435446                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323283                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.398781                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1099609250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.304013                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996688                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996688                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.replacements            322718                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.301604                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22427944                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            323227                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             69.387594                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1102167500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.301604                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996683                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996683                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          354                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          347                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45859770                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45859770                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22435446                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22435446                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total         22435446                       # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total        22435446                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       332792                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        332792                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total         332792                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       332792                       # number of overall misses
-system.cpu.icache.overall_misses::total        332792                       # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total   3372368098                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3372368098                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3372368098                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3372368098                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3372368098                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22768238                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22768238                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22768238                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22768238                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22768238                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22768238                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014617                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014617                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014617                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014617                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014617                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014617                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10133.561197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10133.561197                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       259166                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             14826                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          45847164                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45847164                       # Number of data accesses
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+system.cpu.icache.overall_hits::total        22427950                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       334012                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        334012                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total        334012                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3359547390                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3359547390                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3359547390                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3359547390                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3359547390                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3359547390                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22761962                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22761962                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     22761962                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22761962                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22761962                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014674                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014674                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014674                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014674                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014674                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014674                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10058.163749                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10058.163749                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10058.163749                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10058.163749                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       273191                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          314                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             16668                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    17.480507                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.390149                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          157                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9498                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         9498                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         9498                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         9498                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         9498                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         9498                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323294                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323294                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323294                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323294                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323294                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323294                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2922927754                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2922927754                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2922927754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2922927754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2922927754                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2922927754                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014199                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014199                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014199                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9041.082587                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10772                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        10772                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        10772                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        10772                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        10772                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        10772                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323240                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       323240                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total   3075719938                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3075719938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   3075719938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3075719938                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   3075719938                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014201                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014201                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014201                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9515.282570                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       824420                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       826170                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         1539                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       823311                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826037                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         2394                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78694                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           129309                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16078.989093                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             872580                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           145594                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.993241                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78819                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           129183                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16078.827633                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1332410                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           145465                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.159660                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 12596.793225                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1430.956994                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1951.680185                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    99.558690                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.768847                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087339                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.119121                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006077                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.981384                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           24                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16261                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 12584.053825                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1451.251559                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1933.402514                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   110.119734                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768070                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088577                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.118006                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006721                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.981374                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            7                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2623                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11971                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          617                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          894                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001465                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.992493                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17467290                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17467290                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       314129                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total         620064                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       264409                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       264409                       # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
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-system.cpu.l2cache.overall_hits::total         757328                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         9153                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        31112                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        40265                       # number of ReadReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2635                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12009                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991516                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         24881143                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        24881143                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       256956                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       256956                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        11307                       # number of ReadExReq misses
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-system.cpu.l2cache.overall_misses::cpu.data        42419                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        51572                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    716537990                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2723567713                       # number of ReadReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data   3959005155                       # number of overall miss cycles
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-system.cpu.l2cache.Writeback_accesses::total       264409                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.028313                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78284.495794                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87540.746754                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109263.061997                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109263.061997                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.461538                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.461538                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077164                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.077164                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028163                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028163                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092102                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092102                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028163                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087531                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.063805                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028163                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087531                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063805                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107202.110956                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107202.110956                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77747.445897                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77747.445897                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86483.310243                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86483.310243                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89545.044958                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89545.044958                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1064,141 +1072,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97752                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97752                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           36                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          124                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3154                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3154                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         3278                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         3314                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         3278                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         3314                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9117                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30988                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        40105                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       112705                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        97872                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97872                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3181                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3181                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           46                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           46                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          128                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          128                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           46                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3309                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3355                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           46                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3309                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3355                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3506                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         3506                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       112459                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8153                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8153                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9117                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        39141                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        48258                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9117                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        39141                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       160963                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    636175260                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2451921294                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3088096554                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10874977234                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        82006                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        82006                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    605818037                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    605818037                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    636175260                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3057739331                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   3693914591                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    636175260                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3057739331                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14568891825                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.091940                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.060735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8283                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8283                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9057                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9057                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        30909                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        30909                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9057                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        39192                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        48249                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9057                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        39192                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       160708                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10889744040                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       101500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       101500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    639425500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    639425500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    650223000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    650223000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2490483000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2490483000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    650223000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3129908500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3780131500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    650223000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3129908500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14669875540                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054876                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054876                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.059659                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.461538                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.461538                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055753                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055753                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028021                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.091722                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.091722                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.059657                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.198990                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.198705                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         660341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        660341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       264409                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       151292                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148571                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148571                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       646576                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1235667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1882243                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20690048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     48001728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           68691776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      151304                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1224624                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.123542                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.329058                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        660226                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       354828                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       502259                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       152780                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           13                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           13                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       148567                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148567                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       323240                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       336986                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938639                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406861                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2345500                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20686336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47520576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           68206912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      281979                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1898528                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.148517                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.355611                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1073332     87.65%     87.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             151292     12.35%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1616565     85.15%     85.15% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             281963     14.85%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1224624                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      801075000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     486570693                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1898528                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1065238500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     485020678                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     734618165                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     728403365                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              137030                       # Transaction distribution
-system.membus.trans_dist::ReadResp             137030                       # Transaction distribution
-system.membus.trans_dist::Writeback             97752                       # Transaction distribution
+system.membus.trans_dist::ReadResp             136784                       # Transaction distribution
+system.membus.trans_dist::Writeback             97872                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            30200                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8153                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8153                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       388130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 388130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15547840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15547840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              8283                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8283                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        136784                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       418218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 418218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15548096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15548096                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            242941                       # Request fanout histogram
+system.membus.snoop_fanout::samples            273145                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  242941    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  273145    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              242941                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           691321050                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          757153835                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              273145                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           717072511                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          756625908                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 959bae132..baff53399 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.211096                       # Number of seconds simulated
-sim_ticks                                1211096219500                       # Number of ticks simulated
-final_tick                               1211096219500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.209315                       # Number of seconds simulated
+sim_ticks                                1209314565500                       # Number of ticks simulated
+final_tick                               1209314565500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 325701                       # Simulator instruction rate (inst/s)
-host_op_rate                                   325701                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215976885                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296636                       # Number of bytes of host memory used
-host_seconds                                  5607.53                       # Real time elapsed on the host
+host_inst_rate                                 310001                       # Simulator instruction rate (inst/s)
+host_op_rate                                   310001                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              205263152                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296916                       # Number of bytes of host memory used
+host_seconds                                  5891.53                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125445568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125506880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124968128                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125029440                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65168832                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65168832                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65415808                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65415808                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                958                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1960087                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961045                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018263                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018263                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50625                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103580183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103630808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50625                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50625                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          53809789                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               53809789                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          53809789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50625                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103580183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157440597                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961045                       # Number of read requests accepted
-system.physmem.writeReqs                      1018263                       # Number of write requests accepted
-system.physmem.readBursts                     1961045                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1018263                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125425280                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65167232                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125506880                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65168832                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1275                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data            1952627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1953585                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022122                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022122                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                50700                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            103337983                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103388683                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           50700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              50700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54093294                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54093294                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54093294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               50700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           103337983                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              157481977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1953585                       # Number of read requests accepted
+system.physmem.writeReqs                      1022122                       # Number of write requests accepted
+system.physmem.readBursts                     1953585                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1022122                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                124947328                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     82112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65414528                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125029440                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65415808                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1283                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118758                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114090                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116233                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117775                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117826                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117520                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119879                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124540                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126979                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130098                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128644                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130342                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126070                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125249                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122589                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123178                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61223                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61482                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60569                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61241                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61665                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64149                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65619                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65334                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65779                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65299                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65645                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64166                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64211                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64570                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64186                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118324                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113533                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              115739                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117256                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117310                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117130                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119399                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124116                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126631                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129581                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128158                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             129926                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125582                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124841                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122135                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             122641                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61422                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61664                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60721                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61393                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61822                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63305                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64352                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65861                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65572                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66032                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65638                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65947                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64508                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64525                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64898                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64442                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1211096102000                       # Total gap between requests
+system.physmem.totGap                    1209314463000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961045                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1953585                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1018263                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1837965                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    121788                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1022122                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1829869                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    122416                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    59993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    59990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    59955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59988                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    59992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    60336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    30602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61039                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -193,129 +193,136 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1839625                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.602019                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.031630                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     129.543213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1461173     79.43%     79.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261967     14.24%     93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48998      2.66%     96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20657      1.12%     97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13124      0.71%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7476      0.41%     98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5272      0.29%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4494      0.24%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16464      0.89%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1839625                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59444                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.966456                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      164.214090                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59406     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           13      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            8      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59444                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59444                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.129365                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.093444                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.113658                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27743     46.67%     46.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1259      2.12%     48.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              26068     43.85%     92.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3874      6.52%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                419      0.70%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 52      0.09%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 24      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59444                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36839321750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73585009250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9798850000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18797.78                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples      1831684                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.926852                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.136404                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.467751                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1453241     79.34%     79.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261868     14.30%     93.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48841      2.67%     96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20589      1.12%     97.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13172      0.72%     98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7181      0.39%     98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5391      0.29%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4514      0.25%     99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16887      0.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1831684                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59621                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.743530                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      149.210927                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59467     99.74%     99.74% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          109      0.18%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            6      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-13823            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           59621                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59621                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.143322                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.107211                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.116873                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27512     46.14%     46.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1216      2.04%     48.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26386     44.26%     92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3971      6.66%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                453      0.76%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 62      0.10%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 10      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  9      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59621                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36542895500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73148558000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9761510000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18717.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37547.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         103.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          53.81                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      103.63                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       53.81                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37467.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         103.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          54.09                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      103.39                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       54.09                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.96                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     725244                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    413130                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.01                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.57                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406502.48                       # Average gap between requests
-system.physmem.pageHitRate                      38.23                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6747186600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3681500625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7383597000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3233831040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            79102439520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           416789244855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           361048893750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             877986693390                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.956282                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   597858043000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40440920000                       # Time in different power states
+system.physmem.avgWrQLen                        24.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     723569                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419148                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.06                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                       406395.68                       # Average gap between requests
+system.physmem.pageHitRate                      38.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6717619440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3665367750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7353894600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3243499200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            78986487840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           416110602285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           360579035250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             876656506365                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              724.920562                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   597088834750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     40381640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    572793401000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    571843431500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7160348160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3906936000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7901891400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3364351200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            79102439520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           428401624860                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           350862595500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             880700186640                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.196822                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   580834507250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40440920000                       # Time in different power states
+system.physmem_1.actEnergy                 7129911600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3890328750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7873975200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3379721760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            78986487840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           426511213875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           351455691750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             879227330775                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              727.046416                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   581836550250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     40381640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    589813744000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    587095716000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               246195404                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186411563                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15682149                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            167682775                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165241760                       # Number of BTB hits
+system.cpu.branchPred.lookups               246216332                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186427958                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15694657                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            167633562                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165258832                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.544266                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18427120                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104306                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.583380                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18428300                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104795                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452923392                       # DTB read hits
-system.cpu.dtb.read_misses                    4979932                       # DTB read misses
+system.cpu.dtb.read_hits                    452931478                       # DTB read hits
+system.cpu.dtb.read_misses                    4979966                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457903324                       # DTB read accesses
-system.cpu.dtb.write_hits                   161377581                       # DTB write hits
-system.cpu.dtb.write_misses                   1710142                       # DTB write misses
+system.cpu.dtb.read_accesses                457911444                       # DTB read accesses
+system.cpu.dtb.write_hits                   161379324                       # DTB write hits
+system.cpu.dtb.write_misses                   1710368                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163087723                       # DTB write accesses
-system.cpu.dtb.data_hits                    614300973                       # DTB hits
-system.cpu.dtb.data_misses                    6690074                       # DTB misses
+system.cpu.dtb.write_accesses               163089692                       # DTB write accesses
+system.cpu.dtb.data_hits                    614310802                       # DTB hits
+system.cpu.dtb.data_misses                    6690334                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620991047                       # DTB accesses
-system.cpu.itb.fetch_hits                   598257344                       # ITB hits
+system.cpu.dtb.data_accesses                621001136                       # DTB accesses
+system.cpu.itb.fetch_hits                   598312460                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               598257363                       # ITB accesses
+system.cpu.itb.fetch_accesses               598312479                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -329,82 +336,82 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2422192439                       # number of cpu cycles simulated
+system.cpu.numCycles                       2418629131                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      52052944                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      52090489                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.326227                       # CPI: cycles per instruction
-system.cpu.ipc                               0.754019                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2076133627                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       346058812                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9121955                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.744039                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           601604629                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126051                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.921682                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       16824784000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.744039                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996275                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996275                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.324276                       # CPI: cycles per instruction
+system.cpu.ipc                               0.755130                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2076311536                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       342317595                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121994                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.733344                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601608000                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126090                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.921769                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       16821289500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.733344                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996273                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996273                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1544                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2417                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1558                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1231402079                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1231402079                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    443119981                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       443119981                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158484648                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158484648                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     601604629                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        601604629                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    601604629                       # number of overall hits
-system.cpu.dcache.overall_hits::total       601604629                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7289531                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289531                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2243854                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2243854                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9533385                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9533385                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9533385                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9533385                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 186817706000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 186817706000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108924057250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108924057250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 295741763250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 295741763250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 295741763250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 295741763250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    450409512                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    450409512                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1231414126                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1231414126                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    443125970                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       443125970                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158482030                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158482030                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     601608000                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        601608000                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    601608000                       # number of overall hits
+system.cpu.dcache.overall_hits::total       601608000                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7289546                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289546                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2246472                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2246472                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9536018                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9536018                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9536018                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9536018                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185444020000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185444020000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108463697500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108463697500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293907717500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293907717500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293907717500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293907717500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    450415516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    450415516                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    611138014                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    611138014                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    611138014                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    611138014                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    611144018                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    611144018                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    611144018                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    611144018                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016184                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016184                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013961                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013961                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015599                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015599                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015599                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015599                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25628.220252                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25628.220252                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48543.290807                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48543.290807                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31021.695153                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31021.695153                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31021.695153                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31021.695153                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015604                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015604                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015604                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015604                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25439.721486                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25439.721486                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48281.793630                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48281.793630                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30820.801460                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30820.801460                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30820.801460                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30820.801460                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3700563                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700563                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50798                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50798                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       356536                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       356536                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       407334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       407334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       407334                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       407334                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238733                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238733                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887318                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887318                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126051                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126051                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126051                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126051                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174355280750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 174355280750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  82395435500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  82395435500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256750716250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 256750716250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256750716250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 256750716250                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3686660                       # number of writebacks
+system.cpu.dcache.writebacks::total           3686660                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50795                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50795                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359133                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       359133                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       409928                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       409928                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       409928                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       409928                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238751                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238751                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887339                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887339                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126090                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126090                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126090                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126090                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176979090000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 176979090000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83292376000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83292376000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260271466000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260271466000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260271466000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 260271466000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016071                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016071                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
@@ -447,67 +454,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014933
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014933                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014933                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014933                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24086.436224                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24086.436224                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43657.420477                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43657.420477                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28133.824395                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28133.824395                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28133.824395                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28133.824395                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.843454                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.843454                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44132.175513                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44132.175513                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.493671                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.493671                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.493671                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.493671                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           751.308351                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           598256386                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           751.748828                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           598311502                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          624484.745303                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624542.277662                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   751.308351                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.366850                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.366850                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   751.748828                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.367065                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.367065                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          875                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1196515646                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1196515646                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    598256386                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       598256386                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     598256386                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        598256386                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    598256386                       # number of overall hits
-system.cpu.icache.overall_hits::total       598256386                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        1196625878                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1196625878                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    598311502                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       598311502                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     598311502                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        598311502                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    598311502                       # number of overall hits
+system.cpu.icache.overall_hits::total       598311502                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
 system.cpu.icache.overall_misses::total           958                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     76776500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     76776500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     76776500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     76776500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     76776500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     76776500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    598257344                       # number of ReadReq accesses(hits+misses)
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80142.484342                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80142.484342                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80142.484342                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80142.484342                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80142.484342                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80142.484342                       # average overall miss latency
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 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -522,114 +528,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          958
 system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74938500                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78223.903967                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 79189.457203                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1928309                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30768.375630                       # Cycle average of tags in use
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77223.382046                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87904.062932                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87898.845259                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77223.382046                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87904.062932                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87898.845259                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.213961                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214043                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88108.328059                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88108.328059                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77687.369520                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77687.369520                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87358.078899                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87358.078899                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77687.369520                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87657.973848                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87653.084458                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77687.369520                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87657.973848                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87653.084458                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -638,105 +649,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018263                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018263                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1180648                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1181606                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       779439                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       779439                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1022122                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022122                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          245                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          245                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       780518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172109                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172109                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1960087                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961045                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1952627                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1953585                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1960087                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961045                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     61981000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  88565561250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  88627542250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  58963288250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  58963288250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61981000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147528849500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 147590830500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61981000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147528849500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 147590830500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163101                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163212                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.412988                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412988                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1952627                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1953585                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60964956000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60964956000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64844500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64844500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90672100500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90672100500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64844500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151637056500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 151701901000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64844500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151637056500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 151701901000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413555                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413555                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161921                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161921                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214779                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214862                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213961                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214043                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214779                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214862                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64698.329854                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75014.366052                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75006.002212                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75648.367929                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75648.367929                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64698.329854                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75266.480263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75261.317563                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64698.329854                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75266.480263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75261.317563                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213961                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214043                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78108.328059                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78108.328059                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67687.369520                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77358.078899                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77358.078899                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77657.973848                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.084458                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77657.973848                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.084458                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7239691                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7239691                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700563                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887318                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887318                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1916                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952665                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21954581                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp       7239709                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4708782                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6334073                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887339                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887339                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238751                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374174                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27376093                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820903296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820964608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12827572                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820016000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820077312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1920858                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20169903                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.095234                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.293538                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12827572    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18249045     90.48%     90.48% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1920858      9.52%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12827572                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10114349000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1637500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20169903                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12811182500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1437000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14015266250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1181606                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1181606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018263                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            779439                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           779439                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940353                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4940353                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190675712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190675712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy   13689135000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp            1173067                       # Transaction distribution
+system.membus.trans_dist::Writeback           1022122                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897712                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780518                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780518                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1173067                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827004                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5827004                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190445248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190445248                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2979308                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3873419                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2979308    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3873419    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2979308                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7754390500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10727987500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3873419                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8427454000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        10685206000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 58eeef87c..fd8f8a2dd 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.672882                       # Number of seconds simulated
-sim_ticks                                672881519500                       # Number of ticks simulated
-final_tick                               672881519500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.671755                       # Number of seconds simulated
+sim_ticks                                671754803000                       # Number of ticks simulated
+final_tick                               671754803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 165835                       # Simulator instruction rate (inst/s)
-host_op_rate                                   165835                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64276745                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226308                       # Number of bytes of host memory used
-host_seconds                                 10468.51                       # Real time elapsed on the host
+host_inst_rate                                 168955                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168955                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65376371                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298196                       # Number of bytes of host memory used
+host_seconds                                 10275.19                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             62400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125964544                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            126026944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125486976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125549376                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        62400                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           62400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65296192                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65296192                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65552256                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65552256                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                975                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1968196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1969171                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1020253                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1020253                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                92735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            187201670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               187294405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           92735                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              92735                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          97039657                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               97039657                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          97039657                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               92735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           187201670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              284334062                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1969171                       # Number of read requests accepted
-system.physmem.writeReqs                      1020253                       # Number of write requests accepted
-system.physmem.readBursts                     1969171                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1020253                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125945600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65294336                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 126026944                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65296192                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1271                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data            1960734                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961709                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1024254                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1024254                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                92891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            186804732                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               186897623                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           92891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              92891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97583606                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97583606                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97583606                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               92891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           186804732                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              284481229                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961709                       # Number of read requests accepted
+system.physmem.writeReqs                      1024254                       # Number of write requests accepted
+system.physmem.readBursts                     1961709                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1024254                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125464000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     85376                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65551040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125549376                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65552256                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1334                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              119102                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114505                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116613                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118153                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              118234                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117885                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              120369                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              125035                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127648                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130593                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             129299                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130947                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126747                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125863                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             123089                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123818                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61291                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61585                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60661                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61360                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61790                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63221                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64275                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65726                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65508                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65914                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65448                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65777                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64328                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64347                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64660                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64333                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118672                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113926                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116092                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117630                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117777                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117495                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119900                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124641                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127326                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130085                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128786                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130484                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125416                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122597                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123252                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61496                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61762                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60827                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61508                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61962                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63415                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64494                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65970                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65774                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66157                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65800                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66076                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64701                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64671                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65003                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64619                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    672881423000                       # Total gap between requests
+system.physmem.totGap                    671754707500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1969171                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961709                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1020253                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1621016                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    243733                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     72507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1024254                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1618535                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    241019                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69861                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30932                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    64414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    63055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    27711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49355                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    65054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62836                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -193,143 +193,150 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1777587                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.583217                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.835342                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     136.553801                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1382839     77.79%     77.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       271264     15.26%     93.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53815      3.03%     96.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21128      1.19%     97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12924      0.73%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6598      0.37%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5024      0.28%     98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3881      0.22%     98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20114      1.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1777587                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59878                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.821905                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      161.087941                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59840     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           12      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59878                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59878                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.038378                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.996376                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.234472                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              31771     53.06%     53.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1453      2.43%     55.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              20992     35.06%     90.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4585      7.66%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                809      1.35%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                191      0.32%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 31      0.05%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 14      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.bytesPerActivate::samples      1769993                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.917046                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.949504                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.477186                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1374954     77.68%     77.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       271630     15.35%     93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53313      3.01%     96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21496      1.21%     97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12783      0.72%     97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6453      0.36%     98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4820      0.27%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3869      0.22%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20675      1.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1769993                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60112                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.611592                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      146.109791                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59940     99.71%     99.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          128      0.21%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            7      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60112                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60112                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.038778                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.996488                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.239516                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              31933     53.12%     53.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1463      2.43%     55.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              20988     34.91%     90.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4635      7.71%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                815      1.36%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                185      0.31%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 40      0.07%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 14      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 10      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.00%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::30                  1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::34                  1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  3      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59878                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40967898000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77866023000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9839500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20818.08                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::35                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60112                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40612494250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77369525500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9801875000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20716.70                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39568.08                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         187.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          97.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      187.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       97.04                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39466.70                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         186.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.58                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      186.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.22                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     794560                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    415972                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.38                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.77                       # Row buffer hit rate for writes
-system.physmem.avgGap                       225087.32                       # Average gap between requests
-system.physmem.pageHitRate                      40.51                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6515684280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3555184875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7409165400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3239410320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            43949246640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           305964835695                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           135337912500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             505971439710                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.948773                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   223158478000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     22468940000                       # Time in different power states
+system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     792670                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    421939                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.19                       # Row buffer hit rate for writes
+system.physmem.avgGap                       224970.87                       # Average gap between requests
+system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6484688280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3538272375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7379814000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3249285840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           305078205825                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           135438254250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             505044026010                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.831975                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   223329404750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22431240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    427253308500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    425992710250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6922850760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3777349125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7940244000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3371641200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            43949246640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           312976099035                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           129187681500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             508125112260                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              755.149450                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   212887456750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     22468940000                       # Time in different power states
+system.physmem_1.actEnergy                 6896405880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3762919875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7910526000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3387653280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           312108901605                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           129270987000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             507212899080                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              755.060642                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   213031369750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22431240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    437523815750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    436288612000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               410709882                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         318998342                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          16277823                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            282986544                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               279468528                       # Number of BTB hits
+system.cpu.branchPred.lookups               410738673                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         319032195                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          16276977                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282876736                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               279471264                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.756826                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                26379180                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.796129                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26377862                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    646309229                       # DTB read hits
-system.cpu.dtb.read_misses                   12154225                       # DTB read misses
+system.cpu.dtb.read_hits                    646528255                       # DTB read hits
+system.cpu.dtb.read_misses                   12150594                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                658463454                       # DTB read accesses
-system.cpu.dtb.write_hits                   218201258                       # DTB write hits
-system.cpu.dtb.write_misses                   7510092                       # DTB write misses
+system.cpu.dtb.read_accesses                658678849                       # DTB read accesses
+system.cpu.dtb.write_hits                   218209856                       # DTB write hits
+system.cpu.dtb.write_misses                   7511426                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               225711350                       # DTB write accesses
-system.cpu.dtb.data_hits                    864510487                       # DTB hits
-system.cpu.dtb.data_misses                   19664317                       # DTB misses
+system.cpu.dtb.write_accesses               225721282                       # DTB write accesses
+system.cpu.dtb.data_hits                    864738111                       # DTB hits
+system.cpu.dtb.data_misses                   19662020                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                884174804                       # DTB accesses
-system.cpu.itb.fetch_hits                   422619736                       # ITB hits
-system.cpu.itb.fetch_misses                        46                       # ITB misses
+system.cpu.dtb.data_accesses                884400131                       # DTB accesses
+system.cpu.itb.fetch_hits                   422614397                       # ITB hits
+system.cpu.itb.fetch_misses                        44                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               422619782                       # ITB accesses
+system.cpu.itb.fetch_accesses               422614441                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -343,139 +350,139 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1345763040                       # number of cpu cycles simulated
+system.cpu.numCycles                       1343509607                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          433914332                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3420599858                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   410709882                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          305847708                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     888768265                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                46015780                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          433913722                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3420789895                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   410738673                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          305849126                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     886512749                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                46016020                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1748                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          113                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 422619736                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8427195                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1345692377                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.541888                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.149351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles          1692                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 422614397                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8419525                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1343436257                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.546299                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.150257                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                718495980     53.39%     53.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 48031633      3.57%     56.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 24393578      1.81%     58.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 45267643      3.36%     62.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                143041045     10.63%     72.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 66223895      4.92%     77.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43793513      3.25%     80.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 29627313      2.20%     83.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226817777     16.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                716181443     53.31%     53.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 48040729      3.58%     56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24412482      1.82%     58.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45272149      3.37%     62.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                143062816     10.65%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 66221905      4.93%     77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43789018      3.26%     80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29632862      2.21%     83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226822853     16.88%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1345692377                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305187                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.541755                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                355603714                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             406294583                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 525817435                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              34969591                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               23007054                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             62310888                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   895                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3264812656                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2282                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               23007054                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                373973816                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               212778142                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7997                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 538797541                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             197127827                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3181847820                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1862600                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20249864                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              150635497                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               31416943                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2377870821                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4127617004                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4127447466                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            169537                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1343436257                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305721                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.546160                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                355607674                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             404003493                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 525762782                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              35055109                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23007199                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62310513                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   875                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3265200378                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2135                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               23007199                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                373983702                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               211600441                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6939                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 538809166                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             196028810                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3182220984                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1833786                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20271739                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              149993150                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30859152                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2378179455                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4128151916                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4127979405                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            172510                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1001667858                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                209                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            206                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  99280769                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            719325488                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           272942348                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90808423                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         59047660                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2890368727                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 181                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2624396643                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1584497                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1154325126                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    506084435                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            152                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1345692377                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.950220                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.146970                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps               1001976492                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                195                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            195                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99605318                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            719399499                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272964536                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90785513                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58783416                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2890757443                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 174                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2624793649                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1589988                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1154713835                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    506306579                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            145                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1343436257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.953791                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.147325                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           540762104     40.18%     40.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           169795677     12.62%     52.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           158437148     11.77%     64.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149383051     11.10%     75.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           126329288      9.39%     85.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            84501883      6.28%     91.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            68040537      5.06%     96.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            34033784      2.53%     98.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            14408905      1.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           538259461     40.07%     40.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           170012804     12.66%     52.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           158478310     11.80%     64.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149374624     11.12%     75.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126330762      9.40%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84386661      6.28%     91.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68107665      5.07%     96.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34089750      2.54%     98.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14396220      1.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1345692377                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1343436257                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                13165371     35.79%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               19036657     51.75%     87.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4585623     12.47%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13176390     35.76%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               19068779     51.75%     87.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4600766     12.49%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1719509054     65.52%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  111      0.00%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1719677353     65.52%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  114      0.00%     65.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              896832      0.03%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  17      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 164      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 25      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              897887      0.03%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  16      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 158      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 22      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.55% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.55% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.55% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.55% # Type of FU issued
@@ -497,84 +504,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.55% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.55% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.55% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            673114194     25.65%     91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           230876222      8.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            673327193     25.65%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230890880      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2624396643                       # Type of FU issued
-system.cpu.iq.rate                           1.950118                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36787651                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014018                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6630876089                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4043543263                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2522176401                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1981722                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1297099                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       893189                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2660200136                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  984158                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         69569005                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2624793649                       # Type of FU issued
+system.cpu.iq.rate                           1.953684                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36845935                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014038                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6629473751                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4044314699                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2522399915                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1985727                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1304235                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       894550                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2660653801                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  985783                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69567792                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    274729825                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       379855                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       148630                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    112213846                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    274803836                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       379517                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       149864                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    112236034                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          321                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6130129                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          312                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6300661                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               23007054                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               150994559                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              20053347                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3041642230                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6687101                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             719325488                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            272942348                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                181                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 819254                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              19491023                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         148630                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10888571                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8843177                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19731748                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2578706854                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             658463458                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          45689789                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               23007199                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               150535686                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              19606000                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3042042837                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6687461                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             719399499                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272964536                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                174                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 810054                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              19058140                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         149864                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10895731                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8841524                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19737255                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2579092054                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             658678856                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45701595                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     151273322                       # number of nop insts executed
-system.cpu.iew.exec_refs                    884174883                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                315972780                       # Number of branches executed
-system.cpu.iew.exec_stores                  225711425                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.916167                       # Inst execution rate
-system.cpu.iew.wb_sent                     2553063246                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2523069590                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1489308587                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1920703402                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     151285220                       # number of nop insts executed
+system.cpu.iew.exec_refs                    884400225                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315980786                       # Number of branches executed
+system.cpu.iew.exec_stores                  225721369                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.919668                       # Inst execution rate
+system.cpu.iew.wb_sent                     2553280591                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2523294465                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1489396348                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1920808747                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.874825                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.775397                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.878137                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775401                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts      1005912526                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts      1006176660                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16276987                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1206693157                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.508072                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.543192                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16276166                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1204408845                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.510932                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.544476                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    717446911     59.46%     59.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    159887401     13.25%     72.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     79830197      6.62%     79.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52027392      4.31%     83.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28503242      2.36%     85.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     19553290      1.62%     87.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     20023421      1.66%     89.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23140213      1.92%     91.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106281090      8.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    715098033     59.37%     59.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159881136     13.27%     72.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79829015      6.63%     79.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52096588      4.33%     83.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28578407      2.37%     85.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19544658      1.62%     87.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     20010855      1.66%     89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23112076      1.92%     91.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106258077      8.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1206693157                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1204408845                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -620,340 +627,344 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             106281090                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3840325519                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5790523687                       # The number of ROB writes
-system.cpu.timesIdled                             690                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           70663                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events             106258077                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3838328354                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5791077348                       # The number of ROB writes
+system.cpu.timesIdled                             692                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           73350                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.775190                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.775190                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.290007                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.290007                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3468053564                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2022530151                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     45442                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      563                       # number of floating regfile writes
+system.cpu.cpi                               0.773892                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.773892                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.292171                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.292171                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3468538615                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2022734233                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     46009                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      540                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9208756                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.479772                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           713775439                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9212852                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             77.476056                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5132407000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.479772                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997920                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997920                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9208722                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.471997                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           713777147                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9212818                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.476527                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5130746500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.471997                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997918                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997918                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          697                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2970                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          709                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2958                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1472909430                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1472909430                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    558274718                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       558274718                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155500717                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155500717                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     713775435                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        713775435                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    713775435                       # number of overall hits
-system.cpu.dcache.overall_hits::total       713775435                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12845064                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12845064                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5227785                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5227785                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1473023486                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1473023486                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    558278644                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       558278644                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155498498                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155498498                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            5                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            5                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     713777142                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        713777142                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    713777142                       # number of overall hits
+system.cpu.dcache.overall_hits::total       713777142                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12898182                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12898182                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5230004                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5230004                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     18072849                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       18072849                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     18072849                       # number of overall misses
-system.cpu.dcache.overall_misses::total      18072849                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 414536288750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 316664843212                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     18128186                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18128186                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18128186                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18128186                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 411532558500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315240579886                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 731201131962                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 731201131962                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 731201131962                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 731201131962                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    571119782                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    571119782                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 726773138386                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 726773138386                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 726773138386                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 726773138386                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    571176826                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    571176826                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            5                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            5                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    731848284                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    731848284                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    731848284                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    731848284                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022491                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022491                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032526                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032526                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.200000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.200000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024695                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024695                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024695                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024695                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    731905328                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    731905328                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    731905328                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    731905328                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022582                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022582                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032539                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032539                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024768                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024768                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024768                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024768                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31906.245275                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31906.245275                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60275.399385                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60275.399385                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40458.542644                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40458.542644                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     15275634                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9588635                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1068737                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67992                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.293165                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   141.025930                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40090.781195                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40090.781195                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     15662934                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      9568706                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1102908                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67982                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.201487                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   140.753523                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3742849                       # number of writebacks
-system.cpu.dcache.writebacks::total           3742849                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5511228                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5511228                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3348770                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3348770                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8859998                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8859998                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8859998                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8859998                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333836                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7333836                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879015                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1879015                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3728522                       # number of writebacks
+system.cpu.dcache.writebacks::total           3728522                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5564399                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5564399                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350970                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3350970                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8915369                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8915369                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8915369                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8915369                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333783                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7333783                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879034                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879034                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9212851                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9212851                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9212851                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9212851                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83364623703                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83364623703                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 263886414453                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 263886414453                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012841                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012841                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9212817                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9212817                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9212817                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9212817                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183008143000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183008143000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84351384400                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84351384400                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267359527400                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 267359527400                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267359527400                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 267359527400                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012840                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012840                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011691                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011691                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.200000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012588                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012588                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012588                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012588                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012587                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012587                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.125722                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.125722                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44890.823902                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44890.823902                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           773.497223                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           422618194                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           774.831914                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           422612882                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               975                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          433454.557949                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          433449.109744                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   773.497223                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.377684                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.377684                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   774.831914                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.378336                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.378336                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          974                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          906                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          909                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.475586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         845240447                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        845240447                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    422618194                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       422618194                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     422618194                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        422618194                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    422618194                       # number of overall hits
-system.cpu.icache.overall_hits::total       422618194                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1542                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1542                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1542                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1542                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1542                       # number of overall misses
-system.cpu.icache.overall_misses::total          1542                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    116278500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    116278500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    116278500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    116278500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    116278500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    116278500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    422619736                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    422619736                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    422619736                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    422619736                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    422619736                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    422619736                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         845229769                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        845229769                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    422612882                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       422612882                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     422612882                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        422612882                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    422612882                       # number of overall hits
+system.cpu.icache.overall_hits::total       422612882                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1515                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1515                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1515                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1515                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1515                       # number of overall misses
+system.cpu.icache.overall_misses::total          1515                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    116523500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    116523500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    116523500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    116523500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    116523500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    116523500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    422614397                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    422614397                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    422614397                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    422614397                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    422614397                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    422614397                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75407.587549                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75407.587549                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          435                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76913.201320                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76913.201320                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76913.201320                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76913.201320                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          961                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    62.142857                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   120.125000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          567                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          567                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          567                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          567                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          567                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          567                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          540                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          540                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          975                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          975                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          975                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          975                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79199000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     79199000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     79199000                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 84989.230769                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1936457                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31413.219008                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9110872                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1966244                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.633643                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      28158140750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14523.555801                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.886283                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16862.776924                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615                       # Occupied blocks per task id
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 system.cpu.l2cache.demand_accesses::cpu.inst          975                       # number of demand (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83483.589744                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89704.293647                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89701.201860                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -962,105 +973,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total          1020253                       # number of writebacks
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+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          241                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total      1969171                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     66029500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  92659024750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  92725054250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  59593481750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  59593481750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66029500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66029500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163199                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163311                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.410489                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.410489                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1960734                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961709                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61629949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61629949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     71646500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     71646500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94648969500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94648969500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71646500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71646500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.410986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.410986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162055                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162055                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213636                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.213719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.212910                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213636                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.213719                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.212910                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7334797                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7334797                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3742849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1879030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1879030                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1950                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22168553                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22170503                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp       7334745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4752776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6384952                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          975                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333770                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1951                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27634358                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27636309                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        62400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    829164864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          829227264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12956676                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828245760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          828308160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1929005                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20351521                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.094784                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.292917                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12956676    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18422516     90.52%     90.52% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1929005      9.48%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12956676                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10221187000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1642000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20351521                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12939780000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1462500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14136511250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13819227000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1197850                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1197850                       # Transaction distribution
-system.membus.trans_dist::Writeback           1020253                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            771321                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           771321                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4958595                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4958595                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191323136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191323136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1189447                       # Transaction distribution
+system.membus.trans_dist::Writeback           1024254                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           903687                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            772262                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           772262                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1189447                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5851359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191101632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               191101632                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2989424                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3889650                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2989424    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3889650    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2989424                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7771933000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10726595500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3889650                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8475841500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        10684260000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 6346aa78f..018ebe8b0 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.623365                       # Number of seconds simulated
-sim_ticks                                2623365440500                       # Number of ticks simulated
-final_tick                               2623365440500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.623057                       # Number of seconds simulated
+sim_ticks                                2623057163500                       # Number of ticks simulated
+final_tick                               2623057163500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1411989                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1411989                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2035500124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294160                       # Number of bytes of host memory used
-host_seconds                                  1288.81                       # Real time elapsed on the host
+host_inst_rate                                1251674                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1251674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1804181213                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294596                       # Number of bytes of host memory used
+host_seconds                                  1453.88                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125367104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125418432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124892160                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124943488                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        51328                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           51328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65156928                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65156928                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65405568                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65405568                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                802                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1958861                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1959663                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018077                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018077                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                19566                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47788654                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47808220                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           19566                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              19566                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          24837153                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               24837153                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          24837153                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               19566                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47788654                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               72645373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data            1951440                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1952242                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1021962                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1021962                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                19568                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             47613206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                47632774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           19568                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              19568                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          24934862                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               24934862                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          24934862                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               19568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            47613206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               72567635                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       5246730881                       # number of cpu cycles simulated
+system.cpu.numCycles                       5246114327                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1819780127                       # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs                     611922547                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5246730881                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5246114327                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
@@ -129,14 +129,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1826378509                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9107638                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4079.262739                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4079.260769                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           596212431                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       40977437000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4079.262739                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995914                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995914                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       40977438500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4079.260769                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995913                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data      9111734                       # n
 system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143355355000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57375808000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57375808000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200731163000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200731163000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200731163000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200731163000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143001525000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57421337000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57421337000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200422862000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200422862000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200422862000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200422862000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_miss_rate::total     0.015053                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015053                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22029.963013                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22029.963013                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21996.127411                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21996.127411                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3693497                       # number of writebacks
-system.cpu.dcache.writebacks::total           3693497                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3679426                       # number of writebacks
+system.cpu.dcache.writebacks::total           3679426                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222414                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7222414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889320                       # number of WriteReq MSHR misses
@@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9111734
 system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  54541828000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  54541828000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 187063562000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187063562000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55532017000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  55532017000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191311128000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191311128000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
@@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015053                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           612.458786                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           612.447387                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1826377708                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          2277278.937656                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   612.458786                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.299052                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.299052                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   612.447387                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.299047                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.299047                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          730                       # Occupied blocks per task id
@@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst          802                       # n
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44139500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44139500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44139500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44139500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44139500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44139500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44163500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44163500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44163500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44163500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44163500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44163500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
@@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55036.783042                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55036.783042                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55066.708229                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55066.708229                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -302,114 +302,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          802
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42936500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     42936500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42936500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     42936500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42936500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     42936500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43361500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     43361500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43361500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     43361500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43361500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     43361500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1926937                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30535.253333                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8959453                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1956729                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.578791                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     218167126000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    39.064589                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.464534                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001192                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.466135                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.931862                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1919524                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30534.757407                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14380256                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1949316                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.377078                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     218167130000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    38.972607                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.460854                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001189                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.469803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.931847                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29792                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1060                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1253                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1062                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27300                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106294313                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106294313                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6044854                       # number of ReadReq hits
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+system.cpu.l2cache.tags.tag_accesses        149600036                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149600036                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3679426                       # number of Writeback hits
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61828353000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 102846661500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data 102846661500                       # number of overall miss cycles
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+system.cpu.l2cache.Writeback_accesses::total      3679426                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889320                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889320                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
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 system.cpu.l2cache.demand_accesses::total      9112536                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      9111734                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      9112536                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163042                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413536                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214982                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214982                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.215051                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214168                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214237                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -418,105 +423,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018077                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018077                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177560                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total       781301                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1021962                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1021962                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          243                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          243                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782385                       # number of ReadExReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1958861                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  79340329500                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163042                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163135                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214982                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.215051                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214982                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.215051                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7223216                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       7223216                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3693497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4701388                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6325775                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889320                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889320                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1604                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916965                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21918569                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222414                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1605                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27331106                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27332711                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819534784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          819586112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12806033                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818634240                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          818685568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919524                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20139699                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.095310                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.293643                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12806033    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18220175     90.47%     90.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1919524      9.53%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12806033                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10096513500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.4                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20139699                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12789513500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1203000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13667601000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1178362                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1178362                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018077                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            781301                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           781301                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4937403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190575360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1169857                       # Transaction distribution
+system.membus.trans_dist::Writeback           1021962                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           896683                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            782385                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           782385                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1169857                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5823129                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5823129                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190349056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190349056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2977740                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3872712                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2977740    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3872712    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2977740                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7156873500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3872712                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7960873524                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9798315500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9761522024                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index fd798006f..27ca4a2ca 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.119236                       # Number of seconds simulated
-sim_ticks                                1119236001500                       # Number of ticks simulated
-final_tick                               1119236001500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.117365                       # Number of seconds simulated
+sim_ticks                                1117365374500                       # Number of ticks simulated
+final_tick                               1117365374500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 240571                       # Simulator instruction rate (inst/s)
-host_op_rate                                   259178                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              174324523                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314620                       # Number of bytes of host memory used
-host_seconds                                  6420.42                       # Real time elapsed on the host
+host_inst_rate                                 236504                       # Simulator instruction rate (inst/s)
+host_op_rate                                   254797                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              171091237                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314716                       # Number of bytes of host memory used
+host_seconds                                  6530.82                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         131457472                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131507904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     66959680                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          66959680                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                788                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2054023                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2054811                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1046245                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1046245                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                45059                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117452862                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117497922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           45059                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              45059                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          59826239                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               59826239                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          59826239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               45059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117452862                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177324160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2054811                       # Number of read requests accepted
-system.physmem.writeReqs                      1046245                       # Number of write requests accepted
-system.physmem.readBursts                     2054811                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1046245                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                131422592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     85312                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  66958080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131507904                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               66959680                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1333                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             50752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         130973248                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131024000                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67225152                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          67225152                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                793                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2046457                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2047250                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1050393                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1050393                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                45421                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117216133                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117261554                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           45421                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              45421                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60163984                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60163984                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60163984                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               45421                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117216133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177425537                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2047250                       # Number of read requests accepted
+system.physmem.writeReqs                      1050393                       # Number of write requests accepted
+system.physmem.readBursts                     2047250                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1050393                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                130939136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     84864                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  67223488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131024000                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               67225152                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1326                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              127863                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125217                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122173                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124176                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              123271                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              123280                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123668                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124134                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131770                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              134069                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132400                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133571                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133882                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133894                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129882                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130228                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               65769                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64155                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62373                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               62858                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62829                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               62965                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64230                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65234                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67002                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67576                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67286                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67640                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67022                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67467                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66208                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65606                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              127156                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              124552                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              121687                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              123679                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              122821                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              122785                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123231                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              123758                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131446                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              133531                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132174                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133285                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133312                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133367                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129415                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             129725                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               66071                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               64336                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62582                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               63010                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               63074                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63174                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64441                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65447                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67324                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67820                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67591                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67884                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67359                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67795                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66531                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65928                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1119235907000                       # Total gap between requests
+system.physmem.totGap                    1117365281000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2054811                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2047250                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1046245                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1925781                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    127679                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1050393                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1917221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    128684                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56963                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    61003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56925                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    61237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,108 +193,106 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1918760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.389572                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.724365                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     124.748032                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1494097     77.87%     77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305195     15.91%     93.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52958      2.76%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21140      1.10%     97.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13031      0.68%     98.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7420      0.39%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5500      0.29%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5087      0.27%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14332      0.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1918760                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60963                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.636353                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      160.963797                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60925     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           12      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           11      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1911200                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.683951                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.827915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.443095                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1486351     77.77%     77.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305207     15.97%     93.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52508      2.75%     96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21149      1.11%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13340      0.70%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7581      0.40%     98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5505      0.29%     98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5122      0.27%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14437      0.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1911200                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61162                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.403649                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      159.275472                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61115     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           22      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60963                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60963                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.161557                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.126473                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.099462                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27343     44.85%     44.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1128      1.85%     46.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28298     46.42%     93.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3779      6.20%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                354      0.58%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 49      0.08%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61162                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61162                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.173523                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.138356                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.100510                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27168     44.42%     44.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1036      1.69%     46.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28675     46.88%     93.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3829      6.26%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                390      0.64%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 50      0.08%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  3      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60963                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38392697500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76895410000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10267390000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18696.43                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           61162                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38200049000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76561124000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10229620000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18671.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37446.43                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         117.42                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          59.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      117.50                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       59.83                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37421.29                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         117.19                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          60.16                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      117.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       60.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.38                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.39                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.22                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     774740                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    406194                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.73                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.82                       # Row buffer hit rate for writes
-system.physmem.avgGap                       360920.90                       # Average gap between requests
-system.physmem.pageHitRate                      38.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7079751000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3862959375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7751413800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3307476240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            73102957200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           422173404720                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           301213311750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             818491274085                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.295434                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   498371051250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     37373700000                       # Time in different power states
+system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     773325                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    411756                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.80                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.20                       # Row buffer hit rate for writes
+system.physmem.avgGap                       360714.67                       # Average gap between requests
+system.physmem.pageHitRate                      38.27                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 7043954400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3843427500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7719106200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3318634800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            72980394240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           421878506670                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           300346094250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             817130118060                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.305386                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   496942671500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     37311040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    583490028750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    583108431500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7426074600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4051925625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8265605400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3472029360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            73102957200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           430406880300                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           293990964750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             820716437235                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.283545                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   486308465000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     37373700000                       # Time in different power states
+system.physmem_1.actEnergy                 7404702480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4040264250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8238734400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3487743360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            72980394240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           429447905460                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           293706270750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             819306014940                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.252744                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   485853174500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     37311040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    595553667000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    594197830000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               239764270                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186476421                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14595676                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            130796554                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122091083                       # Number of BTB hits
+system.cpu.branchPred.lookups               239770012                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186474623                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14592511                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            129773424                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122091028                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.344266                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15654091                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             94.080147                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15653619                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -414,68 +412,68 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2238472003                       # number of cpu cycles simulated
+system.cpu.numCycles                       2234730749                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41626992                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41613452                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.449259                       # CPI: cycles per instruction
-system.cpu.ipc                               0.690008                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1834950604                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       403521399                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9221835                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.627405                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624240644                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9225931                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.661534                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        9809256250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.627405                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997468                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997468                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.446837                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691163                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1834912752                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       399817997                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9221614                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.621118                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624237491                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9225710                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.662813                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        9804990500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.621118                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997466                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997466                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          244                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1227                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2564                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276887063                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276887063                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453909121                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453909121                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331400                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331400                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276880692                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276880692                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453906230                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453906230                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331138                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331138                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624240521                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624240521                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624240522                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624240522                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7335273                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7335273                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254647                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254647                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     624237368                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624237368                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624237369                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624237369                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7335089                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7335089                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254909                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254909                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9589920                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9589920                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9589922                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9589922                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 192354012246                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109627439500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 301981451746                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 301981451746                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 301981451746                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 301981451746                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461244394                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461244394                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9589998                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9589998                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9590000                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9590000                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 191000565000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 191000565000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109144177000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109144177000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 300144742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 300144742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 300144742000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 300144742000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461241319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461241319                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -484,28 +482,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633830441                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633830441                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633830444                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633830444                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    633827366                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633827366                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633827369                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633827369                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015903                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015903                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013064                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013064                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013065                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013065                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31489.465162                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31489.458595                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26039.297546                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26039.297546                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48402.918699                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48402.918699                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31297.685568                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31297.685568                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31297.679041                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31297.679041                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -514,38 +512,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3700642                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700642                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       363775                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       363775                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       363990                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       363990                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       363990                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       363990                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7335058                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7335058                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890872                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890872                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3684549                       # number of writebacks
+system.cpu.dcache.writebacks::total           3684549                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          211                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364078                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       364078                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       364289                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       364289                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       364289                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       364289                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334878                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7334878                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890831                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890831                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9225930                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9225930                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9225931                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9225931                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83925664500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83925664500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        73750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        73750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 264859894504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 264859968254                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015903                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015903                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9225709                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9225709                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9225710                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9225710                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183660145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183660145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84822237000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84822237000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        74000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        74000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268482382000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 268482382000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268482456000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 268482456000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for SoftPFReq accesses
@@ -554,69 +552,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014556
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014556                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014556                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014556                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        73750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        73750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25039.291042                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25039.291042                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44859.766420                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44859.766420                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        74000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        74000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29101.544608                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29101.544608                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29101.549474                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29101.549474                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.tagsinuse           662.446494                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           465464024                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               821                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          566947.654080                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                32                       # number of replacements
+system.cpu.icache.tags.tagsinuse           663.200919                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           465452181                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               826                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          563501.429782                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   662.446494                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.323460                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.323460                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          792                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   663.200919                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.323829                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.323829                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          794                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          755                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.386719                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         930930511                       # Number of tag accesses
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-system.cpu.icache.overall_misses::total           821                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     63001249                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     63001249                       # number of ReadReq miss cycles
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
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 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76737.209501                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76737.209501                       # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 76737.209501                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76737.209501                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76737.209501                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.874092                       # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.874092                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76053.874092                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -625,123 +623,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          821                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74832.218027                       # average ReadReq mshr miss latency
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2022107                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31260.648625                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8983908                       # Total number of references to valid blocks.
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87760.853071                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87756.490119                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76398.288973                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87760.853071                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87756.490119                       # average overall miss latency
+system.cpu.l2cache.overall_hits::cpu.data      7179249                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7179281                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       801299                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       801299                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          794                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          794                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1245162                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1245162                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          794                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2046461                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2047255                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          794                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2046461                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2047255                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70488254000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  70488254000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     60418000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     60418000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108710111500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 108710111500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     60418000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 179198365500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 179258783500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     60418000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 179198365500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 179258783500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      3684549                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3684549                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890831                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1890831                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          826                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          826                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7334879                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7334879                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          826                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9225710                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9226536                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          826                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9225710                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9226536                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423781                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.423781                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.961259                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.961259                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169759                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169759                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961259                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.221822                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.221888                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.961259                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.221822                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.221888                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87967.480304                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87967.480304                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76093.198992                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76093.198992                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87305.998336                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87305.998336                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76093.198992                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87565.003926                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87560.554743                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76093.198992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87565.003926                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87560.554743                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -750,114 +754,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1046245                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1046245                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks      1050393                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1050393                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          788                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1254070                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1254858                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       799953                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       799953                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          788                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2054023                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2054811                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          788                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2054023                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2054811                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     50399250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  93887019000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  93937418250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60414024000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60414024000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50399250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50399250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.959805                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.170969                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171058                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959805                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222636                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.222701                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222636                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.222701                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456                       # average overall mshr miss latency
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          246                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          246                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       801299                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       801299                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          793                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          793                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1245158                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1245158                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          793                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2046457                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2047250                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          793                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2046457                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2047250                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62475264000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62475264000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52472500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52472500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  96258268000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  96258268000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52472500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158733532000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 158786004500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52472500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158733532000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 158786004500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423781                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423781                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.960048                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169758                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169758                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221821                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.221887                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221821                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.221887                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77967.480304                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77967.480304                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66169.609079                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77306.067182                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77306.067182                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77565.046322                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77560.632312                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77565.046322                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77560.632312                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7335880                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7335880                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700642                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890872                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890872                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1642                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22152504                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22154146                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827300672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          827353216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12927394                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7335705                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4734942                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6499660                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890831                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890831                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          826                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334879                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1684                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27671440                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27673124                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826256576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          826309440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2014550                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20462732                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.098450                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.297922                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12927394    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18448182     90.16%     90.16% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            2014550      9.84%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12927394                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10164339000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1397749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20462732                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12908640000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1239499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14187903746                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1254858                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1254858                       # Transaction distribution
-system.membus.trans_dist::Writeback           1046245                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            799953                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           799953                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5155867                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5155867                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198467584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198467584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy   13838566996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp            1245951                       # Transaction distribution
+system.membus.trans_dist::Writeback           1050393                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           963109                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            801299                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           801299                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1245951                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6108002                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6108002                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198249152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198249152                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3101056                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4060752                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3101056    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4060752    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3101056                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7929911000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11237799750                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4060752                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8665729500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        11195509250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index d2f403426..493c10cfc 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.771725                       # Number of seconds simulated
-sim_ticks                                771725169000                       # Number of ticks simulated
-final_tick                               771725169000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.770277                       # Number of seconds simulated
+sim_ticks                                770277033000                       # Number of ticks simulated
+final_tick                               770277033000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 137392                       # Simulator instruction rate (inst/s)
-host_op_rate                                   148019                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68646343                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311812                       # Number of bytes of host memory used
-host_seconds                                 11242.04                       # Real time elapsed on the host
+host_inst_rate                                 139677                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150481                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69657391                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313196                       # Number of bytes of host memory used
+host_seconds                                 11058.08                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             66304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         238609216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63286144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            301961664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        66304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           66304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104822848                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104822848                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1036                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3728269                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       988846                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4718151                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1637857                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1637857                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                85917                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            309189366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82006065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               391281347                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           85917                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              85917                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         135829246                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              135829246                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         135829246                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               85917                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           309189366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82006065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              527110594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4718151                       # Number of read requests accepted
-system.physmem.writeReqs                      1637857                       # Number of write requests accepted
-system.physmem.readBursts                     4718151                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1637857                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                301519872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    441792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104820544                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 301961664                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104822848                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     6903                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      19                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             66048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         238802560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63353600                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            302222208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        66048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           66048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104930816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104930816                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3731290                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       989900                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4722222                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1639544                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1639544                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                85746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            310021654                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82247811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               392355211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           85746                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              85746                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         136224776                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              136224776                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         136224776                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               85746                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           310021654                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82247811                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              528579987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4722222                       # Number of read requests accepted
+system.physmem.writeReqs                      1639544                       # Number of write requests accepted
+system.physmem.readBursts                     4722222                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1639544                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                301770432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    451776                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104928448                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 302222208                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104930816                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7059                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              296668                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              294562                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              288307                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              292737                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              290232                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              289394                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              285167                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              280683                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              297292                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              302920                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             295430                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             301815                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             303322                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             302849                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             297025                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             292845                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              103942                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              102053                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99317                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               99871                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               99169                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98963                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102735                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104389                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105226                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104532                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102159                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102806                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103028                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102702                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104263                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102666                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              297173                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              295012                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              289245                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              293018                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              289731                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              289594                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              284433                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              281274                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              297880                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              304149                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             295533                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             302217                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             302962                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             302377                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             297334                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             293231                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              104274                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              102166                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99582                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              100201                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99226                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               98958                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102876                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104542                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105498                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104632                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102325                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102766                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102939                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102535                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104418                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102569                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    771725022000                       # Total gap between requests
+system.physmem.totGap                    770276886500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4718151                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4722222                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1637857                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2774626                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1044189                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    331696                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    233512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    153773                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     84990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     39149                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4255                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1688                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      754                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      411                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1639544                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2779707                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1048806                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    331545                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    232118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    150885                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     83926                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     38903                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23907                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18114                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4239                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      740                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      412                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      195                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    22760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    59860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    75448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    99273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   106536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   107239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   108154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   113547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   106733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   103419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   101598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    23226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    24914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    60170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    75550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    85536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   100036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   106329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   106819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   108389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   111286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   114103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   105493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   102233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   101372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2580                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      427                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -197,122 +197,121 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4287400                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       94.775232                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.917076                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     101.448471                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3413764     79.62%     79.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       675374     15.75%     95.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        96809      2.26%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35249      0.82%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22885      0.53%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12087      0.28%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7187      0.17%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5043      0.12%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19002      0.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4287400                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         98767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.700609                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       32.313411                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       98.282358                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-127           94950     96.14%     96.14% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-255          1367      1.38%     97.52% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-383           770      0.78%     98.30% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-511           428      0.43%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-639           356      0.36%     99.09% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::640-767           374      0.38%     99.47% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-895           247      0.25%     99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::896-1023          145      0.15%     99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1151           66      0.07%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1152-1279           31      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1407           13      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1408-1535            9      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      4293402                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       94.726038                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.887603                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     101.441683                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3419558     79.65%     79.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       676188     15.75%     95.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        96097      2.24%     97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35320      0.82%     98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22691      0.53%     98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12222      0.28%     99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7184      0.17%     99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5103      0.12%     99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19039      0.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4293402                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         98787                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.730481                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       32.341812                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       98.609970                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-127           94999     96.17%     96.17% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-255          1343      1.36%     97.52% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-383           771      0.78%     98.31% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::384-511           397      0.40%     98.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-639           383      0.39%     99.10% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::640-767           367      0.37%     99.47% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-895           255      0.26%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::896-1023          139      0.14%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1151           71      0.07%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1152-1279           36      0.04%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1407           14      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1408-1535            4      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-1663            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1792-1919            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1920-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2688-2815            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2944-3071            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3199            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3200-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2175            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2176-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3328-3455            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           98767                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         98767                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.582674                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.549780                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.086524                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              73305     74.22%     74.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1806      1.83%     76.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18343     18.57%     94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3630      3.68%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                937      0.95%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                387      0.39%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                162      0.16%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                107      0.11%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 60      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 22      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  6      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::3456-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3840-3967            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3968-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           98787                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         98787                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.596384                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.562558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.102794                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              72931     73.83%     73.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1712      1.73%     75.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18497     18.72%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3886      3.93%     98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               1013      1.03%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                377      0.38%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                169      0.17%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 93      0.09%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 49      0.05%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 46      0.05%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 12      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           98767                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   132285118194                       # Total ticks spent queuing
-system.physmem.totMemAccLat              220621018194                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23556240000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28078.57                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           98787                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   131372718643                       # Total ticks spent queuing
+system.physmem.totMemAccLat              219782024893                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23575815000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27861.76                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46828.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         390.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         135.83                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      391.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      135.83                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46611.76                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         391.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         136.22                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      392.36                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      136.22                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.11                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           4.12                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.06                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1709073                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    352585                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.28                       # Row buffer hit rate for reads
+system.physmem.readRowHits                    1708262                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    352995                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.23                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  21.53                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121416.62                       # Average gap between requests
-system.physmem.pageHitRate                      32.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                16073195040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8770096500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               18077007000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5251294800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           410674128390                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           102790850250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             612041479260                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.088667                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   168453702129                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25769380000                       # Time in different power states
+system.physmem.avgGap                       121079.10                       # Average gap between requests
+system.physmem.pageHitRate                      32.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                16098316920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8783803875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               18090555600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5260230720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50310315120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           409970854125                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           102538812000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             611052888360                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.296379                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   168045428834                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25721020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    577496605871                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    576504578166                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16339027320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8915143875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18669222000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5361163200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           412008151545                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           101620654500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             613318269720                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.743144                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   166509885283                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25769380000                       # Time in different power states
+system.physmem_1.actEnergy                16359303240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8926207125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18686249400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5363152560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50310315120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           411485095035                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           101210530500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             612340852980                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.968472                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   165832482361                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25721020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    579440435717                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    578718185889                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286277860                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223409255                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14633591                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157407621                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150346120                       # Number of BTB hits
+system.cpu.branchPred.lookups               286281176                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223407845                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14631280                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158010784                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150352507                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.513876                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641206                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 65                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.153320                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16641956                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -431,128 +430,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1543450339                       # number of cpu cycles simulated
+system.cpu.numCycles                       1540554067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13927699                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067517377                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286277860                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166987326                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1514795150                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29291799                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          907                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656942032                       # Number of cache lines fetched
+system.cpu.fetch.icacheStallCycles           13926810                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067510841                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286281176                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          166994463                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1511903145                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29287205                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          944                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656946227                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   957                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1543369835                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.435149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229340                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples         1540474684                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.437849                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228901                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                460957271     29.87%     29.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465455811     30.16%     60.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101360614      6.57%     66.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515596139     33.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                458056876     29.73%     29.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465435106     30.21%     59.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101413024      6.58%     66.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515569678     33.47%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1543369835                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185479                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.339543                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74619350                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             545977788                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 850086533                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58040967                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14645197                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42200501                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   754                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037190940                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52475133                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14645197                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139685845                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               464851768                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13523                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837895691                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              86277811                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976364426                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26735694                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45105241                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 125505                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1481556                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25500508                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985835865                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128071192                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432849079                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               136                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1540474684                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.185830                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.342057                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74648924                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             543079640                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849978540                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58124682                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14642898                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42203677                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   755                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037193143                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52473156                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14642898                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139724503                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               462464867                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13004                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837848817                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              85780595                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976362381                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26752450                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45148759                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 125663                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1475660                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               24911172                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985832580                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128057886                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432844380                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               133                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                310936920                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                149                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            140                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111342876                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542549398                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199301403                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26926926                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29153523                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1947926711                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 208                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857446823                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13498178                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283894503                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    646939215                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             38                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1543369835                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.203501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.151095                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                310933635                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                157                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            149                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111445716                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542550479                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199301883                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26937332                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         29252722                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1947933921                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 216                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857470724                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13498979                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       283901721                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647143115                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1540474684                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.205778                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150877                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           590630846     38.27%     38.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           325771475     21.11%     59.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378267234     24.51%     83.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219666416     14.23%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            29027688      1.88%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6176      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           587582159     38.14%     38.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326005186     21.16%     59.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378227465     24.55%     83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219635075     14.26%     98.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29018612      1.88%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6187      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1543369835                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1540474684                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166059149     40.99%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1996      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191393147     47.24%     88.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47682914     11.77%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166090735     41.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   2011      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191466761     47.26%     88.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47541933     11.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138268714     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               801071      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138243565     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               801032      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -574,90 +573,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              28      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              29      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532058987     28.64%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186318001     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532113978     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186312098     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857446823                       # Type of FU issued
-system.cpu.iq.rate                           1.203438                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   405137206                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.218115                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5676898637                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2231834122                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805736851                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 228                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                232                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262583902                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     127                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17817639                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1857470724                       # Type of FU issued
+system.cpu.iq.rate                           1.205716                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405101440                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218093                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5674016313                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2231848584                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805694743                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 238                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                230                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262572030                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     134                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         17810782                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84243064                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66651                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13168                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24454358                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84244145                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66602                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13196                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24454838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4525889                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4805394                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4507141                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4884537                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14645197                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25323327                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1332663                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1947926995                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14642898                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25317454                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1284847                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1947934221                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542549398                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199301403                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                146                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 158839                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1172731                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13168                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7701738                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8706499                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16408237                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827783249                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516881888                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29663574                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             542550479                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199301883                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                154                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 159143                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1124751                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13196                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7700546                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8704736                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16405282                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827804607                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516933891                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29666117                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            76                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698636146                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229555717                       # Number of branches executed
-system.cpu.iew.exec_stores                  181754258                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.184219                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808767141                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805736919                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169322951                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689713401                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            84                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698685293                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229544445                       # Number of branches executed
+system.cpu.iew.exec_stores                  181751402                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.186459                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808724876                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805694813                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169261823                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689660637                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.169935                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692024                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.172107                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692010                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       258002520                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       258006259                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14632889                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1503882923                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.106491                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.024391                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14630576                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1500991330                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.108622                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.025694                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    923604765     61.41%     61.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250635322     16.67%     78.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110056363      7.32%     85.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55280526      3.68%     89.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29292132      1.95%     91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34092515      2.27%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24716046      1.64%     94.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18126603      1.21%     96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58078651      3.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    920697347     61.34%     61.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250635150     16.70%     78.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110066020      7.33%     85.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55280178      3.68%     89.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29318113      1.95%     91.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34079049      2.27%     93.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24716376      1.65%     94.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18134019      1.21%     96.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58065078      3.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1503882923                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1500991330                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -703,76 +702,76 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58078651                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3367838627                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883562090                       # The number of ROB writes
-system.cpu.timesIdled                             851                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           80504                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58065078                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3364964346                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883565961                       # The number of ROB writes
+system.cpu.timesIdled                             839                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           79383                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.999280                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.999280                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.000721                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.000721                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175739809                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261583749                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       50                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965641029                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551880821                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675853491                       # number of misc regfile reads
+system.cpu.cpi                               0.997404                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.997404                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.002602                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.002602                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175788919                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261560913                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965670330                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551865131                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675839076                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17005885                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964949                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638186886                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17006397                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.526284                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          78340000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964949                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements          17004565                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.965160                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638055083                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17005077                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.521446                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          77552500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.965160                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          423                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335687679                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335687679                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469400845                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469400845                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168785923                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168785923                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335687503                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335687503                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469335942                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469335942                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168719023                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168719023                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638186768                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638186768                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638186768                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638186768                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17353625                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17353625                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3800124                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3800124                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638054965                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638054965                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638054965                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638054965                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17419100                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17419100                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3867024                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3867024                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21153749                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21153749                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21153751                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21153751                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 417050356298                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149886013526                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       204500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       204500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 566936369824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 566936369824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 566936369824                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 566936369824                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486754470                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486754470                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     21286124                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21286124                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21286126                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21286126                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 415512136500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 149273741664                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       290000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       290000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 564785878164                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 564785878164                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 564785878164                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 564785878164                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486755042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486755042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -781,417 +780,434 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659340517                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659340517                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659340519                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659340519                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035652                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035652                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022019                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022019                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659341089                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659341089                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659341091                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659341091                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035786                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035786                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022406                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022406                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032083                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032083                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032083                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032083                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        51125                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        51125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26800.751480                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26800.748946                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20736521                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3309459                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            945396                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67047                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.934217                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    49.360285                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032284                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032284                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032284                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032284                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26533.054029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26533.051536                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20783046                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3318451                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            945637                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67068                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.977827                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    49.478902                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      4830628                       # number of writebacks
-system.cpu.dcache.writebacks::total           4830628                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3084713                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3084713                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1062640                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1062640                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      4838877                       # number of writebacks
+system.cpu.dcache.writebacks::total           4838877                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151642                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3151642                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129406                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1129406                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4147353                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4147353                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4147353                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4147353                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14268912                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14268912                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737484                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737484                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4281048                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4281048                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4281048                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4281048                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267458                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14267458                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737618                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737618                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17006396                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17006396                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17006397                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17006397                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        67750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        67750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 444043827535                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 444043895285                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029314                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029314                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data     17005076                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17005076                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17005077                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17005077                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 451904447017                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 451904515017                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029311                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029311                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025793                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025793                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025793                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025793                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025791                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025791                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               589                       # number of replacements
-system.cpu.icache.tags.tagsinuse           446.078018                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656940406                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1077                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          609972.521820                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               585                       # number of replacements
+system.cpu.icache.tags.tagsinuse           445.973645                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656944607                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1073                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          612250.332712                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   446.078018                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.871246                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.871246                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   445.973645                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.871042                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.871042                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313885139                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313885139                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656940406                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656940406                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656940406                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656940406                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656940406                       # number of overall hits
-system.cpu.icache.overall_hits::total       656940406                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1625                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1625                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1625                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1625                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1625                       # number of overall misses
-system.cpu.icache.overall_misses::total          1625                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    105016775                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    105016775                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    105016775                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    105016775                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    105016775                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    105016775                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656942031                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656942031                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656942031                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656942031                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656942031                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656942031                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses        1313893525                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313893525                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656944607                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656944607                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656944607                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656944607                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656944607                       # number of overall hits
+system.cpu.icache.overall_hits::total       656944607                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1619                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1619                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1619                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1619                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1619                       # number of overall misses
+system.cpu.icache.overall_misses::total          1619                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    105131986                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    105131986                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    105131986                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    105131986                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    105131986                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    105131986                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656946226                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656946226                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    656946226                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    656946226                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    656946226                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    656946226                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64625.707692                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64625.707692                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        17596                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          547                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               191                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               9                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    92.125654                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    60.777778                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64936.371834                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64936.371834                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17916                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          510                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    93.312500                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    63.750000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          548                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          548                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          548                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          548                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          548                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          548                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1077                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1077                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1077                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1077                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1077                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1077                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76192959                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     76192959                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76192959                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76192959                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76192959                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76192959                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          546                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          546                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          546                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          546                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          546                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          546                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1073                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1073                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1073                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1073                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1073                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1073                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76698989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     76698989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76698989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     76698989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76698989                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     76698989                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71480.884436                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71480.884436                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71480.884436                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     10938258                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11626730                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       430783                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     10956462                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11638997                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       427337                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            3                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4654278                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4710195                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16130.419578                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           15323813                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4726123                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.242364                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      29466216500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5234.041152                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.862974                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7585.301260                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3292.214193                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.319461                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001151                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.462970                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.200941                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984523                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          739                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15189                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          553                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          181                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2391                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1230                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9214                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1849                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.045105                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.927063                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        356873283                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       356873283                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           41                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data     11486555                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       11486596                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      4830628                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      4830628                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1752756                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1752756                       # number of ReadExReq hits
+system.cpu.l2cache.prefetcher.pfRemovedFull            2                       # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage      4654603                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements          4714185                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16129.978160                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           27368962                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4730113                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.786112                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      29467370500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  5231.697931                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.454317                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7577.410769                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3302.415144                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.319318                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001126                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.462488                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.201563                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.984496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          757                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1          554                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          202                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          498                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2399                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1267                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9187                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1820                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.046204                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.925964                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        551303538                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       551303538                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      4838877                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      4838877                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1752165                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1752165                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           41                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           41                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11480053                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total     11480053                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           41                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     13239311                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        13239352                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     13232218                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        13232259                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           41                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     13239311                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       13239352                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1036                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      2782314                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      2783350                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       984772                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       984772                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1036                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      3767086                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       3768122                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1036                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      3767086                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3768122                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     75378470                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 238954793079                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75378470                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 339110454452                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75378470                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 339110454452                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1077                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data     14268869                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     14269946                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      4830628                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      4830628                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737528                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2737528                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1077                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17006397                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17007474                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1077                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17006397                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17007474                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.961931                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.194992                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.195050                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359730                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.359730                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961931                       # miss rate for demand accesses
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 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
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-system.cpu.l2cache.avg_blocked_cycles::no_mshrs    26.500000                       # average number of cycles each access was blocked
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 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95271.320524                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67013.081395                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79908.486054                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79908.486054                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83950.810331                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83946.126087                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83950.810331                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81671.742519                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       14269946                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      14269946                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4830628                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1298291                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737528                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     38843422                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          38845576                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397569600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1397638528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1298291                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     23136394                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.056115                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.230143                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp      14268485                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      6478421                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     15219349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1327311                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737665                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737665                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1073                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14267412                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2727                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50993158                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          50995885                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1398013056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         1398081728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     6041496                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     40052798                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.150838                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.357891                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           21838103     94.39%     94.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1298291      5.61%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           34011302     84.92%     84.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            6041496     15.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       23136394                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    15749679999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1817030                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       40052798                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    21844528998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1609500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   26101043977                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          3.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             3736842                       # Transaction distribution
-system.membus.trans_dist::ReadResp            3736842                       # Transaction distribution
-system.membus.trans_dist::Writeback           1637857                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            981309                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           981309                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     11074159                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               11074159                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    406784512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               406784512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy   25507619991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp            3740347                       # Transaction distribution
+system.membus.trans_dist::Writeback           1639544                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3065371                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            981875                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           981875                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3740347                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14149359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               14149359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    407153024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               407153024                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           6356008                       # Request fanout histogram
+system.membus.snoop_fanout::samples           9427137                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 6356008    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 9427137    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             6356008                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         14483850639                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25655332661                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             9427137                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17268043532                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        25679820043                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 144026919..939603453 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.363663                       # Number of seconds simulated
-sim_ticks                                2363662967500                       # Number of ticks simulated
-final_tick                               2363662967500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.363367                       # Number of seconds simulated
+sim_ticks                                2363367211500                       # Number of ticks simulated
+final_tick                               2363367211500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 734295                       # Simulator instruction rate (inst/s)
-host_op_rate                                   791306                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1127938114                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305424                       # Number of bytes of host memory used
-host_seconds                                  2095.56                       # Real time elapsed on the host
+host_inst_rate                                1091670                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1176427                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1676685643                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312924                       # Number of bytes of host memory used
+host_seconds                                  1409.55                       # Real time elapsed on the host
 sim_insts                                  1538759602                       # Number of instructions simulated
 sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125322112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125361536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124870144                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124909568                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        39424                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           39424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65100672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65100672                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65352128                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65352128                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                616                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1958158                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1958774                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1017198                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1017198                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                16679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53020297                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53036976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           16679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              16679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          27542282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               27542282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          27542282                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               16679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53020297                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               80579258                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data            1951096                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1951712                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1021127                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1021127                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                16681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             52835693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52852374                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           16681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              16681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          27652126                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               27652126                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          27652126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               16681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            52835693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               80504500                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       4727325935                       # number of cpu cycles simulated
+system.cpu.numCycles                       4726734423                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1538759602                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     633153380                       # nu
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               4727325934.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               4726734422.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         213462427                       # Number of branches fetched
@@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032481                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9111140                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4083.733673                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4083.732137                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       25164659000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733673                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle       25164659500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4083.732137                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data      9115235                       # n
 system.cpu.dcache.demand_misses::total        9115235                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143400508500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57355969000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57355969000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200756477500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200756477500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200756477500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200756477500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143051795500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57408921000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57408921000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200460716500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200460716500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200460716500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200460716500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    454909135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
@@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.014526
 system.cpu.dcache.demand_miss_rate::total     0.014526                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.014526                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22024.278858                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22024.276442                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21991.831971                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21991.829559                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -302,8 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3697418                       # number of writebacks
-system.cpu.dcache.writebacks::total           3697418                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3681379                       # number of writebacks
+system.cpu.dcache.writebacks::total           3681379                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7226086                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
@@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9115235
 system.cpu.dcache.demand_mshr_misses::total      9115235                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  54522245500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  54522245500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 187083625000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187083678500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55519772000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  55519772000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191345481500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191345535500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
@@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 7                       # number of replacements
-system.cpu.icache.tags.tagsinuse           515.012767                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           515.003161                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564953                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          2420948.202194                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   515.012767                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.251471                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.251471                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   515.003161                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.251466                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.251466                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          631                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
@@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst          638                       # n
 system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
 system.cpu.icache.overall_misses::total           638                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34207000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34207000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34207000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34207000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34207000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34207000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34212000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34212000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34212000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34212000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34212000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34212000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1544565591                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1544565591                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1544565591                       # number of demand (read+write) accesses
@@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53615.987461                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53615.987461                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53623.824451                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53623.824451                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -411,117 +411,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          638
 system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33250000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     33250000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33250000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     33250000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33250000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     33250000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33574000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     33574000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33574000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     33574000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33574000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     33574000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1926075                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31008.535032                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8967572                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1955843                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.585016                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     150067843000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160482                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.876098                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498452                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.477849                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000729                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.467728                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.946305                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1919018                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31008.198929                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14386233                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1948786                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.382151                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     150067845000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.734669                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.473510                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.472061                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1082                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1084                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1732                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26841                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26839                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106351328                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106351328                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6048805                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6048827                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3697418                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3697418                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108273                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108273                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses        149644895                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149644895                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3681379                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3681379                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1107017                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1107017                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           22                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           22                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6057123                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6057123                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7157078                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7157100                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7164140                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7164162                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7157078                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7157100                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          616                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1177282                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1177898                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       780876                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       780876                       # number of ReadExReq misses
+system.cpu.l2cache.overall_hits::cpu.data      7164140                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7164162                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       782132                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       782132                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          616                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          616                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1168964                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1168964                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          616                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1958158                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1958774                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1951096                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1951712                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1958158                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1958774                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32381000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61822893500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  61855274500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40996230000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  40996230000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     32381000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102851504500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     32381000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102851504500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          638                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7226087                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7226725                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3697418                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3697418                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1951096                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1951712                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41062370000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  41062370000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     32383000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     32383000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  61386841500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  61386841500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32383000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 102481594500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32383000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 102481594500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      3681379                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3681379                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889149                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889149                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          638                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          638                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7226087                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7226087                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          638                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      9115236                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total      9115874                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      9115236                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      9115874                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965517                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.162921                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.162992                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413348                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413348                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.414013                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.414013                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.965517                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.965517                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161770                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161770                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965517                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214823                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214875                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.214048                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214100                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214823                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214875                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214048                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214100                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -530,105 +536,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1017198                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1017198                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          616                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177282                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1177898                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780876                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       780876                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1021127                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1021127                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          226                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          226                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782132                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       782132                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          616                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          616                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1168964                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1168964                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1958158                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1958774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1951096                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1951712                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1958158                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1958774                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24978000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  47681937000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  47706915000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31625653000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31625653000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24978000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  79307590000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  79332568000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24978000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  79307590000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  79332568000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162921                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.162992                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413348                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413348                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1951096                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1951712                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  33241050000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  33241050000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     26223000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     26223000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49697201500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49697201500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     26223000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82938251500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  82964474500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     26223000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82938251500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  82964474500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414013                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.414013                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965517                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161770                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161770                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214823                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214875                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214048                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214100                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214823                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214875                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214048                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214100                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       7226725                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3697418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4702506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6326508                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889149                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889149                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21927890                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21929166                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          638                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7226087                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1283                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27340461                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27341744                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820009856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820050688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12813292                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818983360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          819024192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919018                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20146039                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.095255                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.293567                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12813292    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18227021     90.47%     90.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1919018      9.53%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12813292                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10104064000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.4                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20146039                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12794889500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        957000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13672854000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1177898                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1177898                       # Transaction distribution
-system.membus.trans_dist::Writeback           1017198                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780876                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780876                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4934746                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4934746                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190462208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190462208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1169580                       # Transaction distribution
+system.membus.trans_dist::Writeback           1021127                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897054                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            782132                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           782132                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1169580                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5821605                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5821605                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190261696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190261696                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2975972                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3870264                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2975972    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3870264    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2975972                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7175472500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3870264                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7969342268                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9807518500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9772290268                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index b101e64c0..6d8265542 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.882580                       # Number of seconds simulated
-sim_ticks                                5882580398500                       # Number of ticks simulated
-final_tick                               5882580398500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.882285                       # Number of seconds simulated
+sim_ticks                                5882284743500                       # Number of ticks simulated
+final_tick                               5882284743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 739516                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1152234                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1446192754                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314252                       # Number of bytes of host memory used
-host_seconds                                  4067.63                       # Real time elapsed on the host
+host_inst_rate                                 724530                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1128884                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1416814365                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314268                       # Number of bytes of host memory used
+host_seconds                                  4151.77                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125326976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125370176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124876416                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124919616                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        43200                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           43200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65178944                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65178944                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65426432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65426432                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                675                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1958234                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1958909                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018421                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018421                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data            1951194                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1951869                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022288                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022288                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst                 7344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             21304762                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                21312106                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             21229237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                21236581                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst            7344                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total               7344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11079992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11079992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11079992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11122622                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11122622                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11122622                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst                7344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            21304762                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               32392098                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            21229237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               32359203                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11765160797                       # number of cpu cycles simulated
+system.cpu.numCycles                      11764569487                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  3008081022                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                    1677713084                       # nu
 system.cpu.num_load_insts                  1239184746                       # Number of load instructions
 system.cpu.num_store_insts                  438528338                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               11765160796.998001                       # Number of busy cycles
+system.cpu.num_busy_cycles               11764569486.998001                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
@@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 4686862596                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9108581                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4084.587033                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4084.586459                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs          1668600407                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       58853917000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4084.587033                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       58853917500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4084.586459                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997213                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997213                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
@@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data      9112677                       # n
 system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143328499000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57382147000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57382147000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200710646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200710646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200710646000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200710646000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 142985038000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57429949000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57429949000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200414987000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200414987000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200414987000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200414987000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total   1239184746                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                       # number of WriteReq accesses(hits+misses)
@@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22025.431824                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22025.431824                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21992.987022                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21992.987022                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3697956                       # number of writebacks
-system.cpu.dcache.writebacks::total           3697956                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3682721                       # number of writebacks
+system.cpu.dcache.writebacks::total           3682721                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
@@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9112677
 system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  54547406500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  54547406500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 187041630500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187041630500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55540122000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  55540122000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191302310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191302310000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
@@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                10                       # number of replacements
-system.cpu.icache.tags.tagsinuse           555.705054                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           555.701425                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          4013232207                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               675                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          5945529.195556                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   555.705054                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.271340                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.271340                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   555.701425                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.271339                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.271339                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
@@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst          675                       # n
 system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
 system.cpu.icache.overall_misses::total           675                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     37138500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     37138500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     37138500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     37138500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     37138500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     37138500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     37142500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     37142500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     37142500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     37142500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     37142500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     37142500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   4013232882                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   4013232882                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   4013232882                       # number of demand (read+write) accesses
@@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55020                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        55020                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        55020                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        55020                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        55020                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        55020                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55025.925926                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55025.925926                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -273,114 +273,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          675
 system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36126000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     36126000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36126000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     36126000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36126000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     36126000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36467500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     36467500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36467500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     36467500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36467500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     36467500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53520                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53520                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53520                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53520                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53520                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53520                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1926197                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31136.249311                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8965026                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1955980                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.583393                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     340768621000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.641016                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.469873                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000783                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.479548                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.950203                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1919162                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31136.006197                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14382006                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1948945                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.379380                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     340768623000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.605704                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.465892                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          997                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          743                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27921                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27920                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908905                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106336271                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106336271                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6045911                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6045911                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3697956                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3697956                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108532                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108532                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7154443                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7154443                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7154443                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7154443                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1176939                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1177614                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       781295                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       781295                       # number of ReadExReq misses
+system.cpu.l2cache.tags.tag_accesses        149614316                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149614316                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3682721                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3682721                       # number of Writeback hits
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+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6054089                       # number of ReadSharedReq hits
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+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1168761                       # number of ReadSharedReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1958234                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1958234                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1958909                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     35451000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61789308500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  61824759500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41017993500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41017993500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     35451000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102807302000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102842753000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     35451000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102807302000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102842753000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          675                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7222850                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7223525                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3697956                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3697956                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41077744500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     35453500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     35453500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  61359978500                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::total 102473176500                       # number of overall miss cycles
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          675                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      9112677                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total      9113352                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          675                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      9112677                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      9113352                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.162947                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163025                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413421                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413421                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.414024                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.414024                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161814                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161814                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214891                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214949                       # miss rate for demand accesses
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+system.cpu.l2cache.demand_miss_rate::total     0.214177                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214891                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214949                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52520                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52520                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52520                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214119                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214177                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -389,107 +394,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018421                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018421                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1176939                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1177614                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781295                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       781295                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1022288                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022288                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          218                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          218                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782433                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       782433                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          675                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          675                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1168761                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1168761                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1958234                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1958909                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1951194                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1951869                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1958234                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1958909                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     27350500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  47666040500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  47693391000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31642453500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31642453500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     27350500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  79308494000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  79335844500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     27350500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  79308494000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  79335844500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162947                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163025                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413421                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413421                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1951194                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1951869                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  33253414500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  33253414500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     28703500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     28703500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49672368500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49672368500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28703500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82925783000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  82954486500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28703500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82925783000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  82954486500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414024                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.414024                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161814                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161814                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214891                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214949                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214119                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214177                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214891                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214949                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214119                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214177                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7223525                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       7223525                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3697956                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4705009                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6322744                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1350                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21923310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21924660                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          675                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222850                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1360                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27333935                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27335295                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819880512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          819923712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12811308                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818905472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          818948672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919162                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20141105                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.095286                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.293609                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12811308    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18221943     90.47%     90.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1919162      9.53%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12811308                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10103610000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       20141105                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12793692500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1012500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13669015500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1177614                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1177614                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018421                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            781295                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           781295                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4936239                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4936239                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4936239                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190549120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    190549120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190549120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1169436                       # Transaction distribution
+system.membus.trans_dist::Writeback           1022288                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           896090                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            782433                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           782433                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1169436                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5822116                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5822116                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5822116                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190346048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    190346048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190346048                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2977330                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3870262                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2977330    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3870262    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2977330                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7158077000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3870262                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7959418124                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9794545500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9759348624                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 874972c77..f4338fb5a 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.052048                       # Number of seconds simulated
-sim_ticks                                 52048460500                       # Number of ticks simulated
-final_tick                                52048460500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.052057                       # Number of seconds simulated
+sim_ticks                                 52057006500                       # Number of ticks simulated
+final_tick                                52057006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 350030                       # Simulator instruction rate (inst/s)
-host_op_rate                                   350030                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              198236020                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300292                       # Number of bytes of host memory used
-host_seconds                                   262.56                       # Real time elapsed on the host
+host_inst_rate                                 338250                       # Simulator instruction rate (inst/s)
+host_op_rate                                   338250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              191596351                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300296                       # Number of bytes of host memory used
+host_seconds                                   271.70                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            202688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            202816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340352                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202688                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3167                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               340480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202816                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2151                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5318                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3894217                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2644920                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6539137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3894217                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3894217                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3894217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2644920                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6539137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5318                       # Number of read requests accepted
+system.physmem.num_reads::total                  5320                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3896037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2644486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6540522                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3896037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3896037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3896037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2644486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6540522                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5320                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5318                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5320                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   340352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   340480                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    340352                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    340480                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -49,11 +49,11 @@ system.physmem.perBankRdBursts::4                 224                       # Pe
 system.physmem.perBankRdBursts::5                 238                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 289                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 251                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                255                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                261                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                409                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                410                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                344                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                500                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                448                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     52048372000                       # Total gap between requests
+system.physmem.totGap                     52056919000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5318                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5320                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4920                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4923                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       378                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          976                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      347.672131                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.149483                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     325.651264                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            303     31.05%     31.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          210     21.52%     52.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          100     10.25%     62.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           92      9.43%     72.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      7.27%     79.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           39      4.00%     83.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           30      3.07%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           19      1.95%     88.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          112     11.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            976                       # Bytes accessed per row activation
-system.physmem.totQLat                       32254250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 131966750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26590000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6065.11                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          973                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.809866                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.712248                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.458818                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            301     30.94%     30.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          209     21.48%     52.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           98     10.07%     62.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           92      9.46%     71.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           72      7.40%     79.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           45      4.62%     83.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           24      2.47%     86.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           19      1.95%     88.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          113     11.61%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            973                       # Bytes accessed per row activation
+system.physmem.totQLat                       31528250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 131278250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26600000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5926.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24815.11                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24676.36                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.54                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.54                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4336                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4340                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.53                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.58                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9787207.97                       # Average gap between requests
-system.physmem.pageHitRate                      81.53                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3515400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1918125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19851000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9785135.15                       # Average gap between requests
+system.physmem.pageHitRate                      81.58                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3492720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1905750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19843200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3399215040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1773582930                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29670358500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              34868440995                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.985765                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    49355972750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1737840000                       # Time in different power states
+system.physmem_0.refreshEnergy             3399723600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1761174315                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29685915000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34872054585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.954967                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49382007750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1738100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       949756000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       931384250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                    3825360                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                    2087250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                  21231600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3399215040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1774901340                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            29669193750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              34870438740                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.024328                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    49353927250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1737840000                       # Time in different power states
+system.physmem_1.refreshEnergy             3399723600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1805818995                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29646744750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34879431555                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.096868                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49317281000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1738100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       951967750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       996955000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                11467285                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8228909                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            787075                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6498554                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5367359                       # Number of BTB hits
+system.cpu.branchPred.lookups                11466165                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8229222                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            788767                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6698071                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5372970                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.593128                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1175694                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             80.216677                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1174312                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20428735                       # DTB read hits
-system.cpu.dtb.read_misses                      47112                       # DTB read misses
+system.cpu.dtb.read_hits                     20431374                       # DTB read hits
+system.cpu.dtb.read_misses                      46957                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20475847                       # DTB read accesses
-system.cpu.dtb.write_hits                     6580361                       # DTB write hits
-system.cpu.dtb.write_misses                       271                       # DTB write misses
+system.cpu.dtb.read_accesses                 20478331                       # DTB read accesses
+system.cpu.dtb.write_hits                     6580300                       # DTB write hits
+system.cpu.dtb.write_misses                       270                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580632                       # DTB write accesses
-system.cpu.dtb.data_hits                     27009096                       # DTB hits
-system.cpu.dtb.data_misses                      47383                       # DTB misses
+system.cpu.dtb.write_accesses                 6580570                       # DTB write accesses
+system.cpu.dtb.data_hits                     27011674                       # DTB hits
+system.cpu.dtb.data_misses                      47227                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27056479                       # DTB accesses
-system.cpu.itb.fetch_hits                    23055300                       # ITB hits
-system.cpu.itb.fetch_misses                        88                       # ITB misses
+system.cpu.dtb.data_accesses                 27058901                       # DTB accesses
+system.cpu.itb.fetch_hits                    23067346                       # ITB hits
+system.cpu.itb.fetch_misses                        89                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                23055388                       # ITB accesses
+system.cpu.itb.fetch_accesses                23067435                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +293,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        104096921                       # number of cpu cycles simulated
+system.cpu.numCycles                        104114013                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2232007                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2234090                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.132681                       # CPI: cycles per instruction
-system.cpu.ipc                               0.882861                       # IPC: instructions per cycle
-system.cpu.tickCycles                       102361178                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         1735743                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.132867                       # CPI: cycles per instruction
+system.cpu.ipc                               0.882716                       # IPC: instructions per cycle
+system.cpu.tickCycles                       102384742                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1729271                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.464460                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26584631                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1448.483845                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26587292                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11921.359193                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11922.552466                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1448.464460                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353629                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353629                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1448.483845                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353634                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353634                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
@@ -320,56 +320,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          226
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53178348                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53178348                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20086436                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20086436                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6498195                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6498195                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26584631                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26584631                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26584631                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26584631                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses          53183674                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53183674                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20089099                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20089099                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6498193                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6498193                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26587292                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26587292                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26587292                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26587292                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          520                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           520                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         2908                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2908                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3428                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3428                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3428                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3428                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     41644750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     41644750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    214147250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    214147250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    255792000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    255792000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    255792000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    255792000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20086956                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20086956                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         2910                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2910                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3430                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3430                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40189000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40189000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    213917000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    213917000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    254106000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    254106000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    254106000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    254106000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20089619                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20089619                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26588059                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26588059                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26588059                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26588059                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     26590722                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26590722                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26590722                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26590722                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000447                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000447                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000448                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000448                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80086.057692                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 80086.057692                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73640.732462                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73640.732462                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74618.436406                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74618.436406                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74618.436406                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74618.436406                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74083.381924                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74083.381924                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks          107                       # nu
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           35                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           35                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1163                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         1163                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1198                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1198                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1198                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1198                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1165                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         1165                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1200                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1200                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1200                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1200                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1745                       # number of WriteReq MSHR misses
@@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     38003250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     38003250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    129542250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    129542250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    167545500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    167545500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    167545500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    167545500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36729500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36729500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    130660500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    130660500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    167390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    167390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    167390000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    167390000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78357.216495                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78357.216495                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74236.246418                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74236.246418                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75132.511211                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75132.511211                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75132.511211                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75132.511211                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             13853                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.586076                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            23039482                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15817                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1456.627806                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13848                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1641.495432                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            23051532                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15813                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1457.758300                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.586076                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801067                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801067                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1641.495432                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          669                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          148                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          948                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          46126417                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         46126417                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     23039482                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        23039482                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      23039482                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         23039482                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     23039482                       # number of overall hits
-system.cpu.icache.overall_hits::total        23039482                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        15818                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15818                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        15818                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15818                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        15818                       # number of overall misses
-system.cpu.icache.overall_misses::total         15818                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    408417500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    408417500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    408417500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    408417500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    408417500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    408417500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     23055300                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23055300                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     23055300                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23055300                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     23055300                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23055300                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          668                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          950                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          46150505                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         46150505                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     23051532                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        23051532                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      23051532                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         23051532                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     23051532                       # number of overall hits
+system.cpu.icache.overall_hits::total        23051532                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15814                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15814                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15814                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15814                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15814                       # number of overall misses
+system.cpu.icache.overall_misses::total         15814                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    406574500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    406574500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    406574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    406574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    406574500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    406574500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     23067346                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     23067346                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     23067346                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     23067346                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     23067346                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     23067346                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000686                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000686                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000686                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000686                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000686                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000686                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25819.793906                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25819.793906                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25819.793906                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25819.793906                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25819.793906                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25819.793906                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25709.782471                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25709.782471                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25709.782471                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25709.782471                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25709.782471                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25709.782471                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,123 +483,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15818                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15818                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15818                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15818                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15818                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15818                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    383318000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    383318000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    383318000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    383318000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    383318000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    383318000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15814                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15814                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15814                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15814                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    390761500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    390761500                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24233.025667                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24233.025667                       # average ReadReq mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24709.845706                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 24709.845706                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse         2479.864899                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              12717                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3665                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.469850                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.782834                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.110753                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   360.971312                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          768                       # Occupied blocks per task id
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-system.cpu.l2cache.ReadReq_hits::cpu.inst        12650                       # number of ReadReq hits
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 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_avg_miss_latency::total 75057.446408                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76466.759647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75057.446408                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73928.526349                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73928.526349                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82035.879630                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82035.879630                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 74715.977444                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73928.526349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75876.104138                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74715.977444                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -608,102 +614,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    141699500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    344289000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    202589500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    141699500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    344289000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200228                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200405                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.890722                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.890722                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.294675                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200228                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.294851                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.294675                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61589.043259                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73020.254630                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62961.169769                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61715.968586                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61715.968586                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61589.043259                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63986.285449                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62558.668672                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61589.043259                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63986.285449                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62558.668672                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.294851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          16302                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         16302                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16298                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        13898                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31634                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4567                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             36201                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        15813                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          485                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45474                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4617                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             50091                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012032                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1161856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1161600                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        18154                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        32048                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              18154    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              32048    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          18154                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        9184000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          32048                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       16131000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24412500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      23719500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3745500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3345000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3599                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3599                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3601                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340352                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  340352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3601                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  340480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5318                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5320                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5318    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5320    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5318                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6399500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5320                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6410500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28155000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28166750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index f5ac38df0..2afb0af07 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022229                       # Number of seconds simulated
-sim_ticks                                 22228749500                       # Number of ticks simulated
-final_tick                                22228749500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022173                       # Number of seconds simulated
+sim_ticks                                 22172615500                       # Number of ticks simulated
+final_tick                                22172615500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192800                       # Simulator instruction rate (inst/s)
-host_op_rate                                   192800                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50911418                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230228                       # Number of bytes of host memory used
-host_seconds                                   436.62                       # Real time elapsed on the host
+host_inst_rate                                 207826                       # Simulator instruction rate (inst/s)
+host_op_rate                                   207826                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54740698                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301824                       # Number of bytes of host memory used
+host_seconds                                   405.05                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            196032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138560                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334592                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       196032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          196032                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3063                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5228                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8818850                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6233369                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15052219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8818850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8818850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8818850                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6233369                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15052219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5228                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            196224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               334656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       196224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          196224                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3066                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5229                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8849836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6243377                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15093213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8849836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8849836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8849836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6243377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15093213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5229                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5228                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5229                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334592                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334656                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334592                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334656                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -44,18 +44,18 @@ system.physmem.neitherReadNorWriteReqs              0                       # Nu
 system.physmem.perBankRdBursts::0                 472                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 525                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 219                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 217                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 224                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 217                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 285                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 238                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 279                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                248                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                252                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                253                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                398                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                491                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                493                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22228653000                       # Total gap between requests
+system.physmem.totGap                     22172520500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5228                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5229                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1223                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       210                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1190                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       227                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      383.630485                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     225.895164                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     361.482180                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            274     31.64%     31.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          174     20.09%     51.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           79      9.12%     60.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           66      7.62%     68.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           29      3.35%     71.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           37      4.27%     76.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           36      4.16%     80.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           45      5.20%     85.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          126     14.55%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            866                       # Bytes accessed per row activation
-system.physmem.totQLat                       39875750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 137900750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26140000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7627.34                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      385.112399                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     228.773233                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     362.004147                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            257     29.78%     29.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          196     22.71%     52.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           76      8.81%     61.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           57      6.60%     67.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           37      4.29%     72.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           34      3.94%     76.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           29      3.36%     79.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           50      5.79%     85.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          127     14.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            863                       # Bytes accessed per row activation
+system.physmem.totQLat                       43111750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 141155500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26145000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8244.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26377.34                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.05                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26994.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.09                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.05                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.09                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4353                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4356                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.26                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.30                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4251846.40                       # Average gap between requests
-system.physmem.pageHitRate                      83.26                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3137400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1711875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19476600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4240298.43                       # Average gap between requests
+system.physmem.pageHitRate                      83.30                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3160080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1724250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19492200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1451430240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              894518100                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12548665500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14918939715                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.352430                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20873521000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       742040000                       # Time in different power states
+system.physmem_0.refreshEnergy             1447870320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              926205255                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12488167500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14886619605                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.545103                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20772765250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       740220000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       606815000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       654868750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3349080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1827375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20794800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3311280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1806750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20810400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1451430240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              919030095                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12527163750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14923595340                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.561933                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20841181500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       742040000                       # Time in different power states
+system.physmem_1.refreshEnergy             1447870320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              909735390                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12502614750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14886148890                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.523868                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20796420250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       740220000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       642887000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       631087250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16323961                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11865379                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            978310                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9045215                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7641567                       # Number of BTB hits
+system.cpu.branchPred.lookups                16296711                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11841199                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            977322                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9230824                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7630427                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             84.481872                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1608650                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                453                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.662469                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1605836                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                456                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24152698                       # DTB read hits
-system.cpu.dtb.read_misses                     236585                       # DTB read misses
+system.cpu.dtb.read_hits                     24148862                       # DTB read hits
+system.cpu.dtb.read_misses                     238971                       # DTB read misses
 system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24389283                       # DTB read accesses
-system.cpu.dtb.write_hits                     7160578                       # DTB write hits
-system.cpu.dtb.write_misses                      1214                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7161792                       # DTB write accesses
-system.cpu.dtb.data_hits                     31313276                       # DTB hits
-system.cpu.dtb.data_misses                     237799                       # DTB misses
-system.cpu.dtb.data_acv                             2                       # DTB access violations
-system.cpu.dtb.data_accesses                 31551075                       # DTB accesses
-system.cpu.itb.fetch_hits                    16159751                       # ITB hits
-system.cpu.itb.fetch_misses                        85                       # ITB misses
+system.cpu.dtb.read_accesses                 24387833                       # DTB read accesses
+system.cpu.dtb.write_hits                     7164238                       # DTB write hits
+system.cpu.dtb.write_misses                      1251                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7165489                       # DTB write accesses
+system.cpu.dtb.data_hits                     31313100                       # DTB hits
+system.cpu.dtb.data_misses                     240222                       # DTB misses
+system.cpu.dtb.data_acv                             3                       # DTB access violations
+system.cpu.dtb.data_accesses                 31553322                       # DTB accesses
+system.cpu.itb.fetch_hits                    16134293                       # ITB hits
+system.cpu.itb.fetch_misses                        87                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                16159836                       # ITB accesses
+system.cpu.itb.fetch_accesses                16134380                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,239 +293,239 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         44457500                       # number of cpu cycles simulated
+system.cpu.numCycles                         44345232                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16896881                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      139613933                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16323961                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9250217                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      26293708                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2036816                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           16871286                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      139358892                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16296711                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9236263                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      26208155                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2034698                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                          2                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  203                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2338                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  16159751                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                382144                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           44211553                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.157861                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.431266                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles                  152                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2379                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles            9                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  16134293                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                382507                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           44099332                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.160113                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.432013                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19722112     44.61%     44.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2663068      6.02%     50.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1345508      3.04%     53.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1957580      4.43%     58.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3052640      6.90%     65.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1306785      2.96%     67.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1385791      3.13%     71.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   896674      2.03%     73.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11881395     26.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19660436     44.58%     44.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2660444      6.03%     50.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1334517      3.03%     53.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1958294      4.44%     58.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3041312      6.90%     64.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1304304      2.96%     67.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1378179      3.13%     71.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   896078      2.03%     73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11865768     26.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44211553                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367181                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.140391                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13076592                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8324763                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19681975                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2121490                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1006733                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2681054                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12065                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              133596496                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 48387                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1006733                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 14226924                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4752424                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9184                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20532599                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3683689                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              130038627                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 69797                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2001155                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1372929                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  55394                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            95511389                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             168978901                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        161414982                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7563918                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44099332                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367496                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.142590                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 13096074                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8205573                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19698619                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2093424                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1005642                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2679978                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12191                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              133453867                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 48806                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1005642                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 14231650                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4726220                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9532                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20537255                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3589033                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              129931841                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 72505                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1962504                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1321371                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  55153                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            95440121                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             168856219                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        161261081                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7595137                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27084028                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                772                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            782                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8280120                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             27136625                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8757663                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3565364                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1670156                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  112744524                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2237                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 100145020                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            122649                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        28567051                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21979359                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1848                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44211553                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.265132                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.094303                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 27012760                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                775                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            786                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8114171                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             27101259                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8744711                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3477099                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1649521                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  112647261                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1499                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 100144647                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            120164                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        28469050                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21866284                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1110                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44099332                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.270888                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.097444                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11585483     26.20%     26.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7800031     17.64%     43.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7580714     17.15%     60.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5746471     13.00%     73.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4482670     10.14%     84.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2978699      6.74%     90.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2013201      4.55%     95.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1153505      2.61%     98.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              870779      1.97%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11543505     26.18%     26.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7764590     17.61%     43.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7534716     17.09%     60.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5714671     12.96%     73.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4493321     10.19%     84.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2994712      6.79%     90.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2021459      4.58%     95.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1167850      2.65%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              864508      1.96%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44211553                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44099332                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  481856     20.25%     20.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     20.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   350      0.01%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34531      1.45%     21.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                11644      0.49%     22.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1006485     42.29%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 687304     28.88%     93.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                157568      6.62%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  476525     19.98%     19.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   437      0.02%     20.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34852      1.46%     21.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                11487      0.48%     21.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1008602     42.30%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 692685     29.05%     93.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159938      6.71%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60921013     60.83%     60.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               491088      0.49%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2841000      2.84%     64.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115643      0.12%     64.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2440640      2.44%     66.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             314095      0.31%     67.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              766051      0.76%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24991126     24.95%     92.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7264038      7.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60907964     60.82%     60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               491070      0.49%     61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2843610      2.84%     64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115460      0.12%     64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2441189      2.44%     66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             314170      0.31%     67.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              765827      0.76%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24997693     24.96%     92.74% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7267338      7.26%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              100145020                       # Type of FU issued
-system.cpu.iq.rate                           2.252601                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2379738                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023763                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          231363005                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         131706335                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     90039702                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15640975                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9649243                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7175345                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               94170320                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8354431                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1902679                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              100144647                       # Type of FU issued
+system.cpu.iq.rate                           2.258296                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2384526                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023811                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          231229628                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         131456710                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     90023404                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15663688                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9702849                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7180664                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               94162135                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8367031                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1912696                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7140427                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11100                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        42139                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2256560                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7105061                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11423                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        42083                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2243608                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42760                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1687                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42789                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1006733                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3731793                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                447885                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           123749930                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            277756                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              27136625                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8757663                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2237                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  43684                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                396903                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          42139                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         560048                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       524506                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1084554                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98770041                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24389817                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1374979                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1005642                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3713444                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                450339                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           123646937                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            273080                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              27101259                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8744711                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1499                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  41770                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                401874                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          42083                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         559712                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       524057                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1083769                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98766968                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24388350                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1377679                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      11003169                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31551638                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12536484                       # Number of branches executed
-system.cpu.iew.exec_stores                    7161821                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.221673                       # Inst execution rate
-system.cpu.iew.wb_sent                       97959187                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      97215047                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  67118954                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95176065                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10998177                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31553871                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12528994                       # Number of branches executed
+system.cpu.iew.exec_stores                    7165521                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.227229                       # Inst execution rate
+system.cpu.iew.wb_sent                       97952857                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      97204068                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  67107593                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95129025                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.186696                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705208                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.191985                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705438                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        31848480                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        31745312                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            966635                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39567002                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.322720                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.905630                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            965615                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39467684                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.328565                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.908680                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     15032687     37.99%     37.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8622118     21.79%     59.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3917590      9.90%     69.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1951695      4.93%     74.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1384336      3.50%     78.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1033619      2.61%     80.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       694183      1.75%     82.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       726057      1.84%     84.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6204717     15.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14970260     37.93%     37.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8589907     21.76%     59.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3909988      9.91%     69.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1952996      4.95%     74.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1374473      3.48%     78.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1034336      2.62%     80.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       694993      1.76%     82.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       731194      1.85%     84.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6209537     15.73%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39567002                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39467684                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,344 +571,350 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6204717                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    157112780                       # The number of ROB reads
-system.cpu.rob.rob_writes                   252206838                       # The number of ROB writes
-system.cpu.timesIdled                            4633                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          245947                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6209537                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    156905474                       # The number of ROB reads
+system.cpu.rob.rob_writes                   251988235                       # The number of ROB writes
+system.cpu.timesIdled                            4640                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          245900                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.528126                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.528126                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.893487                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.893487                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                133407543                       # number of integer regfile reads
-system.cpu.int_regfile_writes                73150911                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6256040                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6161921                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  718993                       # number of misc regfile reads
+system.cpu.cpi                               0.526792                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.526792                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.898281                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.898281                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                133413106                       # number of integer regfile reads
+system.cpu.int_regfile_writes                73139309                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6258544                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6168597                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  718994                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements               159                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1458.668074                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28697534                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2246                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12777.174533                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1454.905467                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28683797                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12782.440731                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1458.668074                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.356120                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.356120                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2087                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1454.905467                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355202                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355202                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2085                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509521                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57416312                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57416312                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22204643                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22204643                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492628                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492628                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          263                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          263                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28697271                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28697271                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28697271                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28697271                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1023                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1023                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8475                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8475                       # number of WriteReq misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1386                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509033                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57388820                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57388820                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22190893                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22190893                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492625                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492625                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          279                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          279                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28683518                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28683518                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28683518                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28683518                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1012                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1012                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8478                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8478                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9498                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9498                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9498                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9498                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     69711000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     69711000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    550954965                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    550954965                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9490                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9490                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9490                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9490                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     67994000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     67994000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    547632747                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    547632747                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    620665965                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    620665965                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    620665965                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    620665965                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22205666                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22205666                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    615626747                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    615626747                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    615626747                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    615626747                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22191905                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22191905                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          264                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          264                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28706769                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28706769                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28706769                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28706769                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          280                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          280                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28693008                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28693008                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28693008                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28693008                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001304                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001304                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003788                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003788                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003571                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003571                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000331                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000331                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000331                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65347.016740                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65347.016740                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33287                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64871.100843                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64871.100843                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        33428                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               426                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               398                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.138498                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.989950                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          109                       # number of writebacks
 system.cpu.dcache.writebacks::total               109                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          512                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          512                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6741                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6741                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7253                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7253                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7253                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7253                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          511                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          511                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          503                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          503                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6744                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6744                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7247                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7247                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7247                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7247                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          509                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          509                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1734                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1734                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2245                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2245                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2245                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2245                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     38736500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     38736500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    136484495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    136484495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        83500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        83500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    175220995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    175220995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    175220995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    175220995                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39245500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     39245500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    137397495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    137397495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176642995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    176642995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176642995                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    176642995                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003788                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003788                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003571                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003571                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75805.283757                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75805.283757                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        83500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        83500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79237.309689                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79237.309689                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78753.007133                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78753.007133                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78753.007133                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78753.007133                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              9845                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1600.510636                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            16144798                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11783                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1370.177204                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9772                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1599.606485                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            16119452                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11709                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1376.671962                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1600.510636                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781499                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781499                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1599.606485                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          760                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          936                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.946289                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          32331281                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         32331281                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     16144798                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        16144798                       # number of ReadReq hits
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-system.cpu.icache.overall_hits::total        16144798                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14951                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14951                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14951                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14951                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14951                       # number of overall misses
-system.cpu.icache.overall_misses::total         14951                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    446766000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    446766000                       # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total    446766000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    446766000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    446766000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     16159749                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     16159749                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     16159749                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::cpu.inst     16159749                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     16159749                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000925                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000925                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000925                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000925                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000925                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000925                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29882.014581                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29882.014581                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29882.014581                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29882.014581                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29882.014581                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          502                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          934                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          32280293                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         32280293                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     16119452                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        16119452                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14840                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14840                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total         14840                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    447595000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    447595000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    447595000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    447595000                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total    447595000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     16134292                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     16134292                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     16134292                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     16134292                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     16134292                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000920                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000920                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000920                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000920                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000920                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000920                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30161.388140                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30161.388140                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30161.388140                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30161.388140                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30161.388140                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          223                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    55.777778                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    55.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3168                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3168                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3168                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3168                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3168                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3168                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11783                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11783                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11783                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11783                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11783                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11783                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    332403750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    332403750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    332403750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    332403750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    332403750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    332403750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000729                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000729                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000729                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000729                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000729                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000729                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3131                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3131                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3131                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3131                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3131                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3131                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11709                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11709                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000726                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000726                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28968.998207                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28968.998207                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28968.998207                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2407.331968                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8790                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3587                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.450516                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2400.828541                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              18535                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             5.165831                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.698797                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2011.289043                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   378.344128                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2008.692656                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061380                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          911                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2430                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109467                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.Writeback_hits::writebacks          109                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          109                       # number of Writeback hits
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 system.cpu.l2cache.Writeback_accesses::writebacks          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1734                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1734                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.259951                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985006                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985006                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.011547                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76720.351951                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74780.362390                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.011547                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76720.351951                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.261850                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.892157                       # miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75302.674494                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75302.674494                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83448.351648                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83448.351648                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75302.674494                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79680.998613                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77113.788487                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75302.674494                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79680.998613                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77113.788487                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -917,102 +923,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3063                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1708                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1708                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.259951                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5229                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    117301000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    117301000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200218000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200218000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33419000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33419000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200218000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    150720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    350938000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200218000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    150720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    350938000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985006                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985006                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.259951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963936                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.372657                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.259951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963936                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.372657                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.261850                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.892157                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.892157                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.374758                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.374758                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          12295                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         12295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         12219                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          109                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         9822                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1734                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1734                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23566                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4601                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             28167                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       754112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             904832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11709                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          510                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33190                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4647                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             37837                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       749376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             899968                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        14138                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        23884                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              14138    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              23884    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          14138                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7178000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18279750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          23884                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       12051000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      17563500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3635750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3520                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3520                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3521                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1708                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1708                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10456                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10456                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3521                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10458                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10458                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334656                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5228                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5229                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5228    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5229    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5228                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6467500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5229                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6267000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27502000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27480000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index d21841628..f9aa76ee3 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.131586                       # Number of seconds simulated
-sim_ticks                                131586268500                       # Number of ticks simulated
-final_tick                               131586268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.131585                       # Number of seconds simulated
+sim_ticks                                131584694500                       # Number of ticks simulated
+final_tick                               131584694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 246297                       # Simulator instruction rate (inst/s)
-host_op_rate                                   259636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              188078312                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317920                       # Number of bytes of host memory used
-host_seconds                                   699.64                       # Real time elapsed on the host
+host_inst_rate                                 242795                       # Simulator instruction rate (inst/s)
+host_op_rate                                   255945                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              185402255                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318276                       # Number of bytes of host memory used
+host_seconds                                   709.73                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          138368                       # Nu
 system.physmem.num_reads::cpu.inst               2162                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3870                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1051538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               830725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1882263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1051538                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1051538                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1051538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              830725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1882263                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1051551                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               830735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1882286                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1051551                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1051551                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1051551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              830735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1882286                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          3870                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        3870                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    131586174000                       # Total gap between requests
+system.physmem.totGap                    131584601000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      272.834628                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.187503                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     278.027106                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            257     28.52%     28.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          352     39.07%     67.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           83      9.21%     76.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           53      5.88%     82.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           41      4.55%     87.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           20      2.22%     89.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      1.89%     91.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           20      2.22%     93.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           58      6.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            901                       # Bytes accessed per row activation
-system.physmem.totQLat                       26462250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  99024750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          912                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      269.614035                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.051598                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     274.679496                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            270     29.61%     29.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          347     38.05%     67.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           87      9.54%     77.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           54      5.92%     83.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           40      4.39%     87.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           20      2.19%     89.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           18      1.97%     91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           19      2.08%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           57      6.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            912                       # Bytes accessed per row activation
+system.physmem.totQLat                       27229750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  99792250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6837.79                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7036.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25587.79                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25786.11                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
@@ -216,47 +216,47 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2963                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2952                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.56                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.28                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34001595.35                       # Average gap between requests
-system.physmem.pageHitRate                      76.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3107160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1695375                       # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap                     34001188.89                       # Average gap between requests
+system.physmem.pageHitRate                      76.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             8594155440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3588895845                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            75799905000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              88003936020                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.824061                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   126101706500                       # Time in different power states
+system.physmem_0.actBackEnergy             3579629355                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75808025250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              88002824835                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.815686                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   126113612750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      4393740000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1088502500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1075043250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3689280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2013000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13767000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3749760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2046000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13774800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             8594155440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3567061710                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75819057750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              87999744180                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.792204                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   126130418250                       # Time in different power states
+system.physmem_1.actBackEnergy             3571830900                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75814874250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              88000431150                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.797424                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   126123074750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      4393740000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1056288250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1063297750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                49889699                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39633555                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                49889701                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39633557                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           5745356                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24337780                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             24337782                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                23279998                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.653745                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             95.653737                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1903300                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                140                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        263172537                       # number of cpu cycles simulated
+system.cpu.numCycles                        263169389                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317810                       # Number of instructions committed
 system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11983755                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11983759                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.527251                       # CPI: cycles per instruction
-system.cpu.ipc                               0.654771                       # IPC: instructions per cycle
-system.cpu.tickCycles                       256740434                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         6432103                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.527233                       # CPI: cycles per instruction
+system.cpu.ipc                               0.654779                       # IPC: instructions per cycle
+system.cpu.tickCycles                       256740818                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6428571                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.700648                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40793912                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1377.711326                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40793911                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22538.072928                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22538.072376                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1377.700648                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.336353                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336353                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1377.711326                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.336355                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336355                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
@@ -408,36 +408,36 @@ system.cpu.dcache.tags.tag_accesses          81594514                       # Nu
 system.cpu.dcache.tags.data_accesses         81594514                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     28385993                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        28385993                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12362641                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362641                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12362640                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362640                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          464                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           464                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40748634                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40748634                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40749098                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40749098                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      40748633                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40748633                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40749097                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40749097                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          793                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           793                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1646                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1646                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1647                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1647                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2439                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2439                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2440                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2440                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     57815734                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     57815734                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    126489000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    126489000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184304734                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184304734                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184304734                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184304734                       # number of overall miss cycles
+system.cpu.dcache.demand_misses::cpu.data         2440                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2440                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2441                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2441                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     57382000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     57382000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    126740000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    126740000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    184122000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    184122000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    184122000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    184122000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     28386786                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     28386786                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
@@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000060
 system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75565.696597                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75534.727049                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75459.836066                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75428.922573                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks           16                       # nu
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          548                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          548                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          630                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          549                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          549                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          631                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          631                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          631                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          631                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
@@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1809
 system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51168764                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51168764                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     84319000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     84319000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        69500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        69500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    135487764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    135487764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    135557264                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    135557264                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51034000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     51034000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85245500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85245500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        70000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        70000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136279500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    136279500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136349500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    136349500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        69500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        69500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        70000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        70000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2889                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1425.913177                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71538503                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1425.919952                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            71538505                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4687                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15263.175379                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15263.175805                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1425.913177                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.696247                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.696247                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1425.919952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.696250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.696250                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1798                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
@@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          493
 system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.877930                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         143091069                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        143091069                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71538503                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71538503                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71538503                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71538503                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71538503                       # number of overall hits
-system.cpu.icache.overall_hits::total        71538503                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         143091073                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        143091073                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     71538505                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        71538505                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      71538505                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::cpu.inst     71538505                       # number of overall hits
+system.cpu.icache.overall_hits::total        71538505                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         4688                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          4688                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         4688                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           4688                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         4688                       # number of overall misses
 system.cpu.icache.overall_misses::total          4688                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    200735747                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    200735747                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    200735747                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    200735747                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    200735747                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    200735747                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71543191                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71543191                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71543191                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71543191                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71543191                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71543191                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    199914000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    199914000                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total    199914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    199914000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    199914000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     71543193                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     71543193                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     71543193                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42819.058660                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42819.058660                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42643.771331                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42643.771331                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -597,117 +597,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         4688
 system.cpu.icache.demand_mshr_misses::total         4688                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4688                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4688                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    192780753                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    192780753                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    192780753                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    192780753                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    192780753                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    192780753                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195227000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    195227000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195227000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    195227000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195227000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    195227000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.984642                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41643.984642                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41643.984642                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2002.534339                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2603                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2002.545063                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.sampled_refs             2788                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.933644                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.862267                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.029198                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1508.688891                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   490.816250                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046042                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          155                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085083                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            55998                       # Number of tag accesses
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 system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
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-system.cpu.l2cache.demand_hits::cpu.inst         2522                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
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-system.cpu.l2cache.demand_misses::cpu.inst         2166                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
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 system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst         4688                       # number of demand (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.462031                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.462031                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.598338                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.598184                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76617.431193                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76617.431193                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74690.069284                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74690.069284                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.784810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.784810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74690.069284                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77059.814170                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75739.902238                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74690.069284                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77059.814170                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75739.902238                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -716,93 +722,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2163                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          618                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2781                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2163                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2163                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          618                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          618                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2163                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         3871                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2163                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3871                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    134379750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     40985000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    175364750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     69507000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     69507000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    134379750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    110492000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    244871750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    134379750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    110492000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    244871750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.515000                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72613000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72613000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    139936000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    139936000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     42042000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     42042000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139936000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    114655000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    254591000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139936000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    114655000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    254591000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461391                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.867978                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.595722                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.595722                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           5400                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          5399                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2588                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9375                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3636                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             13011                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          712                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11943                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3656                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             15599                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299968                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             416832                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6514                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9429                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               6514    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               9429    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6514                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        3273000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9429                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        4730500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7492747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7031498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3019736                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       2721986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                2780                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2780                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2780                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7740                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   7740                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247680                       # Cumulative packet size per connected master and slave (bytes)
@@ -818,9 +831,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3870                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4535500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4532500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20561750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20566750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index a8c1caea2..b441da851 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085032                       # Number of seconds simulated
-sim_ticks                                 85032044000                       # Number of ticks simulated
-final_tick                                85032044000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.085019                       # Number of seconds simulated
+sim_ticks                                 85018904000                       # Number of ticks simulated
+final_tick                                85018904000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135904                       # Simulator instruction rate (inst/s)
-host_op_rate                                   143266                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67069129                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314096                       # Number of bytes of host memory used
-host_seconds                                  1267.83                       # Real time elapsed on the host
+host_inst_rate                                 135768                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143122                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               66991355                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 315704                       # Number of bytes of host memory used
+host_seconds                                  1269.10                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            127040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             47488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        71360                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               245888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       127040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          127040                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               1985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1115                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3842                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1494025                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               558472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       839213                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2891710                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1494025                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1494025                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1494025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              558472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       839213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2891710                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3842                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            126976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             47872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        71296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               246144                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       126976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          126976                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               1984                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                748                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1114                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3846                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1493503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               563075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       838590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2895168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1493503                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1493503                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1493503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              563075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       838590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2895168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3846                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3842                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3846                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   245888                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   246144                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    245888                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    246144                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -48,16 +48,16 @@ system.physmem.neitherReadNorWriteReqs              0                       # Nu
 system.physmem.perBankRdBursts::0                 309                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 220                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 142                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 309                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 300                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 262                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 233                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 237                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                292                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                291                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                194                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                191                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                193                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                211                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                211                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                194                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85031900500                       # Total gap between requests
+system.physmem.totGap                     85018760500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3842                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3846                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,16 +94,16 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2554                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        88                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2523                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       883                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        84                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        29                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          763                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      320.083879                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.433795                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     309.783352                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            232     30.41%     30.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          191     25.03%     55.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           88     11.53%     66.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           86     11.27%     78.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           27      3.54%     81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           37      4.85%     86.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           11      1.44%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           17      2.23%     90.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           74      9.70%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            763                       # Bytes accessed per row activation
-system.physmem.totQLat                       43141443                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 115178943                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19210000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11228.90                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          777                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      316.211068                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     199.877402                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     303.919917                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            237     30.50%     30.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          193     24.84%     55.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           84     10.81%     66.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           88     11.33%     77.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           35      4.50%     81.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           40      5.15%     87.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           20      2.57%     89.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           13      1.67%     91.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           67      8.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            777                       # Bytes accessed per row activation
+system.physmem.totQLat                       39111678                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 111224178                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10169.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29978.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.89                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28919.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.30                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.71                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3071                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       3067                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.93                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.75                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22132196.90                       # Average gap between requests
-system.physmem.pageHitRate                      79.93                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    2729160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1489125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     22105761.96                       # Average gap between requests
+system.physmem.pageHitRate                      79.75                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    2744280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1497375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16231800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5553475200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2330695800                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            48971187750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              56875754235                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.921152                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    81466351731                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2839200000                       # Time in different power states
+system.physmem_0.refreshEnergy             5552966640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2336092560                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            48961790250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              56871322905                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.930183                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    81450773508                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2838940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       720558269                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       728623992                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3016440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1645875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13548600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13712400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5553475200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2293230555                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            49004052000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              56868968670                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.841346                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    81522647918                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2839200000                       # Time in different power states
+system.physmem_1.refreshEnergy             5552966640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2289194100                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            49002929250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              56863639980                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.839816                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    81519548908                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2838940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       665486082                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       659848592                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85925704                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68401753                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6018362                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40106814                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39018678                       # Number of BTB hits
+system.cpu.branchPred.lookups                85912123                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68393040                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6015536                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             40101118                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                39014565                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.286905                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3705148                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81894                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.290467                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3703089                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81902                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,130 +381,130 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170064089                       # number of cpu cycles simulated
+system.cpu.numCycles                        170037809                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5613343                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349288276                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85925704                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42723826                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158284040                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12050671                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1737                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5613511                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      349250633                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85912123                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42717654                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     158261511                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12044973                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1577                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         2225                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78959765                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 17996                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          169926703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.150511                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.047128                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         2368                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78950648                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 18008                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169901476                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.150563                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.047122                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17361476     10.22%     10.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30212798     17.78%     28.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31840839     18.74%     46.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90511590     53.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17358895     10.22%     10.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30204196     17.78%     27.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31835534     18.74%     46.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 90502851     53.27%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            169926703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.505255                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.053863                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17566577                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17110905                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122676579                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6722207                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5850435                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11136607                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                190140                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306627324                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27647944                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5850435                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37756146                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8468505                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         579113                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108935441                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8337063                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278668040                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13416082                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3052051                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 841470                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2187697                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  36000                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            26450                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483113762                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1196983953                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297587542                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3006013                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            169901476                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.505253                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.053959                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17563828                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17110473                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 122657456                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6722156                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5847563                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11134699                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                190129                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              306600036                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27639970                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5847563                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37745979                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8468798                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         579877                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108923634                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8335625                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              278650711                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13412582                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3051453                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 842711                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2185712                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  35165                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            26489                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           483080894                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1196921588                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        297573906                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3006747                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190136833                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23525                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23424                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13336678                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34143660                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14476609                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2548114                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1810648                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  264825192                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45854                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214913936                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5193552                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        83235092                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219939501                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            638                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     169926703                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.264745                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                190103965                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23523                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23430                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13336347                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             34142095                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14476543                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2549376                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1793123                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  264810332                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45855                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214902718                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5190620                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        83220233                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    219925398                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            639                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     169901476                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.264867                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        1.017460                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52848454     31.10%     31.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36099011     21.24%     52.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65787739     38.72%     91.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13574201      7.99%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1569834      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47276      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 188      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            52832101     31.10%     31.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            36093158     21.24%     52.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65784259     38.72%     91.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13574357      7.99%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1570220      0.92%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47195      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 186      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       169926703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169901476                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35606881     66.11%     66.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 152777      0.28%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1069      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35605011     66.11%     66.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 152712      0.28%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1068      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35731      0.07%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               243      0.00%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc             1036      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34373      0.06%     66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35741      0.07%     66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               239      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc             1037      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34404      0.06%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14081261     26.14%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3945561      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14078469     26.14%     92.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3945889      7.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167354642     77.87%     77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918991      0.43%     78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             167344164     77.87%     77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               918970      0.43%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.30% # Type of FU issued
@@ -525,91 +525,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.30% # Ty
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd           33018      0.02%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165174      0.08%     78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165202      0.08%     78.39% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt          245708      0.11%     78.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460494      0.21%     78.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206680      0.10%     78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460547      0.21%     78.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206694      0.10%     78.85% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32007537     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13373732      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32006921     14.89%     93.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13373534      6.22%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214913936                       # Type of FU issued
-system.cpu.iq.rate                           1.263723                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53859137                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.250608                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          654855291                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         346101904                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204603491                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3951973                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011176                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806361                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266640239                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2132834                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1601131                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214902718                       # Type of FU issued
+system.cpu.iq.rate                           1.263853                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53854775                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.250601                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          654798543                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         346070765                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204597394                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3953764                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2012584                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806443                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266623027                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2134466                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1601141                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6247516                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7571                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         7104                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1831975                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6245951                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7537                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         7067                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1831909                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25920                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           745                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25713                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           804                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5850435                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5682032                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 37041                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           264886958                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5847563                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5681873                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 37049                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           264872174                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34143660                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14476609                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23446                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3875                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29998                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           7104                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3234550                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3248118                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6482668                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207528127                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30721496                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7385809                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              34142095                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14476543                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23447                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3919                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29963                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           7067                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3232804                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3246682                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6479486                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207521850                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30720954                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7380868                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         15912                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43861162                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44936179                       # Number of branches executed
-system.cpu.iew.exec_stores                   13139666                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.220294                       # Inst execution rate
-system.cpu.iew.wb_sent                      206744895                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206409852                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129477271                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221697359                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         15987                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43860782                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44934590                       # Number of branches executed
+system.cpu.iew.exec_stores                   13139828                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.220445                       # Inst execution rate
+system.cpu.iew.wb_sent                      206738830                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206403837                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129472700                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221699640                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.213718                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584027                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.213870                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.584000                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        69541697                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        69532932                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5843462                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158482976                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.146182                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.646662                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5840613                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158460459                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.146345                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.646701                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73704941     46.51%     46.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41274815     26.04%     72.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22552900     14.23%     86.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9628649      6.08%     92.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3549516      2.24%     95.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2148015      1.36%     96.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1280291      0.81%     97.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       986897      0.62%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3356952      2.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73681032     46.50%     46.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41276330     26.05%     72.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22553900     14.23%     86.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9626912      6.08%     92.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3550160      2.24%     95.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2147757      1.36%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1281176      0.81%     97.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       986541      0.62%     97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3356651      2.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158482976                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158460459                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -655,374 +655,380 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3356952                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406312862                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513841850                       # The number of ROB writes
-system.cpu.timesIdled                            3415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          137386                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3356651                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    406281881                       # The number of ROB reads
+system.cpu.rob.rob_writes                   513821502                       # The number of ROB writes
+system.cpu.timesIdled                            3434                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          136333                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.987006                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.987006                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.013165                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.013165                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218961575                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114515726                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904225                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441500                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709589041                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229545726                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59313943                       # number of misc regfile reads
+system.cpu.cpi                               0.986853                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.986853                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.013322                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.013322                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218956398                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114512064                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904391                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441624                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 709567727                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229536120                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59314176                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72899                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.418278                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41116599                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73411                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.087712                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         506067250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.418278                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998864                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998864                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements             72863                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.419653                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41115439                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73375                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            560.346698                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         504093500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.419653                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998867                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998867                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82531693                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82531693                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28730266                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28730266                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341417                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341417                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          82529747                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82529747                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28729201                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28729201                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341321                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341321                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22149                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22149                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41071683                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41071683                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41072044                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41072044                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89294                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89294                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22870                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22870                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          118                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          118                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          260                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          260                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112164                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112164                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112282                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112282                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    853196487                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    853196487                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    241173427                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    241173427                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2319500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      2319500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1094369914                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1094369914                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1094369914                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1094369914                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28819560                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28819560                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      41070522                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41070522                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41070883                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41070883                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89405                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89405                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22966                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22966                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          117                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          117                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       112371                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112371                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112488                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112488                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    853901000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    853901000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    240852499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    240852499                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2309500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      2309500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1094753499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1094753499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1094753499                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1094753499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28818606                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28818606                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          478                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          478                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22408                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22408                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41183847                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41183847                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41184326                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41184326                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003098                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003098                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001850                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001850                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.246347                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.246347                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011603                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011603                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002723                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002723                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002726                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002726                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9554.913958                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9554.913958                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8921.153846                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8921.153846                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9756.873097                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9756.873097                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9746.619351                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9746.619351                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          167                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         9765                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41182893                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41182893                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41183371                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41183371                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003102                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003102                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001857                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001857                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.244770                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.244770                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011558                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011558                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002729                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002729                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002731                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002731                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9550.931156                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9550.931156                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8916.988417                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8916.988417                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9742.313399                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9742.313399                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9732.180313                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9732.180313                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        10552                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             848                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    11.515330                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_targets             865                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    12.198844                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        64878                       # number of writebacks
-system.cpu.dcache.writebacks::total             64878                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24567                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24567                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14301                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14301                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          260                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          260                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        38868                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38868                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        38868                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38868                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64727                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64727                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8569                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8569                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73411                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73411                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    526755010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    526755010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     81248758                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     81248758                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       920500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       920500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    608003768                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    608003768                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    608924268                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    608924268                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002246                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002246                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001780                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001780                       # mshr miss rate for demand accesses
+system.cpu.dcache.writebacks::writebacks        64850                       # number of writebacks
+system.cpu.dcache.writebacks::total             64850                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24706                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24706                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14404                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14404                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        39110                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39110                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39110                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39110                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64699                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64699                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8562                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8562                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          114                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          114                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data        73261                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        73261                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73375                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73375                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    558347000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    558347000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85131499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85131499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       970000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       970000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    643478499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    643478499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    644448499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    644448499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.238494                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.238494                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001779                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001779                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001782                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8138.103264                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8138.103264                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9481.708251                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9481.708251                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8004.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8004.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8295.183475                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8295.183475                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8294.727875                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8294.727875                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8629.917000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8629.917000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9942.945457                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9942.945457                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8508.771930                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8508.771930                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8783.370402                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8783.370402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8782.943768                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8782.943768                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             54462                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.603252                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78902001                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54974                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1435.260323                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84278847250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.603252                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997272                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997272                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             54433                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.604366                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78892637                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54945                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1435.847429                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84263927500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.604366                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997274                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997274                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          272                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157974458                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157974458                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78902001                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78902001                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78902001                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78902001                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78902001                       # number of overall hits
-system.cpu.icache.overall_hits::total        78902001                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        57741                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         57741                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        57741                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          57741                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        57741                       # number of overall misses
-system.cpu.icache.overall_misses::total         57741                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    606045932                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    606045932                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    606045932                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    606045932                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    606045932                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    606045932                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78959742                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78959742                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78959742                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78959742                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78959742                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78959742                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000731                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000731                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000731                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000731                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000731                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000731                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10495.937583                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10495.937583                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10495.937583                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10495.937583                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10495.937583                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10495.937583                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        55224                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         157956201                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        157956201                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78892637                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78892637                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78892637                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78892637                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78892637                       # number of overall hits
+system.cpu.icache.overall_hits::total        78892637                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57991                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57991                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57991                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57991                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57991                       # number of overall misses
+system.cpu.icache.overall_misses::total         57991                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    602655456                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    602655456                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    602655456                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    602655456                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    602655456                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    602655456                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78950628                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78950628                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78950628                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78950628                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78950628                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78950628                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10392.223897                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10392.223897                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        58612                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2764                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2849                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.979740                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.572833                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2767                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2767                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2767                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2767                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2767                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2767                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54974                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54974                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54974                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54974                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54974                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54974                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    508400239                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    508400239                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    508400239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    508400239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    508400239                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    508400239                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3046                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3046                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3046                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3046                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total         3046                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54945                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54945                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54945                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total        54945                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    535420965                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    535420965                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    535420965                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    535420965                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total    535420965                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000696                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9248.012497                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9248.012497                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9248.012497                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9744.671308                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9744.671308                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9744.671308                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9320                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9320                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9365                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9365                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1320                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1339                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2670.271397                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             178475                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3578                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            49.881219                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2660.276616                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             230314                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3583                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            64.279654                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   701.931689                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.006014                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   417.075318                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   175.258376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   701.934591                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.049531                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   421.061183                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   161.231311                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.042843                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.083985                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.025456                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3314                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           86                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          747                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.data_accesses         3104422                       # Number of data accesses
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-system.cpu.l2cache.Writeback_hits::writebacks        64878                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        64878                       # number of Writeback hits
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+system.cpu.l2cache.tags.data_accesses         3933865                       # Number of data accesses
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+system.cpu.l2cache.Writeback_hits::total        64850                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         8397                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         8397                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadExReq_misses::cpu.data          239                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     37619250                       # number of ReadReq miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks        64878                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        64878                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         8636                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69476.834265                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76864.054393                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76864.054393                       # average ReadExReq miss latency
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+system.cpu.l2cache.overall_hits::total         125573                       # number of overall hits
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+system.cpu.l2cache.Writeback_accesses::total        64850                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.inst        54945                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data        73375                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       128320                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027450                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027450                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.036200                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.036200                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.008047                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.008047                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036200                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.010330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.021407                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036200                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.010330                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.021407                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76008.438819                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76008.438819                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68331.573655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68331.573655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71260.076775                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71260.076775                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68331.573655                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72744.722955                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69549.326538                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68331.573655                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72744.722955                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69549.326538                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1031,126 +1037,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            2                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total            2                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1985                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          505                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2490                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1805                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         1805                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          237                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          237                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1985                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          742                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         2727                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1985                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          742                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1805                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    119139257                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     32909250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    152048507                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     70744400                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     70744400                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     15940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     15940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    119139257                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     48849500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    167988757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    119139257                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     48849500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     70744400                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    238733157                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.007796                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.020793                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1818                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total         1818                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          235                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          235                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1984                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1984                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          513                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          513                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1984                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          748                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         2732                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1984                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          748                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1818                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4550                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     70301588                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     70301588                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16173000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16173000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    123686500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    123686500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33594500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33594500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    123686500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     49767500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    173454000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    123686500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     49767500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     70301588                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    243755588                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010107                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.021241                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010107                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027218                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027218                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.036109                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.007924                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.007924                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010194                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.021291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010194                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.035300                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.035458                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         119749                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        119749                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        64878                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2153                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         8636                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         8636                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       109948                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       211700                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            321648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3518336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8850496                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           12368832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                        2153                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       195416                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.011018                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.104385                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        119686                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        64850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51933                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2160                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         8634                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         8634                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        54945                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64741                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       155973                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       217450                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            373423                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3516480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8846400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           12362880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                        2160                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       257776                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.008379                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.091155                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             193263     98.90%     98.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               2153      1.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             255616     99.16%     99.16% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               2160      0.84%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         195416                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      161509500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         257776                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      192658000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82870477                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      82430973                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110219231                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     110066991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3605                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3605                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               237                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              237                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7684                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7684                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       245888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  245888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3611                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               235                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              235                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3611                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7692                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7692                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       246144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  246144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3842                       # Request fanout histogram
+system.membus.snoop_fanout::samples              3846                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3842    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3846    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3842                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4969720                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                3846                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             5081597                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20244552                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20277583                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 1d32cdbce..8e968af2a 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.081225                       # Number of seconds simulated
-sim_ticks                                 81224844500                       # Number of ticks simulated
-final_tick                                81224844500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.081371                       # Number of seconds simulated
+sim_ticks                                 81371461000                       # Number of ticks simulated
+final_tick                                81371461000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91947                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56548085                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347388                       # Number of bytes of host memory used
-host_seconds                                  1436.39                       # Real time elapsed on the host
+host_inst_rate                                  90424                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151559                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               55711800                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348672                       # Number of bytes of host memory used
+host_seconds                                  1460.58                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            224768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125760                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               350528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       224768                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          224768                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3512                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5477                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2767232                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1548295                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4315527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2767232                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2767232                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2767232                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1548295                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4315527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5477                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            224128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125504                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               349632                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       224128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          224128                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1961                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5463                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2754381                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1542359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4296740                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2754381                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2754381                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2754381                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1542359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4296740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5463                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5477                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5463                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   350528                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   349632                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    350528                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    349632                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            298                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 295                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 355                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 457                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 353                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 337                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 331                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 400                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 389                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 346                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 296                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            312                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 292                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 354                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 456                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 360                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 330                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 342                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 399                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 387                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 324                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                240                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                297                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                270                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                472                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                395                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                294                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                487                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                392                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                328                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     81224754500                       # Total gap between requests
+system.physmem.totGap                     81371407000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5477                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5463                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4344                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       189                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4363                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       914                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       164                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,174 +186,173 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1132                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.296820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.870491                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.897635                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            457     40.37%     40.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          236     20.85%     61.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          108      9.54%     70.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           58      5.12%     75.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           52      4.59%     80.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           57      5.04%     85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           15      1.33%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      1.59%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          131     11.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1132                       # Bytes accessed per row activation
-system.physmem.totQLat                       39829000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 142522750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     27385000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7272.05                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1133                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.177405                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.606569                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.434363                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            453     39.98%     39.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          241     21.27%     61.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          107      9.44%     70.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           66      5.83%     76.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      3.71%     80.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           53      4.68%     84.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      2.65%     87.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           18      1.59%     89.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          123     10.86%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1133                       # Bytes accessed per row activation
+system.physmem.totQLat                       39364000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 141795250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     27315000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7205.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26022.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25955.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.30                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.30                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4337                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4322                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.19                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.11                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14830154.19                       # Average gap between requests
-system.physmem.pageHitRate                      79.19                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4944240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2697750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  22612200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     14895004.03                       # Average gap between requests
+system.physmem.pageHitRate                      79.11                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4898880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2673000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  22627800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5304789360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2574291285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            46473030000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              54382364835                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.579902                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    77308994750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2712060000                       # Time in different power states
+system.physmem_0.refreshEnergy             5314452000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2576418525                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            46559935500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              54481005705                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.574677                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    77452365250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2717000000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1198731250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1197234500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3598560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1963500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  19773000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3643920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1988250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  19640400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5304789360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2411784000                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            46615580250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              54357488670                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.273616                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    77550451000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2712060000                       # Time in different power states
+system.physmem_1.refreshEnergy             5314452000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2400589485                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            46714163250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              54454477305                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.248755                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    77713281250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2717000000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       960225000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       939125250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                21757824                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          21757824                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1548941                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             13682195                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12857487                       # Number of BTB hits
+system.cpu.branchPred.lookups                21769917                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          21769917                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1549122                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             13731962                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12878566                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.972400                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1522808                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21281                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.785331                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1523299                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21478                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        162449690                       # number of cpu cycles simulated
+system.cpu.numCycles                        162742923                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27167357                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      241462052                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    21757824                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           14380295                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     133204520                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3672137                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         11                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 3242                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         32817                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           27183337                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      241535825                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    21769917                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           14401865                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     133481172                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3672135                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                          7                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 3449                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         35973                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          121                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  26014450                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                320059                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          162244149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.449323                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.349447                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  26033005                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                318152                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          162540128                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.445335                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.347989                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 96544935     59.51%     59.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4966288      3.06%     62.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3924303      2.42%     64.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4589791      2.83%     67.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4444336      2.74%     70.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5042325      3.11%     73.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5076481      3.13%     76.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3889378      2.40%     79.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 33766312     20.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 96819226     59.57%     59.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4970692      3.06%     62.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3926504      2.42%     65.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4600449      2.83%     67.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4436163      2.73%     70.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5045508      3.10%     73.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5083113      3.13%     76.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3898601      2.40%     79.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 33759872     20.77%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            162244149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.133936                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.486381                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16503411                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96610290                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  25882430                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21411950                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1836068                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              352729241                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1836068                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24442767                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                33233774                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          31009                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  38303751                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              64396780                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              343252745                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1943                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               56953505                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7545423                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 167940                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           397342568                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             949709399                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        627052131                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4618257                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            162540128                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.133769                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.484156                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16504764                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              96892991                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  25874540                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21431766                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1836067                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              352818767                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1836067                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24444805                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                33422530                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          30828                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  38315708                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              64490190                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              343379412                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1374                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               57139077                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7429063                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 172376                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           397453727                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             950141626                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        627304694                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4642412                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                137913118                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2151                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2060                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 120010907                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             87039709                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            31137080                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          61853756                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         20927707                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  331596276                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4834                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 264603975                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             77857                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       110237726                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    225639096                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3589                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     162244149                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.630900                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.539803                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                138024277                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2171                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2092                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 120106098                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             87123680                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            31143046                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          62089518                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21014033                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  331702995                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4700                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 264529155                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             75427                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       110344311                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    226235086                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3455                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     162540128                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.627470                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.538199                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            42788422     26.37%     26.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47622129     29.35%     55.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            33320454     20.54%     76.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18328192     11.30%     87.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11302199      6.97%     94.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4922011      3.03%     97.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2609014      1.61%     99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              930397      0.57%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              421331      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            42962851     26.43%     26.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            47766675     29.39%     55.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            33381943     20.54%     76.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18299706     11.26%     87.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11254917      6.92%     94.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4928041      3.03%     97.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2601211      1.60%     99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              925935      0.57%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              418849      0.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       162244149                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       162540128                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  230632      7.18%      7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  228422      7.18%      7.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      7.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.18% # attempts to use FU when none available
@@ -382,118 +381,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.18% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2590896     80.61%     87.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                392432     12.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2563241     80.56%     87.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                390075     12.26%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1211493      0.46%      0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             165364025     62.49%     62.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               786761      0.30%     63.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7038559      2.66%     65.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1211557      0.46%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             66257169     25.04%     91.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22734411      8.59%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1211775      0.46%      0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             165335672     62.50%     62.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               786316      0.30%     63.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7038827      2.66%     65.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1212035      0.46%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             66231753     25.04%     91.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22712777      8.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              264603975                       # Type of FU issued
-system.cpu.iq.rate                           1.628836                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3213960                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012146                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          689757647                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         437892717                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    258330357                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4986269                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4261617                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2393080                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              264097165                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2509277                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18796485                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              264529155                       # Type of FU issued
+system.cpu.iq.rate                           1.625442                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3181738                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012028                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          689869496                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         438078029                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    258256761                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4986107                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4289171                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2392105                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              263990006                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2509112                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18745493                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     30390155                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14027                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       322538                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10621363                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     30474102                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13683                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       322031                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10627329                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        52082                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            20                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        52743                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            15                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1836068                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                14114838                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                500285                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           331601110                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            108836                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              87039742                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             31137080                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2060                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 401860                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 61208                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         322538                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         680213                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       929259                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1609472                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             262268386                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              65330198                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2335589                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1836067                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                14124717                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                495168                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           331707695                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            107609                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              87123689                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             31143046                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2075                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 394182                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 62934                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         322031                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         682027                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       925981                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1608008                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             262198462                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              65303975                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2330693                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     87858182                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14520351                       # Number of branches executed
-system.cpu.iew.exec_stores                   22527984                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.614459                       # Inst execution rate
-system.cpu.iew.wb_sent                      261554043                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     260723437                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 208617070                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 375029707                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     87811155                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14511685                       # Number of branches executed
+system.cpu.iew.exec_stores                   22507180                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.611121                       # Inst execution rate
+system.cpu.iew.wb_sent                      261483321                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     260648866                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 208559295                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 374938421                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.604949                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.556268                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.601599                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.556249                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110244875                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       110351288                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1552031                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    147195030                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.503878                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.943897                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1552443                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    147477365                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.500999                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.940236                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     47434016     32.23%     32.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57618157     39.14%     71.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14262797      9.69%     81.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11889308      8.08%     89.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4213027      2.86%     92.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2877009      1.95%     93.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       914800      0.62%     94.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1061572      0.72%     95.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6924344      4.70%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     47558134     32.25%     32.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57784481     39.18%     71.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14247523      9.66%     81.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11907169      8.07%     89.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4233466      2.87%     92.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2889588      1.96%     93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       908406      0.62%     94.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1058674      0.72%     95.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6889924      4.67%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    147195030                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    147477365                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -539,75 +538,74 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6924344                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    471878945                       # The number of ROB reads
-system.cpu.rob.rob_writes                   678308439                       # The number of ROB writes
-system.cpu.timesIdled                            2694                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          205541                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6889924                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    472302113                       # The number of ROB reads
+system.cpu.rob.rob_writes                   678534776                       # The number of ROB writes
+system.cpu.timesIdled                            2601                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          202795                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.230016                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.230016                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.812998                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.812998                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                454025160                       # number of integer regfile reads
-system.cpu.int_regfile_writes               236935746                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3267968                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2053127                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102766500                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 60037026                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               135494920                       # number of misc regfile reads
+system.cpu.cpi                               1.232236                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.232236                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.811533                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.811533                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                453858264                       # number of integer regfile reads
+system.cpu.int_regfile_writes               236894069                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3268800                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2052370                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102728686                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 60021475                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               135450288                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                56                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.236298                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            66889390                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2008                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          33311.449203                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                22                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1449.922463                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            66913357                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1999                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          33473.415208                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1448.236298                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1952                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          484                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1414                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.476562                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         133785736                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        133785736                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     46375033                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        46375033                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513891                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513891                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      66888924                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         66888924                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     66888924                       # number of overall hits
-system.cpu.dcache.overall_hits::total        66888924                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1100                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1100                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1840                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1840                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2940                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2940                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2940                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2940                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     68941167                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     68941167                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    128874548                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    128874548                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    197815715                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    197815715                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    197815715                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    197815715                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46376133                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46376133                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  1449.922463                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353985                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353985                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1977                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          483                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1444                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.482666                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         133833717                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        133833717                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     46399026                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        46399026                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513875                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513875                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      66912901                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         66912901                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     66912901                       # number of overall hits
+system.cpu.dcache.overall_hits::total        66912901                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1102                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1856                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1856                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2958                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2958                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2958                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2958                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     70369000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     70369000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    128824000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    128824000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    199193000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    199193000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    199193000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    199193000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46400128                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46400128                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     66891864                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     66891864                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     66891864                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     66891864                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     66915859                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     66915859                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     66915859                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     66915859                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000090                       # miss rate for WriteReq accesses
@@ -616,258 +614,264 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000044
 system.cpu.dcache.demand_miss_rate::total     0.000044                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000044                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000044                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62673.788182                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62673.788182                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70040.515217                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70040.515217                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67284.256803                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67284.256803                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67284.256803                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67284.256803                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          492                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           82                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63855.716878                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63855.716878                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69409.482759                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69409.482759                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67340.432725                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67340.432725                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67340.432725                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67340.432725                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          318                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           52                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.600000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           52                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
-system.cpu.dcache.writebacks::total                13                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          632                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          632                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          633                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          633                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          468                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          468                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1839                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1839                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2307                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2307                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2307                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2307                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36256250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36256250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    125371702                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    125371702                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161627952                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    161627952                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161627952                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    161627952                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           11                       # number of writebacks
+system.cpu.dcache.writebacks::total                11                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          641                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          641                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          643                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          643                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          643                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          643                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          461                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          461                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1854                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1854                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2315                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2315                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2315                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2315                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36642000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36642000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    126830000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    126830000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    163472000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    163472000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    163472000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    163472000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000090                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000090                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77470.619658                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77470.619658                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68173.845568                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68173.845568                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70059.797139                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70059.797139                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70059.797139                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70059.797139                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79483.731020                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79483.731020                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68408.845739                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68408.845739                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70614.254860                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70614.254860                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70614.254860                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70614.254860                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              5865                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1646.159130                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            26003921                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              7839                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3317.249777                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5619                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1637.148267                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            26022644                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              7593                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3427.188726                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1646.159130                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.803789                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.803789                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1637.148267                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.799389                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.799389                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1974                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          898                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          773                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          882                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          786                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.963867                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          52037036                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         52037036                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     26003921                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        26003921                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      26003921                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         26003921                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     26003921                       # number of overall hits
-system.cpu.icache.overall_hits::total        26003921                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        10528                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         10528                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        10528                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          10528                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        10528                       # number of overall misses
-system.cpu.icache.overall_misses::total         10528                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    430452747                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    430452747                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    430452747                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    430452747                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    430452747                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    430452747                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     26014449                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     26014449                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     26014449                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     26014449                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     26014449                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     26014449                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000405                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000405                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000405                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000405                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000405                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000405                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40886.469130                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40886.469130                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40886.469130                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40886.469130                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40886.469130                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40886.469130                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1891                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          52073916                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         52073916                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     26022649                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        26022649                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      26022649                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         26022649                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     26022649                       # number of overall hits
+system.cpu.icache.overall_hits::total        26022649                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        10355                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         10355                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        10355                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          10355                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        10355                       # number of overall misses
+system.cpu.icache.overall_misses::total         10355                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    419159499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    419159499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    419159499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    419159499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    419159499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    419159499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     26033004                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     26033004                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     26033004                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     26033004                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     26033004                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     26033004                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000398                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000398                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000398                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000398                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000398                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000398                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40478.947272                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 40478.947272                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 40478.947272                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 40478.947272                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 40478.947272                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 40478.947272                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1340                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                28                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    67.535714                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    51.538462                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2389                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2389                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2389                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2389                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2389                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2389                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8139                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         8139                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         8139                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         8139                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         8139                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         8139                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    322188751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    322188751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    322188751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    322188751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    322188751                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    322188751                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39585.790761                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39585.790761                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39585.790761                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39585.790761                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39585.790761                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39585.790761                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2445                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2445                       # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         2445                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7910                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst         7910                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total         7910                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    320594000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    320594000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    320594000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    320594000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    320594000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    320594000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000304                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000304                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000304                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40530.214918                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40530.214918                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40530.214918                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2629.714027                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               4366                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3947                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.106157                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2621.537078                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               9541                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3929                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.428353                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     2.821104                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2311.277195                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   315.615728                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000086                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.070535                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009632                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.080253                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3947                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks     0.832574                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2306.260557                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   314.443947                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000025                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1031                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2655                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.120453                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            86769                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           86769                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4327                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           35                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           4362                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
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-system.cpu.l2cache.demand_hits::cpu.inst         4327                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst         4327                       # number of overall hits
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-system.cpu.l2cache.overall_hits::total           4370                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3513                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          432                       # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::cpu.data          298                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          298                       # number of UpgradeReq misses
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+system.cpu.l2cache.tags.tag_accesses           128128                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          128128                       # Number of data accesses
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+system.cpu.l2cache.Writeback_hits::total           11                       # number of Writeback hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data         1533                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1533                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3513                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1965                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data         1965                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5478                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    268162500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     35336500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    303499000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    114204250                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data    149540750                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7840                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          467                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         8307                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          299                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::total         9848                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.448087                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.925054                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.474901                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.996656                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.996656                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994809                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994809                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.978586                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.556255                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.448087                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.978586                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.556255                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76334.329633                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81797.453704                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76932.572877                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74497.227658                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74497.227658                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76334.329633                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76102.162850                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76251.049653                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76334.329633                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76102.162850                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76251.049653                       # average overall miss latency
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+system.cpu.l2cache.ReadSharedReq_misses::total          428                       # number of ReadSharedReq misses
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+system.cpu.l2cache.overall_miss_latency::total    415260000                       # number of overall miss cycles
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+system.cpu.l2cache.demand_accesses::cpu.data         1999                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9593                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7594                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1999                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9593                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.987342                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.987342                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.996101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461285                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461285                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.930435                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.930435                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461285                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980990                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.569582                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461285                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980990                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.569582                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74643.835616                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74643.835616                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75733.799600                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75733.799600                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83026.869159                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83026.869159                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75733.799600                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76473.482917                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75999.267936                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75733.799600                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76473.482917                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75999.267936                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -876,102 +880,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3513                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          432                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3945                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          298                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          298                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          312                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          312                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1533                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1533                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3513                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1965                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5478                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3513                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1965                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5478                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    224321500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     29932000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    254253500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      5280798                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      5280798                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     95023750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95023750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    224321500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    124955750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    349277250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    224321500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    124955750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    349277250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.448087                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.925054                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.474901                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.996656                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.996656                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994809                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994809                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.448087                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.978586                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.556255                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.448087                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.978586                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.556255                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63854.682607                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69287.037037                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64449.556401                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17720.798658                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17720.798658                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61985.485975                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61985.485975                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63854.682607                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.712468                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63759.994524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63854.682607                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.712468                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63759.994524                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3503                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3503                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          428                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          428                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3503                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1961                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5464                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3503                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1961                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5464                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      6464000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      6464000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     99099000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     99099000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    230285500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    230285500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31255500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31255500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    130354500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    360640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230285500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    130354500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    360640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987342                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987342                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461285                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.930435                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.930435                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980990                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.569582                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980990                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.569582                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20717.948718                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20717.948718                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64643.835616                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64643.835616                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65739.508992                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73026.869159                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73026.869159                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66473.482917                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66002.928258                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66473.482917                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66002.928258                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           8606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          8605                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           13                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1541                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        15978                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4627                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             20605                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       501696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       129344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             631040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         299                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        10459                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp          8368                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           11                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         5412                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          316                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          316                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1539                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1539                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7910                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          460                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20904                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4651                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             25555                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       485888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             614528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         316                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        15866                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              10459    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              15866    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          10459                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5242500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          15866                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7944000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      12871748                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      11862000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3552548                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3157498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3944                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3944                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              298                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             298                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3929                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              312                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             312                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1533                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1533                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       350528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       350528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  350528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3930                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11549                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11549                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11549                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       349568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       349568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  349568                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples              5775                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
@@ -983,9 +993,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                5775                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6990000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7111000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           29627952                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           29581688                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index b3504c645..a85398f56 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,52 +4,52 @@ sim_seconds                                  1.869358                       # Nu
 sim_ticks                                1869358498000                       # Number of ticks simulated
 final_tick                               1869358498000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2576820                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2576818                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            74107088123                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319644                       # Number of bytes of host memory used
-host_seconds                                    25.23                       # Real time elapsed on the host
+host_inst_rate                                2452265                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2452264                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            70524991939                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 374768                       # Number of bytes of host memory used
+host_seconds                                    26.51                       # Real time elapsed on the host
 sim_insts                                    65000470                       # Number of instructions simulated
 sim_ops                                      65000470                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           765760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         66539648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           106432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           763584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         66536960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           106240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data           766208                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68179008                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       765760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       106432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          872192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7831360                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7831360                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1039682                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1663                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             68173952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       763584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       106240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          869824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7835712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7835712                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11931                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1039640                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1660                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data             11972                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1065297                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122365                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122365                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              409638                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35594910                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total               1065218                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122433                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122433                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              408474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            35593472                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56832                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.data              409878                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36471874                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         409638                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56935                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466573                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4189330                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4189330                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4189330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             409638                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35594910                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                36469170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         408474                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56832                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             465306                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4191658                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4191658                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4191658                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             408474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           35593472                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56832                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data             409878                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40661204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40660828                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
@@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       632997                       # number of writebacks
-system.cpu0.dcache.writebacks::total           632997                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       632989                       # number of writebacks
+system.cpu0.dcache.writebacks::total           632989                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements           618298                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.240646                       # Cycle average of tags in use
@@ -655,8 +655,7 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iobus.trans_dist::ReadReq                 7628                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7628                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              14588                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              56140                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14686                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -705,24 +704,24 @@ system.iocache.tags.tag_accesses               375579                       # Nu
 system.iocache.tags.data_accesses              375579                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          179                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               179                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          179                       # number of overall misses
 system.iocache.overall_misses::total              179                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          179                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             179                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          179                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            179                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
@@ -738,89 +737,86 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   999763                       # number of replacements
-system.l2c.tags.tagsinuse                65320.982513                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2387511                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1064813                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.242188                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   999684                       # number of replacements
+system.l2c.tags.tagsinuse                65320.982503                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4588619                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1064734                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.309639                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   56016.894287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4834.499535                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4176.023150                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      178.992489                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      114.573052                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.854750                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073769                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.063721                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002731                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   55911.037805                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4939.570238                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4176.759225                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      179.034361                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      114.580874                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.853135                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.075372                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.063732                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002732                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.001748                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.996719                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65050                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          768                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1         3271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6125                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6123                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::3         5943                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48943                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        48945                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.992584                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 31464842                       # Number of tag accesses
-system.l2c.tags.data_accesses                31464842                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             606959                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             626686                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             379549                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             129013                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1742207                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          777528                       # number of Writeback hits
-system.l2c.Writeback_hits::total               777528                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 49101323                       # Number of tag accesses
+system.l2c.tags.data_accesses                49101323                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          777520                       # number of Writeback hits
+system.l2c.Writeback_hits::total               777520                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data             116                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data             577                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 693                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data            13                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           111433                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           111476                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::cpu1.data            56603                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               168036                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              606959                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              738119                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              379549                       # number of demand (read+write) hits
+system.l2c.ReadExReq_hits::total               168079                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        606993                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        379552                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            986545                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       626685                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       129013                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           755698                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              606993                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              738161                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              379552                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data              185616                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1910243                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             606959                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             738119                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             379549                       # number of overall hits
+system.l2c.demand_hits::total                 1910322                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             606993                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             738161                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             379552                       # number of overall hits
 system.l2c.overall_hits::cpu1.data             185616                       # number of overall hits
-system.l2c.overall_hits::total                1910243                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11965                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           926610                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1663                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1033                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               941271                       # number of ReadReq misses
+system.l2c.overall_hits::total                1910322                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data          3006                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data          2174                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              5180                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu0.data         1175                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data         1110                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total            2285                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113916                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113873                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data          11069                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             124985                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11965                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data           1040526                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1663                       # number of demand (read+write) misses
+system.l2c.ReadExReq_misses::total             124942                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        11931                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         1660                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           13591                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       926611                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         1033                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         927644                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst             11931                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data           1040484                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1660                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data             12102                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1066256                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11965                       # number of overall misses
-system.l2c.overall_misses::cpu0.data          1040526                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1663                       # number of overall misses
+system.l2c.demand_misses::total               1066177                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11931                       # number of overall misses
+system.l2c.overall_misses::cpu0.data          1040484                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1660                       # number of overall misses
 system.l2c.overall_misses::cpu1.data            12102                       # number of overall misses
-system.l2c.overall_misses::total              1066256                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst         618924                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1553296                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         381212                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         130046                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2683478                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       777528                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           777528                       # number of Writeback accesses(hits+misses)
+system.l2c.overall_misses::total              1066177                       # number of overall misses
+system.l2c.Writeback_accesses::writebacks       777520                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           777520                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         3122                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         2751                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            5873                       # number of UpgradeReq accesses(hits+misses)
@@ -830,6 +826,12 @@ system.l2c.SCUpgradeReq_accesses::total          2335                       # nu
 system.l2c.ReadExReq_accesses::cpu0.data       225349                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data        67672                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           293021                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       618924                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       381212                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1000136                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      1553296                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       130046                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1683342                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.inst          618924                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data         1778645                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst          381212                       # number of demand (read+write) accesses
@@ -840,30 +842,31 @@ system.l2c.overall_accesses::cpu0.data        1778645                       # nu
 system.l2c.overall_accesses::cpu1.inst         381212                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data         197718                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2976499                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.019332                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.596544                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004362                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.007943                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.350765                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962844                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.790258                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.882002                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.969472                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.988424                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.978587                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.505509                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.505318                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.163568                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.426539                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.019332                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.585010                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004362                       # miss rate for demand accesses
+system.l2c.ReadExReq_miss_rate::total        0.426393                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.019277                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004355                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.013589                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.596545                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.007943                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.551073                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.019277                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.584987                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004355                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.061208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.358225                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.019332                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.585010                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004362                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::total           0.358198                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.019277                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.584987                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004355                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.061208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.358225                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.358198                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -872,79 +875,84 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               80845                       # number of writebacks
-system.l2c.writebacks::total                    80845                       # number of writebacks
+system.l2c.writebacks::writebacks               80913                       # number of writebacks
+system.l2c.writebacks::total                    80913                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              948899                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948899                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7449                       # Transaction distribution
+system.membus.trans_dist::ReadResp             948863                       # Transaction distribution
 system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             14588                       # Transaction distribution
-system.membus.trans_dist::Writeback            122365                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::Writeback            122433                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           922490                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            19616                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq          14180                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            8160                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            126515                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           124290                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            126472                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           124247                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        941414                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        44074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      2256148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      2300222                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124982                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124982                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2425204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3178369                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3222443                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125161                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       125161                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3347604                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73369984                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     73456146                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5328064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5328064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                78784210                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73369280                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     73455442                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2668736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2668736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                76124178                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1287715                       # Request fanout histogram
+system.membus.snoop_fanout::samples           2210194                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1287715    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2210194    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1287715                       # Request fanout histogram
-system.toL2Bus.trans_dist::ReadReq            2732182                       # Transaction distribution
+system.membus.snoop_fanout::total             2210194                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq               7449                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp           2732182                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            14588                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           777528                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           777520                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2204578                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq           19614                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq         14230                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp          33844                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq           295246                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp          295246                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1237890                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4301779                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       762424                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       627155                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6929248                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq       1000157                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1724576                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1856188                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5450155                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1143095                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       684380                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               9133818                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     39612480                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155758587                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155758075                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     24397568                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23357975                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              243126610                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              243126098                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                           41895                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3895119                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.010714                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.102951                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples          6099689                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.006841                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.082430                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3853388     98.93%     98.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41731      1.07%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                6057958     99.32%     99.32% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  41731      0.68%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3895119                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            6099689                       # Request fanout histogram
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 3fe61f3f7..60a4f6e98 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,42 +4,42 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332273500                       # Number of ticks simulated
 final_tick                               1829332273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2059947                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2059945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            62765242809                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317596                       # Number of bytes of host memory used
-host_seconds                                    29.15                       # Real time elapsed on the host
+host_inst_rate                                2495393                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2495392                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            76033049021                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371696                       # Number of bytes of host memory used
+host_seconds                                    24.06                       # Real time elapsed on the host
 sim_insts                                    60038341                       # Number of instructions simulated
 sim_ops                                      60038341                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66839040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            856000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          66836224                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             67697984                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7411008                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7411008                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044360                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             67693184                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       856000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          856000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7414144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7414144                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1044316                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1057781                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115797                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115797                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               469015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36537397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total               1057706                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115846                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115846                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               467930                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36535858                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37006937                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4051209                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4051209                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4051209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              469015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36537397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                37004313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          467930                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             467930                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4052924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4052924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4052924                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              467930                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36535858                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41058146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41057237                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833501                       # number of writebacks
-system.cpu.dcache.writebacks::total            833501                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       833493                       # number of writebacks
+system.cpu.dcache.writebacks::total            833493                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            919605                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.215260                       # Cycle average of tags in use
@@ -336,84 +336,88 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           992295                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65424.374284                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2433284                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1057458                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.301069                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           992219                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65424.374112                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4561879                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1057382                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.314315                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4866.099732                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.922318                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.859228                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074251                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4923.444270                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4248.032969                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.858351                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075126                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.064820                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.998297                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          781                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3260                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4024                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3055                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54043                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3053                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54045                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         31737815                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        31737815                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       906808                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       811247                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1718055                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       833501                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       833501                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         48768396                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        48768396                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       833493                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       833493                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187243                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187243                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906808                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998490                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905298                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906808                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998490                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905298                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13406                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       941046                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187288                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187288                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906839                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       906839                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811246                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       811246                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       906839                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998534                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1905373                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       906839                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998534                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1905373                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117111                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117111                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13406                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044751                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1058157                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13406                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044751                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1058157                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       920214                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1738887                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2659101                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       833501                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       833501                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data       117066                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       117066                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13375                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        13375                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       927641                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       927641                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        13375                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1044707                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1058082                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        13375                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1044707                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1058082                       # number of overall misses
+system.cpu.l2cache.Writeback_accesses::writebacks       833493                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       833493                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       304354                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       304354                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920214                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       920214                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738887                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1738887                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst       920214                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      2043241                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total      2963455                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst       920214                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      2043241                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      2963455                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014568                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533468                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.353896                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384785                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384785                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014568                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511320                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.357069                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014568                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511320                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.357069                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384638                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384638                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014535                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014535                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533468                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533468                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014535                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.511299                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.357043                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014535                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.511299                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.357043                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -422,36 +426,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74285                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74285                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74334                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74334                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2666303                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       2666303                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       833501                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       833493                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2128840                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       304354                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       304354                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1840464                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4954059                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6794523                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       920232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738887                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760069                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163286                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8923355                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     58894848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184157614                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          243052462                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184157102                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          243051950                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       41883                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3855738                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.010822                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103463                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      5984570                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.006972                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.083208                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3814012     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41726      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5942844     99.30%     99.30% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              41726      0.70%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3855738                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5984570                       # Request fanout histogram
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -467,8 +474,7 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9838                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51390                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -517,24 +523,24 @@ system.iocache.tags.tag_accesses               375534                       # Nu
 system.iocache.tags.data_accesses              375534                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
 system.iocache.overall_misses::total              174                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
@@ -550,41 +556,43 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              948404                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948404                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7184                       # Transaction distribution
+system.membus.trans_dist::ReadResp             948374                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
-system.membus.trans_dist::Writeback            115797                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::Writeback            115846                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           918371                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116991                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116991                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116946                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116946                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        941190                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2190623                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      2224667                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2349631                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3108719                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3142763                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125138                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       125138                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3267901                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72468608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72514734                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5327232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5327232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                77841966                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72466944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72513070                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2667904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2667904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                75180974                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1232714                       # Request fanout histogram
+system.membus.snoop_fanout::samples           2151059                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1232714    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2151059    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1232714                       # Request fanout histogram
+system.membus.snoop_fanout::total             2151059                       # Request fanout histogram
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 3f2e8762f..67605a567 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,117 +1,117 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.962613                       # Number of seconds simulated
-sim_ticks                                1962612686500                       # Number of ticks simulated
-final_tick                               1962612686500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.962608                       # Number of seconds simulated
+sim_ticks                                1962608482500                       # Number of ticks simulated
+final_tick                               1962608482500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1118839                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1118839                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36057415911                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319640                       # Number of bytes of host memory used
-host_seconds                                    54.43                       # Real time elapsed on the host
-sim_insts                                    60898638                       # Number of instructions simulated
-sim_ops                                      60898638                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1019388                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1019388                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32859851956                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 375280                       # Number of bytes of host memory used
+host_seconds                                    59.73                       # Real time elapsed on the host
+sim_insts                                    60884587                       # Number of instructions simulated
+sim_ops                                      60884587                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           836288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24736704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            28736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           435776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           831936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24730240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            31616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           435904                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26038464                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       836288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        28736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7702400                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7702400                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13067                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            386511                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               449                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              6809                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26030656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       831936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        31616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          863552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7705152                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7705152                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             12999                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            386410                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               494                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              6811                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                406851                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120350                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120350                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              426110                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12603966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               14642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              222039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                406729                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          120393                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               120393                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              423893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12600700                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               16109                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              222104                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13267245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         426110                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          14642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             440751                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3924564                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3924564                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3924564                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             426110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12603966                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              14642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             222039                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13263295                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         423893                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          16109                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440002                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3925975                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3925975                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3925975                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             423893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12600700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              16109                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             222104                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              489                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17191810                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        406851                       # Number of read requests accepted
-system.physmem.writeReqs                       161902                       # Number of write requests accepted
-system.physmem.readBursts                      406851                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     161902                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26031872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8721536                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26038464                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10361728                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   25609                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           6974                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25141                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25398                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25524                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24918                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25169                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25258                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25808                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25541                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25675                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25330                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25284                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25615                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25647                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25653                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25754                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25033                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8965                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8625                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8456                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7799                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8065                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8041                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8610                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8172                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8465                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8053                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8222                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8481                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8850                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9510                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9309                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8651                       # Per bank write bursts
+system.physmem.bw_total::total               17189270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        406729                       # Number of read requests accepted
+system.physmem.writeReqs                       120393                       # Number of write requests accepted
+system.physmem.readBursts                      406729                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     120393                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26023296                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7703744                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26030656                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7705152                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          48492                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25025                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25421                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25447                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24899                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25181                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25235                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25799                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25539                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25681                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25348                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25259                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25592                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25653                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25554                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25887                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25094                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7701                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7641                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7454                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6926                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7165                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7117                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7626                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7252                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7527                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7238                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7225                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7418                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7843                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8207                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8447                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7584                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          56                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1962566141500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1962561950500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  406851                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  406729                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 161902                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    406672                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 120393                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    406538                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
@@ -158,190 +158,181 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5516                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5615                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6056                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::29                     7778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1989                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::46                     2742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      189                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::59                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       98                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        67633                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      513.852823                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     307.797069                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.051196                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16141     23.87%     23.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12717     18.80%     42.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5311      7.85%     50.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2897      4.28%     54.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2115      3.13%     57.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1690      2.50%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2144      3.17%     63.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1403      2.07%     65.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23215     34.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          67633                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4988                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        81.544306                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2972.635603                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           4985     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6416                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6086                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::21                     7189                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       58                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67016                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      503.268473                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     299.027850                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     415.161234                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16754     25.00%     25.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        12205     18.21%     43.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5432      8.11%     51.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3034      4.53%     55.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2418      3.61%     59.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1895      2.83%     62.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1494      2.23%     64.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1474      2.20%     66.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22310     33.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67016                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5361                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        75.845178                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2883.640505                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5358     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4988                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4988                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.320369                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.529999                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       62.006905                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4741     95.05%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              52      1.04%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63               5      0.10%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95               6      0.12%     96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              4      0.08%     96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            12      0.24%     96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            26      0.52%     97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            19      0.38%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            10      0.20%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            13      0.26%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             3      0.06%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             4      0.08%     98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.04%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.02%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.04%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             5      0.10%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             5      0.10%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            12      0.24%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            16      0.32%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             4      0.08%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383            10      0.20%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             2      0.04%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.02%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             4      0.08%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.04%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.04%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.04%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559            10      0.20%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             3      0.06%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             1      0.02%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             2      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719             2      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::816-831             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::928-943             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4988                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2137457500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9763982500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2033740000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5254.99                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5361                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5361                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.453087                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.909523                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.339442                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4763     88.85%     88.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             210      3.92%     92.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              83      1.55%     94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              15      0.28%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               3      0.06%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               2      0.04%     94.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               8      0.15%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               9      0.17%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               7      0.13%     95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              35      0.65%     95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            171      3.19%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             7      0.13%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             4      0.07%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             3      0.06%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             3      0.06%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             3      0.06%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             3      0.06%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.07%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             2      0.04%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.07%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             6      0.11%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231            10      0.19%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5361                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2204423500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9828436000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2033070000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5421.42                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24004.99                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24171.42                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.26                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.44                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.27                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.28                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.93                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364433                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110956                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.41                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3450647.54                       # Average gap between requests
-system.physmem.pageHitRate                      87.54                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  253449000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  138290625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1581504600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                432429840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            66287824245                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1119418910250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1316300550720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.688732                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1862013796212                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     65535860000                       # Time in different power states
+system.physmem.avgWrQLen                        24.74                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363741                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96228                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.46                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.93                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3723164.56                       # Average gap between requests
+system.physmem.pageHitRate                      87.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  249797520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  136298250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1579858800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                381555360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           128187633600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            65826808245                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1119818638500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1316180590275                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.630269                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1862676833500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     65535600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35060565038                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     34390001500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  257856480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  140695500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1591129800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                450625680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            66523575105                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1119212111250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1316364135975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.721130                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1861673236216                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     65535860000                       # Time in different power states
+system.physmem_1.actEnergy                  256843440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  140142750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1591730400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                398448720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           128187633600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            66351904785                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1119358027500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1316284731195                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.683332                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1861912025250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     65535600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     35401125034                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     35154809750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7492205                       # DTB read hits
+system.cpu0.dtb.read_hits                     7500026                       # DTB read hits
 system.cpu0.dtb.read_misses                      7443                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5067323                       # DTB write hits
+system.cpu0.dtb.write_hits                    5074087                       # DTB write hits
 system.cpu0.dtb.write_misses                      813                       # DTB write misses
 system.cpu0.dtb.write_acv                         134                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12559528                       # DTB hits
+system.cpu0.dtb.data_hits                    12574113                       # DTB hits
 system.cpu0.dtb.data_misses                      8256                       # DTB misses
 system.cpu0.dtb.data_acv                          344                       # DTB access violations
 system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3501951                       # ITB hits
+system.cpu0.itb.fetch_hits                    3504450                       # ITB hits
 system.cpu0.itb.fetch_misses                     3871                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3505822                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3508321                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -354,91 +345,91 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3923838766                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3923838721                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   47743384                       # Number of instructions committed
-system.cpu0.committedOps                     47743384                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44279734                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                210698                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1202353                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5609016                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44279734                       # number of integer instructions
-system.cpu0.num_fp_insts                       210698                       # number of float instructions
-system.cpu0.num_int_register_reads           60867436                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          32999466                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              102334                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             104190                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12599731                       # number of memory refs
-system.cpu0.num_load_insts                    7519361                       # Number of load instructions
-system.cpu0.num_store_insts                   5080370                       # Number of store instructions
-system.cpu0.num_idle_cycles              3698952400.393103                       # Number of idle cycles
-system.cpu0.num_busy_cycles              224886365.606898                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057313                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942687                       # Percentage of idle cycles
-system.cpu0.Branches                          7198745                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2727567      5.71%      5.71% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 31426598     65.81%     71.52% # Class of executed instruction
-system.cpu0.op_class::IntMult                   52886      0.11%     71.63% # Class of executed instruction
+system.cpu0.committedInsts                   47783493                       # Number of instructions committed
+system.cpu0.committedOps                     47783493                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             44315744                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                211234                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1203861                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5612503                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    44315744                       # number of integer instructions
+system.cpu0.num_fp_insts                       211234                       # number of float instructions
+system.cpu0.num_int_register_reads           60912860                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          33024751                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              102598                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             104462                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     12614351                       # number of memory refs
+system.cpu0.num_load_insts                    7527207                       # Number of load instructions
+system.cpu0.num_store_insts                   5087144                       # Number of store instructions
+system.cpu0.num_idle_cycles              3699336863.028799                       # Number of idle cycles
+system.cpu0.num_busy_cycles              224501857.971201                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.057215                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.942785                       # Percentage of idle cycles
+system.cpu0.Branches                          7204257                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2730537      5.71%      5.71% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 31447784     65.80%     71.51% # Class of executed instruction
+system.cpu0.op_class::IntMult                   52772      0.11%     71.63% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     71.63% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  25715      0.05%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1656      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7694830     16.11%     87.81% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5086464     10.65%     98.46% # Class of executed instruction
-system.cpu0.op_class::IprAccess                736268      1.54%    100.00% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  25731      0.05%     71.68% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1656      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.68% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7703007     16.12%     87.80% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5093240     10.66%     98.46% # Class of executed instruction
+system.cpu0.op_class::IprAccess                737366      1.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  47751984                       # Class of executed instruction
+system.cpu0.op_class::total                  47792093                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6802                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    164994                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   56858     40.19%     40.19% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.28% # number of times we switched to this ipl
+system.cpu0.kern.inst.hwrei                    165261                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   56971     40.19%     40.19% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.29% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1973      1.39%     41.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    421      0.30%     41.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  82092     58.03%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              141475                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56322     49.08%     49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::30                    419      0.30%     41.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  82246     58.03%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              141740                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    56429     49.08%     49.08% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1973      1.72%     50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     421      0.37%     51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   55901     48.72%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               114748                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1900658476000     96.88%     96.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               90840500      0.00%     96.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              754578500      0.04%     96.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              304090000      0.02%     96.94% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            60111368000      3.06%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1961919353000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.990573                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::30                     419      0.36%     51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   56010     48.72%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               114962                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1900835958000     96.89%     96.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               91198500      0.00%     96.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              757506500      0.04%     96.93% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              303704500      0.02%     96.95% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            59930963000      3.05%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1961919330500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.990486                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.680956                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811083                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.681006                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811077                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
@@ -470,124 +461,124 @@ system.cpu0.kern.syscall::144                       2      0.90%     99.10% # nu
 system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  503      0.34%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  500      0.33%      0.33% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.33% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3067      2.05%      2.39% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3072      2.05%      2.38% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      51      0.03%      2.42% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               134616     89.86%     92.28% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6699      4.47%     96.75% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.75% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               134879     89.87%     92.29% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6699      4.46%     96.76% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.76% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.76% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.01%     96.76% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.76% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4333      2.89%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.77% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4337      2.89%     99.66% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 381      0.25%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                149812                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6888                       # number of protection mode switches
+system.cpu0.kern.callpal::total                150081                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6891                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
 system.cpu0.kern.mode_good::kernel               1282                      
 system.cpu0.kern.mode_good::user                 1282                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.186121                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.186040                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.313831                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1958151397500     99.82%     99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3535867500      0.18%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.313716                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1958152340000     99.82%     99.82% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3531530500      0.18%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3068                       # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements          1180939                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.262035                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11368359                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1181356                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.623144                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        112435250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.262035                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986840                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986840                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          417                       # Occupied blocks per task id
+system.cpu0.kern.swap_context                    3073                       # number of times the context was actually changed
+system.cpu0.dcache.tags.replacements          1181794                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.240594                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11382177                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1182212                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.627865                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        112405500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.240594                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986798                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986798                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          418                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          372                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           45                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.814453                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51471280                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51471280                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6411907                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6411907                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4659091                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4659091                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140391                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       140391                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       148074                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       148074                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11070998                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11070998                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11070998                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11070998                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       938638                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       938638                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       251661                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       251661                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13662                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13662                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5430                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5430                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1190299                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1190299                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1190299                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1190299                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  29060390999                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  29060390999                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10906402435                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10906402435                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150333500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    150333500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     48525392                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     48525392                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  39966793434                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  39966793434                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  39966793434                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  39966793434                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7350545                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7350545                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4910752                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4910752                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154053                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       154053                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153504                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       153504                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12261297                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12261297                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12261297                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12261297                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127696                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127696                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051247                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051247                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088684                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088684                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035374                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035374                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097078                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.097078                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097078                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.097078                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8936.536280                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8936.536280                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101                       # average overall miss latency
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.816406                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         51530574                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51530574                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6418852                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6418852                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4665452                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4665452                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140662                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       140662                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       148383                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       148383                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11084304                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11084304                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11084304                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11084304                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       939259                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       939259                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       251797                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       251797                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13671                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13671                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5399                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         5399                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1191056                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1191056                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1191056                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1191056                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  28901225000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  28901225000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10875412500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  10875412500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150368000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    150368000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     47710000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     47710000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  39776637500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  39776637500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  39776637500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  39776637500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7358111                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7358111                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4917249                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4917249                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154333                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       154333                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153782                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       153782                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12275360                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12275360                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12275360                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12275360                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127649                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.127649                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051207                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051207                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088581                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088581                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035108                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035108                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097028                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.097028                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097028                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097028                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8836.821634                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8836.821634                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -596,126 +587,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       679102                       # number of writebacks
-system.cpu0.dcache.writebacks::total           679102                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       938638                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       938638                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251661                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       251661                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13662                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13662                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5430                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5430                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1190299                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1190299                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1190299                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1190299                       # number of overall MSHR misses
+system.cpu0.dcache.writebacks::writebacks       679941                       # number of writebacks
+system.cpu0.dcache.writebacks::total           679941                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       939259                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       939259                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251797                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       251797                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13671                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13671                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5399                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         5399                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1191056                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1191056                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1191056                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1191056                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7110                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10834                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10834                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17944                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17944                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27526583001                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27526583001                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10476952065                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10476952065                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    129828500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    129828500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     40378608                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     40378608                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38003535066                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  38003535066                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38003535066                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  38003535066                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1474416000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1474416000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293892500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293892500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3768308500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3768308500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127696                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127696                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051247                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051247                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088684                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088684                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035374                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035374                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097078                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.097078                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097078                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.097078                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9502.891231                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9502.891231                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7436.207735                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7436.207735                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432                       # average overall mshr uncacheable latency
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10829                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10829                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17939                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17939                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27961966000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27961966000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10623615500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10623615500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    136697000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136697000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     42311000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     42311000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38585581500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  38585581500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38585581500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  38585581500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1492228000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1492228000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2319869500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2319869500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3812097500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3812097500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127649                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127649                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051207                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051207                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088581                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088581                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035108                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035108                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097028                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.097028                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097028                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.097028                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9999.049082                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9999.049082                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7836.821634                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7836.821634                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           698758                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.155937                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47052596                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           699270                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.288166                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      42435665250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.155937                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992492                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992492                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           700401                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.179347                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           47091062                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           700913                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.185317                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      42246954500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.179347                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992538                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992538                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          356                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3          156                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          355                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3          157                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48451372                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48451372                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47052596                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47052596                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47052596                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47052596                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47052596                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47052596                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       699388                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       699388                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       699388                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        699388                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       699388                       # number of overall misses
-system.cpu0.icache.overall_misses::total       699388                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10012837997                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10012837997                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10012837997                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10012837997                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10012837997                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10012837997                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     47751984                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47751984                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     47751984                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47751984                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     47751984                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47751984                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014646                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014646                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014646                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014646                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014646                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014646                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14316.571055                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14316.571055                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         48493124                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48493124                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     47091062                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       47091062                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     47091062                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        47091062                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     47091062                       # number of overall hits
+system.cpu0.icache.overall_hits::total       47091062                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       701031                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       701031                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       701031                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        701031                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       701031                       # number of overall misses
+system.cpu0.icache.overall_misses::total       701031                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10017639000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10017639000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10017639000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10017639000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10017639000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10017639000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     47792093                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     47792093                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     47792093                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     47792093                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     47792093                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     47792093                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014668                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014668                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014668                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014668                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014668                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014668                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14289.865926                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14289.865926                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -724,51 +715,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       699388                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       699388                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       699388                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       699388                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       699388                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       699388                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8958710003                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8958710003                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8958710003                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8958710003                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8958710003                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8958710003                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014646                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014646                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014646                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       701031                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       701031                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       701031                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       701031                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       701031                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       701031                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9316608000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9316608000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9316608000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9316608000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9316608000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9316608000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014668                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014668                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014668                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014668                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014668                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014668                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2419579                       # DTB read hits
+system.cpu1.dtb.read_hits                     2409623                       # DTB read hits
 system.cpu1.dtb.read_misses                      2992                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1757217                       # DTB write hits
+system.cpu1.dtb.write_hits                    1749165                       # DTB write hits
 system.cpu1.dtb.write_misses                      341                       # DTB write misses
 system.cpu1.dtb.write_acv                          29                       # DTB write access violations
 system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4176796                       # DTB hits
+system.cpu1.dtb.data_hits                     4158788                       # DTB hits
 system.cpu1.dtb.data_misses                      3333                       # DTB misses
 system.cpu1.dtb.data_acv                           29                       # DTB access violations
 system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1964101                       # ITB hits
+system.cpu1.itb.fetch_hits                    1960477                       # ITB hits
 system.cpu1.itb.fetch_misses                     1216                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1965317                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1961693                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -781,87 +772,87 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3925225373                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3925216965                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   13155254                       # Number of instructions committed
-system.cpu1.committedOps                     13155254                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             12132982                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                173111                       # Number of float alu accesses
-system.cpu1.num_func_calls                     411301                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1304865                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    12132982                       # number of integer instructions
-system.cpu1.num_fp_insts                       173111                       # number of float instructions
-system.cpu1.num_int_register_reads           16703630                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8903954                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               90570                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              92446                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4200357                       # number of memory refs
-system.cpu1.num_load_insts                    2433886                       # Number of load instructions
-system.cpu1.num_store_insts                   1766471                       # Number of store instructions
-system.cpu1.num_idle_cycles              3876126901.998025                       # Number of idle cycles
-system.cpu1.num_busy_cycles              49098471.001975                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012508                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987492                       # Percentage of idle cycles
-system.cpu1.Branches                          1871330                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               704516      5.35%      5.35% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  7779367     59.12%     64.47% # Class of executed instruction
-system.cpu1.op_class::IntMult                   21509      0.16%     64.64% # Class of executed instruction
+system.cpu1.committedInsts                   13101094                       # Number of instructions committed
+system.cpu1.committedOps                     13101094                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             12083765                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                172106                       # Number of float alu accesses
+system.cpu1.num_func_calls                     409417                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1299945                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    12083765                       # number of integer instructions
+system.cpu1.num_fp_insts                       172106                       # number of float instructions
+system.cpu1.num_int_register_reads           16637487                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           8868500                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               90075                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              91936                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      4182249                       # number of memory refs
+system.cpu1.num_load_insts                    2423870                       # Number of load instructions
+system.cpu1.num_store_insts                   1758379                       # Number of store instructions
+system.cpu1.num_idle_cycles              3876316507.998025                       # Number of idle cycles
+system.cpu1.num_busy_cycles              48900457.001975                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.012458                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.987542                       # Percentage of idle cycles
+system.cpu1.Branches                          1864071                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               700818      5.35%      5.35% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  7749061     59.13%     64.48% # Class of executed instruction
+system.cpu1.op_class::IntMult                   21359      0.16%     64.64% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     64.64% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  14171      0.11%     64.75% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  14141      0.11%     64.75% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     64.75% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                      0      0.00%     64.75% # Class of executed instruction
 system.cpu1.op_class::FloatMult                     0      0.00%     64.75% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1986      0.02%     64.76% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2505658     19.04%     83.80% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1767460     13.43%     97.23% # Class of executed instruction
-system.cpu1.op_class::IprAccess                363949      2.77%    100.00% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1986      0.02%     64.77% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.77% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2495218     19.04%     83.81% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1759360     13.43%     97.23% # Class of executed instruction
+system.cpu1.op_class::IprAccess                362513      2.77%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  13158616                       # Class of executed instruction
+system.cpu1.op_class::total                  13104456                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     78523                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   26526     38.34%     38.34% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1967      2.84%     41.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    503      0.73%     41.91% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  40183     58.09%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               69179                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    25685     48.16%     48.16% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1967      3.69%     51.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     503      0.94%     52.79% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   25182     47.21%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                53337                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1909492808500     97.29%     97.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              698045000      0.04%     97.33% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              344048000      0.02%     97.35% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            52077063000      2.65%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1962611964500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.968295                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2738                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     78185                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   26382     38.32%     38.32% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1969      2.86%     41.18% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    500      0.73%     41.90% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  40003     58.10%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               68854                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    25547     48.14%     48.14% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1969      3.71%     51.85% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     500      0.94%     52.80% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   25048     47.20%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                53064                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1909718189500     97.31%     97.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              702775500      0.04%     97.34% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              343141500      0.02%     97.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            51843654000      2.64%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1962607760500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.968350                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.626683                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.771000                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.626153                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.770674                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
 system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
@@ -877,124 +868,124 @@ system.cpu1.kern.syscall::74                       10      9.62%     97.12% # nu
 system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  421      0.59%      0.59% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  419      0.59%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1997      2.79%      3.39% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1985      2.79%      3.38% # number of callpals executed
 system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                62934     88.05%     91.45% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2145      3.00%     94.46% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.46% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.46% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.47% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3774      5.28%     99.75% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                62619     88.03%     91.42% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2146      3.02%     94.44% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.44% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     94.45% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.45% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3766      5.29%     99.75% # number of callpals executed
 system.cpu1.kern.callpal::callsys                 136      0.19%     99.94% # number of callpals executed
 system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 71473                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2064                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2877                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                890                      
-system.cpu1.kern.mode_good::user                  463                      
-system.cpu1.kern.mode_good::idle                  427                      
-system.cpu1.kern.mode_switch_good::kernel     0.431202                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 71137                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2053                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                465                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2874                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                889                      
+system.cpu1.kern.mode_good::user                  465                      
+system.cpu1.kern.mode_good::idle                  424                      
+system.cpu1.kern.mode_switch_good::kernel     0.433025                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.148418                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.329386                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       17700699500      0.90%      0.90% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1706728000      0.09%      0.99% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1943204535000     99.01%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1998                       # number of times the context was actually changed
-system.cpu1.dcache.tags.replacements           166165                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          485.164459                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4008469                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           166677                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.049323                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      79256927000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.164459                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.947587                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.947587                       # Average percentage of cache occupancy
+system.cpu1.kern.mode_switch_good::idle      0.147530                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.329748                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       17552018500      0.89%      0.89% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1707542500      0.09%      0.98% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1943348197500     99.02%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1986                       # number of times the context was actually changed
+system.cpu1.dcache.tags.replacements           165381                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          485.645767                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3991235                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           165893                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.059092                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1050804836500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.645767                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.948527                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.948527                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           65                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16941101                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16941101                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2255044                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2255044                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1640007                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1640007                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48683                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        48683                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50718                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        50718                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3895051                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3895051                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3895051                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3895051                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       118164                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       118164                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        62534                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        62534                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8914                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8914                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5850                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5850                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       180698                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        180698                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       180698                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       180698                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1427964750                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1427964750                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1264688999                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1264688999                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     81193500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     81193500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     50099897                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     50099897                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2692653749                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2692653749                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2692653749                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2692653749                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2373208                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2373208                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1702541                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1702541                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57597                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        57597                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56568                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        56568                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4075749                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4075749                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4075749                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4075749                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049791                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049791                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036730                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.036730                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.154765                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.154765                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103415                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103415                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044335                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.044335                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044335                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044335                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9108.537133                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9108.537133                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8564.084957                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8564.084957                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164                       # average overall miss latency
+system.cpu1.dcache.tags.tag_accesses         16867850                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        16867850                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2245744                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2245744                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1632527                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1632527                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48591                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        48591                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50409                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        50409                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3878271                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3878271                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3878271                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3878271                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       117597                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       117597                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        62279                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        62279                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8857                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8857                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5813                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         5813                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       179876                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        179876                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       179876                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       179876                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1425631000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1425631000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1255840500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1255840500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80743500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     80743500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     49386500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     49386500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   2681471500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   2681471500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   2681471500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   2681471500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2363341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2363341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1694806                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1694806                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        57448                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56222                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        56222                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      4058147                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4058147                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4058147                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4058147                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049759                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.049759                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036747                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.036747                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.154174                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.154174                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103394                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103394                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044325                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.044325                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044325                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044325                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9116.348651                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9116.348651                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8495.871323                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8495.871323                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1003,128 +994,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       114146                       # number of writebacks
-system.cpu1.dcache.writebacks::total           114146                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118164                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       118164                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62534                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        62534                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8914                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8914                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5850                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5850                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       180698                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       180698                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       180698                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       180698                       # number of overall MSHR misses
+system.cpu1.dcache.writebacks::writebacks       113645                       # number of writebacks
+system.cpu1.dcache.writebacks::total           113645                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       117597                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       117597                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62279                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        62279                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8857                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8857                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5813                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         5813                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       179876                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       179876                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       179876                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       179876                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total           89                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3218                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3218                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3307                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3307                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1250643250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1250643250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1167915001                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1167915001                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67822500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     67822500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     41323103                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     41323103                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2418558251                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2418558251                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2418558251                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2418558251                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18866000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18866000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    716370000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    716370000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    735236000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    735236000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049791                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049791                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036730                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036730                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.154765                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.154765                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103415                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103415                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044335                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.044335                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044335                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.044335                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7608.537133                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7608.537133                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7063.778291                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7063.778291                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760                       # average overall mshr uncacheable latency
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3214                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3214                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3303                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3303                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1308034000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1308034000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1193561500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1193561500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     71886500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     71886500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     43573500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     43573500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2501595500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2501595500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2501595500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2501595500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     19086500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     19086500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    723672500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    723672500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742759000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742759000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049759                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049759                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036747                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036747                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.154174                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.154174                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103394                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103394                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044325                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.044325                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044325                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.044325                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8116.348651                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8116.348651                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7495.871323                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7495.871323                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           315648                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          445.931523                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12842415                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           316160                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            40.619987                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1961765828000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.931523                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870960                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.870960                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           313887                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          445.952187                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           12790016                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           314399                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.680842                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1961762459500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.952187                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871000                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.871000                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13474819                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13474819                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12842415                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12842415                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12842415                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12842415                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12842415                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12842415                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       316202                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       316202                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       316202                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        316202                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       316202                       # number of overall misses
-system.cpu1.icache.overall_misses::total       316202                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4145253739                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4145253739                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4145253739                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4145253739                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4145253739                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4145253739                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13158617                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13158617                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13158617                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13158617                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13158617                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13158617                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024030                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024030                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024030                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024030                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024030                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024030                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13109.511448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13109.511448                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         13418898                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        13418898                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     12790016                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       12790016                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     12790016                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        12790016                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     12790016                       # number of overall hits
+system.cpu1.icache.overall_hits::total       12790016                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       314441                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       314441                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       314441                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        314441                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       314441                       # number of overall misses
+system.cpu1.icache.overall_misses::total       314441                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4125234500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4125234500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4125234500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4125234500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4125234500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4125234500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13104457                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13104457                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13104457                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13104457                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13104457                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13104457                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023995                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.023995                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023995                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.023995                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023995                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.023995                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13119.264027                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13119.264027                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1133,30 +1124,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316202                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       316202                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       316202                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       316202                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       316202                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       316202                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3670775261                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3670775261                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3670775261                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3670775261                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3670775261                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3670775261                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024030                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024030                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024030                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       314441                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       314441                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       314441                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       314441                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       314441                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       314441                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3810793500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3810793500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3810793500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3810793500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3810793500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3810793500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023995                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023995                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023995                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.023995                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023995                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.023995                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1172,10 +1163,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55604                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              14052                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13892                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               55595                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              55595                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13874                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1187,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42502                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42484                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  125936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55496                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1203,11 +1193,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        81834                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        81762                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2743450                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13247000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2743378                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13229000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1229,23 +1219,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           242106937                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216079499                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28450000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28441000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42027500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41948000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41694                       # number of replacements
-system.iocache.tags.tagsinuse                0.567924                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.567878                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1756483552000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.567924                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035495                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035495                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1756483227000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.567878                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035492                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035492                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1253,49 +1243,49 @@ system.iocache.tags.tag_accesses               375534                       # Nu
 system.iocache.tags.data_accesses              375534                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
 system.iocache.overall_misses::total              174                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21822883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21822883                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8775454554                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8775454554                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21822883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21822883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21822883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21822883                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21744883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21744883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4908047616                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4908047616                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21744883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21744883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21744883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21744883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125418.867816                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125418.867816                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125418.867816                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         72753                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124970.591954                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124970.591954                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124970.591954                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 9972                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.295728                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1303,211 +1293,217 @@ system.iocache.writebacks::writebacks           41520                       # nu
 system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          174                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          174                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12615883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12615883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6614750554                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6614750554                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12615883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12615883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12615883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12615883                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13044883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13044883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2830447616                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2830447616                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13044883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13044883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13044883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13044883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72505.074713                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72505.074713                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74970.591954                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74970.591954                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   341367                       # number of replacements
-system.l2c.tags.tagsinuse                65207.739779                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2440642                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   406370                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.005960                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               9165125750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55183.814884                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4854.166492                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5017.337774                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      113.675354                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       38.745274                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.842038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074069                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.076558                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.001735                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000591                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994991                       # Average percentage of cache occupancy
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+system.l2c.tags.tagsinuse                65213.641245                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3683713                       # Total number of references to valid blocks.
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+system.l2c.tags.warmup_cycle               9107201000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   55129.108381                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4852.505635                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5029.950253                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.data       43.323918                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_task_id_blocks::1024        65003                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1104                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5014                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6093                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52607                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2         4999                       # Occupied blocks per task id
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-system.l2c.Writeback_hits::writebacks          793248                       # number of Writeback hits
-system.l2c.Writeback_hits::total               793248                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data             524                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 707                       # number of UpgradeReq hits
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-system.l2c.UpgradeReq_miss_latency::cpu1.data     13268077                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     14903532                       # number of UpgradeReq miss cycles
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-system.l2c.Writeback_accesses::total           793248                       # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.768142                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.868880                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1516,231 +1512,241 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674536000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2827586500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527926500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692156000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4220082500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.290186                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002148                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.138498                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941571                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.768142                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.868880                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.961207                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.973941                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967550                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.477466                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.122420                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.412904                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.041920                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.172964                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.041920                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.172964                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575                       # average overall mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10829                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3214                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        14043                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17939                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3303                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        21242                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     60572500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     35873500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     96446000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     18219500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     18324500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     36544000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7657576500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    472264500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8129841000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    908314000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     35012500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    943326500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  16943229500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     16607000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  16959836500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    908314000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  24600806000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     35012500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    488871500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  26033004000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    908314000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  24600806000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     35012500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    488871500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  26033004000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1403353000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17974000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1421327000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2195335000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    686710000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2882045000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3598688000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    704684000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4303372000                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.944337                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.764109                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.868304                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.953514                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.973828                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.963626                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.476737                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.122956                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.412685                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018543                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.001571                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013288                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.289979                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002168                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260015                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018543                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.328369                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.042012                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.172885                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018543                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.328369                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.042012                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.172885                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 63888.278357                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 63888.278357                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              292759                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292759                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14052                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14052                       # Transaction distribution
-system.membus.trans_dist::Writeback            120350                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            16060                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11220                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            6977                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122543                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121713                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42502                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       927849                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       970351                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124813                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124813                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1095164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81834                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31082624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31164458                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36482026                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            21558                       # Total snoops (count)
-system.membus.snoop_fanout::samples            618592                       # Request fanout histogram
+system.membus.trans_dist::ReadReq                7199                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292720                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14043                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14043                       # Transaction distribution
+system.membus.trans_dist::Writeback            120393                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261901                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            15996                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          11145                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            6943                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122456                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121630                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        285521                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1189359                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1231843                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1356669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81762                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31077568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31159330                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33817570                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            21449                       # Total snoops (count)
+system.membus.snoop_fanout::samples            880387                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  618592    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  880387    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              618592                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40208000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              880387                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40402000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1232118814                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1321574195                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2189522277                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2188968059                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           42501500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72063409                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2102341                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2102326                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14052                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14052                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           793248                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        41590                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           16264                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11280                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          27544                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           297931                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297931                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1398755                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3106837                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       632403                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       482171                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5620166                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44759488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118936680                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20236864                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17747522                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              201680554                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           98552                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3276706                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.012746                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.112175                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq               7199                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2102214                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14043                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14043                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           913999                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1505100                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           16204                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11212                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          27416                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           297872                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297872                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1015472                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1079558                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1960114                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3569990                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       818944                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       514014                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6863062                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44864640                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119041472                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20124160                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17694178                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              201724450                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          480853                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5227539                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.081241                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.273205                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3234942     98.73%     98.73% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41764      1.27%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                4802849     91.88%     91.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                 424690      8.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3276706                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2417745499                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total            5227539                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3202032998                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           238500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1051604997                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1051547997                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1901998326                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1814279465                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         474390739                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         471668486                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         282399146                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         279553995                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 8fa2e66de..5922aa080 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.922414                       # Number of seconds simulated
-sim_ticks                                1922413663500                       # Number of ticks simulated
-final_tick                               1922413663500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.922397                       # Number of seconds simulated
+sim_ticks                                1922397182500                       # Number of ticks simulated
+final_tick                               1922397182500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 912210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   912209                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31217732593                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318584                       # Number of bytes of host memory used
-host_seconds                                    61.58                       # Real time elapsed on the host
-sim_insts                                    56174594                       # Number of instructions simulated
-sim_ops                                      56174594                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1085217                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1085217                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            37124537063                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 372212                       # Number of bytes of host memory used
+host_seconds                                    51.78                       # Real time elapsed on the host
+sim_insts                                    56195121                       # Number of instructions simulated
+sim_ops                                      56195121                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            850624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24859584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            848768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24858048                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25711168                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7404352                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7404352                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388431                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25707776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       848768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          848768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7409088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7409088                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388407                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                401737                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115693                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115693                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               442477                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12931444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                401684                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115767                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115767                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               441515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12930756                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13374420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          442477                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             442477                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3851591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3851591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3851591                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              442477                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12931444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13372770                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          441515                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             441515                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3854088                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3854088                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3854088                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              441515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12930756                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17226012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        401737                       # Number of read requests accepted
-system.physmem.writeReqs                       157245                       # Number of write requests accepted
-system.physmem.readBursts                      401737                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     157245                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25705152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6016                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8387264                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25711168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10063680                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       94                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   26167                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25230                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25660                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25603                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25523                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24970                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24976                       # Per bank write bursts
+system.physmem.bw_total::total               17226858                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        401684                       # Number of read requests accepted
+system.physmem.writeReqs                       115767                       # Number of write requests accepted
+system.physmem.readBursts                      401684                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115767                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25700352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7424                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7407168                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25707776                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7409088                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      116                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          41682                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25233                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25641                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25574                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25503                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               24973                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24969                       # Per bank write bursts
 system.physmem.perBankRdBursts::6               24206                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24492                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25173                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24777                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25267                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24875                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24505                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25378                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25651                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25357                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8677                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8490                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8972                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8549                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8030                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7962                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7256                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7133                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8241                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7447                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7887                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7738                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8187                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8962                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8876                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8644                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24501                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25169                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24770                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25259                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24898                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24500                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25360                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25653                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25359                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7624                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7642                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7864                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7542                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7123                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6988                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6319                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6328                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7314                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6525                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7109                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6927                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7069                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7867                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7675                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          46                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1922401791500                       # Total gap between requests
+system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1922385313500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  401737                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  401684                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 157245                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    401629                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115767                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    401554                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
@@ -148,189 +148,195 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       50                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      526.491275                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.634857                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.364161                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14682     22.67%     22.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11626     17.95%     40.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5040      7.78%     48.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3263      5.04%     53.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2595      4.01%     57.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1540      2.38%     59.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1251      1.93%     61.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1707      2.64%     64.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23050     35.60%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64754                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4707                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        85.326110                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3076.141166                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           4704     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1797                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9305                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                     6596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6732                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64336                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      514.603333                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     307.690032                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.700723                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15764     24.50%     24.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11265     17.51%     42.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5118      7.96%     49.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3016      4.69%     54.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2317      3.60%     58.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1789      2.78%     61.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1464      2.28%     63.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1374      2.14%     65.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22229     34.55%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64336                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5099                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        78.750735                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2955.508201                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5096     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4707                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4707                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.841725                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.684188                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       62.214453                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4459     94.73%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              47      1.00%     95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              10      0.21%     95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               2      0.04%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              12      0.25%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111              3      0.06%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143             7      0.15%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            17      0.36%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            21      0.45%     97.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            12      0.25%     97.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            17      0.36%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             2      0.04%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             5      0.11%     98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             3      0.06%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             1      0.02%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.04%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.08%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335            11      0.23%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            21      0.45%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             6      0.13%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             6      0.13%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             6      0.13%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             8      0.17%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.04%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             2      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             5      0.11%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.04%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             3      0.06%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             3      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::800-815             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::832-847             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4707                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2057087750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9587894000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2008215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5121.68                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5099                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5099                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.697980                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.062005                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.025558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4477     87.80%     87.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              19      0.37%     88.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             190      3.73%     91.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              14      0.27%     92.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              27      0.53%     92.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              53      1.04%     93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.27%     94.02% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::48-51               6      0.12%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.06%     94.25% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::60-63               3      0.06%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               8      0.16%     94.53% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::96-99              18      0.35%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           148      2.90%     98.88% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::164-167             5      0.10%     99.41% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             4      0.08%     99.63% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::196-199             3      0.06%     99.80% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::212-215             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             5      0.10%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5099                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2147063750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9676463750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2007840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5346.70                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23871.68                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24096.70                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.37                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.36                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.85                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.37                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.23                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.85                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.61                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     360176                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    107764                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3439112.16                       # Average gap between requests
-system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  240309720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131121375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1565148000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                421647120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           125562446880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            64744742475                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1096652245500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1289317661070                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.677845                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1824141880650                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     64193480000                       # Time in different power states
+system.physmem.avgWrQLen                        23.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     359411                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93558                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.50                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3715106.00                       # Average gap between requests
+system.physmem.pageHitRate                      87.56                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  236030760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  128786625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1564680000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                372146400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           125561429760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            64059295815                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1097244171000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1289166540360                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.604667                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1825128497250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     64192960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34074451850                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     33072782750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  249230520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  135988875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1567667400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                427563360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           125562446880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            65411599725                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1096067283000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1289421779760                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.732006                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1823167298902                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     64193480000                       # Time in different power states
+system.physmem_1.actEnergy                  250349400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136599375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1567550400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                377829360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           125561429760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            65774789190                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1095739352250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1289407899735                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.730219                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1822618194250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     64192960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     35049033598                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     35583085750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9063642                       # DTB read hits
-system.cpu.dtb.read_misses                      10324                       # DTB read misses
+system.cpu.dtb.read_hits                      9066440                       # DTB read hits
+system.cpu.dtb.read_misses                      10312                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
-system.cpu.dtb.write_hits                     6355525                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
+system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
+system.cpu.dtb.write_hits                     6357400                       # DTB write hits
+system.cpu.dtb.write_misses                      1140                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     15419167                       # DTB hits
-system.cpu.dtb.data_misses                      11466                       # DTB misses
+system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
+system.cpu.dtb.data_hits                     15423840                       # DTB hits
+system.cpu.dtb.data_misses                      11452                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974414                       # ITB hits
-system.cpu.itb.fetch_misses                      5010                       # ITB misses
+system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
+system.cpu.itb.fetch_hits                     4973902                       # ITB hits
+system.cpu.itb.fetch_misses                      4997                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979424                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4978899                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -343,34 +349,34 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3844827327                       # number of cpu cycles simulated
+system.cpu.numCycles                       3844794365                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56174594                       # Number of instructions committed
-system.cpu.committedOps                      56174594                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52047018                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483106                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6467546                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52047018                       # number of integer instructions
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            71310653                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38515122                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15471782                       # number of memory refs
-system.cpu.num_load_insts                     9100493                       # Number of load instructions
-system.cpu.num_store_insts                    6371289                       # Number of store instructions
-system.cpu.num_idle_cycles               3587399919.998134                       # Number of idle cycles
-system.cpu.num_busy_cycles               257427407.001866                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.066954                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.933046                       # Percentage of idle cycles
-system.cpu.Branches                           8421188                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3200330      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36225212     64.47%     70.17% # Class of executed instruction
-system.cpu.op_class::IntMult                    61016      0.11%     70.28% # Class of executed instruction
+system.cpu.committedInsts                    56195121                       # Number of instructions committed
+system.cpu.committedOps                      56195121                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52066883                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324259                       # Number of float alu accesses
+system.cpu.num_func_calls                     1483708                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6469750                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52066883                       # number of integer instructions
+system.cpu.num_fp_insts                        324259                       # number of float instructions
+system.cpu.num_int_register_reads            71341331                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38530727                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163543                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166418                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15476411                       # number of memory refs
+system.cpu.num_load_insts                     9103258                       # Number of load instructions
+system.cpu.num_store_insts                    6373153                       # Number of store instructions
+system.cpu.num_idle_cycles               3587818415.000134                       # Number of idle cycles
+system.cpu.num_busy_cycles               256975949.999866                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.066837                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.933163                       # Percentage of idle cycles
+system.cpu.Branches                           8423975                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3201032      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36240615     64.48%     70.17% # Class of executed instruction
+system.cpu.op_class::IntMult                    61007      0.11%     70.28% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     70.28% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   38087      0.07%     70.35% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   38081      0.07%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     70.35% # Class of executed instruction
@@ -396,34 +402,34 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.35% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::MemRead                  9327578     16.60%     86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6377363     11.35%     98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess                 953205      1.70%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                  9330336     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6379227     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess                 953006      1.70%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56186427                       # Class of executed instruction
+system.cpu.op_class::total                   56206940                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211986                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74892     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211964                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74896     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106213     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183168                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73525     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  106217     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183176                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73529     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73525     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149113                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857939859000     96.65%     96.65% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91692000      0.00%     96.65% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               740049500      0.04%     96.69% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             63641329000      3.31%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1922412929500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981747                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73529     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149121                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1858096797000     96.66%     96.66% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                92317000      0.00%     96.66% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               743733500      0.04%     96.70% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             63463601000      3.30%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1922396448500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692241                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814078                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692253                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814086                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -459,10 +465,10 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4174      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175947     91.21%     93.41% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175955     91.22%     93.41% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
@@ -471,28 +477,28 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.97% # nu
 system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192894                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5905                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192899                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2093                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1910                      
-system.cpu.kern.mode_good::user                  1740                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.323455                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::user                  1741                      
+system.cpu.kern.mode_good::idle                   169                      
+system.cpu.kern.mode_switch_good::kernel     0.323509                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392197                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46428613000      2.42%      2.42% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5237727500      0.27%      2.69% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1870746587000     97.31%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.cpu.dcache.tags.replacements           1391374                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.978196                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14046325                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1391886                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.091577                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         112435250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.978196                       # Average occupied blocks per requestor
+system.cpu.kern.mode_switch_good::idle       0.080745                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392278                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46413360000      2.41%      2.41% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5233781000      0.27%      2.69% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1870749305500     97.31%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
+system.cpu.dcache.tags.replacements           1390740                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.978175                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14051600                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1391252                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.099968                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         112405500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.978175                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999957                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999957                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -500,72 +506,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          187
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63144735                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63144735                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7812525                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7812525                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5851580                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5851580                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182969                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182969                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199234                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199234                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13664105                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13664105                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13664105                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13664105                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1070248                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1070248                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304369                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304369                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17287                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17287                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374617                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374617                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374617                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374617                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  30897353500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  30897353500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11699394130                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11699394130                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    229714500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    229714500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  42596747630                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  42596747630                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  42596747630                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  42596747630                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8882773                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8882773                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6155949                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6155949                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199234                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199234                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15038722                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15038722                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15038722                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15038722                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120486                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120486                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049443                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049443                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086325                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086325                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091405                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091405                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30988.084412                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30988.084412                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63162665                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63162665                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7816092                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7816092                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853262                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853262                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183004                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183004                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199225                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199225                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13669354                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13669354                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13669354                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13669354                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069466                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069466                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304560                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304560                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17244                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17244                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1374026                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1374026                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1374026                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1374026                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  30729736500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  30729736500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11677039000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11677039000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228891000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    228891000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  42406775500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  42406775500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  42406775500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  42406775500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8885558                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8885558                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157822                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157822                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15043380                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15043380                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15043380                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15043380                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120360                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120360                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049459                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049459                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086113                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086113                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091338                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091338                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091338                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091338                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30863.153608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30863.153608                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -574,120 +580,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835634                       # number of writebacks
-system.cpu.dcache.writebacks::total            835634                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1070248                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1070248                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304369                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304369                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17287                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17287                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374617                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374617                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374617                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374617                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       835293                       # number of writebacks
+system.cpu.dcache.writebacks::total            835293                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069466                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069466                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304560                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304560                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17244                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17244                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1374026                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1374026                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1374026                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1374026                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9650                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9650                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16580                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16580                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29166094500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29166094500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11190140370                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11190140370                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    203771000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    203771000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  40356234870                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  40356234870                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40356234870                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  40356234870                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1432759000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1432759000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2025445000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2025445000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3458204000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3458204000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120486                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120486                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049443                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049443                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086325                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086325                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091405                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091405                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091405                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091405                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29660270500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29660270500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11372479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11372479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    211647000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    211647000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41032749500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41032749500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41032749500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41032749500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450110500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450110500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2049565500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2049565500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3499676000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3499676000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120360                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120360                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049459                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049459                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086113                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086113                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091338                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091338                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            928205                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.070911                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55257552                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            928716                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.498869                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42087191250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.070911                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992326                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992326                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            928306                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.094938                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55277964                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            928817                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.514376                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       41861098500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.094938                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992373                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.992373                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57115304                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57115304                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     55257552                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55257552                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55257552                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55257552                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55257552                       # number of overall hits
-system.cpu.icache.overall_hits::total        55257552                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       928876                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928876                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       928876                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         928876                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       928876                       # number of overall misses
-system.cpu.icache.overall_misses::total        928876                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13004894000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13004894000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13004894000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13004894000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13004894000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13004894000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56186428                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56186428                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56186428                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::cpu.inst     56186428                       # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016532                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016532                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016532                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total     0.016532                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14000.678239                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14000.678239                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57135918                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst     55277964                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13003041000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst     56206941                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016528                       # miss rate for ReadReq accesses
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+system.cpu.icache.overall_miss_rate::cpu.inst     0.016528                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016528                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13997.161394                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13997.161394                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13997.161394                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13997.161394                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13997.161394                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13997.161394                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -696,135 +702,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928876                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       928876                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       928876                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       928876                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       928876                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       928876                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11606411000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11606411000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11606411000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11606411000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11606411000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11606411000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016532                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016532                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928977                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total  12074064000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12074064000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12074064000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total  12074064000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016528                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016528                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016528                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12997.161394                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12997.161394                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12997.161394                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12997.161394                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12997.161394                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12997.161394                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           336253                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65287.674931                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2448546                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401415                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.099787                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       7245222750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4753.205077                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5018.688389                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.847104                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072528                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.076579                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996211                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.tagsinuse        65288.878091                       # Cycle average of tags in use
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+system.cpu.l2cache.tags.warmup_cycle       7193890000                       # Cycle when the warmup percentage was hit.
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1009                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4937                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3234                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55805                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1014                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4931                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55807                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         25957144                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        25957144                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       915565                       # number of ReadReq hits
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80123.812396                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80123.812396                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73640.401032                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73854.257708                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -833,114 +845,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74181                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74181                       # number of writebacks
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+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          280                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          280                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9650                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9650                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16580                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16580                       # number of overall MSHR uncacheable misses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       364500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       364500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7775812500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7775812500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    929982000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    929982000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16967384500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16967384500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    929982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  24743197000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  25673179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    929982000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  24743197000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  25673179000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1363485500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1363485500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1938590500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1938590500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3302076000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3302076000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383953                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383953                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014309                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279348                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173269                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014309                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279348                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173269                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383601                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383601                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014276                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014276                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250273                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250273                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014276                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279458                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173286                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014276                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279458                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173286                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2023514                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2023497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2022774                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       835634                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41588                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       951075                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1744381                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304352                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857732                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3652758                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5510490                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59446784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142615892                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          202062676                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       41937                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3214755                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.012990                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.113233                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       304543                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304543                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       928977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1086883                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2786015                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4205333                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6991348                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59453248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142553556                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          202006804                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      419801                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5075497                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.082676                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.275393                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3172994     98.70%     98.70% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41761      1.30%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4655873     91.73%     91.73% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             419624      8.27%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3214755                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2426956000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5075497                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3168054500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1395898500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1393465500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2188894130                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2098643000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -957,8 +980,7 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9650                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51202                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5156                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1013,23 +1035,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           242042219                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216066756                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42024000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.342966                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.342844                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1756462668000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.342966                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.083935                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.083935                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1756461860000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.342844                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.083928                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.083928                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1037,49 +1059,49 @@ system.iocache.tags.tag_accesses               375525                       # Nu
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
 system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21714383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21714383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8755465836                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8755465836                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21714383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21714383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21714383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21714383                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21632883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21632883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907244873                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4907244873                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21632883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21632883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21632883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21632883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125516.664740                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125516.664740                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125516.664740                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         72960                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125045.566474                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125045.566474                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125045.566474                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 9989                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.304034                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1087,79 +1109,81 @@ system.iocache.writebacks::writebacks           41512                       # nu
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12562383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12562383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6594761836                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6594761836                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12562383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12562383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12562383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12562383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12982883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12982883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829644873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2829644873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12982883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12982883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12982883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12982883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72614.930636                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72614.930636                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75045.566474                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75045.566474                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              292358                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292358                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292339                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
-system.membus.trans_dist::Writeback            115693                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::Writeback            115767                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261512                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116738                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116738                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116704                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116704                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        285409                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911318                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1036122                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139625                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172785                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1297602                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30457792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30502356                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                35819412                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30459136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30503700                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33161428                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              431                       # Total snoops (count)
-system.membus.snoop_fanout::samples            576169                       # Request fanout histogram
+system.membus.snoop_fanout::samples            837831                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  576169    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  837831    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              576169                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30034000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              837831                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30056000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1195840311                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1285352189                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2144408870                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2143948368                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           42495000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72076390                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index a436908c3..52cc263b3 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1057273                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1287060                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20615299474                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 562992                       # Number of bytes of host memory used
-host_seconds                                   135.04                       # Real time elapsed on the host
+host_inst_rate                                1269332                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1545209                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24750158617                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625572                       # Number of bytes of host memory used
+host_seconds                                   112.48                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1210788                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10328292                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1207012                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10324836                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11540616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8837568                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11533384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1207012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8840896                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8855092                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858420                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27372                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             161899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             161845                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189295                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138087                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                189182                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138139                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142468                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142520                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               434930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3710052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               433574                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3708811                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4145534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3174565                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          433574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175761                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3180860                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3174565                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3182056                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175761                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              434930                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3716347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              433574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3715106                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7326394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7324992                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -348,8 +348,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       682059                       # number of writebacks
-system.cpu.dcache.writebacks::total            682059                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682040                       # number of writebacks
+system.cpu.dcache.writebacks::total            682040                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1699214                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
@@ -401,22 +401,22 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           110026                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65155.309107                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2727887                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           175307                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            15.560628                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           109913                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65155.309141                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4564556                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           175194                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.054294                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.654943                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.316179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.708883                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.628332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.744080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109777                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.139903                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.110163                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
@@ -424,67 +424,73 @@ system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10699                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26204344                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26204344                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         40896687                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40896687                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1681357                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       505474                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2198053                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       682059                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       682059                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::total          11222                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       682040                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       682040                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151058                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151058                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151146                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151146                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681416                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1681416                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505440                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       505440                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681357                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2349111                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681416                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656586                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2349224                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681357                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656532                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2349111                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681416                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656586                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2349224                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        18357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        15534                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        33900                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         2728                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         2728                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       147864                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       147864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       147776                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       147776                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        18298                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        18298                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        15568                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        15568                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        18357                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       163398                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        181764                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        18298                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       163344                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        181651                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        18357                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       181764                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        18298                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       163344                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       181651                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699714                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       521008                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2231953                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       682059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       682059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11231                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       682040                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       682040                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699714                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1699714                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521008                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
@@ -497,25 +503,27 @@ system.cpu.l2cache.overall_accesses::cpu.data       819930
 system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010800                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029815                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015188                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000801                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494363                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494363                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010765                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029881                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029881                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010800                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071819                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010765                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199217                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071774                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010800                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071819                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010765                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199217                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071774                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -524,46 +532,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101897                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101897                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101949                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101949                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          67802                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       682059                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       682040                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1836576                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417508                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444657                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699732                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116722                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2582000                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37000                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5917595                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7754152                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108818936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96310049                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308833                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205239845                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205238629                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       36631                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3336291                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.019237                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.137356                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      5172848                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.012407                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.110693                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3272112     98.08%     98.08% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              64179      1.92%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5108669     98.76%     98.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              64179      1.24%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3336291                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5172848                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22778                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -630,24 +640,24 @@ system.iocache.tags.tag_accesses               328176                       # Nu
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          240                       # number of overall misses
 system.iocache.overall_misses::total              240                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -663,46 +673,48 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74227                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
+system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::Writeback            138087                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::Writeback            138139                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8204                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            145997                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           145997                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34115                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105404                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       498791                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       606151                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 715269                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       506581                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       613941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723299                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18096316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18259289                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22909145                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092412                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586905                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            426678                       # Request fanout histogram
+system.membus.snoop_fanout::samples            434821                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  426678    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  434821    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              426678                       # Request fanout histogram
+system.membus.snoop_fanout::total              434821                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 8cc51b925..eec67c0c4 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,70 +4,66 @@ sim_seconds                                  2.802895                       # Nu
 sim_ticks                                2802894699500                       # Number of ticks simulated
 final_tick                               2802894699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 935329                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1139685                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17855077822                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 572752                       # Number of bytes of host memory used
-host_seconds                                   156.98                       # Real time elapsed on the host
+host_inst_rate                                1243628                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1515342                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23740372608                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632596                       # Number of bytes of host memory used
+host_seconds                                   118.06                       # Real time elapsed on the host
 sim_insts                                   146828240                       # Number of instructions simulated
 sim_ops                                     178908039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1118628                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          9439908                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           149524                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1084244                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1090916                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          9418084                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           146388                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1083988                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11793968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1118628                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       149524                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1268152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8394176                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11740912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1090916                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       146388                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1237304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8475264                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8411740                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8492828                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             25932                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            148018                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2491                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             25499                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            147677                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2442                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16958                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                193429                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131159                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                192600                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          132426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135550                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136817                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           160                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              399097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3367914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               53346                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              386830                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              389210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3360128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               52227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              386739                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4207781                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         399097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          53346                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             452444                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2994824                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4188852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         389210                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          52227                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             441438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3023754                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6252                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3001090                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2994824                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3030020                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3023754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             399097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3374166                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              53346                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             386844                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             389210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3366380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              52227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             386753                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7208872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7218873                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -309,32 +305,32 @@ system.cpu0.dcache.tags.tag_accesses         74113887                       # Nu
 system.cpu0.dcache.tags.data_accesses        74113887                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data     19108541                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       19108541                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15690414                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15690414                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15690436                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15690436                       # number of WriteReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346093                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       346093                       # number of SoftPFReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379629                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       379629                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363041                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       363041                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     34798955                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        34798955                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     35145048                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       35145048                       # number of overall hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363043                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       363043                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     34798977                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        34798977                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     35145070                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       35145070                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data       373103                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total       373103                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       295771                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       295771                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       295749                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       295749                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100321                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total       100321                       # number of SoftPFReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6742                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         6742                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18444                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        18444                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       668874                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        668874                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       769195                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       769195                       # number of overall misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18442                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        18442                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       668852                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        668852                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       769173                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       769173                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481644                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     19481644                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986185                       # number of WriteReq accesses(hits+misses)
@@ -351,18 +347,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data     35914243
 system.cpu0.dcache.overall_accesses::total     35914243                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019152                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.019152                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018502                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018502                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018500                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018500                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224726                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224726                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017450                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017450                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048348                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048348                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018859                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.018859                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021418                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.021418                       # miss rate for overall accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048343                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048343                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018858                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.018858                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021417                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.021417                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -371,8 +367,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       511485                       # number of writebacks
-system.cpu0.dcache.writebacks::total           511485                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       511204                       # number of writebacks
+system.cpu0.dcache.writebacks::total           511204                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          1109735                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.809992                       # Cycle average of tags in use
@@ -429,123 +425,131 @@ system.cpu0.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          252829                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16127.674334                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1809277                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          269026                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.725287                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements          252605                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16140.025703                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3093887                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          268799                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.510039                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      1764261500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  8127.481443                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.302152                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.089300                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4685.625756                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3313.175683                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.496062                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000079                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.202220                       # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16189                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5612                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7505                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2706                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.988098                       # Percentage of cache occupancy per task id
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-system.cpu0.l2cache.tags.data_accesses       39447877                       # Number of data accesses
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-system.cpu0.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
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-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26231                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26231                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18444                       # number of SCUpgradeReq misses
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-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       480166                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      1601598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       511485                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       511485                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26248                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        26248                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18444                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.090207                       # Average occupied blocks per requestor
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+system.cpu0.l2cache.tags.occ_percent::writebacks     0.494763                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7582                       # Occupied blocks per task id
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+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        44912                       # number of ReadCleanReq misses
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 system.cpu0.l2cache.demand_accesses::cpu0.inst      1110256                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027735                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999352                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999352                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.overall_accesses::total      1871449                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.028831                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.035869                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.030946                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999390                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999390                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.650883                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.650883                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027735                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.040437                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040526                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.405267                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.186611                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027735                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.040437                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040526                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.405267                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.186611                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.649640                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.649640                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040452                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040452                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.267416                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.267416                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.028831                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.035869                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040452                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404831                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.186361                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.028831                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.035869                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040452                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404831                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.186361                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -554,41 +558,44 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       193152                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          193152                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       192999                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          192999                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1651838                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq         61416                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadResp      1651838                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        28341                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        28341                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       511485                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        26248                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18444                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        44692                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       511204                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1292017                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        26226                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18442                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        44668                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExReq       269523                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExResp       269523                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2238556                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2220081                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1110256                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       480166                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3348291                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2402034                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28808                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4500273                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5791961                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     71092472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80905668                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80887684                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         152081412                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     327909                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      2731172                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.090112                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.286342                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total         152063428                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     327822                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4022806                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.061160                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.239623                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2485061     90.99%     90.99% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2            246111      9.01%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           3776773     93.88%     93.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2            246033      6.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       2731172                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total       4022806                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -804,32 +811,32 @@ system.cpu1.dcache.tags.tag_accesses         39751979                       # Nu
 system.cpu1.dcache.tags.data_accesses        39751979                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data     11858694                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total       11858694                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7397479                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7397479                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7397498                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7397498                       # number of WriteReq hits
 system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50099                       # number of SoftPFReq hits
 system.cpu1.dcache.SoftPFReq_hits::total        50099                       # number of SoftPFReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91447                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        91447                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72442                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        72442                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19256173                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19256173                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19306272                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19306272                       # number of overall hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72436                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        72436                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19256192                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19256192                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19306291                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19306291                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data       136630                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total       136630                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        92483                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        92483                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        92464                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        92464                       # number of WriteReq misses
 system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30719                       # number of SoftPFReq misses
 system.cpu1.dcache.SoftPFReq_misses::total        30719                       # number of SoftPFReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5318                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         5318                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22537                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        22537                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       229113                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        229113                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       259832                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       259832                       # number of overall misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22543                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        22543                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       229094                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        229094                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       259813                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       259813                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995324                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     11995324                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489962                       # number of WriteReq accesses(hits+misses)
@@ -846,18 +853,18 @@ system.cpu1.dcache.overall_accesses::cpu1.data     19566104
 system.cpu1.dcache.overall_accesses::total     19566104                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011390                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.011390                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012348                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.012348                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012345                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.012345                       # miss rate for WriteReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380101                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380101                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054958                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054958                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237284                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237284                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011758                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.011758                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013280                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.013280                       # miss rate for overall accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237347                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237347                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011757                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.011757                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -866,8 +873,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       120843                       # number of writebacks
-system.cpu1.dcache.writebacks::total           120843                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       120813                       # number of writebacks
+system.cpu1.dcache.writebacks::total           120813                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements           523373                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          499.711129                       # Cycle average of tags in use
@@ -923,121 +930,129 @@ system.cpu1.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           48543                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15314.912528                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            717091                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           63380                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           11.314153                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements           48465                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15315.522353                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1307502                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           63323                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           20.648137                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  8302.426392                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.123905                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.034953                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3306.071742                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3701.255535                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.506740                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000191                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000124                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.201787                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.225907                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.934748                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           29                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14808                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8309.782152                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.119682                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.019591                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3270.237857                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3730.363071                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.507189                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000190                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000123                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.199599                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.227683                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.934785                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14839                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          531                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9377                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4900                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001770                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903809                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        15213000                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       15213000                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3125                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1708                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       510060                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data        99394                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        614287                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       120843                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       120843                       # number of Writeback hits
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          554                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9338                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4947                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.905701                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        24723530                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       24723530                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3108                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1684                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total          4792                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       120813                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       120813                       # number of Writeback hits
 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            8                       # number of UpgradeReq hits
 system.cpu1.l2cache.UpgradeReq_hits::total            8                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19811                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        19811                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3125                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1708                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       510060                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       119205                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         634098                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3125                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1708                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       510060                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       119205                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        634098                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          344                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          267                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst        13825                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        73273                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        87709                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28859                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28859                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22537                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22537                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43805                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        43805                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          344                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          267                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        13825                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       117078                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       131514                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          344                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          267                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        13825                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       117078                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       131514                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3469                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1975                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       523885                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data       172667                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       701996                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       120843                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       120843                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28867                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        28867                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22537                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        22537                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19803                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        19803                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       510140                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       510140                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99386                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        99386                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3108                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1684                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       510140                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       119189                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         634121                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3108                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1684                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       510140                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       119189                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        634121                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          340                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          270                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          610                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28840                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        28840                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22543                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22543                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43813                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        43813                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13745                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        13745                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73281                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        73281                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          340                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          270                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        13745                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       117094                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       131449                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          340                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          270                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        13745                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       117094                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       131449                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3448                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1954                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total         5402                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       120813                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       120813                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28848                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        28848                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22543                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        22543                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63616                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::total        63616                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3469                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1975                       # number of demand (read+write) accesses
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       523885                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       523885                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       172667                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       172667                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3448                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1954                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.inst       523885                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.data       236283                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       765612                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3469                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1975                       # number of overall (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       765570                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3448                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1954                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.inst       523885                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.data       236283                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       765612                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.099164                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.135190                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.026389                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.424360                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.124942                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_accesses::total       765570                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.098608                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.138178                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.112921                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999723                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999723                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.688585                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.688585                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.099164                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.135190                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026389                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495499                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.171776                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.099164                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.135190                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026389                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495499                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.171776                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.688710                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.688710                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026237                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026237                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.424407                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.424407                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.098608                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.138178                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026237                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495567                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.171701                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.098608                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.138178                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026237                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495567                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.171701                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1046,46 +1061,48 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        32966                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           32966                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        32917                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           32917                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        709301                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq         12749                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadResp       709301                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         2505                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         2505                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       120843                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        28867                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22537                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        51404                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       120813                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict       594498                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        28848                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22543                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        51391                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExReq        63616                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExResp        63616                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1048124                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707677                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       523885                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       172667                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1571497                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       778746                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12078                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          1774495                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2368937                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33529348                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22875246                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22873326                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24156                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          56441982                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     568922                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1446930                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.351508                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.477442                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total          56440062                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     568500                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2040956                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.248991                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.432428                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            938322     64.85%     64.85% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2            508608     35.15%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1532777     75.10%     75.10% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2            508179     24.90%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1446930                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total       2040956                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30995                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30995                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59419                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              23195                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59419                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56582                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1152,24 +1169,24 @@ system.iocache.tags.tag_accesses               328284                       # Nu
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -1185,183 +1202,175 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   107655                       # number of replacements
-system.l2c.tags.tagsinuse                62149.484460                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     208536                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168097                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.240569                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   106825                       # number of replacements
+system.l2c.tags.tagsinuse                62089.721630                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     288805                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   167355                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.725703                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48591.950970                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.942995                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030795                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7375.890834                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3824.198641                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.861600                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1621.181926                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      731.426698                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.741454                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data       0.058353                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.024737                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.011161                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.948326                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        60436                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           70                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1845                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        13049                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        45441                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.922180                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  4909092                       # Number of tag accesses
-system.l2c.tags.data_accesses                 4909092                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker           79                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           78                       # number of ReadReq hits
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-system.l2c.Writeback_hits::writebacks          226118                       # number of Writeback hits
-system.l2c.Writeback_hits::total               226118                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             498                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              64                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 562                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            63                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            12                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                75                       # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::total                17117                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker            79                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            78                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               28077                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               90292                       # number of demand (read+write) hits
+system.l2c.tags.occ_blocks::writebacks   47734.864298                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.041981                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.data      726.922600                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        60523                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2         1889                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        13006                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        45532                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.923508                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5581048                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5581048                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          225916                       # number of Writeback hits
+system.l2c.Writeback_hits::total               225916                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             290                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              72                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 362                       # number of UpgradeReq hits
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-system.l2c.overall_hits::cpu0.itb.walker           78                       # number of overall hits
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-system.l2c.overall_hits::total                 144520                       # number of overall hits
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-system.l2c.UpgradeReq_misses::total             13279                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          754                       # number of SCUpgradeReq misses
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 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
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-system.l2c.overall_misses::cpu0.data           148086                       # number of overall misses
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-system.l2c.overall_misses::cpu1.data            16977                       # number of overall misses
-system.l2c.overall_misses::total               184317                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker           87                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total             159142                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       226118                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           226118                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        10504                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3337                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           13841                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          817                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2005                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       150778                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        18917                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           169695                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker           87                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           80                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           44994                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          238378                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           43                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           36                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           13825                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           31394                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              328837                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker           87                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           80                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          44994                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         238378                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           43                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           36                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          13825                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          31394                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             328837                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.025000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.375983                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.129304                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.023256                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.168246                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.092811                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.199438                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.952589                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.980821                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.959396                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.922889                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.989899                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.962594                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.907022                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.836232                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.899131                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.025000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.375983                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.621223                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.023256                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.168246                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.540772                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.560512                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.025000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.375983                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.621223                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.023256                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.168246                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.540772                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.560512                       # miss rate for overall accesses
+system.l2c.overall_misses::cpu0.inst            16484                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           147794                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2277                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            16974                       # number of overall misses
+system.l2c.overall_misses::total               183538                       # number of overall misses
+system.l2c.Writeback_accesses::writebacks       225916                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           225916                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        10274                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         3369                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           13643                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          818                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1186                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2004                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       150664                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        18923                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           169587                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          100                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           66                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        44909                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        87630                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           42                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           35                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        13741                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        12518                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       159041                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          100                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           66                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           44909                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          238294                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           42                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           35                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           13741                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           31441                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              328628                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          100                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           66                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          44909                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         238294                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           42                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           35                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          13741                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          31441                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             328628                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.971773                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.978629                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.973466                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.926650                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.993255                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.966068                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.906474                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.836865                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.898707                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.070000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.367053                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.128050                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.165708                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.090909                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.195729                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.070000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.367053                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.620217                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.165708                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.539868                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.558498                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.070000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.367053                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.620217                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.165708                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.539868                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.558498                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1370,49 +1379,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               94969                       # number of writebacks
-system.l2c.writebacks::total                    94969                       # number of writebacks
+system.l2c.writebacks::writebacks               96236                       # number of writebacks
+system.l2c.writebacks::total                    96236                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               75988                       # Transaction distribution
-system.membus.trans_dist::ReadResp              75988                       # Transaction distribution
+system.membus.trans_dist::ReadReq               43997                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75378                       # Transaction distribution
 system.membus.trans_dist::WriteReq              30846                       # Transaction distribution
 system.membus.trans_dist::WriteResp             30846                       # Transaction distribution
-system.membus.trans_dist::Writeback            131159                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::Writeback            132426                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15436                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            60361                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40906                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15595                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            196283                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           152192                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40917                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15653                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            196055                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           151973                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         31381                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107876                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       652086                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       773470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109142                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109142                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 882612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       666939                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       788323                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109394                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109394                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 897717                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162766                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17906316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18096098                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4650624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4650624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22746722                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17934348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18124130                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2332288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2332288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20456418                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            571767                       # Request fanout histogram
+system.membus.snoop_fanout::samples            587643                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  571767    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  587643    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              571767                       # Request fanout histogram
+system.membus.snoop_fanout::total              587643                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1444,33 +1455,35 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             305452                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            305452                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              44000                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            305308                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             30846                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            30846                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           226118                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           60537                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40981                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         101518                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           213786                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          213786                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1118722                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       410600                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1529322                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34707388                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10425906                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               45133294                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::Writeback           225916                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           84734                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           60287                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40985                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         101272                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           213669                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          213669                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       261308                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1184948                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       427892                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1612840                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34685820                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10417842                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45103662                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                           36713                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           914196                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.039900                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.195723                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples           998221                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.036541                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.187632                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 877720     96.01%     96.01% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36476      3.99%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 961745     96.35%     96.35% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36476      3.65%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             914196                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total             998221                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 383222d5f..19a0730a6 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1032026                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1256326                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20123025378                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560940                       # Number of bytes of host memory used
-host_seconds                                   138.34                       # Real time elapsed on the host
+host_inst_rate                                1280569                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1558887                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24969250003                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 621096                       # Number of bytes of host memory used
+host_seconds                                   111.49                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1210788                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10328292                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1207012                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10324836                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11540616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8837568                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11533384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1207012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8840896                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8855092                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858420                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27372                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             161899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             161845                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189295                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138087                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                189182                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138139                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142468                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142520                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               434930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3710052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               433574                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3708811                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4145534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3174565                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          433574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175761                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3180860                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3174565                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3182056                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175761                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              434930                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3716347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              433574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3715106                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7326394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7324992                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -348,8 +348,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       682059                       # number of writebacks
-system.cpu.dcache.writebacks::total            682059                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682040                       # number of writebacks
+system.cpu.dcache.writebacks::total            682040                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1699214                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
@@ -401,22 +401,22 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           110026                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65155.309107                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2727887                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           175307                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            15.560628                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           109913                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65155.309141                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4564556                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           175194                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.054294                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.654943                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.316179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.708883                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.628332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.744080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109777                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.139903                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.110163                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
@@ -424,67 +424,73 @@ system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10699                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26204344                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26204344                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         40896687                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40896687                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1681357                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       505474                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2198053                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       682059                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       682059                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::total          11222                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       682040                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       682040                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151058                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151058                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151146                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151146                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681416                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1681416                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505440                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       505440                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681357                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2349111                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681416                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656586                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2349224                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681357                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656532                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2349111                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681416                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656586                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2349224                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        18357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        15534                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        33900                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         2728                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         2728                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       147864                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       147864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       147776                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       147776                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        18298                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        18298                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        15568                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        15568                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        18357                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       163398                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        181764                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        18298                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       163344                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        181651                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        18357                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       181764                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        18298                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       163344                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       181651                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699714                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       521008                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2231953                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       682059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       682059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11231                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       682040                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       682040                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699714                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1699714                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521008                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
@@ -497,25 +503,27 @@ system.cpu.l2cache.overall_accesses::cpu.data       819930
 system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010800                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029815                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015188                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000801                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494363                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494363                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010765                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029881                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029881                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010800                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071819                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010765                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199217                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071774                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010800                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071819                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010765                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199217                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071774                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -524,46 +532,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101897                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101897                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101949                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101949                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          67802                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       682059                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       682040                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1836576                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417508                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444657                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699732                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116722                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2582000                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37000                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5917595                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7754152                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108818936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96310049                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308833                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205239845                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205238629                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       36631                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3336291                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.019237                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.137356                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      5172848                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.012407                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.110693                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3272112     98.08%     98.08% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              64179      1.92%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5108669     98.76%     98.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              64179      1.24%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3336291                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5172848                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22778                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -630,24 +640,24 @@ system.iocache.tags.tag_accesses               328176                       # Nu
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          240                       # number of overall misses
 system.iocache.overall_misses::total              240                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -663,46 +673,48 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74227                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
+system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::Writeback            138087                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::Writeback            138139                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8204                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            145997                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           145997                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34115                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105404                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       498791                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       606151                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 715269                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       506581                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       613941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723299                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18096316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18259289                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22909145                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092412                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586905                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            426678                       # Request fanout histogram
+system.membus.snoop_fanout::samples            434821                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  426678    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  434821    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              426678                       # Request fanout histogram
+system.membus.snoop_fanout::total              434821                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 81dc58761..b0093ef47 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.868578                       # Number of seconds simulated
-sim_ticks                                2868577613500                       # Number of ticks simulated
-final_tick                               2868577613500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.868721                       # Number of seconds simulated
+sim_ticks                                2868720569000                       # Number of ticks simulated
+final_tick                               2868720569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 558438                       # Simulator instruction rate (inst/s)
-host_op_rate                                   675477                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12195118142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 590596                       # Number of bytes of host memory used
-host_seconds                                   235.22                       # Real time elapsed on the host
-sim_insts                                   131357672                       # Number of instructions simulated
-sim_ops                                     158887964                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 718623                       # Simulator instruction rate (inst/s)
+host_op_rate                                   869205                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15661016649                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 645712                       # Number of bytes of host memory used
+host_seconds                                   183.18                       # Real time elapsed on the host
+sim_insts                                   131634295                       # Number of instructions simulated
+sim_ops                                     159217322                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1167908                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1250980                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8365696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1149540                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1292388                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8590592                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           137236                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           508432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       356544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           151892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           585104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       399936                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11788332                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1167908                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       137236                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1305144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8293056                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12171052                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1149540                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       151892                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1301432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8736704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8310620                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8754268                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26702                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20066                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       130714                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20713                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134228                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2299                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              7964                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5571                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2528                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9162                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6249                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                193340                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          129579                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                199320                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          136511                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133970                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               140902                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              407138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              436098                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2916322                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              400715                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              450510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2994573                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               47841                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              177242                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       124293                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               52948                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              203960                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       139413                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4109469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         407138                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          47841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             454979                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2890999                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4242676                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         400715                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          52948                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             453663                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3045505                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6109                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2897122                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2890999                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3051628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3045505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             407138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             442207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2916322                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             400715                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             456619                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2994573                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              47841                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             177256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       124293                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              52948                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             203974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       139413                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7006592                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        193340                       # Number of read requests accepted
-system.physmem.writeReqs                       170194                       # Number of write requests accepted
-system.physmem.readBursts                      193340                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     170194                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12365312                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9398080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11788332                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10628956                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      132                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23320                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          12970                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11741                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11572                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11914                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12194                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               20279                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11715                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11292                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11716                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11966                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12328                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11336                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10554                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10992                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11462                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10907                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11240                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9545                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9662                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9792                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9578                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8974                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9217                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9112                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9138                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9280                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9864                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9143                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8671                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8940                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8704                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8686                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8539                       # Per bank write bursts
+system.physmem.bw_total::total                7294304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        199320                       # Number of read requests accepted
+system.physmem.writeReqs                       140902                       # Number of write requests accepted
+system.physmem.readBursts                      199320                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     140902                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12746944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8766656                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12171052                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8754268                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          49030                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12070                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11831                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12274                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12388                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               20676                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12594                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12033                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12197                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12580                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12376                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11749                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11049                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11595                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11646                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10943                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11170                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8793                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8761                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9161                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8988                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8395                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9123                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8851                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8630                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9078                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8912                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8485                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8089                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8403                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8019                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7666                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7625                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2868577154000                       # Total gap between requests
+system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2868720108500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9731                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  183581                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  189561                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 165803                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    135144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15528                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      9961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8501                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6878                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5365                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4499                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3767                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       47                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 136511                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138723                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     15961                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     10493                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8947                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5591                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4693                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3946                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3444                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -184,163 +184,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      985                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       90                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        83936                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      259.284788                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     144.169379                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     318.901486                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          42814     51.01%     51.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16839     20.06%     71.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5671      6.76%     77.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3554      4.23%     82.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2350      2.80%     84.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1452      1.73%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1048      1.25%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          956      1.14%     88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9252     11.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          83936                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6009                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.152937                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      562.980980                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6006     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6009                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6009                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.437510                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.815074                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       42.361816                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5653     94.08%     94.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              88      1.46%     95.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              21      0.35%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              11      0.18%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              30      0.50%     96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             35      0.58%     97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            32      0.53%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            15      0.25%     97.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            11      0.18%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             9      0.15%     98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            22      0.37%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            19      0.32%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             8      0.13%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             2      0.03%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             4      0.07%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.05%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.05%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.03%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             5      0.08%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             5      0.08%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             6      0.10%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             6      0.10%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             1      0.02%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             2      0.03%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             2      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             4      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             2      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             2      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6009                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4585121898                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8207771898                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    966040000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23731.53                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4887                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5950                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6970                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      131                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        88863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      242.097791                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     137.224347                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     303.120448                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46751     52.61%     52.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18086     20.35%     72.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6032      6.79%     79.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3695      4.16%     83.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2426      2.73%     86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1553      1.75%     88.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1048      1.18%     89.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          926      1.04%     90.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8346      9.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88863                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6835                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.139722                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      544.203282                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6833     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6835                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6835                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.040819                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.588322                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.942463                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5790     84.71%     84.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             288      4.21%     88.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             181      2.65%     91.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              61      0.89%     92.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              66      0.97%     93.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             161      2.36%     95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              22      0.32%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.15%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              10      0.15%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               9      0.13%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               9      0.13%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.16%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             163      2.38%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.10%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.07%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.12%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.19%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6835                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4713712824                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8448169074                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    995855000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23666.66                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42481.53                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.28                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.71                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42416.66                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.06                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     161661                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94455                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  64.31                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7890808.44                       # Average gap between requests
-system.physmem.pageHitRate                      75.31                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  329026320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  179528250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 798891600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                486116640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           187361132400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            84057386715                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1647408374250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1920620456175                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.538978                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2740481725360                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95787900000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.14                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166377                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80909                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  59.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8431906.54                       # Average gap between requests
+system.physmem.pageHitRate                      73.56                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  348886440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  190364625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 827283600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                458148960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            84523956795                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1647087865500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1920807300960                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.569582                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2739939393002                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95792840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32307893640                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32988240498                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  305529840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  166707750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 708123000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                465438960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           187361132400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82818901260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1648494765000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1920320598210                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.434445                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2742293590423                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95787900000                       # Time in different power states
+system.physmem_1.actEnergy                  322917840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  176195250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 726242400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                429474960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            83768933655                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1647750166500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1920544725645                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.478051                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2741046257852                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95792840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30490063327                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31880394648                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
@@ -396,58 +389,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     7618                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                7618                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1341                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6277                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         7618                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           7618    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         7618                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6224                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean  9157.575514                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  8041.236075                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5531.388532                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6077     97.64%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          137      2.20%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            1      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6224                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   1121059000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     1121059000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   1121059000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         4922     79.08%     79.08% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1302     20.92%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6224                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7618                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                     7828                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7828                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1457                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6371                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         7828                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7828    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7828                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6434                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9317.145265                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5859.670820                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6278     97.58%     97.58% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          144      2.24%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151            7      0.11%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6434                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   1109412500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     1109412500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   1109412500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5016     77.96%     77.96% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1418     22.04%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6434                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7828                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7618                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6224                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7828                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6434                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6224                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        13842                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6434                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        14262                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25125547                       # DTB read hits
-system.cpu0.dtb.read_misses                      6527                       # DTB read misses
-system.cpu0.dtb.write_hits                   18731781                       # DTB write hits
-system.cpu0.dtb.write_misses                     1091                       # DTB write misses
+system.cpu0.dtb.read_hits                    22804186                       # DTB read hits
+system.cpu0.dtb.read_misses                      6713                       # DTB read misses
+system.cpu0.dtb.write_hits                   17553531                       # DTB write hits
+system.cpu0.dtb.write_misses                     1115                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3404                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3455                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1741                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1817                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25132074                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18732872                       # DTB write accesses
+system.cpu0.dtb.read_accesses                22810899                       # DTB read accesses
+system.cpu0.dtb.write_accesses               17554646                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         43857328                       # DTB hits
-system.cpu0.dtb.misses                           7618                       # DTB misses
-system.cpu0.dtb.accesses                     43864946                       # DTB accesses
+system.cpu0.dtb.hits                         40357717                       # DTB hits
+system.cpu0.dtb.misses                           7828                       # DTB misses
+system.cpu0.dtb.accesses                     40365545                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -485,20 +477,21 @@ system.cpu0.itb.walker.walkWaitTime::samples         3348
 system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean  9422.169811                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  8126.335555                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5925.919906                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          980     42.02%     42.02% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1299     55.70%     97.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575            3      0.13%     97.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           45      1.93%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            3      0.13%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9538.524469                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5751.182189                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          887     38.04%     38.04% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1322     56.69%     94.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575           85      3.64%     98.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           28      1.20%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            7      0.30%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   1120687000                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     1120687000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   1120687000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::samples   1109040500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     1109040500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   1109040500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walkPageSizes::4K         2034     87.22%     87.22% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::1M          298     12.78%    100.00% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::total         2332                       # Table walker page sizes translated
@@ -509,7 +502,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   118901491                       # ITB inst hits
+system.cpu0.itb.inst_hits                   108563333                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -526,172 +519,172 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               118904839                       # ITB inst accesses
-system.cpu0.itb.hits                        118901491                       # DTB hits
+system.cpu0.itb.inst_accesses               108566681                       # ITB inst accesses
+system.cpu0.itb.hits                        108563333                       # DTB hits
 system.cpu0.itb.misses                           3348                       # DTB misses
-system.cpu0.itb.accesses                    118904839                       # DTB accesses
-system.cpu0.numCycles                      5737155227                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                    108566681                       # DTB accesses
+system.cpu0.numCycles                      5737441138                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  115236645                       # Number of instructions committed
-system.cpu0.committedOps                    139243080                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            123236123                       # Number of integer alu accesses
+system.cpu0.committedInsts                  105480509                       # Number of instructions committed
+system.cpu0.committedOps                    127164191                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            112285314                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
-system.cpu0.num_func_calls                   12671679                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     15683932                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   123236123                       # number of integer instructions
+system.cpu0.num_func_calls                   10414111                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14574473                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   112285314                       # number of integer instructions
 system.cpu0.num_fp_insts                         9820                       # number of float instructions
-system.cpu0.num_int_register_reads          226877119                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          85629478                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          205015592                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          77505457                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           504430555                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           52228186                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     44991026                       # number of memory refs
-system.cpu0.num_load_insts                   25375377                       # Number of load instructions
-system.cpu0.num_store_insts                  19615649                       # Number of store instructions
-system.cpu0.num_idle_cycles              5465784255.910094                       # Number of idle cycles
-system.cpu0.num_busy_cycles              271370971.089905                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.047301                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.952699                       # Percentage of idle cycles
-system.cpu0.Branches                         29094451                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           459494635                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           48916829                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     41493426                       # number of memory refs
+system.cpu0.num_load_insts                   23055800                       # Number of load instructions
+system.cpu0.num_store_insts                  18437626                       # Number of store instructions
+system.cpu0.num_idle_cycles              5489199817.904087                       # Number of idle cycles
+system.cpu0.num_busy_cycles              248241320.095913                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.043267                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.956733                       # Percentage of idle cycles
+system.cpu0.Branches                         25703635                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 97895605     68.46%     68.46% # Class of executed instruction
-system.cpu0.op_class::IntMult                  108367      0.08%     68.53% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              8067      0.01%     68.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.54% # Class of executed instruction
-system.cpu0.op_class::MemRead                25375377     17.74%     86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite               19615649     13.72%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 88750967     68.09%     68.09% # Class of executed instruction
+system.cpu0.op_class::IntMult                   92819      0.07%     68.16% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.16% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8217      0.01%     68.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.17% # Class of executed instruction
+system.cpu0.op_class::MemRead                23055800     17.69%     85.86% # Class of executed instruction
+system.cpu0.op_class::MemWrite               18437626     14.14%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 143005338                       # Class of executed instruction
+system.cpu0.op_class::total                 130347702                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1891                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           691902                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          493.788529                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42987184                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           692414                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            62.083066                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1147014500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.788529                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.964431                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.964431                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1862                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           694931                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.123274                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           39503506                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           695443                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            56.803370                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1135131000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.123274                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965085                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.965085                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88350780                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88350780                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     23864345                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23864345                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     18002045                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18002045                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319294                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       319294                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365178                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       365178                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362317                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       362317                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     41866390                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41866390                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     42185684                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       42185684                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       396651                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       396651                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       323350                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       323350                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127092                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       127092                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21763                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21763                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19681                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        19681                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       720001                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        720001                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       847093                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       847093                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5048891005                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5048891005                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5105410053                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5105410053                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330377500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    330377500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    436252524                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    436252524                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1279500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1279500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  10154301058                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  10154301058                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  10154301058                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  10154301058                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     24260996                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     24260996                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     18325395                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     18325395                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446386                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       446386                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386941                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       386941                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381998                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381998                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     42586391                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     42586391                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     43032777                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     43032777                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016349                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.016349                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017645                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017645                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.284713                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.284713                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056244                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056244                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051521                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051521                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016907                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.016907                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019685                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.019685                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15789.114127                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15789.114127                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15180.696595                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15180.696595                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22166.176719                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22166.176719                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         81393420                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        81393420                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     21551304                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       21551304                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     16831338                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      16831338                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318322                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       318322                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365658                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       365658                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362750                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       362750                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     38382642                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        38382642                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     38700964                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       38700964                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       398253                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       398253                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       324071                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       324071                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       128299                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       128299                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21791                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21791                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19751                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19751                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       722324                       # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::cpu0.data       850623                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       850623                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5056802000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5056802000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5106772500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5106772500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    332740500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    332740500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    437773500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    437773500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1801500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1801500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  10163574500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  10163574500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  10163574500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  10163574500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     21949557                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     21949557                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17155409                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17155409                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446621                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446621                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387449                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       387449                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382501                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       382501                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     39104966                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     39104966                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     39551587                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     39551587                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.018144                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.018144                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018890                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018890                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.287266                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.287266                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056242                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056242                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051636                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051636                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018471                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.018471                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021507                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.021507                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14103.176326                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11987.232875                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -700,147 +693,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       505765                       # number of writebacks
-system.cpu0.dcache.writebacks::total           505765                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25164                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25164                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15036                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15036                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        25164                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        25164                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        25164                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        25164                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371487                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       371487                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       323350                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       323350                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100065                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       100065                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6727                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6727                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19681                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        19681                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       694837                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       694837                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       794902                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       794902                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31775                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28452                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60227                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4098614569                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4098614569                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4609386947                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4609386947                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1545410442                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1545410442                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97646500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97646500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    406311476                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    406311476                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1224000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1224000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8708001516                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   8708001516                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10253411958                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10253411958                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6180823750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6180823750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4817819000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4817819000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10998642750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10998642750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017645                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017645                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224167                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224167                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017385                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017385                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051521                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051521                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016316                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016316                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018472                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018472                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11032.995957                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11032.995957                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14255.101120                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14255.101120                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15444.065777                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15444.065777                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14515.608741                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14515.608741                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20644.859306                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20644.859306                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       507088                       # number of writebacks
+system.cpu0.dcache.writebacks::total           507088                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25317                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25317                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15125                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15125                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        25317                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        25317                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        25317                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        25317                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372936                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       372936                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324071                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       324071                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100997                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       100997                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6666                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6666                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19751                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19751                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       697007                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       697007                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       798004                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       798004                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21110                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40796                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4291277500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4291277500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4782701500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4782701500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1606991500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1606991500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101428000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101428000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    418075500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    418075500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1748500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1748500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9073979000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9073979000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10680970500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10680970500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4433767500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4433767500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3394597500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3394597500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7828365000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7828365000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016991                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016991                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018890                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018890                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226136                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226136                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017205                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017205                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051636                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051636                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017824                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.017824                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020176                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020176                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12532.437847                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12532.437847                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12898.963593                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12898.963593                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194518.450039                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194518.450039                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169331.470547                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169331.470547                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182619.800920                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182619.800920                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1099684                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.454126                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          117801286                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1100196                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           107.073000                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      13491746250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.454126                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998934                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998934                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1106064                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.455953                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          107456748                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1106576                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            97.107427                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13496677000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.455953                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998937                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998937                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        238903187                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       238903187                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    117801286                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      117801286                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    117801286                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       117801286                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    117801286                       # number of overall hits
-system.cpu0.icache.overall_hits::total      117801286                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1100205                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1100205                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1100205                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1100205                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1100205                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1100205                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10864366523                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10864366523                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10864366523                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10864366523                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10864366523                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10864366523                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    118901491                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    118901491                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    118901491                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    118901491                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    118901491                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    118901491                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009253                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009253                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009253                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009253                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009253                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009253                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9874.856525                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9874.856525                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9874.856525                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9874.856525                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9874.856525                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9874.856525                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        218233251                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       218233251                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    107456748                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      107456748                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    107456748                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       107456748                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    107456748                       # number of overall hits
+system.cpu0.icache.overall_hits::total      107456748                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1106585                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1106585                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1106585                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1106585                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1106585                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1106585                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10879255500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10879255500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10879255500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10879255500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10879255500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10879255500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    108563333                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    108563333                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    108563333                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    108563333                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    108563333                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    108563333                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010193                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.010193                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010193                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.010193                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010193                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.010193                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9831.378069                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9831.378069                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9831.378069                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9831.378069                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -849,228 +842,239 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1100205                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1100205                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1100205                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1100205                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1100205                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1100205                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1106585                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1106585                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1106585                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1106585                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1106585                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1106585                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9757723477                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9757723477                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9757723477                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9757723477                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9757723477                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9757723477                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    802157500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    802157500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    802157500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    802157500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009253                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009253                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009253                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8869.004846                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8869.004846                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8869.004846                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88911.272445                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88911.272445                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10325963000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10325963000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10325963000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10325963000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10325963000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10325963000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    800795500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    800795500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010193                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010193                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010193                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9331.378069                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1850277                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1850277                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1850657                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1850711                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           45                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       235795                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          266928                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16114.496747                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1972101                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          283159                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.964642                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7721.313532                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.317590                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.113534                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4537.329831                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1964.577716                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1889.844545                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.471272                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000080                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.276937                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119908                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.115347                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983551                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1123                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15100                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          269                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          368                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          474                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage       237577                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          266648                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16090.167348                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3241094                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          282873                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.457771                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle    2844827650500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7840.907632                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.369036                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.138555                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4562.781634                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1957.525775                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1727.444715                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.478571                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000084                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278490                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119478                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.105435                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.982066                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1088                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15130                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          359                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          432                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3254                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7638                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4052                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.068542                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.921631                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        39669375                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       39669375                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7528                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3363                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1053127                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       384165                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1448183                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       505760                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       505760                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28149                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28149                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1715                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1715                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       225012                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       225012                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7528                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3363                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1053127                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       609177                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1673195                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7528                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3363                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1053127                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       609177                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1673195                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          209                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          123                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        47078                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        94114                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       141524                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26175                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26175                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        17961                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        17961                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44014                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        44014                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          209                       # number of demand (read+write) misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total    482009840                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19676                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.035284                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.042790                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.481831                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.912838                       # miss rate for SCUpgradeReq accesses
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3231                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7855                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.066406                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.923462                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        60109727                       # Number of tag accesses
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.478697                       # miss rate for UpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.163605                       # miss rate for ReadExReq accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22991.626794                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 50087.205850                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29384.092632                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36255.848626                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18414.893601                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18414.893601                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20373.825901                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20373.825901                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 237199.600000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 237199.600000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44507.037374                       # average ReadExReq miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average overall miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34202.965633                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38213.225668                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22991.626794                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 50087.205850                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34202.965633                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38213.225668                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154445                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154445                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042186                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042186                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.196501                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.196501                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042186                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.181384                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.097983                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042186                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.181384                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.097983                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23380.530973                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18474.993278                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18474.993278                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20365.189978                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20365.189978                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       416749                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       416749                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46842.540574                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46842.540574                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49635.769676                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49635.769676                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29307.789237                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29307.789237                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38467.800951                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38467.800951                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1079,192 +1083,207 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       194963                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          194963                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data           34                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total           34                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1200                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1200                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1234                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         1234                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1234                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         1234                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          209                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          123                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        47078                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        94080                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total       141490                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245498                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       245498                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26175                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26175                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        17961                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17961                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42814                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        42814                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          209                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          123                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        47078                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136894                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       184304                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          209                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          123                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        47078                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136894                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245498                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       429802                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       195259                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          195259                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1202                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1202                       # number of ReadExReq MSHR hits
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+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           29                       # number of ReadSharedReq MSHR hits
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+system.cpu0.l2cache.demand_mshr_hits::total         1231                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8231                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         8231                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       244881                       # number of HardPFReq MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26033                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26033                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18081                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18081                       # number of SCUpgradeReq MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total       426761                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40797                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28452                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69249                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2045556523                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2147080077                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   4198090850                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13523341666                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13523341666                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    511152796                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    511152796                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    258980524                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    258980524                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       945498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       945498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1561585422                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1561585422                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2045556523                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3708665499                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   5759676272                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2045556523                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3708665499                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  19283017938                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    730253500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5926417500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6656671000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4604429000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4604429000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    730253500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10530846500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11261100000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.196705                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.089004                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        49818                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of ReadReq MSHR miss cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5892000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13903852400                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    522651500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    522651500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    269507500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    269507500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1348996                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2037005000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2037005000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2197124000                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2037005000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3786507000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   5829404000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2037005000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3786507000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  19733256400                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4264886500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4998017000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3246952500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3246952500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7511839000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8244969500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028404                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.481831                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.481831                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.912838                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.912838                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.478697                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.478697                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.915633                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.915633                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159144                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159144                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.183184                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.099156                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.183184                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149988                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149988                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042186                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.196440                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.196440                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.097324                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231234                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22821.854560                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29670.583433                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19528.282560                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36473.710048                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36473.710048                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27091.512404                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31250.956420                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44864.886478                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186511.959087                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163165.698458                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161831.470547                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161831.470547                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 174852.582729                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228360                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       337249                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       337249                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1738254                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1687491                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        30889                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28452                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       505760                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       309559                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        88185                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42256                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       111549                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           50                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       297072                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       284592                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2218454                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2369943                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9884                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        21632                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4619913                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70449208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84455860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        30948                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         154949960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     641653                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3048291                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.181009                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.385025                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq         64679                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1685922                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19686                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       869596                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1383128                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       312557                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        88259                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42246                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       111569                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       298532                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       285304                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1106585                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       579491                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3316089                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2519725                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10102                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22430                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5868346                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70857528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84663704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        32924                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         155568972                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1147635                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4840235                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.218671                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.413345                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2496524     81.90%     81.90% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2            551767     18.10%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           3781818     78.13%     78.13% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1058417     21.87%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3048291                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1778395498                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4840235                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2418139995                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    114075998                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    114234000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1664668023                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1668899500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1210905566                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1193519480                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu0.toL2Bus.respLayer2.occupancy      6398000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     13895250                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     14203990                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1295,59 +1314,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     3295                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                3295                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          601                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2694                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         3295                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           3295    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         3295                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2525                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean  9355.742574                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  8433.023249                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5123.717679                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191          905     35.84%     35.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1497     59.29%     95.13% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575           62      2.46%     97.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           54      2.14%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959            2      0.08%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            4      0.16%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2525                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1642630968                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1642630968    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1642630968                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1932     76.51%     76.51% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          593     23.49%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2525                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3295                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                     3364                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                3364                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          665                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2699                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         3364                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           3364    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         3364                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2594                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9203.479719                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5035.039152                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         1036     39.94%     39.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1440     55.51%     95.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575           55      2.12%     97.57% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.16%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151            6      0.23%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2594                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1650887468                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1650887468    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1650887468                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1937     74.67%     74.67% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          657     25.33%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2594                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3364                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3295                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2525                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3364                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2594                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2525                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         5820                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2594                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         5958                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3921520                       # DTB read hits
-system.cpu1.dtb.read_misses                      2787                       # DTB read misses
-system.cpu1.dtb.write_hits                    3403460                       # DTB write hits
-system.cpu1.dtb.write_misses                      508                       # DTB write misses
+system.cpu1.dtb.read_hits                     6310579                       # DTB read hits
+system.cpu1.dtb.read_misses                      2859                       # DTB read misses
+system.cpu1.dtb.write_hits                    4631996                       # DTB write hits
+system.cpu1.dtb.write_misses                      505                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2006                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    2036                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   344                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   323                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3924307                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3403968                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 6313438                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4632501                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7324980                       # DTB hits
-system.cpu1.dtb.misses                           3295                       # DTB misses
-system.cpu1.dtb.accesses                      7328275                       # DTB accesses
+system.cpu1.dtb.hits                         10942575                       # DTB hits
+system.cpu1.dtb.misses                           3364                       # DTB misses
+system.cpu1.dtb.accesses                     10945939                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1377,43 +1395,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     1740                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1740                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          164                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1576                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1740                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1740    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1740                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1101                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean  9831.970936                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  8728.225186                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5541.612386                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095          184     16.71%     16.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          162     14.71%     31.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          497     45.14%     76.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          204     18.53%     95.10% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     95.19% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.54%     97.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.73%     99.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.27%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.18%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1101                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1642083968                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1642083968    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1642083968                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          937     85.10%     85.10% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          164     14.90%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1101                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9680.648713                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5669.589944                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          351     31.71%     31.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          484     43.72%     75.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          202     18.25%     93.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           20      1.81%     95.48% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           23      2.08%     97.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           15      1.36%     99.01% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            5      0.45%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            6      0.54%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1650350468                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1650350468    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1650350468                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1740                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1740                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1101                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1101                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         2841                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    16475856                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1740                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    27093131                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1422,178 +1439,178 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1142                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1148                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                16477596                       # ITB inst accesses
-system.cpu1.itb.hits                         16475856                       # DTB hits
-system.cpu1.itb.misses                           1740                       # DTB misses
-system.cpu1.itb.accesses                     16477596                       # DTB accesses
-system.cpu1.numCycles                      5736236800                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                27094877                       # ITB inst accesses
+system.cpu1.itb.hits                         27093131                       # DTB hits
+system.cpu1.itb.misses                           1746                       # DTB misses
+system.cpu1.itb.accesses                     27094877                       # DTB accesses
+system.cpu1.numCycles                      5736521358                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   16121027                       # Number of instructions committed
-system.cpu1.committedOps                     19644884                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             17715670                       # Number of integer alu accesses
+system.cpu1.committedInsts                   26153786                       # Number of instructions committed
+system.cpu1.committedOps                     32053131                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             28968286                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1024357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1805296                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    17715670                       # number of integer instructions
+system.cpu1.num_func_calls                    3299674                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2947168                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    28968286                       # number of integer instructions
 system.cpu1.num_fp_insts                         1857                       # number of float instructions
-system.cpu1.num_int_register_reads           32157611                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          12423544                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           54552282                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          20759353                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            71811842                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            6390929                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      7557236                       # number of memory refs
-system.cpu1.num_load_insts                    4032278                       # Number of load instructions
-system.cpu1.num_store_insts                   3524958                       # Number of store instructions
-system.cpu1.num_idle_cycles              5685648636.968273                       # Number of idle cycles
-system.cpu1.num_busy_cycles              50588163.031727                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.008819                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.991181                       # Percentage of idle cycles
-system.cpu1.Branches                          2908306                       # Number of branches fetched
+system.cpu1.num_cc_register_reads           117965505                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            9826508                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     11178844                       # number of memory refs
+system.cpu1.num_load_insts                    6422284                       # Number of load instructions
+system.cpu1.num_store_insts                   4756560                       # Number of store instructions
+system.cpu1.num_idle_cycles              5660914446.273914                       # Number of idle cycles
+system.cpu1.num_busy_cycles              75606911.726086                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.013180                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.986820                       # Percentage of idle cycles
+system.cpu1.Branches                          6348758                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 12407832     62.06%     62.06% # Class of executed instruction
-system.cpu1.op_class::IntMult                   25890      0.13%     62.19% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              3309      0.02%     62.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.20% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4032278     20.17%     82.37% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3524958     17.63%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 21763864     65.97%     65.97% # Class of executed instruction
+system.cpu1.op_class::IntMult                   43243      0.13%     66.10% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     66.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3315      0.01%     66.11% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     66.11% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     66.11% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     66.11% # Class of executed instruction
+system.cpu1.op_class::MemRead                 6422284     19.47%     85.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite                4756560     14.42%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  19994333                       # Class of executed instruction
+system.cpu1.op_class::total                  32989332                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2782                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements           185399                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          466.419324                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            7065195                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           185751                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.035838                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     104846956000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   466.419324                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.910975                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.910975                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          268                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           84                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         14867676                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        14867676                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3611065                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3611065                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3216741                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3216741                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48524                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        48524                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78212                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78212                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70143                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        70143                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      6827806                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         6827806                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      6876330                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        6876330                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       133141                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       133141                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        90456                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        90456                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30283                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30283                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17238                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17238                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23491                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23491                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       223597                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        223597                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       253880                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       253880                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1928381738                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1928381738                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2296114353                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2296114353                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319996750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    319996750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    553086757                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    553086757                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2433500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2433500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4224496091                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4224496091                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4224496091                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4224496091                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3744206                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3744206                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3307197                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3307197                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        78807                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        78807                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        95450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        93634                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        93634                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      7051403                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      7051403                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      7130210                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      7130210                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035559                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035559                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027351                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.027351                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.384268                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.384268                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.180597                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.180597                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.250881                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250881                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031710                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031710                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035606                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035606                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.755853                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14483.755853                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25383.770596                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25383.770596                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18563.449936                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18563.449936                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2773                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements           185916                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          465.807736                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           10656106                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           186281                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            57.204471                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     104850302500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   465.807736                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.909781                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.909781                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           66                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         22064450                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        22064450                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      5988472                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        5988472                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4434786                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4434786                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48931                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        48931                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78766                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78766                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70801                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70801                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     10423258                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        10423258                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     10472189                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       10472189                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       133050                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       133050                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        91601                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        91601                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30372                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30372                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17242                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17242                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23381                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23381                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       224651                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        224651                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       255023                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       255023                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1943965500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1943965500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2376775500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2376775500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    323304000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    323304000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    547906000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    547906000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2312500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2312500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4320741000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4320741000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4320741000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4320741000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      6121522                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      6121522                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4526387                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4526387                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79303                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79303                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96008                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        96008                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94182                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94182                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     10647909                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     10647909                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     10727212                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     10727212                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.021735                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.021735                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020237                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.020237                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382987                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382987                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.179589                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.179589                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248253                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248253                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.021098                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.021098                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.023773                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.023773                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1602,147 +1619,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       114520                       # number of writebacks
-system.cpu1.dcache.writebacks::total           114520                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          275                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          275                       # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12066                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12066                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          275                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          275                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          275                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          275                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       132866                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       132866                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        90456                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        90456                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29572                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        29572                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5172                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5172                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23491                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23491                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       223322                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       223322                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       252894                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       252894                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3084                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3084                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2437                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5521                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5521                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1717533750                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1717533750                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2155103647                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2155103647                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    472304765                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    472304765                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84734500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84734500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    516677243                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    516677243                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2366000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2366000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3872637397                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3872637397                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4344942162                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4344942162                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    406850750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    406850750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    279944500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    279944500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    686795250                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    686795250                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035486                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035486                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027351                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027351                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.375246                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.375246                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054185                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054185                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.250881                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250881                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031671                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031671                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035468                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035468                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       116022                       # number of writebacks
+system.cpu1.dcache.writebacks::total           116022                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          266                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12054                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12054                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          266                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          266                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          266                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          266                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       132784                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       132784                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91601                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        91601                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29597                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29597                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5188                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5188                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23381                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23381                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       224385                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       224385                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       253982                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       253982                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        13773                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25000                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1804303500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1804303500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2285174500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2285174500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494107000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494107000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90251000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90251000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524565000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524565000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2272500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2272500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4089478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4089478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4583585000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4583585000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2232716000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2232716000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1768357000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1768357000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4001073000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4001073000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.021691                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.021691                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.020237                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.020237                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373214                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373214                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054037                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054037                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248253                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248253                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.021073                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.021073                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.023676                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.023676                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13588.259881                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13588.259881                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24947.047521                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24947.047521                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16694.496064                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16694.496064                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17396.106399                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17396.106399                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22435.524571                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22435.524571                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160042.920000                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160042.920000                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           502966                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.575795                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           15972373                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           503478                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            31.724073                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      84694032500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.575795                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973781                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973781                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           505537                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.573002                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           26587077                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           506049                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            52.538543                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      84702248000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.573002                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973775                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973775                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          121                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          392                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          117                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         33455180                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        33455180                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     15972373                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       15972373                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     15972373                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        15972373                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     15972373                       # number of overall hits
-system.cpu1.icache.overall_hits::total       15972373                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       503478                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       503478                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       503478                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        503478                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       503478                       # number of overall misses
-system.cpu1.icache.overall_misses::total       503478                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4406075262                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4406075262                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4406075262                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4406075262                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4406075262                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4406075262                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     16475851                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     16475851                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     16475851                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     16475851                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     16475851                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     16475851                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030559                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.030559                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030559                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.030559                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030559                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.030559                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8751.276644                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8751.276644                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8751.276644                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8751.276644                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8751.276644                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8751.276644                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         54692301                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        54692301                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     26587077                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       26587077                       # number of ReadReq hits
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+system.cpu1.icache.demand_hits::total        26587077                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     26587077                       # number of overall hits
+system.cpu1.icache.overall_hits::total       26587077                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       506049                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       506049                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       506049                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        506049                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       506049                       # number of overall misses
+system.cpu1.icache.overall_misses::total       506049                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4455517000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4455517000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4455517000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4455517000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4455517000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4455517000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     27093126                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     27093126                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     27093126                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     27093126                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     27093126                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     27093126                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018678                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.018678                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018678                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.018678                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018678                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.018678                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8804.516954                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8804.516954                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8804.516954                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8804.516954                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1751,224 +1768,237 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       503478                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       503478                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       503478                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       503478                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       503478                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       503478                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506049                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       506049                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       506049                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       506049                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       506049                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       506049                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3901799738                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3901799738                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3901799738                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3901799738                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3901799738                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3901799738                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15252750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15252750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15252750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     15252750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030559                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.030559                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.030559                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7749.692614                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  7749.692614                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  7749.692614                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86173.728814                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86173.728814                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4202492500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4202492500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4202492500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4202492500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4202492500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4202492500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15340000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     15340000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018678                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.018678                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.018678                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8304.516954                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86666.666667                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86666.666667                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       195194                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       195194                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       199458                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       199458                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        57534                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           39835                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14698.947760                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            703731                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           54406                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           12.934805                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        58862                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           46506                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15029.734126                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1265349                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           61182                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           20.681720                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  8839.546228                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.119643                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.076473                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3192.274029                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1936.419828                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   726.511560                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.539523                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000129                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8657.593794                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.281679                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.079815                       # Average occupied blocks per requestor
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 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.Writeback_accesses::writebacks       116022                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       116022                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29567                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29567                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23379                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23379                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62034                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        62034                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506049                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       506049                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       167569                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       167569                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3405                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1975                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       506049                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       229603                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       741032                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3405                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1975                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       506049                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       229603                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       741032                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.107807                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950215                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950215                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963985                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963985                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554469                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554469                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.092442                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.134441                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025741                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.440661                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.155126                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.092442                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.134441                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025741                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.440661                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.155126                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35513.212809                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21706.137674                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23920.006740                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19178.071897                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19178.071897                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20164.163608                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20164.163608                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       232100                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       232100                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36948.076833                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36948.076833                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35513.212809                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26849.908936                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 27796.424926                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35513.212809                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26849.908936                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 27796.424926                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.559612                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.559612                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027181                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027181                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.407432                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.407432                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027181                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.448548                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.158324                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027181                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.448548                       # miss rate for overall accesses
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average ReadReq miss latency
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20078.448276                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19156.753871                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19156.753871                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20002.551360                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20002.551360                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1106250                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1106250                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38512.818666                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38512.818666                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35797.201018                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35797.201018                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21846.044556                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21846.044556                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 28404.520000                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 28404.520000                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1977,196 +2007,210 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        25678                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           25678                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           69                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total           69                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data           69                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data           69                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total           69                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          318                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          267                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        12960                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        66868                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        80413                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        22290                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        22290                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        27915                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27915                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22615                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22615                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           10                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33992                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        33992                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          318                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          267                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12960                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       100860                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       114405                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          318                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          267                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12960                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       100860                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        22290                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       136695                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        30696                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           30696                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           90                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total           90                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data           90                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total           90                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data           90                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total           90                       # number of overall MSHR hits
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+system.cpu1.l2cache.ReadReq_mshr_misses::total          580                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2031                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         2031                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23725                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        23725                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28095                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28095                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22537                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22537                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total       140958                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3084                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3261                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2437                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        13950                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5521                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5698                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    375210762                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1016628986                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1399818998                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    742843274                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    742843274                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    439552298                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    439552298                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    340829757                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    340829757                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2028500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2028500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1027563755                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1027563755                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    375210762                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2044192741                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2427382753                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    375210762                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2044192741                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    742843274                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   3170226027                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13847750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    382171500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    396019250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    261667000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    261667000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13847750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    643838500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    657686250                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.398950                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.118864                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        25177                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      8165500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    839425646                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    455073500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    455073500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    349086500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    349086500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1119618000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1119618000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    409860500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    409860500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1081857000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1081857000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    409860500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2201475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2619501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    409860500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2201475000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   3458926646                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2122532000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2136544500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1684154500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1684154500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3806686500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3820699000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.107807                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.961724                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.961724                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963119                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963119                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950215                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950215                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963985                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963985                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.553345                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.553345                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.440360                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.155032                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.440360                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.558162                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.558162                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027181                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.407432                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.407432                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158202                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.185238                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       202850                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       202850                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.190219                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14078.448276                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35381.481391                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16197.668624                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16197.668624                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15489.483960                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       986250                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       986250                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22344.399614                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 151753.544902                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1060646                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       722071                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        30889                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2437                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       114520                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        27384                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        75380                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41410                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85537                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        84086                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66129                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1007310                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       764894                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5302                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9429                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          1786935                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32223300                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24770860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          57015864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     636167                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1470628                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.384445                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.486464                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq         53469                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       734633                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11227                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       478531                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict       680350                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        29761                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        73690                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41411                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85868                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           55                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        84408                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        66733                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506049                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       504061                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1509072                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       874243                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5299                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9468                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2398082                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32387844                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24934344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7900                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13620                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          57343708                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1094784                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2530004                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.405048                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.490902                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            905253     61.56%     61.56% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2            565375     38.44%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1505230     59.50%     59.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1024774     40.50%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1470628                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     573017999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       2530004                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     878944000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     81259000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     80122000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    755831512                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    759250500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    377529095                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    390308000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      3316000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      5989250                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      6063998                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -2257,23 +2301,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           199086925                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187549442                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36785519                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36445                       # number of replacements
-system.iocache.tags.tagsinuse               14.391068                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.390664                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         288263513000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.391068                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.899442                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.899442                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         288350117000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.390664                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.899417                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.899417                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2281,49 +2325,49 @@ system.iocache.tags.tag_accesses               328311                       # Nu
 system.iocache.tags.data_accesses              328311                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          255                       # number of overall misses
 system.iocache.overall_misses::total              255                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32671377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32671377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6655899029                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6655899029                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32671377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32671377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32671377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32671377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32656876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32656876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4281964566                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4281964566                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32656876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32656876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32656876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32656876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128123.047059                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128123.047059                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183742.795633                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183742.795633                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128123.047059                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128123.047059                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128123.047059                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128123.047059                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         23173                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128066.180392                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128066.180392                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128066.180392                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           265                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3543                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.540502                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs   132.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2331,325 +2375,325 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19404377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19404377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4772213067                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4772213067                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19404377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19404377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19404377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19404377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19906876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19906876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2470764566                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2470764566                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19906876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19906876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19906876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19906876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76095.596078                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76095.596078                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131741.747653                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131741.747653                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76095.596078                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76095.596078                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76095.596078                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76095.596078                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   122211                       # number of replacements
-system.l2c.tags.tagsinuse                63914.238063                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     336222                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   186592                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.801910                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   130439                       # number of replacements
+system.l2c.tags.tagsinuse                63983.082008                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     387954                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   194793                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.991622                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   11496.547602                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.049900                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.062133                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7182.549375                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2988.985612                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38830.864169                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955834                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1379.188596                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      342.352201                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1689.682641                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.175423                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000047                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   12138.175325                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.910023                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.041062                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7215.667264                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2903.196215                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37504.021978                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955808                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1528.247767                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      561.168860                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2127.697705                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.185214                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data       0.045608                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.021045                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.005224                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::total           0.975254                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        32922                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_blocks::1024        31453                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          129                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4653                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        28140                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
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 system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          241                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1024     0.479935                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  4784413                       # Number of tag accesses
-system.l2c.tags.data_accesses                 4784413                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker           69                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           62                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu0.data              44972                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        45934                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           27                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           29                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              10817                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data               7566                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         4637                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 143498                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          220641                       # number of Writeback hits
-system.l2c.Writeback_hits::total               220641                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            2604                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             702                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3306                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           145                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           242                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               387                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4135                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total                 5899                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker            69                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu0.inst               29385                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               49107                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        45934                       # number of demand (read+write) hits
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+system.l2c.Writeback_hits::total               225955                       # number of Writeback hits
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-system.l2c.UpgradeReq_miss_latency::cpu1.data      2717413                       # number of UpgradeReq miss cycles
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 system.l2c.overall_accesses::cpu1.dtb.walker           28                       # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.792798                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.771274                       # miss rate for UpgradeReq accesses
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-system.l2c.overall_miss_rate::cpu0.itb.walker     0.031250                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu0.data      0.287168                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.172170                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.482123                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.558408                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.372793                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.292721                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.165355                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.460351                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.551951                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80877.862092                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 86894.728819                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        96750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82768.665422                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 106052.442836                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 95728.210925                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1348.283503                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1011.695086                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1267.185863                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2563.736402                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   775.436247                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1270.976812                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87935.724877                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81219.968767                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85258.851157                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80877.862092                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 87471.767831                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        96750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82768.665422                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83375.922980                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 94690.956896                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80877.862092                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 87471.767831                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        96750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82768.665422                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83375.922980                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 94690.956896                       # average overall miss latency
+system.l2c.overall_miss_rate::cpu1.inst      0.172170                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.558408                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   978.429269                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   860.377358                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   950.095100                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2760.162602                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   916.735708                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1450.559152                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87988.514680                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81084.915997                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 85123.699101                       # average ReadExReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89298.832272                       # average ReadSharedReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 94462.355113                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 87341.004902                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 94462.355113                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2658,265 +2702,271 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               93389                       # number of writebacks
-system.l2c.writebacks::total                    93389                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                15                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            6                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu0.data         8817                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       130884                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu1.data          691                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::total          165793                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8462                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2686                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11148                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          478                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1247                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1725                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        10966                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         7268                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         18234                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR misses
+system.l2c.writebacks::writebacks              100321                       # number of writebacks
+system.l2c.writebacks::total                   100321                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
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+system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
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+system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3050                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3050                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8391                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2650                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11041                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          492                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1207                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17687                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        19783                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5571                       # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::cpu0.dtb.walker            6                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3080                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        44054                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        30889                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        13769                       # number of ReadReq MSHR uncacheable
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5517                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        74943                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       140000                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    655819176                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    149987000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     64618762                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::total  13820147295                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    151117443                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     47855180                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    198972623                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8594976                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     22191743                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     30786719                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    828734841                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    499414267                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1328149108                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       140000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1208996486                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1484554017                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    149987000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    564033029                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    579886727                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  15148296403                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       140000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1208996486                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1484554017                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11160223644                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    149987000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    564033029                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    579886727                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  15148296403                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    549810500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5306043500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10310750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    321686500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6187851250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4077783000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    216378500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4294161500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    549810500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9383826500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10310750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    538065000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10482012750                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.163918                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083687                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.536016                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.764685                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.792798                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.771274                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.767255                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.837475                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.816761                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726177                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.804694                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.755563                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.287168                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        24996                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        74991                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    174583000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     55064000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    229647000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     10311000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25083500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     35394500                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    583891500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1486998500                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     74699500                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::total  14558926649                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu0.inst   1228508000                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.inst    170183500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    658591000                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total  16045925149                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       146000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1228508000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   1577756500                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    170183500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    658591000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16045925149                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3884897500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1874631500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6341089500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2912289500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1493293500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4405583000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6797187000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3367925000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10746672500                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.797017                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800362                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.797818                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784689                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.892751                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858514                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.751899                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.848992                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.789360                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.162461                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.101116                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.540012                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.460351                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.551906                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.287168                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.558390                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.460351                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.551906                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74381.215379                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 93514.850941                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 83357.845597                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17858.360080                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17816.522710                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17848.279781                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17981.121339                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.105052                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17847.373333                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75573.120646                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68714.125894                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72839.152572                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 82315.618920                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 82315.618920                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516                       # average overall mshr uncacheable latency
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.558390                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20805.982600                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20778.867925                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.474685                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20957.317073                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20781.690141                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20832.548558                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77988.514680                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71084.915997                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 75123.699101                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              210102                       # Transaction distribution
-system.membus.trans_dist::ReadResp             210102                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30889                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30889                       # Transaction distribution
-system.membus.trans_dist::Writeback            129579                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            77022                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40122                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12986                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           33                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             38648                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18121                       # Transaction distribution
+system.membus.trans_dist::ReadReq               44078                       # Transaction distribution
+system.membus.trans_dist::ReadResp             214515                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
+system.membus.trans_dist::Writeback            136511                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15728                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            75283                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40251                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12822                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40262                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19712                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        170437                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       639843                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       761429                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 870337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       672670                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       794352                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 903273                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17781832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17971968                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22607424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           125322                       # Total snoops (count)
-system.membus.snoop_fanout::samples            562672                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18608200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18798528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21115648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123870                       # Total snoops (count)
+system.membus.snoop_fanout::samples            589976                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  562672    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  589976    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              562672                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88118500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              589976                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88273000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               18500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11425000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11464500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1114763998                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1021914451                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1110191376                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1141120383                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37521481                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64390592                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2949,44 +2999,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             475433                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            475418                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30889                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30889                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           220641                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           80215                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40509                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         120724                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           82                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50702                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50702                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1061225                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       262179                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1323404                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31467168                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4256160                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               35723328                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          289388                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           934737                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.039071                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.193764                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              44082                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            479204                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           362509                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           82484                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           77999                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40531                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         118530                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           93                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51218                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51218                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       435137                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1069100                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       319954                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1389054                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31596740                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4900924                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               36497664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          452334                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1194337                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.170309                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.375904                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 898216     96.09%     96.09% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36521      3.91%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 990931     82.97%     82.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 203406     17.03%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             934737                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          749457686                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1194337                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          799819351                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           360000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         652203239                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         609335323                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         220037759                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         239074701                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index c544f96e6..21bc80649 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.903548                       # Number of seconds simulated
-sim_ticks                                2903547931500                       # Number of ticks simulated
-final_tick                               2903547931500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.903468                       # Number of seconds simulated
+sim_ticks                                2903467553500                       # Number of ticks simulated
+final_tick                               2903467553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 571103                       # Simulator instruction rate (inst/s)
-host_op_rate                                   688575                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14743405801                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560940                       # Number of bytes of host memory used
-host_seconds                                   196.94                       # Real time elapsed on the host
-sim_insts                                   112472279                       # Number of instructions simulated
-sim_ops                                     135607130                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 736333                       # Simulator instruction rate (inst/s)
+host_op_rate                                   887789                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19005878440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 619548                       # Number of bytes of host memory used
+host_seconds                                   152.77                       # Real time elapsed on the host
+sim_insts                                   112487279                       # Number of instructions simulated
+sim_ops                                     135624752                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1191972                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9040292                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1189412                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9042916                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10233800                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1191972                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1191972                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7641920                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10233864                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1189412                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1189412                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7647616                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7659444                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7665140                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27078                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27038                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141815                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168876                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          119405                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                168877                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          119494                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123786                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123875                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               410523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3113533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               409652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3114523                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3524584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          410523                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             410523                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2631925                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6035                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2637960                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2631925                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3524704                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          409652                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             409652                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2633960                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6036                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2639995                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2633960                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              410523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3119568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              409652                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3120558                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6162545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        168876                       # Number of read requests accepted
-system.physmem.writeReqs                       160010                       # Number of write requests accepted
-system.physmem.readBursts                      168876                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     160010                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10798592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8731520                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10233800                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9977780                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23557                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4508                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10030                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9665                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9920                       # Per bank write bursts
+system.physmem.bw_total::total                6164699                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168877                       # Number of read requests accepted
+system.physmem.writeReqs                       123875                       # Number of write requests accepted
+system.physmem.readBursts                      168877                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123875                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10799552                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8576                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7677760                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10233864                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7665140                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      134                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40733                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10018                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9658                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10300                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9945                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18863                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10093                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10296                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10091                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10302                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               10601                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9928                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10198                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9956                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9036                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9857                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10481                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9974                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9528                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8313                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8253                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9067                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8494                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8419                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8394                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8676                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8975                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8824                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8984                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8586                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8136                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8548                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8715                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8203                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7843                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9921                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10207                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9962                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9026                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9868                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10473                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9981                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9527                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7412                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7255                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8123                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7537                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7355                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7348                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7577                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7905                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7603                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7853                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7551                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6940                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7397                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7831                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7359                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6919                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          46                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2903547607000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2903467231500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159304                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159305                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 155629                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    167922                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       242                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 119494                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167939                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       544                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       248                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,163 +159,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1887                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1944                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       63                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        60277                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      324.004977                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.393020                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.651376                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21725     36.04%     36.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14933     24.77%     60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5631      9.34%     70.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3281      5.44%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2561      4.25%     79.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1497      2.48%     82.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1055      1.75%     84.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1109      1.84%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8485     14.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          60277                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5494                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.709319                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      577.316613                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5492     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5494                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5494                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.832545                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.556239                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       46.623010                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            5170     94.10%     94.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              87      1.58%     95.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              17      0.31%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              12      0.22%     96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              19      0.35%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             28      0.51%     97.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            22      0.40%     97.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            14      0.25%     97.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159             9      0.16%     97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             4      0.07%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            29      0.53%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            12      0.22%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             6      0.11%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             2      0.04%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.04%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             1      0.02%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.04%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             7      0.13%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             8      0.15%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             4      0.07%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             4      0.07%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            10      0.18%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             2      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.05%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.02%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             4      0.07%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             3      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.04%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             6      0.11%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5494                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1499821694                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4663471694                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    843640000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8888.99                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7455                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        59281                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.689209                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.095727                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.740944                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21592     36.42%     36.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15113     25.49%     61.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5696      9.61%     71.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3272      5.52%     77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2400      4.05%     81.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1627      2.74%     83.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1059      1.79%     85.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          986      1.66%     87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7536     12.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          59281                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5916                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.520960                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      582.774923                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5915     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5916                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5916                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.278059                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.578317                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.228760                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5122     86.58%     86.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              35      0.59%     87.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             194      3.28%     90.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              61      1.03%     91.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              61      1.03%     92.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             181      3.06%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.24%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               5      0.08%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.12%     96.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.08%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.08%     96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.12%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             163      2.76%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.03%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.12%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               6      0.10%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               4      0.07%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.29%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5916                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1515248250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4679179500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    843715000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8979.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27638.99                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27729.62                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.72                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     138826                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    106054                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.28                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.72                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8828431.76                       # Average gap between requests
-system.physmem.pageHitRate                      80.24                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  233551080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  127433625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 700206000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                444469680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           189645583920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            87280455420                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1665566622000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1943998321725                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.525264                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2770655896974                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     96955820000                       # Time in different power states
+system.physmem.avgWrQLen                        27.93                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138696                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90730                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9917839.10                       # Average gap between requests
+system.physmem.pageHitRate                      79.46                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  229068000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  124987500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 700268400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392117760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           189639989760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            87025634640                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1665738759750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1943850825810                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.494214                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2770947478500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     96952960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35935671776                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     35561301500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222143040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121209000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 615864600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                439596720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           189645583920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85782200445                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1666880880750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1943707478475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.425095                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2772857314224                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     96955820000                       # Time in different power states
+system.physmem_1.actEnergy                  219096360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119546625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 615919200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385255440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           189639989760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            85786607970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1666825625250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1943592040605                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.405084                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2772773591250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     96952960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     33734699276                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     33740904250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -365,57 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                      9545                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                 9545                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1267                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8278                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples         9545                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0            9545    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total         9545                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7381                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  8418.408390                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  7914.312600                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767         7376     99.93%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-98303            2      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7381                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    937449500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       937449500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    937449500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6161     83.47%     83.47% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1220     16.53%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7381                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9545                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                      9548                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                 9548                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1269                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8279                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples         9548                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0            9548    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total         9548                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7384                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9756.046308                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7392.958780                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383         5809     78.67%     78.67% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         1570     21.26%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7384                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    925393500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       925393500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    925393500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6162     83.45%     83.45% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1222     16.55%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7384                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9548                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9545                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7381                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9548                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7384                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7381                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        16926                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7384                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        16932                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24524755                       # DTB read hits
-system.cpu.dtb.read_misses                       8132                       # DTB read misses
-system.cpu.dtb.write_hits                    19610055                       # DTB write hits
-system.cpu.dtb.write_misses                      1413                       # DTB write misses
+system.cpu.dtb.read_hits                     24527083                       # DTB read hits
+system.cpu.dtb.read_misses                       8134                       # DTB read misses
+system.cpu.dtb.write_hits                    19611642                       # DTB write hits
+system.cpu.dtb.write_misses                      1414                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4269                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1678                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   1680                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24532887                       # DTB read accesses
-system.cpu.dtb.write_accesses                19611468                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24535217                       # DTB read accesses
+system.cpu.dtb.write_accesses                19613056                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44134810                       # DTB hits
-system.cpu.dtb.misses                            9545                       # DTB misses
-system.cpu.dtb.accesses                      44144355                       # DTB accesses
+system.cpu.dtb.hits                          44138725                       # DTB hits
+system.cpu.dtb.misses                            9548                       # DTB misses
+system.cpu.dtb.accesses                      44148273                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -453,18 +448,18 @@ system.cpu.itb.walker.walkWaitTime::samples         4762                       #
 system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkCompletionTime::samples         3107                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 10683.778565                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  8326.699765                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7409.739384                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1442     46.41%     46.41% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383          985     31.70%     78.11% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          678     21.82%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11752.816221                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  9620.437143                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7446.323545                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1417     45.61%     45.61% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1012     32.57%     78.18% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          676     21.76%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::total         3107                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    937122000                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       937122000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    937122000                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::samples    925066000                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       925066000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    925066000                       # Table walker pending requests distribution
 system.cpu.itb.walker.walkPageSizes::4K          2798     90.05%     90.05% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::1M           309      9.95%    100.00% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::total         3107                       # Table walker page sizes translated
@@ -475,7 +470,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    115569545                       # ITB inst hits
+system.cpu.itb.inst_hits                    115585268                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -492,38 +487,38 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                115574307                       # ITB inst accesses
-system.cpu.itb.hits                         115569545                       # DTB hits
+system.cpu.itb.inst_accesses                115590030                       # ITB inst accesses
+system.cpu.itb.hits                         115585268                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     115574307                       # DTB accesses
-system.cpu.numCycles                       5807095863                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     115590030                       # DTB accesses
+system.cpu.numCycles                       5806935107                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112472279                       # Number of instructions committed
-system.cpu.committedOps                     135607130                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             119910547                       # Number of integer alu accesses
+system.cpu.committedInsts                   112487279                       # Number of instructions committed
+system.cpu.committedOps                     135624752                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119926396                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
-system.cpu.num_func_calls                     9892504                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15232384                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    119910547                       # number of integer instructions
+system.cpu.num_func_calls                     9895067                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15234125                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119926396                       # number of integer instructions
 system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218091200                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           82658465                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           218121828                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82669566                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            489812948                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            51900975                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      45415290                       # number of memory refs
-system.cpu.num_load_insts                    24846976                       # Number of load instructions
-system.cpu.num_store_insts                   20568314                       # Number of store instructions
-system.cpu.num_idle_cycles               5385642355.670145                       # Number of idle cycles
-system.cpu.num_busy_cycles               421453507.329855                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.072576                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.927424                       # Percentage of idle cycles
-system.cpu.Branches                          25918910                       # Number of branches fetched
+system.cpu.num_cc_register_reads            489877250                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51907763                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45420046                       # number of memory refs
+system.cpu.num_load_insts                    24850080                       # Number of load instructions
+system.cpu.num_store_insts                   20569966                       # Number of store instructions
+system.cpu.num_idle_cycles               5385437399.888144                       # Number of idle cycles
+system.cpu.num_busy_cycles               421497707.111855                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.072585                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.927415                       # Percentage of idle cycles
+system.cpu.Branches                          25923230                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  93186875     67.17%     67.17% # Class of executed instruction
-system.cpu.op_class::IntMult                   114498      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93200379     67.17%     67.18% # Class of executed instruction
+system.cpu.op_class::IntMult                   114573      0.08%     67.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
@@ -547,260 +542,260 @@ system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Cl
 system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               8463      0.01%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8455      0.01%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::MemRead                 24846976     17.91%     85.17% # Class of executed instruction
-system.cpu.op_class::MemWrite                20568314     14.83%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 24850080     17.91%     85.17% # Class of executed instruction
+system.cpu.op_class::MemWrite                20569966     14.83%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  138727463                       # Class of executed instruction
+system.cpu.op_class::total                  138745790                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3032                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements            820494                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.827736                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43242693                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            821006                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             52.670374                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1008712250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.827736                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999664                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999664                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3030                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements            820821                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.829842                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            43246183                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            821333                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.653653                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         996611500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.829842                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999668                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999668                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         177143306                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        177143306                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23115915                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23115915                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18827300                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18827300                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       392830                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        392830                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443506                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443506                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460403                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460403                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41943215                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41943215                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42336045                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42336045                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       400875                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        400875                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       298693                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       298693                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       118357                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       118357                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22685                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22685                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         177159261                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177159261                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23117842                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23117842                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18828857                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18828857                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392869                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392869                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443457                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443457                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460420                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460420                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41946699                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41946699                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42339568                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42339568                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       401262                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        401262                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       298702                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       298702                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       118314                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       118314                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22748                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22748                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       699568                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         699568                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       817925                       # number of overall misses
-system.cpu.dcache.overall_misses::total        817925                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5965444702                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5965444702                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12639649008                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12639649008                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    280760500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    280760500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       699964                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         699964                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       818278                       # number of overall misses
+system.cpu.dcache.overall_misses::total        818278                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5968529500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5968529500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12574790000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12574790000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    282012000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    282012000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18605093710                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18605093710                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18605093710                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18605093710                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23516790                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23516790                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19125993                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19125993                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511187                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511187                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466191                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466191                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460405                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460405                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42642783                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42642783                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43153970                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43153970                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017046                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.017046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015617                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231534                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.231534                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048660                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048660                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  18543319500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18543319500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18543319500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18543319500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23519104                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23519104                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19127559                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19127559                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511183                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511183                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466205                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466205                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460422                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460422                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42646663                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42646663                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43157846                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43157846                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017061                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.017061                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015616                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015616                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231451                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.231451                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048794                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048794                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016405                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.018954                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.018954                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016413                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016413                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.018960                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.018960                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14874.395034                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14874.395034                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42098.111161                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42098.111161                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12397.221734                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12397.221734                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26595.118287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22746.698915                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           57                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26491.818865                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26491.818865                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22661.393194                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22661.393194                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       683915                       # number of writebacks
-system.cpu.dcache.writebacks::total            683915                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          674                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          674                       # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14143                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14143                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          674                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          674                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       400201                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       400201                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298693                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298693                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116343                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       116343                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8542                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8542                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       682374                       # number of writebacks
+system.cpu.dcache.writebacks::total            682374                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          680                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          680                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14211                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14211                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          680                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          680                       # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total          680                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       400582                       # number of ReadReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total       116284                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8537                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8537                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       698894                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       698894                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       815237                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       815237                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5349732750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5349732750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12133728492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12133728492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1470377548                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1470377548                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    105335000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    105335000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17483461242                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17483461242                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18953838790                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18953838790                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5833129500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5833129500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4513032000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4513032000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10346161500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10346161500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017018                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017018                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227594                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227594                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018323                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018323                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       699284                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       699284                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       815568                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       815568                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31142                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31142                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27594                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27594                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58736                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58736                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5554957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5554957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12276088000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12276088000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1529661500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1529661500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110084000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110084000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17831045000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17831045000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19360706500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  19360706500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5907914500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5907914500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4572592500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4572592500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10480507000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10480507000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017032                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017032                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015616                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015616                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227480                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227480                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018312                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018312                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016390                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016390                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018891                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.018891                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016397                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016397                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018897                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.018897                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13867.215701                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13867.215701                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41098.111161                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41098.111161                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13154.531148                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23738.923670                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189708.897951                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189708.897951                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165709.665145                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165709.665145                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178434.128984                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178434.128984                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1698619                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.734312                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           113870408                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1699131                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.016850                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       25693423250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.734312                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997528                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997528                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1698833                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.737457                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113885917                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699345                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.017537                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       25666177500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.737457                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997534                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997534                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         117268682                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        117268682                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    113870408                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113870408                       # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_latency::cpu.inst  23363194999                       # number of ReadReq miss cycles
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014702                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.014702                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014702                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.014702                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.014702                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.014702                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13750.036047                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13750.036047                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.652549                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13741.652549                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.652549                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13741.652549                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.652549                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13741.652549                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -809,200 +804,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1699137                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  20807922501                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  20807922501                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014702                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014702                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014702                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.014702                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014702                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.014702                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12741.652549                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12741.652549                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75035.912215                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            89783                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64925.975304                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2753164                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           155016                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            17.760515                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            89784                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64924.949267                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4551273                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           155017                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            29.359832                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.807659                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012269                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9560.730853                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4902.381289                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.769944                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50366.375395                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.807733                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012270                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9623.804573                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4930.949297                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768530                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.145885                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.074804                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.990692                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65228                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2130                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6958                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56095                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995300                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26192754                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26192754                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6798                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        2204235                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       683915                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       683915                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         40578005                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40578005                       # Number of data accesses
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
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 system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.174520                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063766                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001029                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000563                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010631                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.174520                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063766                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        82750                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   194.724761                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   194.724761                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.442656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.442656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010606                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010606                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023449                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023449                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001009                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000556                       # miss rate for demand accesses
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+system.cpu.l2cache.demand_miss_rate::total     0.063749                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001009                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010606                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::total     0.063749                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84642.857143                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        83000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 84277.777778                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   192.775525                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   192.775525                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        82750                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        82750                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76422.426361                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76422.426361                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80080.452755                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80080.452755                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82705.316558                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82705.316558                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84642.857143                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80080.452755                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76962.471482                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77311.133903                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84642.857143                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80080.452755                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76962.471482                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77311.133903                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1011,167 +1018,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83215                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83215                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        83304                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83304                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        18063                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        12253                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        30325                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2714                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2714                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2713                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2713                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131035                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       131035                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131011                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131011                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        18023                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        18023                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12320                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12320                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        18063                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143288                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::total       161363                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        18063                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143288                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       161360                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        18023                       # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total       161363                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31142                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       635250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       140500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1231366500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    861613702                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2093755952                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     48365714                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       135000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       135000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8377798294                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8377798294                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       635250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       140500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1231366500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9239411996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10471554246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       635250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       140500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1231366500                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total  10471554246                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    546237750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5396778750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5943016500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4154268500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4154268500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    546237750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9551047250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10097285000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001029                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010631                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.023335                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013571                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991597                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991597                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58736                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67758                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       522500                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total       668500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     56418000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     56418000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       139000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8702068500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8702068500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1263060000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1263060000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    895729500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    895729500                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9597798000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5518638500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6082837500                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9773900000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10338099000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001009                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000854                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991594                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991594                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442752                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442752                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001029                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010631                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.174520                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063766                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001029                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010631                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.174520                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063766                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        90750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        70250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        90750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        70250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        90750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        70250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010606                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010606                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010606                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.174503                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063749                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000556                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010606                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.174503                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063749                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2291655                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2291640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       683915                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2737                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          67206                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2292179                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27594                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27594                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       801878                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1805693                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2736                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2739                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295956                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295956                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3416297                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2449150                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12768                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5902843                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108779512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96514397                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14212                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27220                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205335341                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       53413                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3338113                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.019032                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.136637                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2738                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295966                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295966                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699351                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       525637                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5084414                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2579570                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12812                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24764                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7701560                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108793272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96436737                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14388                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27748                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205272145                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      179423                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5300588                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.035792                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.185771                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3274582     98.10%     98.10% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              63531      1.90%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5110870     96.42%     96.42% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             189718      3.58%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3338113                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2348519500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5300588                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3265127000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       328500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2563126749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2558048500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1308606460                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1278361999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       9215000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      17823250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      17827000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1262,23 +1279,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198904691                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187438974                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36849506                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.079220                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.134160                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         309085643000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.079220                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067451                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067451                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         299040065000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.134160                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.070885                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.070885                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1286,49 +1303,49 @@ system.iocache.tags.tag_accesses               328122                       # Nu
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28886876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28886876                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6649316309                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6649316309                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28886876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28886876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28886876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28886876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28776877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28776877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4271537097                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4271537097                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28776877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28776877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28776877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28776877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123448.188034                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123448.188034                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123448.188034                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123448.188034                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123448.188034                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22762                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122978.106838                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 122978.106838                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122978.106838                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 122978.106838                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122978.106838                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3430                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.636152                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1336,88 +1353,90 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16499876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16499876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4765656321                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4765656321                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16499876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16499876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16499876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16499876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17076877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17076877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460337097                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2460337097                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17076877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17076877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17076877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17076877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70512.290598                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70512.290598                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72978.106838                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72978.106838                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               70719                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70719                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
-system.membus.trans_dist::Writeback            119405                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4508                       # Transaction distribution
+system.membus.trans_dist::ReadReq               40164                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70750                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27594                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27594                       # Transaction distribution
+system.membus.trans_dist::Writeback            119494                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6493                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4509                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4510                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129241                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129241                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129215                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129215                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30586                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       438994                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       546586                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 655473                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2122                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       445567                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 662077                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15576124                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15739477                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20374933                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15581884                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15745273                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18062393                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              498                       # Total snoops (count)
-system.membus.snoop_fanout::samples            387734                       # Request fanout histogram
+system.membus.snoop_fanout::samples            394512                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  387734    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  394512    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              387734                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90499500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              394512                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90495000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1700000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1709000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           980923653                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           834776313                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          964658040                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          964479239                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37509494                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64484992                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 2cf9c3fee..948865e8c 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,70 +4,70 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 898221                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1093441                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17514028577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560944                       # Number of bytes of host memory used
-host_seconds                                   158.95                       # Real time elapsed on the host
+host_inst_rate                                1197854                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1458195                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23356431621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 621348                       # Number of bytes of host memory used
+host_seconds                                   119.19                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           728356                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4660384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           725796                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4660896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           482432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5667588                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           481216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5663620                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11540232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       728356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       482432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8837184                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11533000                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       725796                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       481216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8840512                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8854708                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858036                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             19834                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             19794                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73345                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7538                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             88557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7519                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             88495                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189289                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138081                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                189176                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138133                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142462                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142514                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           115                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              261635                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1674068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              260715                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1674252                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              173296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2035869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              172859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2034443                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4145396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         261635                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         173296                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3174427                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         260715                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         172859                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175623                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6292                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3180722                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3174427                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3181918                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175623                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          115                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             261635                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1680360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             260715                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1680544                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             173296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2035872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             172859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2034446                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7326119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7324716                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -393,8 +393,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       682283                       # number of writebacks
-system.cpu0.dcache.writebacks::total           682283                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       682264                       # number of writebacks
+system.cpu0.dcache.writebacks::total           682264                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          1699214                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.663681                       # Cycle average of tags in use
@@ -661,8 +661,7 @@ system.cpu1.kern.inst.quiesce                       0                       # nu
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22778                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -729,24 +728,24 @@ system.iocache.tags.tag_accesses               328176                       # Nu
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          240                       # number of overall misses
 system.iocache.overall_misses::total              240                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -762,28 +761,28 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   110020                       # number of replacements
-system.l2c.tags.tagsinuse                65155.309107                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2731325                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   175301                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    15.580772                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   109907                       # number of replacements
+system.l2c.tags.tagsinuse                65155.309141                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4567770                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   175188                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    26.073532                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48893.438134                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   48764.072075                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924326                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5044.354241                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4729.333214                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5143.224775                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4734.504525                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.978702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4020.194257                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2464.086137                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.746055                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu1.inst     4025.377664                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2484.226979                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.744081                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.076971                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.072164                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.078479                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.072243                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061343                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037599                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061422                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.037906                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.994191                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65277                       # Occupied blocks per task id
@@ -791,90 +790,90 @@ system.l2c.tags.age_task_id_blocks_1023::4            4                       #
 system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        10699                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        50642                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.996048                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26231874                       # Number of tag accesses
-system.l2c.tags.data_accesses                26231874                       # Number of data accesses
+system.l2c.tags.tag_accesses                 40922425                       # Number of tag accesses
+system.l2c.tags.data_accesses                40922425                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         4700                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         2287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             833711                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             246358                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker         5001                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.itb.walker         2453                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             847646                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             259121                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2201277                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          682283                       # number of Writeback hits
-system.l2c.Writeback_hits::total               682283                       # number of Writeback hits
+system.l2c.ReadReq_hits::total                  14441                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          682264                       # number of Writeback hits
+system.l2c.Writeback_hits::total               682264                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              15                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::cpu0.data            72515                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            78543                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               151058                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            78631                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               151146                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        833751                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        847665                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1681416                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       246350                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       259095                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           505445                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.dtb.walker          4700                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker          2287                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              833711                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              318873                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              833751                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              318865                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.dtb.walker          5001                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.itb.walker          2453                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              847646                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              337664                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2352335                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              847665                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              337726                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2352448                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker         4700                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker         2287                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             833711                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             318873                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             833751                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             318865                       # number of overall hits
 system.l2c.overall_hits::cpu1.dtb.walker         5001                       # number of overall hits
 system.l2c.overall_hits::cpu1.itb.walker         2453                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             847646                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             337664                       # number of overall hits
-system.l2c.overall_hits::total                2352335                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             847665                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             337726                       # number of overall hits
+system.l2c.overall_hits::total                2352448                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            10819                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             9770                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             7538                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             5759                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                33894                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                    8                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data          1249                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data          1479                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2728                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data          63964                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          83900                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             147864                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          83812                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             147776                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        10779                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         7519                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           18298                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         9778                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         5785                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total          15563                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             10819                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             73734                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             10779                       # number of demand (read+write) misses
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 system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              7538                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             89659                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                181758                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              7519                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             89597                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                181645                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            10819                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            73734                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            10779                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            73742                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             7538                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            89659                       # number of overall misses
-system.l2c.overall_misses::total               181758                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             7519                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            89597                       # number of overall misses
+system.l2c.overall_misses::total               181645                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu0.dtb.walker         4705                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker         2288                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         844530                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         256128                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker         5003                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker         2453                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         855184                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         264880                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2235171                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       682283                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           682283                       # number of Writeback accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              14449                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       682264                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           682264                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         1262                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         1494                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            2756                       # number of UpgradeReq accesses(hits+misses)
@@ -883,6 +882,12 @@ system.l2c.SCUpgradeReq_accesses::total             2                       # nu
 system.l2c.ReadExReq_accesses::cpu0.data       136479                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data       162443                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           298922                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       844530                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       855184                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1699714                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       256128                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       264880                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.dtb.walker         4705                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.itb.walker         2288                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.inst          844530                       # number of demand (read+write) accesses
@@ -903,36 +908,38 @@ system.l2c.overall_accesses::cpu1.data         427323                       # nu
 system.l2c.overall_accesses::total            2534093                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.012811                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.038145                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.008814                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.021742                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015164                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.000554                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989699                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989960                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.989840                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.468673                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.516489                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.494657                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.515947                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.494363                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.012763                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008792                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.038176                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021840                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.029871                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.012811                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.187806                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.012763                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.187827                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.008814                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.209816                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.071725                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008792                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.209670                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.071680                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.012811                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.187806                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.012763                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.187827                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008814                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.209816                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.071725                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008792                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.209670                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.071680                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -941,49 +948,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              101891                       # number of writebacks
-system.l2c.writebacks::total                   101891                       # number of writebacks
+system.l2c.writebacks::writebacks              101943                       # number of writebacks
+system.l2c.writebacks::total                   101943                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74221                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74221                       # Transaction distribution
+system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74196                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::Writeback            138081                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::Writeback            138133                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8204                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            145997                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           145997                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34109                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105404                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       498773                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       606133                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 715251                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       506563                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       613923                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723281                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18095548                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18258521                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22908377                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18091644                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18254617                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586137                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            426666                       # Request fanout histogram
+system.membus.snoop_fanout::samples            434809                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  426666    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  434809    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              426666                       # Request fanout histogram
+system.membus.snoop_fanout::total              434809                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1015,37 +1024,40 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2291984                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              71244                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp           2291984                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27546                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27546                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           682283                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           682264                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1836352                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2756                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2758                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq           298922                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp          298922                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3417508                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2444881                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq       1699732                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5116722                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2582000                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20804                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41510                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5924703                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7761036                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108818936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96324385                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96323169                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41608                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83020                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              205267949                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205266733                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                           36631                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3339957                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.020246                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.140841                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples          5176290                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.013064                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.113547                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3272336     97.98%     97.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  67621      2.02%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5108669     98.69%     98.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  67621      1.31%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3339957                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            5176290                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 5b65637a2..505a1af3b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.903641                       # Number of seconds simulated
-sim_ticks                                2903640922500                       # Number of ticks simulated
-final_tick                               2903640922500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.903518                       # Number of seconds simulated
+sim_ticks                                2903517798500                       # Number of ticks simulated
+final_tick                               2903517798500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 541770                       # Simulator instruction rate (inst/s)
-host_op_rate                                   653210                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13988619879                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 561968                       # Number of bytes of host memory used
-host_seconds                                   207.57                       # Real time elapsed on the host
-sim_insts                                   112456119                       # Number of instructions simulated
-sim_ops                                     135587804                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 707460                       # Simulator instruction rate (inst/s)
+host_op_rate                                   852978                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18263496849                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 621100                       # Number of bytes of host memory used
+host_seconds                                   158.98                       # Real time elapsed on the host
+sim_insts                                   112471533                       # Number of instructions simulated
+sim_ops                                     135605825                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           582564                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          3808480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           588836                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          3938784                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           602944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5025476                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           600704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5102020                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10021000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       582564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       602944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1185508                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7434688                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10231944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       588836                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       600704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1189540                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7646016                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7452212                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7663540                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             17556                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             60026                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             17654                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             62062                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9421                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             78524                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9386                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             79720                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165551                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116167                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                168847                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          119469                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120548                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               123850                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              200632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1311622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              202801                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1356556                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              207651                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1730750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              206888                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1757186                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3451184                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         200632                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         207651                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             408283                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2560471                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6032                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3523982                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         202801                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         206888                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             409689                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2633363                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6033                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2566506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2560471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2639398                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2633363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             200632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1317655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             202801                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1362589                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             207651                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1730753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             206888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1757188                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6017690                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165551                       # Number of read requests accepted
-system.physmem.writeReqs                       156772                       # Number of write requests accepted
-system.physmem.readBursts                      165551                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     156772                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10588736                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8522624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10021000                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9770548                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   23601                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4489                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9899                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9526                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9759                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9793                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18999                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10033                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10462                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10803                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9925                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10243                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9858                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9250                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9247                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9475                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9028                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9149                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8258                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8244                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8572                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8149                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8563                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8536                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8718                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9117                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8657                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8771                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8610                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7990                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7949                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7964                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7531                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7537                       # Per bank write bursts
+system.physmem.bw_total::total                6163380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168847                       # Number of read requests accepted
+system.physmem.writeReqs                       123850                       # Number of write requests accepted
+system.physmem.readBursts                      168847                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123850                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10798016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7677504                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10231944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7663540                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40733                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10014                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9659                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10299                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9948                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18863                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10091                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10301                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10599                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9915                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10209                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9947                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9027                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9869                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10471                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9980                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9527                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7419                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7262                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8122                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7539                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7355                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7348                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7576                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7905                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7603                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7846                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7540                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6940                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7394                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7835                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7358                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6919                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          32                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2903640597500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2903517476500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  155979                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159275                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 152391                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164623                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       272                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 119469                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167922                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       537                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       248                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -161,183 +161,178 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       195                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      164                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5453                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        57876                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      330.211072                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     191.290947                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     346.940345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          20714     35.79%     35.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14256     24.63%     60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5208      9.00%     69.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3123      5.40%     74.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2440      4.22%     79.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1489      2.57%     81.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1071      1.85%     83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1111      1.92%     85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8464     14.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          57876                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5262                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        31.441087                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      579.786182                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5260     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::14                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6093                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8840                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6966                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        59278                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.674753                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     182.487125                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.482596                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21806     36.79%     36.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14989     25.29%     62.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5586      9.42%     71.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3267      5.51%     77.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2330      3.93%     80.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1628      2.75%     83.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1108      1.87%     85.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1064      1.79%     87.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7500     12.65%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          59278                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5882                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.683781                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      547.352228                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5880     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5262                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5262                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.307108                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.699141                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       47.946490                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15               45      0.86%      0.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4897     93.06%     93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              79      1.50%     95.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              16      0.30%     95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              14      0.27%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              19      0.36%     96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             31      0.59%     96.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            27      0.51%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            13      0.25%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159             8      0.15%     97.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             3      0.06%     97.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            23      0.44%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            14      0.27%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            10      0.19%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             3      0.06%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             3      0.06%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.06%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             4      0.08%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             8      0.15%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             4      0.08%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.06%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             5      0.10%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             8      0.15%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             1      0.02%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.02%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             3      0.06%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.06%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             3      0.06%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-623             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5262                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1437662314                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4539831064                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    827245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8689.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5882                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5882                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.394594                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.624984                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.894436                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                16      0.27%      0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 8      0.14%      0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                7      0.12%      0.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              10      0.17%      0.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4921     83.66%     84.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              66      1.12%     85.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             241      4.10%     89.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              88      1.50%     91.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              77      1.31%     92.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             178      3.03%     95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.24%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.12%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.15%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              13      0.22%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.09%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             174      2.96%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.07%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.05%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.05%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.24%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5882                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1493162250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4656643500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    843595000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8849.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27439.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.65                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.94                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.45                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.36                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27599.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.72                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.50                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     136363                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    104375                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.42                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9008480.93                       # Average gap between requests
-system.physmem.pageHitRate                      80.62                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  229453560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125197875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 696337200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                441657360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           189651686640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86953063950                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1665909868500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1944007265085                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.506799                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2771232360210                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     96958940000                       # Time in different power states
+system.physmem.avgWrQLen                        12.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138806                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90595                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.27                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.52                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9919874.40                       # Average gap between requests
+system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  229302360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125115375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 700237200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392208480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           189643549680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            87298782345                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1665531858750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1943921054190                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.505834                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2770598960250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     96954780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35449523540                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     35962503500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  208089000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  113540625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 594157200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                421258320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           189651686640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            84877892595                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1667730194250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1943596818630                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.365444                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2774279366726                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     96958940000                       # Time in different power states
+system.physmem_1.actEnergy                  218839320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119406375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 615763200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385138800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           189643549680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            86123693430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1666562638500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1943669029305                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.419034                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2772326743250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     96954780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     32402517024                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34236177250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -387,56 +382,60 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     6899                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                6899                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2220                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4679                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         6899                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           6899    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         6899                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         5841                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6688.963614                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         4458     76.32%     76.32% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1381     23.64%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         5841                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    937449500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      937449500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    937449500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3645     62.40%     62.40% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         2196     37.60%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5841                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6899                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                     6827                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                6827                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2216                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4610                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples         6826                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           6826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         6826                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         5786                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6703.217150                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         4631     80.04%     80.04% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1152     19.91%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-180223            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         5786                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  -1209080312                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.765375                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      925400000    -76.54%    -76.54% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -2134480312    176.54%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  -1209080312                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3595     62.14%     62.14% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         2190     37.86%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5785                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6827                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6899                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5841                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6827                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5785                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5841                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        12740                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5785                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        12612                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12462635                       # DTB read hits
-system.cpu0.dtb.read_misses                      5988                       # DTB read misses
-system.cpu0.dtb.write_hits                    9832923                       # DTB write hits
-system.cpu0.dtb.write_misses                      911                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2938                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     496                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    12507441                       # DTB read hits
+system.cpu0.dtb.read_misses                      5917                       # DTB read misses
+system.cpu0.dtb.write_hits                    9856816                       # DTB write hits
+system.cpu0.dtb.write_misses                      910                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2937                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     486                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    4660                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    4603                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   940                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   884                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      240                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12468623                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9833834                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      232                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12513358                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9857726                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         22295558                       # DTB hits
-system.cpu0.dtb.misses                           6899                       # DTB misses
-system.cpu0.dtb.accesses                     22302457                       # DTB accesses
+system.cpu0.dtb.hits                         22364257                       # DTB hits
+system.cpu0.dtb.misses                           6827                       # DTB misses
+system.cpu0.dtb.accesses                     22371084                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -466,456 +465,457 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3577                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3577                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          835                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2742                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3577                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3577    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3577                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2726                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6704.748097                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          633     23.22%     23.22% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1408     51.65%     74.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          683     25.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     3521                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3521                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          830                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2691                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3521                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3521    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3521                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2670                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6917.920498                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          769     28.80%     28.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1283     48.05%     76.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          616     23.07%     99.93% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2726                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    937122000                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      937122000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    937122000                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1891     69.37%     69.37% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          835     30.63%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2726                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2670                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    925066000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      925066000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    925066000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1840     68.91%     68.91% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          830     31.09%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2670                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3577                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3577                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3521                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3521                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2726                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2726                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6303                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    58414032                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3577                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2670                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2670                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6191                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    58595537                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3521                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2938                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     496                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                        2937                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     486                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2760                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2691                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                58417609                       # ITB inst accesses
-system.cpu0.itb.hits                         58414032                       # DTB hits
-system.cpu0.itb.misses                           3577                       # DTB misses
-system.cpu0.itb.accesses                     58417609                       # DTB accesses
-system.cpu0.numCycles                      2904051621                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                58599058                       # ITB inst accesses
+system.cpu0.itb.hits                         58595537                       # DTB hits
+system.cpu0.itb.misses                           3521                       # DTB misses
+system.cpu0.itb.accesses                     58599058                       # DTB accesses
+system.cpu0.numCycles                      2904052506                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   56844590                       # Number of instructions committed
-system.cpu0.committedOps                     68476862                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             60556147                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5891                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5072041                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7664286                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    60556147                       # number of integer instructions
-system.cpu0.num_fp_insts                         5891                       # number of float instructions
-system.cpu0.num_int_register_reads          110162183                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41899351                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4609                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1284                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           247668564                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           26017746                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     22952183                       # number of memory refs
-system.cpu0.num_load_insts                   12628752                       # Number of load instructions
-system.cpu0.num_store_insts                  10323431                       # Number of store instructions
-system.cpu0.num_idle_cycles              2690582406.498001                       # Number of idle cycles
-system.cpu0.num_busy_cycles              213469214.501999                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.073507                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.926493                       # Percentage of idle cycles
-system.cpu0.Branches                         13135796                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2207      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 47055843     67.15%     67.15% # Class of executed instruction
-system.cpu0.op_class::IntMult                   59396      0.08%     67.24% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4431      0.01%     67.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.25% # Class of executed instruction
-system.cpu0.op_class::MemRead                12628752     18.02%     85.27% # Class of executed instruction
-system.cpu0.op_class::MemWrite               10323431     14.73%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   57017963                       # Number of instructions committed
+system.cpu0.committedOps                     68702056                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             60736686                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5415                       # Number of float alu accesses
+system.cpu0.num_func_calls                    5101109                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7710665                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    60736686                       # number of integer instructions
+system.cpu0.num_fp_insts                         5415                       # number of float instructions
+system.cpu0.num_int_register_reads          110496547                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          42022968                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4193                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           248490103                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           26091255                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     23020484                       # number of memory refs
+system.cpu0.num_load_insts                   12672781                       # Number of load instructions
+system.cpu0.num_store_insts                  10347703                       # Number of store instructions
+system.cpu0.num_idle_cycles              2689228469.175671                       # Number of idle cycles
+system.cpu0.num_busy_cycles              214824036.824329                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.073974                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.926026                       # Percentage of idle cycles
+system.cpu0.Branches                         13203328                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2205      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 47217639     67.16%     67.16% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59885      0.09%     67.25% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.25% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4420      0.01%     67.26% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.26% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.26% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.26% # Class of executed instruction
+system.cpu0.op_class::MemRead                12672781     18.03%     85.28% # Class of executed instruction
+system.cpu0.op_class::MemWrite               10347703     14.72%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  70074060                       # Class of executed instruction
+system.cpu0.op_class::total                  70304633                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3032                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           821716                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.827808                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43234238                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           822228                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            52.581812                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1008982250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   377.484524                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   134.343284                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.737274                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.262389                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999664                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    3029                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           820099                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.829843                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43241744                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           820611                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.694570                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        996611500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   401.515698                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   110.314145                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.784210                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.215457                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999668                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          373                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        177115546                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       177115546                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11742107                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     11368313                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23110420                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9438605                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      9386535                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18825140                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200385                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       191808                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       392193                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       230728                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       212742                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       443470                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       239351                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       220930                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460281                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     21180712                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20754848                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41935560                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     21381097                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     20946656                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       42327753                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       202379                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       199779                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       402158                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       143306                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       155169                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       298475                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        60388                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        58192                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       118580                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        11633                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        10971                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22604                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        177137427                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       177137427                       # Number of data accesses
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
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-system.cpu0.dcache.overall_misses::total       819213                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2998718242                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2978169130                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5976887372                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5523492960                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6886936529                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  12410429489                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    144593750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    135344000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    279937750                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total    281291500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       164000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
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-system.cpu0.dcache.overall_miss_latency::cpu0.data   8522211202                       # number of overall miss cycles
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9581911                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::total     19123615                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       260773                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       250000                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       510773                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       242361                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       223713                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       466074                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       239353                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       220930                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::cpu0.data     21526397                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     21109796                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     42636193                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     21787170                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     21359796                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     43146966                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016943                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017270                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.017104                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014956                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.016262                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015608                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.231573                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.232768                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.232158                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047999                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049041                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048499                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8634810000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   9881380000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  18516190000                       # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::cpu1.data   9881380000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  18516190000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11988820                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_accesses::total       511021                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       223273                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       466162                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       220488                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460381                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::total     42641631                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     21854341                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     21298311                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     43152652                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016908                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017170                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.017036                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014948                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.016285                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.015614                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228144                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.234831                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231423                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047680                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049715                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048655                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016059                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016814                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.016433                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018638                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019342                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.018987                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016036                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016770                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.016398                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018564                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019335                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.018945                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14855.663924                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14905.012606                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14880.043682                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39166.370664                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44706.658239                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 42042.831884                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12453.976341                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12347.927928                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12402.076628                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs           57                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24935.630869                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27995.591593                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 26480.222983                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21283.889208                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23994.939426                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 22649.552053                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       687030                       # number of writebacks
-system.cpu0.dcache.writebacks::total           687030                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          287                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          373                       # number of ReadReq MSHR hits
+system.cpu0.dcache.writebacks::writebacks       683625                       # number of writebacks
+system.cpu0.dcache.writebacks::total           683625                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          291                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          369                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_hits::total          660                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7066                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7026                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14092                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          287                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          373                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7077                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7054                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14131                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          291                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          369                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_hits::total          660                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          287                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          373                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          291                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          369                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_hits::total          660                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       202092                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       199406                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       401498                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       143306                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       155169                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       298475                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        59468                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57033                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       116501                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4567                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         3945                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8512                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       202413                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       197552                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       399965                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       143580                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       155041                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       298621                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58532                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57717                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       116249                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4504                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4046                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8550                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       345398                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       354575                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       699973                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       404866                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       411608                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       816474                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15569                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15573                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31142                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15798                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11796                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27594                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31367                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        27369                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58736                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2687850000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2671783250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5359633250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5284681040                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6621405971                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11906087011                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    749127008                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    719245636                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1468372644                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     55884250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     49619250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    105503500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7972531040                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9293189221                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  17265720261                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8721658048                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10012434857                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  18734092905                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2822172000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3011105500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5833277500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2259926000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2253271000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4513197000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5082098000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5264376500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10346474500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016919                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017238                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017076                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014956                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.016262                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015608                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228045                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.228132                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228088                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018844                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.017634                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018263                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       345993                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       352593                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       698586                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       404525                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       410310                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       814835                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15867                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15271                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15968                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11621                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31835                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26892                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2803165500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2746358000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5549523500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5479927500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6776324000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12256251500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    768422500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    755594500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1524017000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     57248500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52551500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    109800000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       162000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8283093000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9522682000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  17805775000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9051515500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10278276500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  19329792000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2904028500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3003756000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5907784500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2320925500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2251479500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4572405000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5224954000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5255235500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10480189500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016883                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017138                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017008                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014948                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.016285                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015614                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224761                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.230313                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227484                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018543                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018121                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018341                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000008                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016045                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016797                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016417                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018583                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019270                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018923                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016023                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016752                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016383                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018510                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019265                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018883                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        81000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25050.026809                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23722.338878                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183023.161278                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196696.745465                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189729.093070                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145348.540832                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 193742.319938                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165732.900794                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164126.087639                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 195420.031980                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178456.067907                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1701384                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.734068                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          113852033                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1701896                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            66.897174                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      25697074250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   399.197143                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   111.536926                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.779682                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.217846                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997527                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1697906                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.737364                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          113870601                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1698418                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.045098                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      25672110500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   416.223441                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    94.513923                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.812936                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.184598                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997534                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          251                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        117255837                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       117255837                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     57557381                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     56294652                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      113852033                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     57557381                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     56294652                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       113852033                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     57557381                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     56294652                       # number of overall hits
-system.cpu0.icache.overall_hits::total      113852033                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       856651                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       845251                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1701902                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       856651                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       845251                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1701902                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       856651                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       845251                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1701902                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11730914498                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11646451999                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  23377366497                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11730914498                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  11646451999                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  23377366497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11730914498                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  11646451999                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  23377366497                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     58414032                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     57139903                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115553935                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     58414032                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     57139903                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115553935                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     58414032                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     57139903                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115553935                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014665                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014793                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014728                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014665                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014793                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014728                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014665                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014793                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014728                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13736.023870                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13736.023870                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        117267449                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       117267449                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     57739156                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     56131445                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      113870601                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     57739156                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     56131445                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       113870601                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     57739156                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     56131445                       # number of overall hits
+system.cpu0.icache.overall_hits::total      113870601                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       856381                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       842043                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1698424                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       856381                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       842043                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1698424                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       856381                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       842043                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1698424                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11736376500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11602280500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  23338657000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11736376500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  11602280500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  23338657000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11736376500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  11602280500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  23338657000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     58595537                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     56973488                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115569025                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     58595537                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     56973488                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115569025                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     58595537                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     56973488                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115569025                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014615                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014780                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014696                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014615                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014780                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014696                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014615                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014780                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014696                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13704.620373                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.726858                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13741.360814                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13704.620373                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.726858                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13741.360814                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13704.620373                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.726858                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13741.360814                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -924,54 +924,54 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       856651                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       845251                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1701902                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       856651                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       845251                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1701902                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       856651                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       845251                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1701902                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       856381                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       842043                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1698424                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       856381                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       842043                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1698424                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       856381                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       842043                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1698424                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10442855002                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10375133501                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  20817988503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10442855002                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10375133501                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  20817988503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10442855002                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10375133501                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  20817988503                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    677067750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    677067750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    677067750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    677067750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014665                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014793                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014728                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014665                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014793                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014728                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014665                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014793                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014728                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10879995500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10760237500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  21640233000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10879995500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10760237500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  21640233000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10879995500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10760237500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  21640233000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    676974000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    676974000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    676974000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    676974000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014696                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014696                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014696                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12741.360814                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1002,60 +1002,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     6646                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                6646                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1848                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4797                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walks                     6604                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6604                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1835                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4768                       # Level at which table walker walks with short descriptors terminate
 system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples         6645                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           6645    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         6645                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5540                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6654.820556                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         1371     24.75%     24.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2761     49.84%     74.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1405     25.36%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::samples         6603                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6603    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6603                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5481                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6472.015315                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         1651     30.12%     30.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2769     50.52%     80.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1058     19.30%     99.95% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.05%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5540                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   -586099820                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     2.706592                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkCompletionTime::total         5481                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1004634564                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     1.995586                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1000233500   -170.66%   -170.66% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    -1586333320    270.66%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   -586099820                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3714     67.05%     67.05% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1825     32.95%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5539                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6646                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walksPending::0     1000200000    -99.56%    -99.56% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -2004834564    199.56%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1004634564                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3666     66.90%     66.90% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1814     33.10%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5480                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6604                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6646                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5539                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6604                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5480                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5539                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        12185                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5480                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        12084                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12057381                       # DTB read hits
-system.cpu1.dtb.read_misses                      5757                       # DTB read misses
-system.cpu1.dtb.write_hits                    9774636                       # DTB write hits
-system.cpu1.dtb.write_misses                      889                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2932                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     421                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    12016469                       # DTB read hits
+system.cpu1.dtb.read_misses                      5667                       # DTB read misses
+system.cpu1.dtb.write_hits                    9752712                       # DTB write hits
+system.cpu1.dtb.write_misses                      937                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2933                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     431                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    4087                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    4084                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1001                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   937                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      205                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12063138                       # DTB read accesses
-system.cpu1.dtb.write_accesses                9775525                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12022136                       # DTB read accesses
+system.cpu1.dtb.write_accesses                9753649                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         21832017                       # DTB hits
-system.cpu1.dtb.misses                           6646                       # DTB misses
-system.cpu1.dtb.accesses                     21838663                       # DTB accesses
+system.cpu1.dtb.hits                         21769181                       # DTB hits
+system.cpu1.dtb.misses                           6604                       # DTB misses
+system.cpu1.dtb.accesses                     21775785                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1085,124 +1085,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     3230                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                3230                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          673                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walks                     3234                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3234                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          677                       # Level at which table walker walks with short descriptors terminate
 system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2557                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         3230                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           3230    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         3230                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2426                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6275.492791                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::2048-4095          541     22.30%     22.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          673     27.74%     50.04% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335          619     25.52%     75.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-22527          528     21.76%     97.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575           65      2.68%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2426                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1000198000                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1000198000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1000198000                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1753     72.26%     72.26% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          673     27.74%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2426                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkWaitTime::samples         3234                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3234    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3234                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2430                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6613.791032                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          712     29.30%     29.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.04%     29.34% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          673     27.70%     57.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335          477     19.63%     76.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383           16      0.66%     77.33% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          551     22.67%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2430                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1000178000                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000178000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000178000                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1753     72.14%     72.14% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          677     27.86%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2430                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3230                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3230                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3234                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3234                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2426                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2426                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         5656                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    57139903                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3230                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2430                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2430                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         5664                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    56973488                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3234                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2932                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     421                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                        2933                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     431                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2427                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2428                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                57143133                       # ITB inst accesses
-system.cpu1.itb.hits                         57139903                       # DTB hits
-system.cpu1.itb.misses                           3230                       # DTB misses
-system.cpu1.itb.accesses                     57143133                       # DTB accesses
-system.cpu1.numCycles                      2903230224                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                56976722                       # ITB inst accesses
+system.cpu1.itb.hits                         56973488                       # DTB hits
+system.cpu1.itb.misses                           3234                       # DTB misses
+system.cpu1.itb.accesses                     56976722                       # DTB accesses
+system.cpu1.numCycles                      2902983091                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   55611529                       # Number of instructions committed
-system.cpu1.committedOps                     67110942                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             59336824                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5270                       # Number of float alu accesses
-system.cpu1.num_func_calls                    4819801                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      7566653                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    59336824                       # number of integer instructions
-system.cpu1.num_fp_insts                         5270                       # number of float instructions
-system.cpu1.num_int_register_reads          107900734                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          40745080                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3840                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1432                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           242074272                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           25879956                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     22456627                       # number of memory refs
-system.cpu1.num_load_insts                   12214155                       # Number of load instructions
-system.cpu1.num_store_insts                  10242472                       # Number of store instructions
-system.cpu1.num_idle_cycles              2696428184.778518                       # Number of idle cycles
-system.cpu1.num_busy_cycles              206802039.221482                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.071232                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.928768                       # Percentage of idle cycles
-system.cpu1.Branches                         12781357                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                  130      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 46119057     67.20%     67.20% # Class of executed instruction
-system.cpu1.op_class::IntMult                   54779      0.08%     67.28% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4036      0.01%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.28% # Class of executed instruction
-system.cpu1.op_class::MemRead                12214155     17.80%     85.08% # Class of executed instruction
-system.cpu1.op_class::MemWrite               10242472     14.92%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   55453570                       # Number of instructions committed
+system.cpu1.committedOps                     66903769                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             59172733                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5746                       # Number of float alu accesses
+system.cpu1.num_func_calls                    4791563                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      7521701                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    59172733                       # number of integer instructions
+system.cpu1.num_fp_insts                         5746                       # number of float instructions
+system.cpu1.num_int_register_reads          107592864                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          40634379                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4256                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           241317525                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           25809860                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     22393766                       # number of memory refs
+system.cpu1.num_load_insts                   12173697                       # Number of load instructions
+system.cpu1.num_store_insts                  10220069                       # Number of store instructions
+system.cpu1.num_idle_cycles              2697480671.520393                       # Number of idle cycles
+system.cpu1.num_busy_cycles              205502419.479607                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.070790                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.929210                       # Percentage of idle cycles
+system.cpu1.Branches                         12715726                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  132      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 45969122     67.18%     67.19% # Class of executed instruction
+system.cpu1.op_class::IntMult                   54656      0.08%     67.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4033      0.01%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.27% # Class of executed instruction
+system.cpu1.op_class::MemRead                12173697     17.79%     85.06% # Class of executed instruction
+system.cpu1.op_class::MemWrite               10220069     14.94%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  68634629                       # Class of executed instruction
+system.cpu1.op_class::total                  68421709                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1293,23 +1293,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           198848287                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187451467                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36807005                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.134606                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.079135                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         299121172000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.134606                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.070913                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.070913                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         309074032000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.079135                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067446                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067446                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1317,49 +1317,49 @@ system.iocache.tags.tag_accesses               328122                       # Nu
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29267377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29267377                       # number of ReadReq miss cycles
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-system.iocache.WriteInvalidateReq_miss_latency::total   6633096905                       # number of WriteInvalidateReq miss cycles
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-system.iocache.overall_miss_latency::total     29267377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28776877                       # number of ReadReq miss cycles
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+system.iocache.WriteLineReq_miss_latency::realview.ide   4271859590                       # number of WriteLineReq miss cycles
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 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
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 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
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 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125074.260684                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125074.260684                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125074.260684                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125074.260684                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125074.260684                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22198                       # number of cycles access was blocked
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+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3387                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.553882                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1367,272 +1367,284 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
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-system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
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 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
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-system.l2c.tags.tagsinuse                64916.534496                       # Cycle average of tags in use
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-system.l2c.overall_miss_rate::cpu1.inst      0.011146                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.192187                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.062127                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        87250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        83000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 82769.621486                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 81110.010168                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   255.597160                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   318.304762                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   287.264151                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.396333                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.485711                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.442756                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010088                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011147                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010613                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.023104                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.023751                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.023424                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000693                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000723                       # miss rate for demand accesses
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   182.357302                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   192.817680                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 76295.089727                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        87250                       # average overall miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::total 80006.241331                       # average ReadCleanReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 76474.778476                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 76474.778476                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 77177.826952                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1641,221 +1653,231 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79977                       # number of writebacks
-system.l2c.writebacks::total                    79977                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            3                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               83279                       # number of writebacks
+system.l2c.writebacks::total                    83279                       # number of writebacks
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         8541                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         9421                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6147                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1338                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1365                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2703                       # number of UpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1349                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         8541                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15569                       # number of ReadReq MSHR uncacheable
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31367                       # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::total     48152203                       # number of UpgradeReq MSHR miss cycles
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-system.l2c.overall_mshr_uncacheable_latency::total  10097469500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000461                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000569                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009970                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.022455                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000643                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011146                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.023607                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.013388                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.988183                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.990566                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.989385                       # mshr miss rate for UpgradeReq accesses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31835                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26892                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       145500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total       801500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     28392000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28047500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     56439500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       139000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3757418500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4925762000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8683180500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    604558000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    657304500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1261862500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    446355500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    445666000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    892021500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       145500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    604558000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4203774000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    657304500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5371428000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  10837866000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       145500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    604558000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4203774000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    657304500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5371428000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  10837866000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    564199000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2705690000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2812868500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6082757500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2137293500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2117838000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4255131500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    564199000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4842983500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4930706500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10337889000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000577                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990573                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992642                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991600                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.383799                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.477609                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.432582                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000461                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000569                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009970                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.148150                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000643                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011146                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.192187                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.062127                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000461                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000569                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009970                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.148150                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000643                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011146                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.192187                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.062127                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 64693.110291                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        70000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 64693.110291                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.396333                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.485711                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.442756                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010613                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.023104                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.023751                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023424                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.153298                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.195653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063607                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.153298                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.195653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063607                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total        80150                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 67177.826952                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 67177.826952                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               70492                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70492                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27594                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27594                       # Transaction distribution
-system.membus.trans_dist::Writeback            116167                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4489                       # Transaction distribution
+system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70721                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
+system.membus.trans_dist::Writeback            119469                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6488                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4509                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4491                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            126147                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           126147                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129210                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129210                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30561                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       429068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       536678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 645565                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       445477                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       553069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 661969                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15156092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     15319481                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19954937                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15578364                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     15741717                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18058837                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              498                       # Total snoops (count)
-system.membus.snoop_fanout::samples            381147                       # Request fanout histogram
+system.membus.snoop_fanout::samples            394437                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  381147    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  394437    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              381147                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90494500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              394437                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90486000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1721500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1696500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           960656101                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           834684564                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          947025657                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          964305240                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           37465995                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64480996                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1888,50 +1910,53 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2303937                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2303837                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             27594                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            27594                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           687030                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36246                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2732                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              74970                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2298377                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           803098                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1802826                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2738                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2734                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295743                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295743                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3421816                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2454612                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18880                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        35749                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5931057                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108955768                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96785921                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50916                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              205819701                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           52269                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3353284                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.021354                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.144561                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp           2740                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295883                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295883                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1698424                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       524998                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5081680                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2577380                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18024                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34106                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7711190                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108733880                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96470557                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24084                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        45196                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205273717                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          180370                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5305015                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.037219                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.189299                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3281678     97.86%     97.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  71606      2.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5107565     96.28%     96.28% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 197450      3.72%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3353284                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2359229000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5305015                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3268607000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           201000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           328500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2567253247                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2556658000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1309775845                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1277273499                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          12106000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          12003000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          23020250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          22807000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 131e14cd8..fee5e3090 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,50 +4,50 @@ sim_seconds                                  5.112152                       # Nu
 sim_ticks                                5112152301500                       # Number of ticks simulated
 final_tick                               5112152301500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1219492                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2496566                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31160731508                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 598628                       # Number of bytes of host memory used
-host_seconds                                   164.06                       # Real time elapsed on the host
+host_inst_rate                                1340669                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2744641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34257071569                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654012                       # Number of bytes of host memory used
+host_seconds                                   149.23                       # Real time elapsed on the host
 sim_insts                                   200066731                       # Number of instructions simulated
 sim_ops                                     409580371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            854656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10616192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            853568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10615616                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11499584                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       854656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          854656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9265728                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9265728                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11497920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       853568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          853568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9269440                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9269440                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              13354                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             165878                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              13337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             165869                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                179681                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          144777                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144777                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                179655                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          144835                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               144835                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               167181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2076658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               166968                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2076545                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2249460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          167181                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             167181                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1812491                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1812491                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1812491                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 2249135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          166968                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             166968                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1813217                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1813217                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1813217                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              167181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2076658                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              166968                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2076545                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4061951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4062352                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.numCycles                      10224308568                       # number of cpu cycles simulated
@@ -176,8 +176,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1535783                       # number of writebacks
-system.cpu.dcache.writebacks::total           1535783                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1535779                       # number of writebacks
+system.cpu.dcache.writebacks::total           1535779                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         7749                       # number of replacements
 system.cpu.dtb_walker_cache.tags.tagsinuse     5.013997                       # Cycle average of tags in use
@@ -335,22 +335,22 @@ system.cpu.itb_walker_cache.cache_copies            0                       # nu
 system.cpu.itb_walker_cache.writebacks::writebacks          545                       # number of writebacks
 system.cpu.itb_walker_cache.writebacks::total          545                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           106219                       # number of replacements
+system.cpu.l2cache.tags.replacements           106193                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        64823.931305                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3459867                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           170177                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            20.330991                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.total_refs            4345511                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           170151                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            25.539145                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002478                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132289                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2455.813677                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.792375                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.135113                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2531.452775                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.791178                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.037473                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.159285                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.038627                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.159327                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.989135                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        63958                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
@@ -359,59 +359,62 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3349
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20908                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39411                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975922                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32212786                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32212786                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6656                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2896                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       779367                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1275199                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2064118                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1538781                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1538781                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         39306136                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39306136                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1538777                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1538777                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           21                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           21                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       179771                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       179771                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       179780                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       179780                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       779384                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       779384                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6656                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2896                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1275199                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1284751                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         6656                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2896                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       779367                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1454970                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2243889                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       779384                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1454979                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2243915                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         6656                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         2896                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       779367                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1454970                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2243889                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13355                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        32163                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        45524                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::cpu.inst       779384                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1454979                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2243915                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         1808                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         1808                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134650                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       134650                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       134641                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       134641                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13338                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        13338                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker            1                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        32163                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        32169                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        13355                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       166813                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        180174                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        13338                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       166804                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        180148                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        13355                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       166813                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       180174                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6657                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2901                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       792722                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307362                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2109642                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1538781                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1538781                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.inst        13338                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       166804                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       180148                       # number of overall misses
+system.cpu.l2cache.Writeback_accesses::writebacks      1538777                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1538777                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1829                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1829                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       314421                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       314421                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       792722                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       792722                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6657                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2901                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1307362                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1316920                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6657                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2901                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst       792722                       # number of demand (read+write) accesses
@@ -422,25 +425,26 @@ system.cpu.l2cache.overall_accesses::cpu.itb.walker         2901
 system.cpu.l2cache.overall_accesses::cpu.inst       792722                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1621783                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      2424063                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001724                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016847                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024601                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021579                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988518                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988518                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428247                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.428247                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428219                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.428219                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016826                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016826                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001724                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024601                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024427                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001724                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016847                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102858                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.074327                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016826                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102852                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.074317                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001724                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016847                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102858                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074327                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016826                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102852                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074317                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -449,47 +453,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98110                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98110                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98168                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98168                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       15971490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       13857337                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp      15971490                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13943                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13943                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1538781                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1538777                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       886676                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       314426                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       314426                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1585470                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32527769                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9455                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        20367                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          34143061                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       792735                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1321418                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2377686                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32613888                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        12496                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        25663                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          35029733                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50735040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227550521                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227550265                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       320000                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       730240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          279335801                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          279335545                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       49698                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     17890240                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.002757                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.052432                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples     18776912                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.002627                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.051183                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3           17840921     99.72%     99.72% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              49319      0.28%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3           18727593     99.74%     99.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              49319      0.26%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       17890240                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       18776912                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq             10012057                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            10012057                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57724                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              11004                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57724                       # Transaction distribution
 system.iobus.trans_dist::MessageReq              1696                       # Transaction distribution
 system.iobus.trans_dist::MessageResp             1696                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
@@ -556,24 +562,24 @@ system.iocache.tags.tag_accesses               428607                       # Nu
 system.iocache.tags.data_accesses              428607                       # Number of data accesses
 system.iocache.ReadReq_misses::pc.south_bridge.ide          903                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
 system.iocache.demand_misses::pc.south_bridge.ide          903                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               903                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          903                       # number of overall misses
 system.iocache.overall_misses::total              903                       # number of overall misses
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::pc.south_bridge.ide          903                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             903                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::pc.south_bridge.ide          903                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            903                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
@@ -589,49 +595,51 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq            13903764                       # Transaction distribution
-system.membus.trans_dist::ReadResp           13903764                       # Transaction distribution
+system.membus.trans_dist::ReadReq            13857337                       # Transaction distribution
+system.membus.trans_dist::ReadResp           13903747                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13943                       # Transaction distribution
-system.membus.trans_dist::Writeback            144777                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.membus.trans_dist::Writeback            144835                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9844                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             2546                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            2094                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            134369                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           134364                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            134360                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134355                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         46410                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1696                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1696                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20044316                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      7698244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462531                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28205091                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141913                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141913                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28350396                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       471480                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28214040                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       142814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28360246                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10028276                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio     15396485                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17791872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43216633                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6034560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6034560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                49257977                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17793920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43218681                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3044480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3044480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                46269945                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples          14247815                       # Request fanout histogram
+system.membus.snoop_fanout::samples          14257691                       # Request fanout histogram
 system.membus.snoop_fanout::mean             1.000119                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.010910                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.010906                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                14246119     99.99%     99.99% # Request fanout histogram
+system.membus.snoop_fanout::1                14255995     99.99%     99.99% # Request fanout histogram
 system.membus.snoop_fanout::2                    1696      0.01%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total            14247815                       # Request fanout histogram
+system.membus.snoop_fanout::total            14257691                       # Request fanout histogram
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 999af0daa..2f3799b17 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,124 +1,124 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.184750                       # Number of seconds simulated
-sim_ticks                                5184749789500                       # Number of ticks simulated
-final_tick                               5184749789500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.184733                       # Number of seconds simulated
+sim_ticks                                5184732721500                       # Number of ticks simulated
+final_tick                               5184732721500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 812427                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1566083                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32734861616                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 599680                       # Number of bytes of host memory used
-host_seconds                                   158.39                       # Real time elapsed on the host
-sim_insts                                   128677191                       # Number of instructions simulated
-sim_ops                                     248045844                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 808289                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1558079                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32570584041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654268                       # Number of bytes of host memory used
+host_seconds                                   159.18                       # Real time elapsed on the host
+sim_insts                                   128667033                       # Number of instructions simulated
+sim_ops                                     248022101                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            827904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9015040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            825344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9044928                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9871616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       827904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          827904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8126080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8126080                       # Number of bytes written to this memory
+system.physmem.bytes_read::total              9898944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       825344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          825344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8133056                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8133056                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12936                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140860                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12896                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141327                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                154244                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126970                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126970                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                154671                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          127079                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               127079                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               159681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1738761                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               159187                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1744531                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1903972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          159681                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             159681                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1567304                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1567304                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1567304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 1909249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          159187                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             159187                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1568655                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1568655                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1568655                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              159681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1738761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              159187                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1744531                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3471276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        154244                       # Number of read requests accepted
-system.physmem.writeReqs                       173690                       # Number of write requests accepted
-system.physmem.readBursts                      154244                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     173690                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9865536                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6080                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9446080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9871616                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               11116160                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       95                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   26079                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1619                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9927                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9220                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9906                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9744                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9716                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9338                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9475                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9515                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8926                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                9405                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9702                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9402                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9788                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10193                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9798                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10094                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9407                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8748                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9677                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9718                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9428                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9072                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8868                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9192                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8615                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8711                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9601                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9113                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9702                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9421                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9363                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8959                       # Per bank write bursts
+system.physmem.bw_total::total                3477903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        154671                       # Number of read requests accepted
+system.physmem.writeReqs                       127079                       # Number of write requests accepted
+system.physmem.readBursts                      154671                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     127079                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9888768                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8131392                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9898944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8133056                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          48348                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9772                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9412                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9829                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9622                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9563                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9720                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9664                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9219                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9313                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9431                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9415                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9985                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10194                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10163                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9855                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8316                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7960                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8144                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8236                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8504                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7731                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7974                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7835                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7118                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7555                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7609                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7637                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8092                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8095                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8240                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8007                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          68                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5184749726000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5184732588500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154244                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154671                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 173690                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150873                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2864                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        53                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        47                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        42                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 127079                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2887                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        48                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        40                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
@@ -152,194 +152,189 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     3046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     3049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     2755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      127                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        57050                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      338.502226                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     199.067588                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     346.604467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19329     33.88%     33.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13844     24.27%     58.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5928     10.39%     68.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3298      5.78%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2346      4.11%     78.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1576      2.76%     81.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1245      2.18%     83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          971      1.70%     85.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8513     14.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          57050                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5294                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.117303                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      658.027323                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5293     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2360                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2863                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6760                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        55882                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      322.466912                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     190.971568                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.231986                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19566     35.01%     35.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13855     24.79%     59.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5752     10.29%     70.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3280      5.87%     75.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2436      4.36%     80.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1597      2.86%     83.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1106      1.98%     85.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          958      1.71%     86.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7332     13.12%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          55882                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5902                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.177906                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      623.301246                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5901     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5294                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5294                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.879675                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.284410                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       52.982511                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            4909     92.73%     92.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              99      1.87%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              16      0.30%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79               5      0.09%     94.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              10      0.19%     95.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             12      0.23%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            21      0.40%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            16      0.30%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            28      0.53%     96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             6      0.11%     96.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            43      0.81%     97.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            33      0.62%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223             9      0.17%     98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             4      0.08%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             1      0.02%     98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271             3      0.06%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             2      0.04%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             9      0.17%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             7      0.13%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             3      0.06%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351            17      0.32%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            15      0.28%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             2      0.04%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             3      0.06%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.04%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             4      0.08%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             3      0.06%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             5      0.09%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             2      0.04%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5294                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1425306951                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4315600701                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    770745000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9246.29                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5902                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5902                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.527109                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.363013                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.814592                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4841     82.02%     82.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              49      0.83%     82.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             261      4.42%     87.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              70      1.19%     88.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              69      1.17%     89.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             251      4.25%     93.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              22      0.37%     94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              13      0.22%     94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.25%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.08%     94.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.12%     94.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.08%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             235      3.98%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.08%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.14%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            27      0.46%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5902                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1454171981                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4351271981                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    772560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9411.39                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27996.29                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.14                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28161.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     126892                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    117801                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.81                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15810345.15                       # Average gap between requests
-system.physmem.pageHitRate                      81.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  212315040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  115846500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 599352000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                480232800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           338642475600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           133930593495                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2993365419750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3467346235185                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.758961                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4979642480610                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    173130100000                       # Time in different power states
+system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     126926                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98756                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.15                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18401890.29                       # Average gap between requests
+system.physmem.pageHitRate                      80.15                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  207522000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  113231250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 600100800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                419256000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           338641458480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           134001495225                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2993293881750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3467276945505                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.747605                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4979520185732                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    173129580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31977087390                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32082834268                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  218982960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  119484750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 603002400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                476182800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           338642475600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           134835847830                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2992571337000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3467467313340                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.782314                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4978313509331                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    173130100000                       # Time in different power states
+system.physmem_1.actEnergy                  214945920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  117282000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 605085000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                404047440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           338641458480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           134530881300                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2992829508000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3467343208140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.760386                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4978746411720                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    173129580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     33303731919                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32855777030                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10369499579                       # number of cpu cycles simulated
+system.cpu.numCycles                      10369465443                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128677191                       # Number of instructions committed
-system.cpu.committedOps                     248045844                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             232619140                       # Number of integer alu accesses
+system.cpu.committedInsts                   128667033                       # Number of instructions committed
+system.cpu.committedOps                     248022101                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             232599125                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                     2317433                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23196735                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    232619140                       # number of integer instructions
+system.cpu.num_func_calls                     2317363                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23194478                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    232599125                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           435790308                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          198379629                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           435753384                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          198362025                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            133146964                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95675934                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22361713                       # number of memory refs
-system.cpu.num_load_insts                    13951833                       # Number of load instructions
-system.cpu.num_store_insts                    8409880                       # Number of store instructions
-system.cpu.num_idle_cycles               9769324889.998116                       # Number of idle cycles
-system.cpu.num_busy_cycles               600174689.001884                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.057879                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.942121                       # Percentage of idle cycles
-system.cpu.Branches                          26373024                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                172503      0.07%      0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu                 225254349     90.81%     90.88% # Class of executed instruction
-system.cpu.op_class::IntMult                   140413      0.06%     90.94% # Class of executed instruction
-system.cpu.op_class::IntDiv                    123366      0.05%     90.99% # Class of executed instruction
+system.cpu.num_cc_register_reads            133133176                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95670461                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22356642                       # number of memory refs
+system.cpu.num_load_insts                    13946240                       # Number of load instructions
+system.cpu.num_store_insts                    8410402                       # Number of store instructions
+system.cpu.num_idle_cycles               9769457503.998116                       # Number of idle cycles
+system.cpu.num_busy_cycles               600007939.001884                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.057863                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.942137                       # Percentage of idle cycles
+system.cpu.Branches                          26370667                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                172538      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 225235379     90.81%     90.88% # Class of executed instruction
+system.cpu.op_class::IntMult                   140393      0.06%     90.94% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123647      0.05%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCvt                      16      0.00%     90.99% # Class of executed instruction
@@ -366,214 +361,215 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     90.99% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     90.99% # Class of executed instruction
-system.cpu.op_class::MemRead                 13946864      5.62%     96.61% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8409880      3.39%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 13941273      5.62%     96.61% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8410402      3.39%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  248047391                       # Class of executed instruction
+system.cpu.op_class::total                  248023648                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements           1622522                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996992                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20153045                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1623034                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.416896                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          54942250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996992                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1621027                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996962                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20151381                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1621539                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.427318                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          54359500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996962                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88765477                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88765477                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12014873                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12014873                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8077139                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8077139                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        58853                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         58853                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20092012                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20092012                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20150865                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20150865                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       906821                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        906821                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       324755                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       324755                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       403161                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       403161                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1231576                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1231576                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1634737                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1634737                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12835976218                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12835976218                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12149973597                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12149973597                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  24985949815                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24985949815                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  24985949815                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24985949815                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12921694                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12921694                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8401894                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8401894                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       462014                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       462014                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21323588                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21323588                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21785602                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21785602                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070178                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070178                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038653                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.038653                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872616                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.872616                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.057757                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.057757                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.075037                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.075037                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20287.785581                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15284.385082                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5424                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88751069                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88751069                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12012436                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12012436                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8077606                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8077606                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59170                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59170                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      20090042                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20090042                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20149212                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20149212                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       905821                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        905821                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       324802                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       324802                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402538                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402538                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1230623                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1230623                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1633161                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1633161                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12812474000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12812474000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12127378479                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12127378479                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24939852479                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24939852479                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24939852479                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24939852479                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12918257                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12918257                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8402408                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8402408                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461708                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461708                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21320665                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21320665                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21782373                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21782373                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070119                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070119                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038656                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.038656                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871845                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.871845                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057720                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057720                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074976                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074976                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20266.037998                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15270.908673                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         5798                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                73                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                72                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    74.301370                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    80.527778                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1539491                       # number of writebacks
-system.cpu.dcache.writebacks::total           1539491                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          290                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          290                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9162                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         9162                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         9452                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         9452                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         9452                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         9452                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906531                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       906531                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315593                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       315593                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403125                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       403125                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1222124                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1222124                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1625249                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1625249                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       574812                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total       574812                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.writebacks::writebacks      1537873                       # number of writebacks
+system.cpu.dcache.writebacks::total           1537873                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          288                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          288                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9093                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         9093                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9381                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9381                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9381                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9381                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       905533                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       905533                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315709                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315709                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402504                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402504                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1221242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1221242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1623746                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1623746                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       572954                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total       572954                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13916                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        13916                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       588728                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       588728                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11468758782                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11468758782                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11117329359                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11117329359                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5627297500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5627297500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22586088141                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22586088141                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28213385641                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28213385641                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94364463500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94364463500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2593293500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2593293500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96957757000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96957757000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070156                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070156                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037562                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037562                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.872538                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.872538                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057313                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057313                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074602                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074602                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       586870                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       586870                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11904745500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11904745500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11312729479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11312729479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5814985000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5814985000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23217474979                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23217474979                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29032459979                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29032459979                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94684333500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94684333500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2622247500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2622247500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97306581000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  97306581000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070097                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070097                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037574                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037574                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871772                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871772                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057280                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057280                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074544                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074544                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         8888                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.045606                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12184                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         8903                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.368527                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.045606                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315350                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315350                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements         7782                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.044171                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13071                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7797                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.676414                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.044171                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315261                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315261                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        54641                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        54641                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12184                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12184                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12184                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12184                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12184                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12184                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        10091                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        10091                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        10091                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        10091                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        10091                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        10091                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    104642000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    104642000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    104642000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    104642000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    104642000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    104642000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        22275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22275                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        22275                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22275                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        22275                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.453019                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.453019                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.453019                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.453019                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.453019                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.453019                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses        53116                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53116                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13073                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13073                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13073                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13073                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13073                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13073                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8990                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8990                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8990                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8990                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8990                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8990                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     97324000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     97324000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     97324000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     97324000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     97324000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     97324000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22063                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22063                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22063                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22063                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22063                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22063                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.407470                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.407470                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.407470                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.407470                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.407470                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.407470                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -582,86 +578,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         3116                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         3116                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        10091                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        10091                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        10091                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        10091                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        10091                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        10091                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     89505500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     89505500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     89505500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     89505500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     89505500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     89505500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.453019                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.453019                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.453019                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.453019                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.453019                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.453019                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8869.834506                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8869.834506                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8869.834506                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8869.834506                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8869.834506                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8869.834506                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3106                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3106                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8990                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8990                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8990                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8990                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8990                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8990                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     88334000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     88334000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     88334000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     88334000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     88334000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     88334000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.407470                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.407470                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.407470                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.407470                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.407470                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.407470                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9825.806452                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9825.806452                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9825.806452                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9825.806452                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9825.806452                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9825.806452                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            794465                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.329327                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144962865                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            794977                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.348502                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      161575846250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.329327                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996737                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996737                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            792637                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.330403                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144952019                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            793149                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.755093                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      161555480500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.330403                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996739                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996739                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          301                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          289                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146552833                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146552833                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144962865                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144962865                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144962865                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144962865                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144962865                       # number of overall hits
-system.cpu.icache.overall_hits::total       144962865                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       794984                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        794984                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       794984                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         794984                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       794984                       # number of overall misses
-system.cpu.icache.overall_misses::total        794984                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11253068237                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11253068237                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11253068237                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11253068237                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11253068237                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11253068237                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145757849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145757849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145757849                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145757849                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145757849                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145757849                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005454                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005454                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005454                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005454                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005454                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005454                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14155.087696                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14155.087696                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146538331                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146538331                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144952019                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144952019                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144952019                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144952019                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144952019                       # number of overall hits
+system.cpu.icache.overall_hits::total       144952019                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       793156                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        793156                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       793156                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         793156                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       793156                       # number of overall misses
+system.cpu.icache.overall_misses::total        793156                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11221653000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11221653000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11221653000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11221653000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11221653000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11221653000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145745175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145745175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145745175                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145745175                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145745175                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145745175                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005442                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005442                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005442                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005442                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005442                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005442                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14148.103274                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14148.103274                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -670,88 +666,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       794984                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       794984                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       794984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       794984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       794984                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       794984                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10055806763                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10055806763                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10055806763                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10055806763                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10055806763                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10055806763                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005454                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005454                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005454                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005454                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005454                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005454                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       793156                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       793156                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       793156                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       793156                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       793156                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       793156                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10428497000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10428497000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10428497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10428497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10428497000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10428497000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005442                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005442                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005442                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005442                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005442                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005442                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         4440                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.061283                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7028                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         4451                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.578971                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.061283                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191330                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.191330                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements         3538                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.060279                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7930                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3549                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.234432                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.060279                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191267                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.191267                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        29974                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        29974                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7029                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7029                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        29062                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        29062                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7929                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7929                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7031                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7031                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7031                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7031                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         5304                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         5304                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         5304                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         5304                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         5304                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         5304                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     51550250                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     51550250                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     51550250                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     51550250                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     51550250                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     51550250                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12333                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12333                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7931                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7931                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7931                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7931                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4400                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4400                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4400                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4400                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4400                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4400                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     45407000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     45407000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     45407000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     45407000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     45407000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     45407000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12329                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12329                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12335                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12335                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12335                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12335                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.430066                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.430066                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.429996                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.429996                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.429996                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.429996                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9719.127074                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9719.127074                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9719.127074                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9719.127074                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9719.127074                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9719.127074                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12331                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12331                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12331                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12331                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.356882                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.356882                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.356824                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.356824                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.356824                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.356824                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -760,163 +756,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          759                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          759                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         5304                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         5304                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         5304                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         5304                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         5304                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         5304                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     43592750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     43592750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     43592750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     43592750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     43592750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     43592750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.430066                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.430066                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.429996                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.429996                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.429996                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.429996                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8218.844268                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8218.844268                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8218.844268                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8218.844268                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8218.844268                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8218.844268                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          796                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          796                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4400                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4400                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4400                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4400                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4400                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4400                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     41007000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     41007000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     41007000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     41007000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     41007000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     41007000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.356882                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.356882                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.356824                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.356824                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.356824                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.356824                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9319.772727                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9319.772727                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9319.772727                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9319.772727                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9319.772727                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9319.772727                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            87146                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64741.188816                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3494549                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151845                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.013922                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87263                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64757.225173                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4369524                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           151965                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            28.753489                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141667                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3260.512095                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.769879                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.145028                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3328.329800                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909                       # Average occupied blocks per requestor
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 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1674                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80879.002869                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77485.076306                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77767.274215                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        80300                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80879.002869                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77485.076306                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77767.274215                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -925,143 +927,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        80303                       # number of writebacks
-system.cpu.l2cache.writebacks::total            80303                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12937                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28518                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        41460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1358                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1358                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113272                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113272                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        80412                       # number of writebacks
+system.cpu.l2cache.writebacks::total            80412                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           30                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total           30                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1367                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1367                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113781                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       113781                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        12897                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        12897                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28476                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28481                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12937                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141790                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154732                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12897                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       142257                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       155159                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12937                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141790                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       154732                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       574812                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total       574812                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12897                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       142257                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       155159                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       572954                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total       572954                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13916                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13916                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       588728                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       588728                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       325250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    887274749                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1984560718                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2872160717                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     24705840                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     24705840                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7236225029                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7236225029                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       325250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    887274749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9220785747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10108385746                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       325250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    887274749                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9220785747                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10108385746                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86143480500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86143480500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2411090500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2411090500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88554571000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88554571000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001500                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016274                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021788                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019609                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.811231                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.811231                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361420                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361420                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001500                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016274                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087402                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063735                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001500                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016274                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087402                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063735                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        65050                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        65050                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        65050                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       586870                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       586870                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29036000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29036000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7556492000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7556492000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    914126500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    914126500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       351500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2043732500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2044084000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       351500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    914126500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9600224500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10514702500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       351500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    914126500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9600224500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10514702500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  87522404500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  87522404500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2462213500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2462213500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89984618000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89984618000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.816607                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.816607                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362897                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362897                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016261                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016261                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.001654                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.021783                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.021625                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001654                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016261                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087769                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.064017                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001654                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016261                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087769                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.064017                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        70300                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        70300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        70300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2695684                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2695162                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         572954                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2687857                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13916                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13916                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1543366                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2193                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2193                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       313413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       313413                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1668857                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       884964                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       313540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       313540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       793156                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322272                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::MessageReq         1652                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1589955                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5966477                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9396                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        20349                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7586177                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50878144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204018925                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       261888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       656512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          255815469                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       55819                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4616997                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.010670                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.102742                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2378925                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6040657                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8974                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        20226                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8448782                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50761152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203819691                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       244416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       629120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          255454379                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      189246                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5626152                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.032703                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.177859                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4567735     98.93%     98.93% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              49262      1.07%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            5442159     96.73%     96.73% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             183993      3.27%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4616997                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3834191500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5626152                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4269812500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       472500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       480000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1194868737                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1189734000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3047835587                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3013374987                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       7956750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6600000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      15136500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13485000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               228399                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              228399                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               226549                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              226549                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              11006                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
 system.iobus.trans_dist::MessageReq              1652                       # Transaction distribution
 system.iobus.trans_dist::MessageResp             1652                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
@@ -1072,7 +1084,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       432904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       429188                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
@@ -1082,12 +1094,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       477136                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95114                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95114                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       473420                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95130                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95130                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3304                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3304                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  575554                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  571854                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -1096,7 +1108,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       216452                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       214594                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
@@ -1106,13 +1118,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       244848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       242990                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027304                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3278696                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3940536                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  3276902                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3939784                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1130,7 +1142,7 @@ system.iobus.reqLayer7.occupancy                50000                       # La
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            216453000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            214595000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1148,169 +1160,171 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           257203754                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           242362178                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           466130000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           462414000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50194752                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50042000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy             1652000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47502                       # number of replacements
-system.iocache.tags.tagsinuse                0.095966                       # Cycle average of tags in use
+system.iocache.tags.replacements                47510                       # number of replacements
+system.iocache.tags.tagsinuse                0.095938                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47518                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47526                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5046161981000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.095966                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005998                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005998                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5046145075000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.095938                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005996                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005996                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428013                       # Number of tag accesses
-system.iocache.tags.data_accesses              428013                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          837                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              837                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          837                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               837                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          837                       # number of overall misses
-system.iocache.overall_misses::total              837                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    132288440                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    132288440                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8590965562                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8590965562                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    132288440                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    132288440                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    132288440                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    132288440                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          837                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            837                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          837                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             837                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          837                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            837                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428085                       # Number of tag accesses
+system.iocache.tags.data_accesses              428085                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          845                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              845                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          845                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               845                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          845                       # number of overall misses
+system.iocache.overall_misses::total              845                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    134017694                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    134017694                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5509470484                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5509470484                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    134017694                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    134017694                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    134017694                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    134017694                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          845                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            845                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          845                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             845                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          845                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            845                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158050.704898                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 158050.704898                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 158050.704898                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         29647                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 158600.821302                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 158600.821302                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 158600.821302                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           341                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 4442                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   28                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.674246                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.178571                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          837                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          837                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          837                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          837                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          837                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          837                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88419930                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     88419930                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6161511576                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6161511576                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     88419930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     88419930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     88419930                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     88419930                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          845                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          845                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          845                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          845                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          845                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          845                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     91767694                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     91767694                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3173470484                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3173470484                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     91767694                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     91767694                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     91767694                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     91767694                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 105639.103943                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 105639.103943                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 108600.821302                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 108600.821302                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              617109                       # Transaction distribution
-system.membus.trans_dist::ReadResp             617109                       # Transaction distribution
+system.membus.trans_dist::ReadReq              572954                       # Transaction distribution
+system.membus.trans_dist::ReadResp             615177                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13916                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13916                       # Transaction distribution
-system.membus.trans_dist::Writeback            126970                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2156                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1637                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            112993                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           112993                       # Transaction distribution
+system.membus.trans_dist::Writeback            127079                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7222                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2154                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1646                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            113502                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           113502                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         42223                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1652                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1652                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3304                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3304                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       477136                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       473420                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       700320                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       392332                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1569788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141387                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141387                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1714479                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       400152                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1573892                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141767                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141767                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1718963                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       244848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242990                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1400637                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14982656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16628141                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22639869                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1583                       # Total snoops (count)
-system.membus.snoop_fanout::samples            921584                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001793                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.042301                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15016960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16660587                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19682235                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1580                       # Total snoops (count)
+system.membus.snoop_fanout::samples            927896                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001780                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.042157                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  919932     99.82%     99.82% # Request fanout histogram
+system.membus.snoop_fanout::1                  926244     99.82%     99.82% # Request fanout histogram
 system.membus.snoop_fanout::2                    1652      0.18%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total              921584                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           362661000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              927896                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           359896000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           527980000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           527973000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy             3304000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1034075968                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           848970266                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer0.occupancy            1652000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2159262414                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2157850870                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           51084248                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           85904679                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 6eb08a8bc..b5554ceae 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000038                       # Number of seconds simulated
-sim_ticks                                    37930000                       # Number of ticks simulated
-final_tick                                   37930000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    37623000                       # Number of ticks simulated
+final_tick                                   37623000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161486                       # Simulator instruction rate (inst/s)
-host_op_rate                                   161429                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              956403338                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294064                       # Number of bytes of host memory used
+host_inst_rate                                 152308                       # Simulator instruction rate (inst/s)
+host_op_rate                                   152258                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              894784408                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293572                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           23296                       # Nu
 system.physmem.num_reads::cpu.inst                364                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            614184023                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            285156868                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               899340891                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       614184023                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          614184023                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           614184023                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           285156868                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              899340891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            619195705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            287483720                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               906679425                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       619195705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          619195705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           619195705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           287483720                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              906679425                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        37824500                       # Total gap between requests
+system.physmem.totGap                        37518500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        86                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -187,32 +187,32 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           84                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      381.714286                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     247.680361                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.730884                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             19     22.62%     22.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           20     23.81%     46.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     247.494057                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.812732                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             20     23.81%     23.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     22.62%     46.43% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           10     11.90%     58.33% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511           11     13.10%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      4.76%     76.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      3.57%     79.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.38%     82.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            6      7.14%     89.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     10.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.38%     73.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            5      5.95%     79.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      3.57%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            6      7.14%     90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            8      9.52%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             84                       # Bytes accessed per row activation
-system.physmem.totQLat                        3251500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13245250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3336750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13330500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6100.38                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6260.32                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24850.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         899.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25010.32                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         906.68                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      899.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      906.68                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.08                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.08                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,43 +220,43 @@ system.physmem.readRowHits                        437                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70965.29                       # Average gap between requests
+system.physmem.avgGap                        70391.18                       # Average gap between requests
 system.physmem.pageHitRate                      81.99                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     234360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     127875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                     226800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     123750                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                   2043600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               21404070                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  67500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 25911645                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              825.080242                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         372750                       # Time in different power states
+system.physmem_0.actBackEnergy               21178350                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 265500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 25872240                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              823.825505                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         435750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        30362750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        30032750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     340200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     185625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1521000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     347760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     189750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1544400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               20293425                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                1041750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 25416240                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              809.305525                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1595750                       # Time in different power states
+system.physmem_1.actBackEnergy               20558475                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 809250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 25483875                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              811.459163                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1209750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        28783000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        29169000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1964                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1204                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    1965                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1205                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1555                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                 1556                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     382                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             24.565916                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             24.550129                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -276,10 +276,10 @@ system.cpu.dtb.data_hits                         2255                       # DT
 system.cpu.dtb.data_misses                         14                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_accesses                     2269                       # DTB accesses
-system.cpu.itb.fetch_hits                        2638                       # ITB hits
+system.cpu.itb.fetch_hits                        2639                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2655                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2656                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +293,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            75860                       # number of cpu cycles simulated
+system.cpu.numCycles                            75246                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1116                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1115                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              11.853125                       # CPI: cycles per instruction
-system.cpu.ipc                               0.084366                       # IPC: instructions per cycle
-system.cpu.tickCycles                           12560                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           63300                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              11.757188                       # CPI: cycles per instruction
+system.cpu.ipc                               0.085054                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12577                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           62669                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.899066                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1976                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           103.998872                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1975                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.692308                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.686391                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.899066                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025366                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025366                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.998872                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025390                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025390                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
@@ -321,28 +321,28 @@ system.cpu.dcache.tags.tag_accesses              4573                       # Nu
 system.cpu.dcache.tags.data_accesses             4573                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1235                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1235                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          741                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            741                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1976                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1976                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1976                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1976                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1975                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1975                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1975                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1975                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          124                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          124                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          226                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            226                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          226                       # number of overall misses
-system.cpu.dcache.overall_misses::total           226                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8144750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8144750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      9233750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      9233750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17378500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17378500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17378500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17378500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          227                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          227                       # number of overall misses
+system.cpu.dcache.overall_misses::total           227                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8109500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8109500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      9137500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      9137500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     17247000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     17247000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     17247000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     17247000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1337                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1337                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -353,20 +353,20 @@ system.cpu.dcache.overall_accesses::cpu.data         2202
 system.cpu.dcache.overall_accesses::total         2202                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076290                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.076290                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.143353                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.143353                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.102634                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.102634                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102634                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102634                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76896.017699                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76896.017699                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.103088                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.103088                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.103088                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.103088                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73100                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        73100                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75977.973568                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75977.973568                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           51                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           51                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           57                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           57                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           57                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           57                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           58                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
@@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          169
 system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7564250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7564250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5364250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5364250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12928500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12928500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12928500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12928500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7616500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7616500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5372000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5372000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12988500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12988500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12988500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12988500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071803                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071803                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076748
 system.cpu.dcache.demand_mshr_miss_rate::total     0.076748                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076748                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.076748                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        76500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        76500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        76500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        76500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           175.739822                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2273                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           175.991805                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2274                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.227397                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.230137                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   175.739822                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085810                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085810                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   175.991805                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085933                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085933                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5641                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5641                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         2273                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2273                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2273                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2273                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2273                       # number of overall hits
-system.cpu.icache.overall_hits::total            2273                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5643                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5643                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         2274                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2274                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2274                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2274                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2274                       # number of overall hits
+system.cpu.icache.overall_hits::total            2274                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28333750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28333750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28333750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28333750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28333750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28333750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2638                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2638                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2638                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2638                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138362                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138362                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138362                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138362                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.138362                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.138362                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77626.712329                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77626.712329                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     28165000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     28165000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     28165000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     28165000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     28165000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     28165000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2639                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2639                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2639                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2639                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2639                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2639                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138310                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.138310                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.138310                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.138310                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.138310                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.138310                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77164.383562                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77164.383562                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -481,103 +481,108 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          365
 system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27622750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27622750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27622750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27622750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27622750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27622750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138362                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138362                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138362                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138362                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138362                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138362                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27800000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     27800000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     27800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27800000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     27800000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138310                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.138310                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.138310                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.394654                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          233.662872                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.771828                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.622826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005364                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001759                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007123                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   176.005347                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.657524                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005371                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001760                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           96                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          460                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          364                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          364                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           96                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           96                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          169                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          364                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     27246750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7466750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     34713500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5290250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5290250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     27246750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12757000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     40003750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     27246750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12757000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     40003750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          365                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           96                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5261500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5261500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27241500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27241500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7471000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7471000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27241500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12732500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39974000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27241500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12732500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39974000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          365                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          365                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           96                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           96                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          365                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          169                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          534                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          365                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          169                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          534                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.997260                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997831                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.997260                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.997260                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.997260                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997260                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -586,55 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          364                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          460                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          364                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          364                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           96                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           96                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22686750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6260250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     28947000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4378250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4378250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22686750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10638500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     33325250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22686750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10638500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     33325250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4531500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4531500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23601500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23601500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6511000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6511000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23601500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11042500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     34644000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23601500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11042500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     34644000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.997260                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          365                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           96                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
@@ -655,14 +665,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        629250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        286000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        547500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                460                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           460                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
@@ -678,9 +688,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 533                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              605500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              605000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2833250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2833000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 4b8e35ff8..96f652b92 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    22074000                       # Number of ticks simulated
-final_tick                                   22074000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21947000                       # Number of ticks simulated
+final_tick                                   21947000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27311                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27309                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               94600483                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225500                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  95577                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95558                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              329070081                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294868                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           20032                       # Nu
 system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                173                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   486                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            907492978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            501585576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1409078554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       907492978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          907492978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           907492978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           501585576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1409078554                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            912744339                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            504488085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1417232424                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       912744339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          912744339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           912744339                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           504488085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1417232424                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           486                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         486                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21941500                       # Total gap between requests
+system.physmem.totGap                        21815000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       138                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        56                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           81                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      332.641975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     207.818416                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     321.662840                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     207.725130                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     321.981029                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             25     30.86%     30.86% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255           18     22.22%     53.09% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            9     11.11%     64.20% # Bytes accessed per row activation
@@ -199,19 +199,19 @@ system.physmem.bytesPerActivate::640-767            1      1.23%     83.95% # By
 system.physmem.bytesPerActivate::768-895            3      3.70%     87.65% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     12.35%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             81                       # Bytes accessed per row activation
-system.physmem.totQLat                        4363750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13476250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        4379250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13491750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2430000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8978.91                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9010.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27728.91                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1409.08                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27760.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1417.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1409.08                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1417.23                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.07                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.07                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -219,7 +219,7 @@ system.physmem.readRowHits                        390                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.25                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45147.12                       # Average gap between requests
+system.physmem.avgGap                        44886.83                       # Average gap between requests
 system.physmem.pageHitRate                      80.25                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     219240                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     119625                       # Energy for precharge commands per rank (pJ)
@@ -230,55 +230,55 @@ system.physmem_0.actBackEnergy               10785825                       # En
 system.physmem_0.preBackEnergy                  38250                       # Energy for precharge background per rank (pJ)
 system.physmem_0.totalEnergy                 13833660                       # Total energy per rank (pJ)
 system.physmem_0.averagePower              873.750829                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         118250                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        15303750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     325080                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     177375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1255800                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   1271400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10123200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 619500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13518075                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              853.818096                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         963500                       # Time in different power states
+system.physmem_1.actBackEnergy               10129185                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 614250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13534410                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              854.849834                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         953500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14362750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14372750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2808                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1660                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               479                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2112                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     676                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2810                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1662                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               478                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2116                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     679                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.007576                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     398                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 30                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             32.088847                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     396                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 29                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         2105                       # DTB read hits
-system.cpu.dtb.read_misses                         56                       # DTB read misses
+system.cpu.dtb.read_misses                         55                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2161                       # DTB read accesses
+system.cpu.dtb.read_accesses                     2160                       # DTB read accesses
 system.cpu.dtb.write_hits                        1074                       # DTB write hits
 system.cpu.dtb.write_misses                        30                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                    1104                       # DTB write accesses
 system.cpu.dtb.data_hits                         3179                       # DTB hits
-system.cpu.dtb.data_misses                         86                       # DTB misses
+system.cpu.dtb.data_misses                         85                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3265                       # DTB accesses
-system.cpu.itb.fetch_hits                        2195                       # ITB hits
+system.cpu.dtb.data_accesses                     3264                       # DTB accesses
+system.cpu.itb.fetch_hits                        2194                       # ITB hits
 system.cpu.itb.fetch_misses                        34                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2229                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2228                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -292,131 +292,131 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            44149                       # number of cpu cycles simulated
+system.cpu.numCycles                            43895                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8603                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16272                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2808                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1074                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4302                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1040                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               8597                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16278                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2810                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1075                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4298                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1038                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           735                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2195                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   341                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14185                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.147127                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.556854                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           740                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2194                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   338                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14179                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.148036                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.557344                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11330     79.87%     79.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      287      2.02%     81.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      214      1.51%     83.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11320     79.84%     79.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      289      2.04%     81.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      216      1.52%     83.40% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                      204      1.44%     84.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      242      1.71%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      209      1.47%     88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      241      1.70%     89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      178      1.25%     90.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1280      9.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      243      1.71%     86.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      208      1.47%     88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      242      1.71%     89.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      175      1.23%     90.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1282      9.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14185                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.063603                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.368570                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8626                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2504                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2413                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   199                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    443                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                14179                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.064016                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.370840                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8623                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2500                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2414                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   200                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    442                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  227                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    83                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14877                       # Number of instructions handled by decode
+system.cpu.decode.BranchMispred                    81                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  14886                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   224                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    443                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8799                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1077                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            424                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2422                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1020                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14259                       # Number of instructions processed by rename
+system.cpu.rename.SquashCycles                    442                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8796                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1074                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            427                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2425                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1015                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14276                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     15                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     32                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    922                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               10782                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17904                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17895                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                     19                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                     33                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    937                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               10794                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17927                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17918                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6212                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     6224                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       534                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                       538                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2680                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1315                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12936                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      12940                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10742                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     10735                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                20                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6591                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3553                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            6595                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3561                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14185                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.757279                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.490412                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14179                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.757106                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.490778                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10181     71.77%     71.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1265      8.92%     80.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 910      6.42%     87.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 677      4.77%     91.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 530      3.74%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 330      2.33%     97.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 213      1.50%     99.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  54      0.38%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  25      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10173     71.75%     71.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1278      9.01%     80.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 898      6.33%     87.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 679      4.79%     91.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 528      3.72%     95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 333      2.35%     97.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 209      1.47%     99.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  55      0.39%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  26      0.18%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14185                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14179                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      29     19.86%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     74     50.68%     70.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    43     29.45%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      29     20.14%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     73     50.69%     70.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    42     29.17%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7248     67.47%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7243     67.47%     67.49% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.50% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.52% # Type of FU issued
@@ -445,23 +445,23 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.52% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2358     21.95%     89.47% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1131     10.53%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2356     21.95%     89.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1131     10.54%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10742                       # Type of FU issued
-system.cpu.iq.rate                           0.243312                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         146                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013592                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              35814                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19563                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9787                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10735                       # Type of FU issued
+system.cpu.iq.rate                           0.244561                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         144                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013414                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              35792                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             19571                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9784                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10875                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10866                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               71                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread0.squashedLoads         1497                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
@@ -472,57 +472,57 @@ system.cpu.iew.lsq.thread0.blockedLoads             0                       # Nu
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            65                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    443                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1035                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13050                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    442                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1033                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    23                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               13054                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               109                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts                  2680                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1315                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    22                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      1                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    20                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             81                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          391                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  472                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10248                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2164                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               494                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          395                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  476                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 10242                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2163                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               493                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            86                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3270                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1599                       # Number of branches executed
+system.cpu.iew.exec_refs                         3269                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1598                       # Number of branches executed
 system.cpu.iew.exec_stores                       1106                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.232123                       # Inst execution rate
-system.cpu.iew.wb_sent                           9960                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9797                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5308                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7306                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.233330                       # Inst execution rate
+system.cpu.iew.wb_sent                           9957                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9794                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      5300                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7297                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.221908                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.726526                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.223123                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.726326                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            6660                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6664                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               402                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12983                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.492105                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.404730                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               401                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.492295                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.405132                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10525     81.07%     81.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1166      8.98%     90.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          505      3.89%     93.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10520     81.06%     81.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1167      8.99%     90.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          504      3.88%     93.94% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          209      1.61%     95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          137      1.06%     96.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           75      0.58%     97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          136      1.05%     96.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           76      0.59%     97.18% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           89      0.69%     97.87% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           87      0.67%     98.54% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          190      1.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12983                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12978                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
 system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -569,101 +569,101 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   190                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        25491                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27316                       # The number of ROB writes
-system.cpu.timesIdled                             260                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29964                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        25490                       # The number of ROB reads
+system.cpu.rob.rob_writes                       27321                       # The number of ROB writes
+system.cpu.timesIdled                             258                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29716                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
 system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.928594                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.928594                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.144329                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.144329                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13019                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7461                       # number of integer regfile writes
+system.cpu.cpi                               6.888732                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.888732                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145165                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.145165                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13013                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7460                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.596270                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2347                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           107.548347                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2343                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               173                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.566474                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.543353                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.596270                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026269                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026269                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.548347                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026257                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026257                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          173                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.042236                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5893                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5893                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1838                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1838                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          509                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            509                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2347                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2347                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2347                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2347                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          157                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           157                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          356                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          356                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          513                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            513                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          513                       # number of overall misses
-system.cpu.dcache.overall_misses::total           513                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     12056250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     12056250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24043225                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24043225                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36099475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36099475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36099475                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36099475                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1995                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1995                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses              5891                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5891                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1835                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1835                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          508                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            508                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2343                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2343                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2343                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2343                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          159                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           159                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          357                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          357                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          516                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            516                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          516                       # number of overall misses
+system.cpu.dcache.overall_misses::total           516                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11993500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11993500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     24175975                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     24175975                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     36169475                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     36169475                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     36169475                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     36169475                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1994                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1994                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2860                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2860                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2860                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2860                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078697                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.078697                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.179371                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.179371                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.179371                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.179371                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70369.346979                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70369.346979                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2245                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2859                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2859                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2859                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2859                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079739                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.079739                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.412717                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.412717                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.180483                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.180483                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.180483                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.180483                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70095.881783                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70095.881783                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         2284                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                38                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                41                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    59.078947                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.707317                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          340                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          340                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          340                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          340                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          285                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          285                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          343                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          343                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          343                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          343                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
@@ -672,82 +672,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          173
 system.cpu.dcache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8557250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8557250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5645250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5645250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14202500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14202500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14202500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14202500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050627                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050627                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8588000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8588000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5911000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5911000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14499000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     14499000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14499000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     14499000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050652                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050652                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.060490                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.060490                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.060490                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.060490                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.060511                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.060511                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.060511                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.060511                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           158.400693                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1716                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           158.228991                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1714                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.464968                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.458599                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   158.400693                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077344                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077344                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   158.228991                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077260                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077260                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4704                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4704                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1716                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1716                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1716                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1716                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1716                       # number of overall hits
-system.cpu.icache.overall_hits::total            1716                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          479                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           479                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          479                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            479                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          479                       # number of overall misses
-system.cpu.icache.overall_misses::total           479                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34067500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34067500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34067500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34067500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34067500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34067500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2195                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2195                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2195                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2195                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.218223                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.218223                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.218223                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.218223                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.218223                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.218223                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71122.129436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71122.129436                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              4702                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4702                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1714                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1714                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1714                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1714                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1714                       # number of overall hits
+system.cpu.icache.overall_hits::total            1714                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          480                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           480                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          480                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            480                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          480                       # number of overall misses
+system.cpu.icache.overall_misses::total           480                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     33574500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     33574500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     33574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     33574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     33574500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     33574500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2194                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2194                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2194                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2194                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2194                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2194                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.218778                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.218778                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.218778                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.218778                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.218778                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.218778                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69946.875000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69946.875000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -756,115 +756,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          165                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          165                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          165                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          165                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          165                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          166                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          166                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          166                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          166                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          314                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          314                       # number of demand (read+write) MSHR misses
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse          219.195035                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   158.471795                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    60.723240                       # Average occupied blocks per requestor
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-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 77949.588477                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -873,55 +878,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            415                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           415                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          101                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          346                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               974                       # Packet count per connected master and slave (bytes)
@@ -942,14 +952,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            487                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         243500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        535750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        285500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 414                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        471000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        259500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                414                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           414                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          972                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    972                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31104                       # Cumulative packet size per connected master and slave (bytes)
@@ -965,9 +975,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 486                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              605500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              594500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2581250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2585500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index aeda1c330..88733611d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000139                       # Number of seconds simulated
-sim_ticks                                      138637                       # Number of ticks simulated
-final_tick                                     138637                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      138724                       # Number of ticks simulated
+final_tick                                     138724                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45640                       # Simulator instruction rate (inst/s)
-host_op_rate                                    45635                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 990010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 451208                       # Number of bytes of host memory used
+host_inst_rate                                  45032                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45028                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 977453                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451780                       # Number of bytes of host memory used
 host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1460                       #
 system.mem_ctrls.num_reads::total                1460                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          277                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                277                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    673990349                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             673990349                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    127873511                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            127873511                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    801863860                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            801863860                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    673567660                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             673567660                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    127793316                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            127793316                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    801360976                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            801360976                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1460                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        277                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1460                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      277                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  74880                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   18560                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    6400                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  75008                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   18432                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    6464                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   93440                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                17728                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    290                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.servicedByWrQ                    288                       # Number of DRAM read bursts serviced by the write queue
 system.mem_ctrls.mergedWrBursts                   155                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0               102                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                61                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                90                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                90                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4               103                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                22                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4               105                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                21                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 4                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               84                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               87                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               75                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               26                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              396                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              394                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14               67                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               48                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                29                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                30                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 6                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                5                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               19                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               16                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        138534                       # Total gap between requests
+system.mem_ctrls.totGap                        138621                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  277                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1170                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1172                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,12 +136,12 @@ system.mem_ctrls.wrQLenPdf::12                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      4                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                      7                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                      7                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      7                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::22                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                      6                       # What write queue length does an incoming req see
@@ -184,86 +184,88 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          224                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    353.142857                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   223.489977                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   324.415911                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           59     26.34%     26.34% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           55     24.55%     50.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           31     13.84%     64.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           15      6.70%     71.43% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           13      5.80%     77.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           14      6.25%     83.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            7      3.12%     86.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            9      4.02%     90.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           21      9.38%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          224                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          233                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    343.622318                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   215.641138                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   323.027267                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           63     27.04%     27.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           61     26.18%     53.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           29     12.45%     65.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           14      6.01%     71.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           15      6.44%     78.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           14      6.01%     84.12% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            7      3.00%     87.12% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            7      3.00%     90.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           23      9.87%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          233                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean            178                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    127.889331                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev    115.157284                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     179.333333                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    129.319022                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev    112.290100                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::16-31             1     16.67%     16.67% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::64-79             1     16.67%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-207            2     33.33%     66.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-207            1     16.67%     50.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::208-223            1     16.67%     66.67% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::240-255            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::336-351            1     16.67%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::320-335            1     16.67%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total             6                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.666667                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.640671                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.032796                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                4     66.67%     66.67% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.833333                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.809662                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.983192                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16                3     50.00%     50.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1     16.67%     66.67% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::18                2     33.33%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             6                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         7999                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   30229                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5850                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.84                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         8028                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   30296                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5860                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         6.85                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.84                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       540.12                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        46.16                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    673.99                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    127.87                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   25.85                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       540.70                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        46.60                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    673.57                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    127.79                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         4.58                       # Data bus utilization in percentage
+system.mem_ctrls.busUtil                         4.59                       # Data bus utilization in percentage
 system.mem_ctrls.busUtilRead                     4.22                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.36                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      23.33                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      948                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      22.86                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      943                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      92                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.03                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 80.46                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                75.41                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         79.75                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    80.50                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   559440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   310800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5828160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 362880                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgGap                         79.80                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    79.98                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   604800                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   336000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5840640                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 383616                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              8645520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             75338496                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             13486800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy              104532096                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            788.195744                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        25869                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             75398688                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             13434000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy              104643264                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            789.033976                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        25868                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          4420                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT        106214                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT        106302                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1103760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   613200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 8112000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 673920                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                  1118880                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   621600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 8087040                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              8645520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             89081424                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1431600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy              109661424                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            826.872042                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1728                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             89353656                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1192800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy              109683048                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            827.035092                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1330                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          4420                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT        126488                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        126886                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -299,7 +301,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                           138637                       # number of cpu cycles simulated
+system.cpu.numCycles                           138724                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6390                       # Number of instructions committed
@@ -318,7 +320,7 @@ system.cpu.num_mem_refs                          2058                       # nu
 system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     138637                       # Number of busy cycles
+system.cpu.num_busy_cycles                     138724                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
@@ -361,9 +363,9 @@ system.ruby.clk_domain.clock                        1                       # Cl
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   9645                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.162779                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.010338                       # delay histogram for all message
-system.ruby.delayHist                    |        9295     96.37%     96.37% |           0      0.00%     96.37% |         205      2.13%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::mean                  0.162571                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.010166                       # delay histogram for all message
+system.ruby.delayHist                    |        9296     96.38%     96.38% |           0      0.00%     96.38% |         204      2.12%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
 system.ruby.delayHist::total                     9645                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
@@ -375,10 +377,10 @@ system.ruby.outstanding_req_hist::total          8449
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              15.410630                      
-system.ruby.latency_hist::gmean              5.220490                      
-system.ruby.latency_hist::stdev             29.556532                      
-system.ruby.latency_hist                 |        7278     86.15%     86.15% |        1151     13.62%     99.78% |           3      0.04%     99.81% |           2      0.02%     99.83% |           6      0.07%     99.91% |           8      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              15.420928                      
+system.ruby.latency_hist::gmean              5.221828                      
+system.ruby.latency_hist::stdev             29.495379                      
+system.ruby.latency_hist                 |        7276     86.13%     86.13% |        1152     13.64%     99.76% |           4      0.05%     99.81% |           4      0.05%     99.86% |           4      0.05%     99.91% |           8      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8448                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -390,10 +392,10 @@ system.ruby.hit_latency_hist::total              6958
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1490                      
-system.ruby.miss_latency_hist::mean         73.365772                      
-system.ruby.miss_latency_hist::gmean        69.377440                      
-system.ruby.miss_latency_hist::stdev        29.580633                      
-system.ruby.miss_latency_hist            |         320     21.48%     21.48% |        1151     77.25%     98.72% |           3      0.20%     98.93% |           2      0.13%     99.06% |           6      0.40%     99.46% |           8      0.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         73.424161                      
+system.ruby.miss_latency_hist::gmean        69.478292                      
+system.ruby.miss_latency_hist::stdev        29.116195                      
+system.ruby.miss_latency_hist            |         318     21.34%     21.34% |        1152     77.32%     98.66% |           4      0.27%     98.93% |           4      0.27%     99.19% |           4      0.27%     99.46% |           8      0.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1490                      
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1249                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          799                       # Number of cache demand misses
@@ -414,7 +416,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits           30                       # N
 system.ruby.l2_cntrl0.L2cache.demand_misses         1460                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1490                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     3.776229                      
+system.ruby.network.routers0.percent_links_utilized     3.773860                      
 system.ruby.network.routers0.msg_count.Control::0         1490                      
 system.ruby.network.routers0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers0.msg_count.Response_Data::1         1490                      
@@ -431,7 +433,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2         6392
 system.ruby.network.routers0.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers1.percent_links_utilized     7.332278                      
+system.ruby.network.routers1.percent_links_utilized     7.327679                      
 system.ruby.network.routers1.msg_count.Control::0         2950                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers1.msg_count.Response_Data::1         3227                      
@@ -448,14 +450,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2         6392
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers2.percent_links_utilized     3.556049                      
+system.ruby.network.routers2.percent_links_utilized     3.553819                      
 system.ruby.network.routers2.msg_count.Control::0         1460                      
 system.ruby.network.routers2.msg_count.Response_Data::1         1737                      
 system.ruby.network.routers2.msg_count.Response_Control::1         2627                      
 system.ruby.network.routers2.msg_bytes.Control::0        11680                      
 system.ruby.network.routers2.msg_bytes.Response_Data::1       125064                      
 system.ruby.network.routers2.msg_bytes.Response_Control::1        21016                      
-system.ruby.network.routers3.percent_links_utilized     4.888185                      
+system.ruby.network.routers3.percent_links_utilized     4.885120                      
 system.ruby.network.routers3.msg_count.Control::0         2950                      
 system.ruby.network.routers3.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers3.msg_count.Response_Data::1         3227                      
@@ -484,14 +486,14 @@ system.ruby.network.msg_byte.Response_Data       697032
 system.ruby.network.msg_byte.Response_Control       114288                      
 system.ruby.network.msg_byte.Writeback_Data        61776                      
 system.ruby.network.msg_byte.Writeback_Control         6984                      
-system.ruby.network.routers0.throttle0.link_utilization     5.369057                      
+system.ruby.network.routers0.throttle0.link_utilization     5.365690                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1         1490                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          436                      
 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1       107280                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         3488                      
-system.ruby.network.routers0.throttle1.link_utilization     2.183400                      
+system.ruby.network.routers0.throttle1.link_utilization     2.182031                      
 system.ruby.network.routers0.throttle1.msg_count.Control::0         1490                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1          900                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          799                      
@@ -504,7 +506,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         639
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers1.throttle0.link_utilization     7.446064                      
+system.ruby.network.routers1.throttle0.link_utilization     7.441394                      
 system.ruby.network.routers1.throttle0.msg_count.Control::0         1490                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1         1460                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1         2352                      
@@ -519,7 +521,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         639
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers1.throttle1.link_utilization     7.218491                      
+system.ruby.network.routers1.throttle1.link_utilization     7.213964                      
 system.ruby.network.routers1.throttle1.msg_count.Control::0         1460                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1767                      
@@ -528,26 +530,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0        11680
 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       127224                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1        12888                      
-system.ruby.network.routers2.throttle0.link_utilization     1.849434                      
+system.ruby.network.routers2.throttle0.link_utilization     1.848274                      
 system.ruby.network.routers2.throttle0.msg_count.Control::0         1460                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          277                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1         1175                      
 system.ruby.network.routers2.throttle0.msg_bytes.Control::0        11680                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        19944                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1         9400                      
-system.ruby.network.routers2.throttle1.link_utilization     5.262664                      
+system.ruby.network.routers2.throttle1.link_utilization     5.259364                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1         1460                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1         1452                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1       105120                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1        11616                      
-system.ruby.network.routers3.throttle0.link_utilization     5.369057                      
+system.ruby.network.routers3.throttle0.link_utilization     5.365690                      
 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1         1490                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          436                      
 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1       107280                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         3488                      
-system.ruby.network.routers3.throttle1.link_utilization     7.446064                      
+system.ruby.network.routers3.throttle1.link_utilization     7.441394                      
 system.ruby.network.routers3.throttle1.msg_count.Control::0         1490                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1         1460                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1         2352                      
@@ -562,7 +564,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         639
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers3.throttle2.link_utilization     1.849434                      
+system.ruby.network.routers3.throttle2.link_utilization     1.848274                      
 system.ruby.network.routers3.throttle2.msg_count.Control::0         1460                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          277                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1         1175                      
@@ -579,9 +581,9 @@ system.ruby.delayVCHist.vnet_0::total            2725                       # de
 system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::samples          5879                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.069740                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.366932                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        5674     96.51%     96.51% |           0      0.00%     96.51% |         205      3.49%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.069400                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.366068                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |        5675     96.53%     96.53% |           0      0.00%     96.53% |         204      3.47%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::total            5879                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
@@ -591,10 +593,10 @@ system.ruby.delayVCHist.vnet_2::total            1041                       # de
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           35.343195                      
-system.ruby.LD.latency_hist::gmean          13.647233                      
-system.ruby.LD.latency_hist::stdev          36.940945                      
-system.ruby.LD.latency_hist              |         797     67.37%     67.37% |         383     32.38%     99.75% |           1      0.08%     99.83% |           0      0.00%     99.83% |           1      0.08%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           35.984784                      
+system.ruby.LD.latency_hist::gmean          13.718106                      
+system.ruby.LD.latency_hist::stdev          39.109328                      
+system.ruby.LD.latency_hist              |         793     67.03%     67.03% |         384     32.46%     99.49% |           1      0.08%     99.58% |           1      0.08%     99.66% |           2      0.17%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -606,18 +608,18 @@ system.ruby.LD.hit_latency_hist::total            600
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          583                      
-system.ruby.LD.miss_latency_hist::mean      68.629503                      
-system.ruby.LD.miss_latency_hist::gmean     64.886248                      
-system.ruby.LD.miss_latency_hist::stdev     24.148594                      
-system.ruby.LD.miss_latency_hist         |         197     33.79%     33.79% |         383     65.69%     99.49% |           1      0.17%     99.66% |           0      0.00%     99.66% |           1      0.17%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      69.931389                      
+system.ruby.LD.miss_latency_hist::gmean     65.571846                      
+system.ruby.LD.miss_latency_hist::stdev     28.816437                      
+system.ruby.LD.miss_latency_hist         |         193     33.10%     33.10% |         384     65.87%     98.97% |           1      0.17%     99.14% |           1      0.17%     99.31% |           2      0.34%     99.66% |           2      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           583                      
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           17.890173                      
-system.ruby.ST.latency_hist::gmean           6.261514                      
-system.ruby.ST.latency_hist::stdev          30.772511                      
-system.ruby.ST.latency_hist              |         767     88.67%     88.67% |          95     10.98%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           18.053179                      
+system.ruby.ST.latency_hist::gmean           6.262232                      
+system.ruby.ST.latency_hist::stdev          31.945584                      
+system.ruby.ST.latency_hist              |         769     88.90%     88.90% |          92     10.64%     99.54% |           1      0.12%     99.65% |           0      0.00%     99.65% |           1      0.12%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -629,18 +631,18 @@ system.ruby.ST.hit_latency_hist::total            649
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          216                      
-system.ruby.ST.miss_latency_hist::mean      62.629630                      
-system.ruby.ST.miss_latency_hist::gmean     57.125913                      
-system.ruby.ST.miss_latency_hist::stdev     33.544027                      
-system.ruby.ST.miss_latency_hist         |         118     54.63%     54.63% |          95     43.98%     98.61% |           1      0.46%     99.07% |           0      0.00%     99.07% |           0      0.00%     99.07% |           2      0.93%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      63.282407                      
+system.ruby.ST.miss_latency_hist::gmean     57.152160                      
+system.ruby.ST.miss_latency_hist::stdev     36.903379                      
+system.ruby.ST.miss_latency_hist         |         120     55.56%     55.56% |          92     42.59%     98.15% |           1      0.46%     98.61% |           0      0.00%     98.61% |           1      0.46%     99.07% |           2      0.93%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           216                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean       11.391094                      
-system.ruby.IFETCH.latency_hist::gmean       4.264782                      
-system.ruby.IFETCH.latency_hist::stdev      26.130654                      
-system.ruby.IFETCH.latency_hist          |        5714     89.28%     89.28% |         673     10.52%     99.80% |           1      0.02%     99.81% |           2      0.03%     99.84% |           5      0.08%     99.92% |           5      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean       11.264062                      
+system.ruby.IFETCH.latency_hist::gmean       4.262075                      
+system.ruby.IFETCH.latency_hist::stdev      25.133535                      
+system.ruby.IFETCH.latency_hist          |        5714     89.28%     89.28% |         676     10.56%     99.84% |           2      0.03%     99.88% |           3      0.05%     99.92% |           1      0.02%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -652,10 +654,10 @@ system.ruby.IFETCH.hit_latency_hist::total         5709
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          691                      
-system.ruby.IFETCH.miss_latency_hist::mean    80.717800                      
-system.ruby.IFETCH.miss_latency_hist::gmean    78.004389                      
-system.ruby.IFETCH.miss_latency_hist::stdev    30.603968                      
-system.ruby.IFETCH.miss_latency_hist     |           5      0.72%      0.72% |         673     97.40%     98.12% |           1      0.14%     98.26% |           2      0.29%     98.55% |           5      0.72%     99.28% |           5      0.72%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    79.541245                      
+system.ruby.IFETCH.miss_latency_hist::gmean    77.547127                      
+system.ruby.IFETCH.miss_latency_hist::stdev    24.993726                      
+system.ruby.IFETCH.miss_latency_hist     |           5      0.72%      0.72% |         676     97.83%     98.55% |           2      0.29%     98.84% |           3      0.43%     99.28% |           1      0.14%     99.42% |           4      0.58%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          691                      
 system.ruby.Directory_Controller.Fetch           1460      0.00%      0.00%
 system.ruby.Directory_Controller.Data             277      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index d5c587675..216848fe0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000126                       # Number of seconds simulated
-sim_ticks                                      126195                       # Number of ticks simulated
-final_tick                                     126195                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      126343                       # Number of ticks simulated
+final_tick                                     126343                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  43805                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43801                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 864948                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 454088                       # Number of bytes of host memory used
+host_inst_rate                                  43834                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43830                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 866526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 454420                       # Number of bytes of host memory used
 host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1182                       #
 system.mem_ctrls.num_reads::total                1182                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          194                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                194                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    599453227                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             599453227                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0     98387416                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total             98387416                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    697840643                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            697840643                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    598751019                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             598751019                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0     98272164                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total             98272164                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    697023183                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            697023183                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1182                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        194                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1182                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      194                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  64576                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   11072                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    5248                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  64512                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   11136                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5376                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   75648                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                12416                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    173                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    83                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    174                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    78                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                83                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                81                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                75                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                91                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                99                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                20                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 2                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               56                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               21                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              365                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               71                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              363                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               67                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               40                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                15                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                21                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 9                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                2                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               15                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               37                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        126127                       # Total gap between requests
+system.mem_ctrls.totGap                        126275                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  194                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1009                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1008                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,8 +135,8 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      3                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
@@ -149,9 +149,9 @@ system.mem_ctrls.wrQLenPdf::25                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::26                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
@@ -184,86 +184,86 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          211                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    327.582938                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   201.542711                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   321.278601                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           66     31.28%     31.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           57     27.01%     58.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           21      9.95%     68.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           10      4.74%     72.99% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           14      6.64%     79.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           12      5.69%     85.31% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            5      2.37%     87.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      1.42%     89.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           23     10.90%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          211                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          212                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    326.339623                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   200.746581                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   319.329567                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           67     31.60%     31.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           54     25.47%     57.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           23     10.85%     67.92% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           13      6.13%     74.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           12      5.66%     79.72% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           12      5.66%     85.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            6      2.83%     88.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      1.42%     89.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           22     10.38%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          212                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean            141                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    106.525720                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     81.341871                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     136.800000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    103.930082                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     78.649221                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::120-127            1     20.00%     40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-119            1     20.00%     40.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::128-135            1     20.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-215            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-199            1     20.00%     80.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.400000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.381380                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.894427                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                4     80.00%     80.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                1     20.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.800000                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.771851                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.095445                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16                3     60.00%     60.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                2     40.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         7775                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   26946                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5045                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         7.71                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         7952                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   27104                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5040                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         7.89                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   26.71                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       511.72                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        41.59                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    599.45                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                     98.39                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   26.89                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       510.61                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        42.55                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    598.75                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                     98.27                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.mem_ctrls.busUtil                         4.32                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.00                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.32                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtilRead                     3.99                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.33                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      22.42                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      799                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                      76                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.19                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                68.47                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         91.66                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    78.12                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   551880                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   306600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 4992000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 186624                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen                      22.50                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      801                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                      74                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 79.46                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                63.79                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         91.77                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    77.85                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   567000                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   315000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5116800                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 311040                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              8136960                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             64142784                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             18636000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               96952848                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            776.641738                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        31414                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             63365076                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             19318200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               97130076                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            778.061425                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        32699                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          4160                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         90106                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         88969                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1035720                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   575400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 7450560                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                  1028160                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   571200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 7300800                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 559872                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              8136960                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             84064968                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1160400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy              103087560                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            825.783908                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1262                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             84071808                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1154400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy              102823200                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            823.666250                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1294                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          4160                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT        119428                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        119396                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -299,7 +299,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                           126195                       # number of cpu cycles simulated
+system.cpu.numCycles                           126343                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6390                       # Number of instructions committed
@@ -318,7 +318,7 @@ system.cpu.num_mem_refs                          2058                       # nu
 system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     126195                       # Number of busy cycles
+system.cpu.num_busy_cycles                     126343                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
@@ -368,10 +368,10 @@ system.ruby.outstanding_req_hist::total          8449
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              13.937855                      
-system.ruby.latency_hist::gmean              4.957827                      
-system.ruby.latency_hist::stdev             28.413153                      
-system.ruby.latency_hist                 |        7438     88.04%     88.04% |         992     11.74%     99.79% |           2      0.02%     99.81% |           1      0.01%     99.82% |          11      0.13%     99.95% |           3      0.04%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              13.955374                      
+system.ruby.latency_hist::gmean              4.957459                      
+system.ruby.latency_hist::stdev             28.739433                      
+system.ruby.latency_hist                 |        7439     88.06%     88.06% |         992     11.74%     99.80% |           2      0.02%     99.82% |           0      0.00%     99.82% |           4      0.05%     99.87% |          10      0.12%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8448                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -383,10 +383,10 @@ system.ruby.hit_latency_hist::total              7027
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1421                      
-system.ruby.miss_latency_hist::mean         68.026742                      
-system.ruby.miss_latency_hist::gmean        59.451968                      
-system.ruby.miss_latency_hist::stdev        35.813966                      
-system.ruby.miss_latency_hist            |         411     28.92%     28.92% |         992     69.81%     98.73% |           2      0.14%     98.87% |           1      0.07%     98.94% |          11      0.77%     99.72% |           3      0.21%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         68.130894                      
+system.ruby.miss_latency_hist::gmean        59.425748                      
+system.ruby.miss_latency_hist::stdev        37.179084                      
+system.ruby.miss_latency_hist            |         412     28.99%     28.99% |         992     69.81%     98.80% |           2      0.14%     98.94% |           0      0.00%     98.94% |           4      0.28%     99.23% |          10      0.70%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1421                      
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1273                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          775                       # Number of cache demand misses
@@ -398,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits          239                       # N
 system.ruby.l2_cntrl0.L2cache.demand_misses         1182                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1421                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.974286                      
+system.ruby.network.routers0.percent_links_utilized     5.967287                      
 system.ruby.network.routers0.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers0.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2          239                      
@@ -411,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2        17208
 system.ruby.network.routers0.msg_bytes.Writeback_Data::2        94176                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0        21664                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::2        11736                      
-system.ruby.network.routers1.percent_links_utilized     8.972820                      
+system.ruby.network.routers1.percent_links_utilized     8.962309                      
 system.ruby.network.routers1.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers1.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers1.msg_count.Response_Data::2         2364                      
@@ -428,7 +428,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2       108144
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0        21664                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1         3104                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2        21192                      
-system.ruby.network.routers2.percent_links_utilized     2.998534                      
+system.ruby.network.routers2.percent_links_utilized     2.995021                      
 system.ruby.network.routers2.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers2.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers2.msg_count.Writeback_Data::2          194                      
@@ -439,7 +439,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2        85104
 system.ruby.network.routers2.msg_bytes.Writeback_Data::2        13968                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::1         3104                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::2         9456                      
-system.ruby.network.routers3.percent_links_utilized     5.981880                      
+system.ruby.network.routers3.percent_links_utilized     5.974873                      
 system.ruby.network.routers3.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers3.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers3.msg_count.Response_Data::2         2364                      
@@ -468,14 +468,14 @@ system.ruby.network.msg_byte.ResponseL2hit_Data        51624
 system.ruby.network.msg_byte.Writeback_Data       324432                      
 system.ruby.network.msg_byte.Writeback_Control        74304                      
 system.ruby.network.msg_byte.Unblock_Control        63576                      
-system.ruby.network.routers0.throttle0.link_utilization     5.603629                      
+system.ruby.network.routers0.throttle0.link_utilization     5.597065                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2          239                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0         1354                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        85104                      
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2        17208                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0        10832                      
-system.ruby.network.routers0.throttle1.link_utilization     6.344942                      
+system.ruby.network.routers0.throttle1.link_utilization     6.337510                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2         1308                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0         1354                      
@@ -484,7 +484,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0        11368
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        94176                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0        10832                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2        11736                      
-system.ruby.network.routers1.throttle0.link_utilization    10.636713                      
+system.ruby.network.routers1.throttle0.link_utilization    10.624253                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2         1308                      
@@ -497,7 +497,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        94176
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0        10832                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2        11736                      
-system.ruby.network.routers1.throttle1.link_utilization     7.308927                      
+system.ruby.network.routers1.throttle1.link_utilization     7.300365                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2          239                      
@@ -512,7 +512,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        13968
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0        10832                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         9456                      
-system.ruby.network.routers2.throttle0.link_utilization     1.705297                      
+system.ruby.network.routers2.throttle0.link_utilization     1.703300                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2          194                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1          194                      
@@ -521,19 +521,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         9456
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2        13968                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         9456                      
-system.ruby.network.routers2.throttle1.link_utilization     4.291771                      
+system.ruby.network.routers2.throttle1.link_utilization     4.286743                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1          194                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        85104                      
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1         1552                      
-system.ruby.network.routers3.throttle0.link_utilization     5.603629                      
+system.ruby.network.routers3.throttle0.link_utilization     5.597065                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2          239                      
 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0         1354                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        85104                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2        17208                      
 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0        10832                      
-system.ruby.network.routers3.throttle1.link_utilization    10.636713                      
+system.ruby.network.routers3.throttle1.link_utilization    10.624253                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0         1421                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2         1308                      
@@ -546,7 +546,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        94176
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0        10832                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2        11736                      
-system.ruby.network.routers3.throttle2.link_utilization     1.705297                      
+system.ruby.network.routers3.throttle2.link_utilization     1.703300                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1         1182                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2          194                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1          194                      
@@ -558,10 +558,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         9456
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           29.370245                      
-system.ruby.LD.latency_hist::gmean          10.775321                      
-system.ruby.LD.latency_hist::stdev          36.738545                      
-system.ruby.LD.latency_hist              |         860     72.70%     72.70% |         320     27.05%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           29.639053                      
+system.ruby.LD.latency_hist::gmean          10.782209                      
+system.ruby.LD.latency_hist::stdev          38.418359                      
+system.ruby.LD.latency_hist              |         863     72.95%     72.95% |         315     26.63%     99.58% |           1      0.08%     99.66% |           0      0.00%     99.66% |           1      0.08%     99.75% |           3      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -573,18 +573,18 @@ system.ruby.LD.hit_latency_hist::total            658
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          525                      
-system.ruby.LD.miss_latency_hist::mean      62.420952                      
-system.ruby.LD.miss_latency_hist::gmean     53.507846                      
-system.ruby.LD.miss_latency_hist::stdev     32.816863                      
-system.ruby.LD.miss_latency_hist         |         202     38.48%     38.48% |         320     60.95%     99.43% |           0      0.00%     99.43% |           0      0.00%     99.43% |           2      0.38%     99.81% |           1      0.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      63.026667                      
+system.ruby.LD.miss_latency_hist::gmean     53.584951                      
+system.ruby.LD.miss_latency_hist::stdev     36.351224                      
+system.ruby.LD.miss_latency_hist         |         205     39.05%     39.05% |         315     60.00%     99.05% |           1      0.19%     99.24% |           0      0.00%     99.24% |           1      0.19%     99.43% |           3      0.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           525                      
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           19.187283                      
-system.ruby.ST.latency_hist::gmean           6.808148                      
-system.ruby.ST.latency_hist::stdev          31.171451                      
-system.ruby.ST.latency_hist              |         753     87.05%     87.05% |         108     12.49%     99.54% |           2      0.23%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           18.927168                      
+system.ruby.ST.latency_hist::gmean           6.798661                      
+system.ruby.ST.latency_hist::stdev          29.816693                      
+system.ruby.ST.latency_hist              |         751     86.82%     86.82% |         112     12.95%     99.77% |           1      0.12%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -596,18 +596,18 @@ system.ruby.ST.hit_latency_hist::total            615
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          250                      
-system.ruby.ST.miss_latency_hist::mean      59.008000                      
-system.ruby.ST.miss_latency_hist::gmean     51.116604                      
-system.ruby.ST.miss_latency_hist::stdev     33.649742                      
-system.ruby.ST.miss_latency_hist         |         138     55.20%     55.20% |         108     43.20%     98.40% |           2      0.80%     99.20% |           0      0.00%     99.20% |           1      0.40%     99.60% |           1      0.40%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      58.108000                      
+system.ruby.ST.miss_latency_hist::gmean     50.870585                      
+system.ruby.ST.miss_latency_hist::stdev     30.281947                      
+system.ruby.ST.miss_latency_hist         |         136     54.40%     54.40% |         112     44.80%     99.20% |           1      0.40%     99.60% |           0      0.00%     99.60% |           0      0.00%     99.60% |           1      0.40%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           250                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean       10.375781                      
-system.ruby.IFETCH.latency_hist::gmean       4.114880                      
-system.ruby.IFETCH.latency_hist::stdev      24.994631                      
-system.ruby.IFETCH.latency_hist          |        5825     91.02%     91.02% |         564      8.81%     99.83% |           0      0.00%     99.83% |           1      0.02%     99.84% |           8      0.12%     99.97% |           1      0.02%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean       10.384375                      
+system.ruby.IFETCH.latency_hist::gmean       4.114767                      
+system.ruby.IFETCH.latency_hist::stdev      25.220182                      
+system.ruby.IFETCH.latency_hist          |        5825     91.02%     91.02% |         565      8.83%     99.84% |           0      0.00%     99.84% |           0      0.00%     99.84% |           3      0.05%     99.89% |           6      0.09%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -619,10 +619,10 @@ system.ruby.IFETCH.hit_latency_hist::total         5754
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          646                      
-system.ruby.IFETCH.miss_latency_hist::mean    76.072755                      
-system.ruby.IFETCH.miss_latency_hist::gmean    68.664868                      
-system.ruby.IFETCH.miss_latency_hist::stdev    37.280241                      
-system.ruby.IFETCH.miss_latency_hist     |          71     10.99%     10.99% |         564     87.31%     98.30% |           0      0.00%     98.30% |           1      0.15%     98.45% |           8      1.24%     99.69% |           1      0.15%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    76.157895                      
+system.ruby.IFETCH.miss_latency_hist::gmean    68.646090                      
+system.ruby.IFETCH.miss_latency_hist::stdev    38.613086                      
+system.ruby.IFETCH.miss_latency_hist     |          71     10.99%     10.99% |         565     87.46%     98.45% |           0      0.00%     98.45% |           0      0.00%     98.45% |           3      0.46%     98.92% |           6      0.93%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          646                      
 system.ruby.Directory_Controller.GETX             198      0.00%      0.00%
 system.ruby.Directory_Controller.GETS             984      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 23f7e060f..ca7e00529 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000117                       # Number of seconds simulated
-sim_ticks                                      116770                       # Number of ticks simulated
-final_tick                                     116770                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000116                       # Number of seconds simulated
+sim_ticks                                      116369                       # Number of ticks simulated
+final_tick                                     116369                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  63656                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63646                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1162909                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 451252                       # Number of bytes of host memory used
+host_inst_rate                                  61340                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61332                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1116785                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 453376                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -21,35 +21,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1176                       #
 system.mem_ctrls.num_reads::total                1176                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          228                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                228                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    644549114                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             644549114                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    124963604                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            124963604                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    769512717                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            769512717                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    646770188                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             646770188                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    125394220                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            125394220                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    772164408                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            772164408                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1176                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        228                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1176                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      228                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  64960                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   10304                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    6144                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  64320                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   10944                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5120                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   75264                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                14592                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    161                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   109                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    171                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   116                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                86                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                52                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                82                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                77                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                92                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                87                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               61                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               56                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               53                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               22                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::13              361                       # Per bank write bursts
@@ -59,21 +59,21 @@ system.mem_ctrls.perBankWrBursts::0                 0                       # Pe
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                26                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                15                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                5                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               21                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               44                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               18                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        116679                       # Total gap between requests
+system.mem_ctrls.totGap                        116278                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  228                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1015                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1005                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -137,12 +137,12 @@ system.mem_ctrls.wrQLenPdf::13                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                      6                       # What write queue length does an incoming req see
@@ -152,7 +152,7 @@ system.mem_ctrls.wrQLenPdf::28                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -184,85 +184,84 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          202                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    339.643564                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   206.317034                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   334.142270                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           63     31.19%     31.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           47     23.27%     54.46% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           25     12.38%     66.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           13      6.44%     73.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           14      6.93%     80.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            7      3.47%     83.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            3      1.49%     85.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            5      2.48%     87.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           25     12.38%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          202                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean     155.833333                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    115.513983                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     90.977836                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-31             1     16.67%     16.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-95             1     16.67%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::160-175            1     16.67%     50.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-207            1     16.67%     66.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-223            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::256-271            1     16.67%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total             6                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
+system.mem_ctrls.bytesPerActivate::samples          201                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    334.328358                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   202.953148                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   329.613215                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           65     32.34%     32.34% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           44     21.89%     54.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           26     12.94%     67.16% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           14      6.97%     74.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           13      6.47%     80.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            7      3.48%     84.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            4      1.99%     86.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            5      2.49%     88.56% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           23     11.44%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          201                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean            135                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     98.212508                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     84.208076                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87             1     20.00%     40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::160-167            1     20.00%     60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-199            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::mean             16                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                6    100.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total             6                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         7533                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   26818                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5075                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         7.42                       # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::16                5    100.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                         7422                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   26517                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5025                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         7.39                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   26.42                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       556.31                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        52.62                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    644.55                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    124.96                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   26.39                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       552.72                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        44.00                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    646.77                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    125.39                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         4.76                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.35                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.41                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.66                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.32                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.34                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      22.40                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      810                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                      92                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.80                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                77.31                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         83.10                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    79.54                       # Row buffer hit rate, read and write combined
+system.mem_ctrls.avgWrQLen                      22.99                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      804                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                      74                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 80.00                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                66.07                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         82.82                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    78.60                       # Row buffer hit rate, read and write combined
 system.mem_ctrls_0.actEnergy                   514080                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_0.preEnergy                   285600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5041920                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 269568                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4992000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
 system.mem_ctrls_0.actBackEnergy             60923196                       # Energy for active background per rank (pJ)
 system.mem_ctrls_0.preBackEnergy             12117000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               86271204                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            789.566591                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        22175                       # Time in different power states
+system.mem_ctrls_0.totalEnergy               86117604                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            788.160821                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        25118                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT         85821                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                   937440                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                   520800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 6764160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 725760                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6776640                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             72391140                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             72408924                       # Energy for active background per rank (pJ)
 system.mem_ctrls_1.preBackEnergy              2062800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               90521940                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            828.401709                       # Core power per rank (mW)
+system.mem_ctrls_1.totalEnergy               90489996                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            827.912387                       # Core power per rank (mW)
 system.mem_ctrls_1.memoryStateTime::IDLE         2878                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT        102769                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        102795                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -298,7 +297,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                           116770                       # number of cpu cycles simulated
+system.cpu.numCycles                           116369                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6390                       # Number of instructions committed
@@ -317,7 +316,7 @@ system.cpu.num_mem_refs                          2058                       # nu
 system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     116770                       # Number of busy cycles
+system.cpu.num_busy_cycles                     116369                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
@@ -367,10 +366,10 @@ system.ruby.outstanding_req_hist::total          8449
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              12.822206                      
-system.ruby.latency_hist::gmean              3.506830                      
-system.ruby.latency_hist::stdev             27.805292                      
-system.ruby.latency_hist                 |        7433     87.99%     87.99% |         995     11.78%     99.76% |           6      0.07%     99.83% |           2      0.02%     99.86% |           8      0.09%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              12.774740                      
+system.ruby.latency_hist::gmean              3.504112                      
+system.ruby.latency_hist::stdev             27.744497                      
+system.ruby.latency_hist                 |        7443     88.10%     88.10% |         986     11.67%     99.78% |           5      0.06%     99.83% |           2      0.02%     99.86% |           7      0.08%     99.94% |           5      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8448                      
 system.ruby.hit_latency_hist::bucket_size            4                      
 system.ruby.hit_latency_hist::max_bucket           39                      
@@ -383,10 +382,10 @@ system.ruby.hit_latency_hist::total              7272
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1176                      
-system.ruby.miss_latency_hist::mean         75.774660                      
-system.ruby.miss_latency_hist::gmean        72.686009                      
-system.ruby.miss_latency_hist::stdev        29.375504                      
-system.ruby.miss_latency_hist            |         161     13.69%     13.69% |         995     84.61%     98.30% |           6      0.51%     98.81% |           2      0.17%     98.98% |           8      0.68%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         75.433673                      
+system.ruby.miss_latency_hist::gmean        72.282303                      
+system.ruby.miss_latency_hist::stdev        29.690242                      
+system.ruby.miss_latency_hist            |         171     14.54%     14.54% |         986     83.84%     98.38% |           5      0.43%     98.81% |           2      0.17%     98.98% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1176                      
 system.ruby.Directory.incomplete_times           1175                      
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1311                       # Number of cache demand hits
@@ -399,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits          189                       # N
 system.ruby.l2_cntrl0.L2cache.demand_misses         1194                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1383                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.578702                      
+system.ruby.network.routers0.percent_links_utilized     5.597926                      
 system.ruby.network.routers0.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4          207                      
@@ -412,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4        14904
 system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::4        97488                      
 system.ruby.network.routers0.msg_bytes.Persistent_Control::3          320                      
-system.ruby.network.routers1.percent_links_utilized     4.210200                      
+system.ruby.network.routers1.percent_links_utilized     4.224708                      
 system.ruby.network.routers1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4          207                      
@@ -427,7 +426,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4            8
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4       113904                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4         7728                      
 system.ruby.network.routers1.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers2.percent_links_utilized     3.172048                      
+system.ruby.network.routers2.percent_links_utilized     3.182978                      
 system.ruby.network.routers2.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers2.msg_count.Writeback_Data::4          228                      
@@ -438,7 +437,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4        84672
 system.ruby.network.routers2.msg_bytes.Writeback_Data::4        16416                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::4         7728                      
 system.ruby.network.routers2.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers3.percent_links_utilized     4.320316                      
+system.ruby.network.routers3.percent_links_utilized     4.335204                      
 system.ruby.network.routers3.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers3.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers3.msg_count.Response_Data::4         1176                      
@@ -469,7 +468,7 @@ system.ruby.network.msg_byte.Response_Control           24
 system.ruby.network.msg_byte.Writeback_Data       341712                      
 system.ruby.network.msg_byte.Writeback_Control        23184                      
 system.ruby.network.msg_byte.Persistent_Control          960                      
-system.ruby.network.routers0.throttle0.link_utilization     5.338700                      
+system.ruby.network.routers0.throttle0.link_utilization     5.357097                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4          207                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4            1                      
@@ -478,21 +477,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        84672
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4        14904                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers0.throttle1.link_utilization     5.818703                      
+system.ruby.network.routers0.throttle1.link_utilization     5.838754                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4         1354                      
 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3           20                      
 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        97488                      
 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers1.throttle0.link_utilization     5.818703                      
+system.ruby.network.routers1.throttle0.link_utilization     5.838754                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4         1354                      
 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3           20                      
 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        97488                      
 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers1.throttle1.link_utilization     2.601696                      
+system.ruby.network.routers1.throttle1.link_utilization     2.610661                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4          207                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4            1                      
@@ -503,7 +502,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4        14
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        16416                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4         7728                      
-system.ruby.network.routers2.throttle0.link_utilization     1.812109                      
+system.ruby.network.routers2.throttle0.link_utilization     1.818354                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          228                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4          966                      
@@ -512,24 +511,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         9552
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        16416                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4         7728                      
 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers2.throttle1.link_utilization     4.531986                      
+system.ruby.network.routers2.throttle1.link_utilization     4.547603                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        84672                      
-system.ruby.network.routers3.throttle0.link_utilization     5.330136                      
+system.ruby.network.routers3.throttle0.link_utilization     5.348503                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4          207                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4            1                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        84672                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4        14904                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.throttle1.link_utilization     5.818703                      
+system.ruby.network.routers3.throttle1.link_utilization     5.838754                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4         1354                      
 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3           20                      
 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        97488                      
 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers3.throttle2.link_utilization     1.812109                      
+system.ruby.network.routers3.throttle2.link_utilization     1.818354                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2         1194                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4          228                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4          966                      
@@ -541,10 +540,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           29.646661                      
-system.ruby.LD.latency_hist::gmean           8.889029                      
-system.ruby.LD.latency_hist::stdev          37.195991                      
-system.ruby.LD.latency_hist              |         844     71.34%     71.34% |         335     28.32%     99.66% |           0      0.00%     99.66% |           2      0.17%     99.83% |           1      0.08%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           29.333897                      
+system.ruby.LD.latency_hist::gmean           8.854915                      
+system.ruby.LD.latency_hist::stdev          36.549796                      
+system.ruby.LD.latency_hist              |         850     71.85%     71.85% |         330     27.90%     99.75% |           0      0.00%     99.75% |           1      0.08%     99.83% |           1      0.08%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            4                      
 system.ruby.LD.hit_latency_hist::max_bucket           39                      
@@ -557,18 +556,18 @@ system.ruby.LD.hit_latency_hist::total            760
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          423                      
-system.ruby.LD.miss_latency_hist::mean      73.808511                      
-system.ruby.LD.miss_latency_hist::gmean     70.625115                      
-system.ruby.LD.miss_latency_hist::stdev     26.886169                      
-system.ruby.LD.miss_latency_hist         |          84     19.86%     19.86% |         335     79.20%     99.05% |           0      0.00%     99.05% |           2      0.47%     99.53% |           1      0.24%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      72.933806                      
+system.ruby.LD.miss_latency_hist::gmean     69.869692                      
+system.ruby.LD.miss_latency_hist::stdev     25.813501                      
+system.ruby.LD.miss_latency_hist         |          90     21.28%     21.28% |         330     78.01%     99.29% |           0      0.00%     99.29% |           1      0.24%     99.53% |           1      0.24%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           423                      
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           15.620809                      
-system.ruby.ST.latency_hist::gmean           4.414027                      
-system.ruby.ST.latency_hist::stdev          30.143438                      
-system.ruby.ST.latency_hist              |         774     89.48%     89.48% |          87     10.06%     99.54% |           2      0.23%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           15.470520                      
+system.ruby.ST.latency_hist::gmean           4.402566                      
+system.ruby.ST.latency_hist::stdev          29.923272                      
+system.ruby.ST.latency_hist              |         778     89.94%     89.94% |          83      9.60%     99.54% |           2      0.23%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            4                      
 system.ruby.ST.hit_latency_hist::max_bucket           39                      
@@ -581,18 +580,18 @@ system.ruby.ST.hit_latency_hist::total            697
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          168                      
-system.ruby.ST.miss_latency_hist::mean      66.535714                      
-system.ruby.ST.miss_latency_hist::gmean     61.950283                      
-system.ruby.ST.miss_latency_hist::stdev     36.753409                      
-system.ruby.ST.miss_latency_hist         |          77     45.83%     45.83% |          87     51.79%     97.62% |           2      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           2      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      65.761905                      
+system.ruby.ST.miss_latency_hist::gmean     61.126570                      
+system.ruby.ST.miss_latency_hist::stdev     36.894126                      
+system.ruby.ST.miss_latency_hist         |          81     48.21%     48.21% |          83     49.40%     97.62% |           2      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           2      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           168                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean        9.334062                      
-system.ruby.IFETCH.latency_hist::gmean       2.862491                      
-system.ruby.IFETCH.latency_hist::stdev      24.016058                      
-system.ruby.IFETCH.latency_hist          |        5815     90.86%     90.86% |         573      8.95%     99.81% |           4      0.06%     99.87% |           0      0.00%     99.87% |           7      0.11%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean        9.349531                      
+system.ruby.IFETCH.latency_hist::gmean       2.862602                      
+system.ruby.IFETCH.latency_hist::stdev      24.187807                      
+system.ruby.IFETCH.latency_hist          |        5815     90.86%     90.86% |         573      8.95%     99.81% |           3      0.05%     99.86% |           1      0.02%     99.87% |           6      0.09%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            4                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket           39                      
@@ -605,10 +604,10 @@ system.ruby.IFETCH.hit_latency_hist::total         5815
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          585                      
-system.ruby.IFETCH.miss_latency_hist::mean    79.849573                      
-system.ruby.IFETCH.miss_latency_hist::gmean    77.699044                      
-system.ruby.IFETCH.miss_latency_hist::stdev    27.992378                      
-system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         573     97.95%     97.95% |           4      0.68%     98.63% |           0      0.00%     98.63% |           7      1.20%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    80.018803                      
+system.ruby.IFETCH.miss_latency_hist::gmean    77.731964                      
+system.ruby.IFETCH.miss_latency_hist::stdev    29.160832                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         573     97.95%     97.95% |           3      0.51%     98.46% |           1      0.17%     98.63% |           6      1.03%     99.66% |           2      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          585                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket            9                      
@@ -628,10 +627,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total          207
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1176                      
-system.ruby.Directory.miss_mach_latency_hist::mean    75.774660                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    72.686009                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    29.375504                      
-system.ruby.Directory.miss_mach_latency_hist |         161     13.69%     13.69% |         995     84.61%     98.30% |           6      0.51%     98.81% |           2      0.17%     98.98% |           8      0.68%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    75.433673                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    72.282303                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    29.690242                      
+system.ruby.Directory.miss_mach_latency_hist |         171     14.54%     14.54% |         986     83.84%     98.38% |           5      0.43%     98.81% |           2      0.17%     98.98% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1176                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -677,10 +676,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total          102
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          423                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    73.808511                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    70.625115                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    26.886169                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |          84     19.86%     19.86% |         335     79.20%     99.05% |           0      0.00%     99.05% |           2      0.47%     99.53% |           1      0.24%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    72.933806                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    69.869692                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    25.813501                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |          90     21.28%     21.28% |         330     78.01%     99.29% |           0      0.00%     99.29% |           1      0.24%     99.53% |           1      0.24%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          423                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
@@ -700,10 +699,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           44
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          168                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    66.535714                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    61.950283                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    36.753409                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          77     45.83%     45.83% |          87     51.79%     97.62% |           2      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           2      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    65.761905                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    61.126570                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    36.894126                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          81     48.21%     48.21% |          83     49.40%     97.62% |           2      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           2      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          168                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
@@ -723,10 +722,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total           61
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          585                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    79.849573                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    77.699044                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    27.992378                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         573     97.95%     97.95% |           4      0.68%     98.63% |           0      0.00%     98.63% |           7      1.20%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    80.018803                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    77.731964                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    29.160832                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         573     97.95%     97.95% |           3      0.51%     98.46% |           1      0.17%     98.63% |           6      1.03%     99.66% |           2      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          585                      
 system.ruby.Directory_Controller.GETX             209      0.00%      0.00%
 system.ruby.Directory_Controller.GETS            1013      0.00%      0.00%
@@ -773,7 +772,7 @@ system.ruby.L1Cache_Controller.S.Ifetch           331      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.Store             21      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.L1_Replacement          142      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Load             184      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch          3298      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Ifetch          3297      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Store             32      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.L1_Replacement          944      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock            9      0.00%      0.00%
@@ -782,7 +781,7 @@ system.ruby.L1Cache_Controller.MM.Store           330      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.L1_Replacement          268      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock            1      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Load            80      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch         2125      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch         2126      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Store           25      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.L1_Replacement            6      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers          982      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 4d5f2d93a..3b710633b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000096                       # Number of seconds simulated
-sim_ticks                                       96381                       # Number of ticks simulated
-final_tick                                      96381                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                       96151                       # Number of ticks simulated
+final_tick                                      96151                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66831                       # Simulator instruction rate (inst/s)
-host_op_rate                                    66821                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1007748                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 449612                       # Number of bytes of host memory used
+host_inst_rate                                  62758                       # Simulator instruction rate (inst/s)
+host_op_rate                                    62749                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 944082                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451988                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1159                       #
 system.mem_ctrls.num_reads::total                1159                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          220                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                220                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    769612268                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             769612268                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    146086884                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            146086884                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    915699152                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            915699152                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    771453235                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             771453235                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    146436335                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            146436335                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    917889570                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            917889570                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1159                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        220                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1159                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      220                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  64192                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    9984                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    5568                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  63936                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   10240                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5504                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   74176                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                14080                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    156                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.servicedByWrQ                    160                       # Number of DRAM read bursts serviced by the write queue
 system.mem_ctrls.mergedWrBursts                   104                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                86                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                52                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                82                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                77                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                96                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                98                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               59                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               54                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               47                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               22                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::13              358                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               61                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               60                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               40                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                21                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 2                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                23                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 5                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               17                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               41                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         96301                       # Total gap between requests
+system.mem_ctrls.totGap                         96071                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  220                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1003                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     999                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,7 +136,7 @@ system.mem_ctrls.wrQLenPdf::12                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      4                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      4                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
@@ -149,7 +149,7 @@ system.mem_ctrls.wrQLenPdf::25                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::26                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
@@ -184,87 +184,86 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          194                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    352.659794                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   217.534506                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   333.874690                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           55     28.35%     28.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           50     25.77%     54.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           18      9.28%     63.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           17      8.76%     72.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           12      6.19%     78.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            7      3.61%     81.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            7      3.61%     85.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            5      2.58%     88.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           23     11.86%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          194                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          191                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    356.858639                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   222.990773                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   333.933268                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           49     25.65%     25.65% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           54     28.27%     53.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           20     10.47%     64.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           14      7.33%     71.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           12      6.28%     78.01% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            7      3.66%     81.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            8      4.19%     85.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      2.09%     87.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           23     12.04%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          191                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean            140                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    105.715654                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     81.473922                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     140.600000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    106.599883                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     79.767161                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::120-127            1     20.00%     40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::128-135            1     20.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-215            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143            1     20.00%     60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::200-207            1     20.00%     80.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      17.400000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.358321                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.341641                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      17.200000                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     17.171629                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.095445                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                2     40.00%     40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                2     40.00%     80.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                1     20.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                3     60.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         6850                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   25907                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5015                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.83                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         6736                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   25717                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4995                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         6.74                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.83                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       666.02                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        57.77                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    769.61                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    146.09                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   25.74                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       664.95                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        57.24                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    771.45                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    146.44                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         5.65                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     5.20                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtil                         5.64                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     5.19                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.45                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.24                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      808                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      21.88                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      806                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      82                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 80.56                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 80.68                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                70.69                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         69.83                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    79.54                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   476280                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   264600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5104320                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 238464                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgGap                         69.67                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    79.64                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   483840                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   268800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5129280                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 290304                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             54887580                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              8068200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               75142164                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            802.012594                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        14237                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             54680328                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              8250000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               75205272                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            802.686163                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        14296                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3120                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         77447                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         77144                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   975240                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   541800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 7063680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                   945000                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   525000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 7026240                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 601344                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             61908840                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1909200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               79165032                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            844.949750                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         2762                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             61762464                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              2037600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               79000368                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            843.192247                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         2976                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3120                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         87824                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         87610                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -300,7 +299,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            96381                       # number of cpu cycles simulated
+system.cpu.numCycles                            96151                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6390                       # Number of instructions committed
@@ -319,7 +318,7 @@ system.cpu.num_mem_refs                          2058                       # nu
 system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      96381                       # Number of busy cycles
+system.cpu.num_busy_cycles                      96151                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
@@ -369,10 +368,10 @@ system.ruby.outstanding_req_hist::total          8449
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              10.408736                      
-system.ruby.latency_hist::gmean              3.320047                      
-system.ruby.latency_hist::stdev             22.995606                      
-system.ruby.latency_hist                 |        8209     97.17%     97.17% |         227      2.69%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           7      0.08%     99.94% |           5      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              10.381510                      
+system.ruby.latency_hist::gmean              3.318518                      
+system.ruby.latency_hist::stdev             22.902466                      
+system.ruby.latency_hist                 |        8210     97.18%     97.18% |         226      2.68%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           7      0.08%     99.94% |           5      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8448                      
 system.ruby.hit_latency_hist::bucket_size            2                      
 system.ruby.hit_latency_hist::max_bucket           19                      
@@ -385,10 +384,10 @@ system.ruby.hit_latency_hist::total              7289
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1159                      
-system.ruby.miss_latency_hist::mean         61.364970                      
-system.ruby.miss_latency_hist::gmean        57.952099                      
-system.ruby.miss_latency_hist::stdev        28.717200                      
-system.ruby.miss_latency_hist            |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         61.166523                      
+system.ruby.miss_latency_hist::gmean        57.757809                      
+system.ruby.miss_latency_hist::stdev        28.525461                      
+system.ruby.miss_latency_hist            |         921     79.47%     79.47% |         226     19.50%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1159                      
 system.ruby.Directory.incomplete_times           1158                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
@@ -404,7 +403,7 @@ system.ruby.l1_cntrl0.L2cache.demand_hits          203                       # N
 system.ruby.l1_cntrl0.L2cache.demand_misses         1159                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L2cache.demand_accesses         1362                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     4.652888                      
+system.ruby.network.routers0.percent_links_utilized     4.664018                      
 system.ruby.network.routers0.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers0.msg_count.Writeback_Data::5          220                      
@@ -419,7 +418,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2         9144
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3         9144                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers1.percent_links_utilized     4.652888                      
+system.ruby.network.routers1.percent_links_utilized     4.664018                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers1.msg_count.Writeback_Data::5          220                      
@@ -434,7 +433,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2         9144
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3         9144                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers2.percent_links_utilized     4.652888                      
+system.ruby.network.routers2.percent_links_utilized     4.664018                      
 system.ruby.network.routers2.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers2.msg_count.Writeback_Data::5          220                      
@@ -459,12 +458,12 @@ system.ruby.network.msg_byte.Response_Data       250344
 system.ruby.network.msg_byte.Writeback_Data        47520                      
 system.ruby.network.msg_byte.Writeback_Control        77016                      
 system.ruby.network.msg_byte.Unblock_Control        27816                      
-system.ruby.network.routers0.throttle0.link_utilization     6.004295                      
+system.ruby.network.routers0.throttle0.link_utilization     6.018658                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1143                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        83448                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers0.throttle1.link_utilization     3.301481                      
+system.ruby.network.routers0.throttle1.link_utilization     3.309378                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2         1143                      
@@ -475,7 +474,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         9144                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers1.throttle0.link_utilization     3.301481                      
+system.ruby.network.routers1.throttle0.link_utilization     3.309378                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2         1143                      
@@ -486,17 +485,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         9144                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers1.throttle1.link_utilization     6.004295                      
+system.ruby.network.routers1.throttle1.link_utilization     6.018658                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1143                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        83448                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers2.throttle0.link_utilization     6.004295                      
+system.ruby.network.routers2.throttle0.link_utilization     6.018658                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1143                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        83448                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers2.throttle1.link_utilization     3.301481                      
+system.ruby.network.routers2.throttle1.link_utilization     3.309378                      
 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2         1159                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2         1143                      
@@ -507,13 +506,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         9144                      
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.LD.latency_hist::bucket_size           32                      
-system.ruby.LD.latency_hist::max_bucket           319                      
+system.ruby.LD.latency_hist::bucket_size           64                      
+system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           22.819949                      
-system.ruby.LD.latency_hist::gmean           7.633765                      
-system.ruby.LD.latency_hist::stdev          29.454181                      
-system.ruby.LD.latency_hist              |         845     71.43%     71.43% |         248     20.96%     92.39% |          86      7.27%     99.66% |           2      0.17%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           22.845309                      
+system.ruby.LD.latency_hist::gmean           7.610394                      
+system.ruby.LD.latency_hist::stdev          30.590449                      
+system.ruby.LD.latency_hist              |        1093     92.39%     92.39% |          87      7.35%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            2                      
 system.ruby.LD.hit_latency_hist::max_bucket           19                      
@@ -523,21 +522,21 @@ system.ruby.LD.hit_latency_hist::gmean       2.587610
 system.ruby.LD.hit_latency_hist::stdev       3.791932                      
 system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |         658     86.24%     86.24% |           0      0.00%     86.24% |           0      0.00%     86.24% |           0      0.00%     86.24% |           0      0.00%     86.24% |         105     13.76%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist::total            763                      
-system.ruby.LD.miss_latency_hist::bucket_size           32                      
-system.ruby.LD.miss_latency_hist::max_bucket          319                      
+system.ruby.LD.miss_latency_hist::bucket_size           64                      
+system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          420                      
-system.ruby.LD.miss_latency_hist::mean      57.892857                      
-system.ruby.LD.miss_latency_hist::gmean     54.485563                      
-system.ruby.LD.miss_latency_hist::stdev     22.570398                      
-system.ruby.LD.miss_latency_hist         |          82     19.52%     19.52% |         248     59.05%     78.57% |          86     20.48%     99.05% |           2      0.48%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           2      0.48%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      57.964286                      
+system.ruby.LD.miss_latency_hist::gmean     54.017024                      
+system.ruby.LD.miss_latency_hist::stdev     26.398202                      
+system.ruby.LD.miss_latency_hist         |         330     78.57%     78.57% |          87     20.71%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           2      0.48%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           420                      
 system.ruby.ST.latency_hist::bucket_size           16                      
 system.ruby.ST.latency_hist::max_bucket           159                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           11.716763                      
-system.ruby.ST.latency_hist::gmean           3.868197                      
-system.ruby.ST.latency_hist::stdev          20.732802                      
-system.ruby.ST.latency_hist              |         707     81.73%     81.73% |          44      5.09%     86.82% |           0      0.00%     86.82% |          74      8.55%     95.38% |          36      4.16%     99.54% |           4      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           11.801156                      
+system.ruby.ST.latency_hist::gmean           3.876538                      
+system.ruby.ST.latency_hist::stdev          20.845047                      
+system.ruby.ST.latency_hist              |         707     81.73%     81.73% |          41      4.74%     86.47% |           0      0.00%     86.47% |          78      9.02%     95.49% |          35      4.05%     99.54% |           4      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            2                      
 system.ruby.ST.hit_latency_hist::max_bucket           19                      
@@ -550,18 +549,18 @@ system.ruby.ST.hit_latency_hist::total            707
 system.ruby.ST.miss_latency_hist::bucket_size           16                      
 system.ruby.ST.miss_latency_hist::max_bucket          159                      
 system.ruby.ST.miss_latency_hist::samples          158                      
-system.ruby.ST.miss_latency_hist::mean      52.898734                      
-system.ruby.ST.miss_latency_hist::gmean     50.075344                      
-system.ruby.ST.miss_latency_hist::stdev     15.909453                      
-system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |          44     27.85%     27.85% |           0      0.00%     27.85% |          74     46.84%     74.68% |          36     22.78%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      53.360759                      
+system.ruby.ST.miss_latency_hist::gmean     50.669354                      
+system.ruby.ST.miss_latency_hist::stdev     15.502298                      
+system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |          41     25.95%     25.95% |           0      0.00%     25.95% |          78     49.37%     75.32% |          35     22.15%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           158                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean        7.937812                      
-system.ruby.IFETCH.latency_hist::gmean       2.788278                      
-system.ruby.IFETCH.latency_hist::stdev      21.093490                      
-system.ruby.IFETCH.latency_hist          |        6291     98.30%     98.30% |          99      1.55%     99.84% |           0      0.00%     99.84% |           0      0.00%     99.84% |           5      0.08%     99.92% |           5      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean        7.885781                      
+system.ruby.IFETCH.latency_hist::gmean       2.787351                      
+system.ruby.IFETCH.latency_hist::stdev      20.631367                      
+system.ruby.IFETCH.latency_hist          |        6291     98.30%     98.30% |         100      1.56%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           5      0.08%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            2                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket           19                      
@@ -574,10 +573,10 @@ system.ruby.IFETCH.hit_latency_hist::total         5819
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          581                      
-system.ruby.IFETCH.miss_latency_hist::mean    66.177281                      
-system.ruby.IFETCH.miss_latency_hist::gmean    63.050334                      
-system.ruby.IFETCH.miss_latency_hist::stdev    34.037169                      
-system.ruby.IFETCH.miss_latency_hist     |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           0      0.00%     98.28% |           5      0.86%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    65.604131                      
+system.ruby.IFETCH.miss_latency_hist::gmean    62.819819                      
+system.ruby.IFETCH.miss_latency_hist::stdev    31.817772                      
+system.ruby.IFETCH.miss_latency_hist     |         472     81.24%     81.24% |         100     17.21%     98.45% |           0      0.00%     98.45% |           0      0.00%     98.45% |           5      0.86%     99.31% |           4      0.69%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          581                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket            9                      
@@ -596,10 +595,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total          203
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1159                      
-system.ruby.Directory.miss_mach_latency_hist::mean    61.364970                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    57.952099                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    28.717200                      
-system.ruby.Directory.miss_mach_latency_hist |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    61.166523                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    57.757809                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    28.525461                      
+system.ruby.Directory.miss_mach_latency_hist |         921     79.47%     79.47% |         226     19.50%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1159                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -641,13 +640,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean           13
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean    13.000000                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         105    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total          105                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          420                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    57.892857                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    54.485563                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    22.570398                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |          82     19.52%     19.52% |         248     59.05%     78.57% |          86     20.48%     99.05% |           2      0.48%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           2      0.48%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    57.964286                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    54.017024                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    26.398202                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |         330     78.57%     78.57% |          87     20.71%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           2      0.48%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          420                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
@@ -666,10 +665,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           33
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           16                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          159                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          158                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    52.898734                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    50.075344                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    15.909453                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |          44     27.85%     27.85% |           0      0.00%     27.85% |          74     46.84%     74.68% |          36     22.78%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    53.360759                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    50.669354                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    15.502298                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |          41     25.95%     25.95% |           0      0.00%     25.95% |          78     49.37%     75.32% |          35     22.15%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          158                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
@@ -688,10 +687,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total           65
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          581                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    66.177281                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    63.050334                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    34.037169                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           0      0.00%     98.28% |           5      0.86%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    65.604131                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    62.819819                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    31.817772                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         472     81.24%     81.24% |         100     17.21%     98.45% |           0      0.00%     98.45% |           0      0.00%     98.45% |           5      0.86%     99.31% |           4      0.69%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          581                      
 system.ruby.Directory_Controller.GETX             185      0.00%      0.00%
 system.ruby.Directory_Controller.GETS            1020      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index e18c35fff..8d98e090f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000124                       # Number of seconds simulated
-sim_ticks                                      123564                       # Number of ticks simulated
-final_tick                                     123564                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      123531                       # Number of ticks simulated
+final_tick                                     123531                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  69668                       # Simulator instruction rate (inst/s)
-host_op_rate                                    69633                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1346306                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 450680                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  63521                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63513                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1227662                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451804                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1730                       #
 system.mem_ctrls.num_reads::total                1730                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1726                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1726                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    896053867                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             896053867                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    893982066                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            893982066                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1790035933                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1790035933                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    896293238                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             896293238                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    894220884                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            894220884                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1790514122                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1790514122                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1730                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1726                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1730                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1726                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  56704                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   54016                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   57536                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  56832                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   53888                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   56512                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                  110720                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys               110464                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    844                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   803                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    842                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   814                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                85                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                44                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2                71                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                65                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4               112                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                22                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                82                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1                51                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2                81                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                66                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4               118                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                25                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               55                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               32                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12               20                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              276                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               80                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               19                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                84                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1                44                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2                73                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                62                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4               130                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                23                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               52                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               33                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12               18                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              264                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               73                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               20                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                81                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1                51                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2                85                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                63                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4               127                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                25                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               53                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               48                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11               32                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               15                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13              277                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               81                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12               12                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13              260                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               74                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15               20                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        123476                       # Total gap between requests
+system.mem_ctrls.totGap                        123443                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1726                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     886                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     888                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      9                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                     12                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     52                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     59                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     51                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     55                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     55                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                     55                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                     55                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::26                     55                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::27                     55                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     55                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     54                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     54                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     54                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     54                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          258                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    429.147287                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   269.046347                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   361.589640                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           63     24.42%     24.42% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           51     19.77%     44.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           24      9.30%     53.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           27     10.47%     63.95% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           14      5.43%     69.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           11      4.26%     73.64% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           12      4.65%     78.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023           14      5.43%     83.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           42     16.28%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          258                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           55                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      15.927273                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.760356                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.949291                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            29     52.73%     52.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            21     38.18%     90.91% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             4      7.27%     98.18% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37             1      1.82%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            55                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           55                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.345455                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.329469                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.750757                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               44     80.00%     80.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                4      7.27%     87.27% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                6     10.91%     98.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                1      1.82%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            55                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        10464                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   27298                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4430                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        11.81                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          268                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    416.477612                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   263.436899                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   359.508293                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           60     22.39%     22.39% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           57     21.27%     43.66% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           40     14.93%     58.58% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           20      7.46%     66.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           10      3.73%     69.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           14      5.22%     75.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895           11      4.10%     79.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023           12      4.48%     83.58% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           44     16.42%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          268                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           54                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.203704                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.997541                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.176444                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             2      3.70%      3.70% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            22     40.74%     44.44% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            22     40.74%     85.19% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             6     11.11%     96.30% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23             1      1.85%     98.15% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37             1      1.85%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            54                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           54                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.351852                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.333537                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.804642                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               45     83.33%     83.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                8     14.81%     98.15% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                1      1.85%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            54                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        10373                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   27245                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4440                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        11.68                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   30.81                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       458.90                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       465.64                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    896.05                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    893.98                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   30.68                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       460.06                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       457.47                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    896.29                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    894.22                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         7.22                       # Data bus utilization in percentage
+system.mem_ctrls.busUtil                         7.17                       # Data bus utilization in percentage
 system.mem_ctrls.busUtilRead                     3.59                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    3.64                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtilWrite                    3.57                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.06                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      665                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     854                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 75.06                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                92.52                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         35.73                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    83.97                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   771120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   428400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 4879680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                4281984                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen                      25.91                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      672                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     824                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 75.68                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                90.35                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         35.72                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    83.11                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   824040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   457800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5229120                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                4520448                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             69480720                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              9282000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               96752304                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            826.589526                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        15125                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             66802176                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             11631600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               97093584                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            829.505203                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        19845                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3900                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         98100                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         94170                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1081080                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   600600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 5466240                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                4323456                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                  1118880                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   621600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 5191680                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                4136832                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             69027912                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              9680400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               97808088                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            835.595188                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        15368                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             69356232                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              9391800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               97445424                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            832.503985                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE        15122                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3900                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         97798                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         98043                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -300,7 +301,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                           123564                       # number of cpu cycles simulated
+system.cpu.numCycles                           123531                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6390                       # Number of instructions committed
@@ -319,7 +320,7 @@ system.cpu.num_mem_refs                          2058                       # nu
 system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     123564                       # Number of busy cycles
+system.cpu.num_busy_cycles                     123531                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
@@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total          8449
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              13.626420                      
-system.ruby.latency_hist::gmean              5.329740                      
-system.ruby.latency_hist::stdev             25.242996                      
-system.ruby.latency_hist                 |        8195     97.01%     97.01% |         199      2.36%     99.36% |          43      0.51%     99.87% |           2      0.02%     99.89% |           5      0.06%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              13.622514                      
+system.ruby.latency_hist::gmean              5.329433                      
+system.ruby.latency_hist::stdev             25.311843                      
+system.ruby.latency_hist                 |        8197     97.03%     97.03% |         202      2.39%     99.42% |          36      0.43%     99.85% |           3      0.04%     99.88% |           8      0.09%     99.98% |           1      0.01%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8448                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total              6718
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1730                      
-system.ruby.miss_latency_hist::mean         54.891329                      
-system.ruby.miss_latency_hist::gmean        49.648144                      
-system.ruby.miss_latency_hist::stdev        31.153546                      
-system.ruby.miss_latency_hist            |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         54.872254                      
+system.ruby.miss_latency_hist::gmean        49.634160                      
+system.ruby.miss_latency_hist::stdev        31.450318                      
+system.ruby.miss_latency_hist            |        1479     85.49%     85.49% |         202     11.68%     97.17% |          36      2.08%     99.25% |           3      0.17%     99.42% |           8      0.46%     99.88% |           1      0.06%     99.94% |           1      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1730                      
 system.ruby.Directory.incomplete_times           1729                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1730                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8448                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.992328                      
+system.ruby.network.routers0.percent_links_utilized     6.994196                      
 system.ruby.network.routers0.msg_count.Control::2         1730                      
 system.ruby.network.routers0.msg_count.Data::2         1726                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1730                      
@@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2        13840
 system.ruby.network.routers0.msg_bytes.Data::2       124272                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers1.percent_links_utilized     6.992328                      
+system.ruby.network.routers1.percent_links_utilized     6.994196                      
 system.ruby.network.routers1.msg_count.Control::2         1730                      
 system.ruby.network.routers1.msg_count.Data::2         1726                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1730                      
@@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2        13840
 system.ruby.network.routers1.msg_bytes.Data::2       124272                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers2.percent_links_utilized     6.992328                      
+system.ruby.network.routers2.percent_links_utilized     6.994196                      
 system.ruby.network.routers2.msg_count.Control::2         1730                      
 system.ruby.network.routers2.msg_count.Data::2         1726                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1730                      
@@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control            41520
 system.ruby.network.msg_byte.Data              372816                      
 system.ruby.network.msg_byte.Response_Data       373680                      
 system.ruby.network.msg_byte.Writeback_Control        41424                      
-system.ruby.network.routers0.throttle0.link_utilization     6.998802                      
+system.ruby.network.routers0.throttle0.link_utilization     7.000672                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1730                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1726                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers0.throttle1.link_utilization     6.985853                      
+system.ruby.network.routers0.throttle1.link_utilization     6.987720                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1730                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1726                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        13840                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2       124272                      
-system.ruby.network.routers1.throttle0.link_utilization     6.985853                      
+system.ruby.network.routers1.throttle0.link_utilization     6.987720                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1730                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1726                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        13840                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2       124272                      
-system.ruby.network.routers1.throttle1.link_utilization     6.998802                      
+system.ruby.network.routers1.throttle1.link_utilization     7.000672                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1730                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1726                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers2.throttle0.link_utilization     6.998802                      
+system.ruby.network.routers2.throttle0.link_utilization     7.000672                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1730                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1726                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers2.throttle1.link_utilization     6.985853                      
+system.ruby.network.routers2.throttle1.link_utilization     6.987720                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1730                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1726                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        13840                      
@@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total            1726                       # de
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           33.711750                      
-system.ruby.LD.latency_hist::gmean          16.462445                      
-system.ruby.LD.latency_hist::stdev          33.973523                      
-system.ruby.LD.latency_hist              |        1077     91.04%     91.04% |          86      7.27%     98.31% |          15      1.27%     99.58% |           2      0.17%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           32.793745                      
+system.ruby.LD.latency_hist::gmean          16.273400                      
+system.ruby.LD.latency_hist::stdev          32.397171                      
+system.ruby.LD.latency_hist              |        1086     91.80%     91.80% |          85      7.19%     98.99% |           8      0.68%     99.66% |           1      0.08%     99.75% |           2      0.17%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total            456
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          727                      
-system.ruby.LD.miss_latency_hist::mean      52.975241                      
-system.ruby.LD.miss_latency_hist::gmean     47.891138                      
-system.ruby.LD.miss_latency_hist::stdev     30.251097                      
-system.ruby.LD.miss_latency_hist         |         621     85.42%     85.42% |          86     11.83%     97.25% |          15      2.06%     99.31% |           2      0.28%     99.59% |           2      0.28%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      51.481431                      
+system.ruby.LD.miss_latency_hist::gmean     46.999464                      
+system.ruby.LD.miss_latency_hist::stdev     28.311858                      
+system.ruby.LD.miss_latency_hist         |         630     86.66%     86.66% |          85     11.69%     98.35% |           8      1.10%     99.45% |           1      0.14%     99.59% |           2      0.28%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           727                      
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           18.557225                      
-system.ruby.ST.latency_hist::gmean           7.162336                      
-system.ruby.ST.latency_hist::stdev          28.547301                      
-system.ruby.ST.latency_hist              |         834     96.42%     96.42% |          21      2.43%     98.84% |           9      1.04%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           18.649711                      
+system.ruby.ST.latency_hist::gmean           7.153271                      
+system.ruby.ST.latency_hist::stdev          30.101235                      
+system.ruby.ST.latency_hist              |         832     96.18%     96.18% |          24      2.77%     98.96% |           6      0.69%     99.65% |           1      0.12%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total            592
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          273                      
-system.ruby.ST.miss_latency_hist::mean      52.293040                      
-system.ruby.ST.miss_latency_hist::gmean     47.271858                      
-system.ruby.ST.miss_latency_hist::stdev     30.324989                      
-system.ruby.ST.miss_latency_hist         |         242     88.64%     88.64% |          21      7.69%     96.34% |           9      3.30%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      52.586081                      
+system.ruby.ST.miss_latency_hist::gmean     47.082552                      
+system.ruby.ST.miss_latency_hist::stdev     34.484663                      
+system.ruby.ST.miss_latency_hist         |         240     87.91%     87.91% |          24      8.79%     96.70% |           6      2.20%     98.90% |           1      0.37%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           273                      
-system.ruby.IFETCH.latency_hist::bucket_size           64                      
-system.ruby.IFETCH.latency_hist::max_bucket          639                      
+system.ruby.IFETCH.latency_hist::bucket_size           32                      
+system.ruby.IFETCH.latency_hist::max_bucket          319                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean        9.247344                      
-system.ruby.IFETCH.latency_hist::gmean       4.157427                      
-system.ruby.IFETCH.latency_hist::stdev      20.515003                      
-system.ruby.IFETCH.latency_hist          |        6284     98.19%     98.19% |          92      1.44%     99.63% |          19      0.30%     99.92% |           0      0.00%     99.92% |           3      0.05%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean        9.399375                      
+system.ruby.IFETCH.latency_hist::gmean       4.166708                      
+system.ruby.IFETCH.latency_hist::stdev      20.983950                      
+system.ruby.IFETCH.latency_hist          |        5670     88.59%     88.59% |         609      9.52%     98.11% |          88      1.38%     99.48% |           5      0.08%     99.56% |           5      0.08%     99.64% |          17      0.27%     99.91% |           1      0.02%     99.92% |           0      0.00%     99.92% |           1      0.02%     99.94% |           4      0.06%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -535,21 +536,21 @@ system.ruby.IFETCH.hit_latency_hist::mean            3
 system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
 system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        5670    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist::total         5670                      
-system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
-system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
+system.ruby.IFETCH.miss_latency_hist::bucket_size           32                      
+system.ruby.IFETCH.miss_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.miss_latency_hist::samples          730                      
-system.ruby.IFETCH.miss_latency_hist::mean    57.771233                      
-system.ruby.IFETCH.miss_latency_hist::gmean    52.414605                      
-system.ruby.IFETCH.miss_latency_hist::stdev    32.138819                      
-system.ruby.IFETCH.miss_latency_hist     |         614     84.11%     84.11% |          92     12.60%     96.71% |          19      2.60%     99.32% |           0      0.00%     99.32% |           3      0.41%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    59.104110                      
+system.ruby.IFETCH.miss_latency_hist::gmean    53.449398                      
+system.ruby.IFETCH.miss_latency_hist::stdev    32.750880                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         609     83.42%     83.42% |          88     12.05%     95.48% |           5      0.68%     96.16% |           5      0.68%     96.85% |          17      2.33%     99.18% |           1      0.14%     99.32% |           0      0.00%     99.32% |           1      0.14%     99.45% |           4      0.55%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          730                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1730                      
-system.ruby.Directory.miss_mach_latency_hist::mean    54.891329                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    49.648144                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    31.153546                      
-system.ruby.Directory.miss_mach_latency_hist |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    54.872254                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    49.634160                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    31.450318                      
+system.ruby.Directory.miss_mach_latency_hist |        1479     85.49%     85.49% |         202     11.68%     97.17% |          36      2.08%     99.25% |           3      0.17%     99.42% |           8      0.46%     99.88% |           1      0.06%     99.94% |           1      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1730                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          727                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    52.975241                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    47.891138                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    30.251097                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |         621     85.42%     85.42% |          86     11.83%     97.25% |          15      2.06%     99.31% |           2      0.28%     99.59% |           2      0.28%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    51.481431                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    46.999464                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    28.311858                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |         630     86.66%     86.66% |          85     11.69%     98.35% |           8      1.10%     99.45% |           1      0.14%     99.59% |           2      0.28%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          727                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          273                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    52.293040                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.271858                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    30.324989                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |         242     88.64%     88.64% |          21      7.69%     96.34% |           9      3.30%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    52.586081                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.082552                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    34.484663                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |         240     87.91%     87.91% |          24      8.79%     96.70% |           6      2.20%     98.90% |           1      0.37%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          273                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           32                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          730                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    57.771233                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    52.414605                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    32.138819                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         614     84.11%     84.11% |          92     12.60%     96.71% |          19      2.60%     99.32% |           0      0.00%     99.32% |           3      0.41%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    59.104110                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    53.449398                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    32.750880                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         609     83.42%     83.42% |          88     12.05%     95.48% |           5      0.68%     96.16% |           5      0.68%     96.85% |          17      2.33%     99.18% |           1      0.14%     99.32% |           0      0.00%     99.32% |           1      0.14%     99.45% |           4      0.55%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          730                      
 system.ruby.Directory_Controller.GETX            1730      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1726      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 95d6f5391..2c1174c59 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                    32544500                       # Number of ticks simulated
 final_tick                                   32544500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 643051                       # Simulator instruction rate (inst/s)
-host_op_rate                                   642147                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3266208350                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291356                       # Number of bytes of host memory used
+host_inst_rate                                 619666                       # Simulator instruction rate (inst/s)
+host_op_rate                                   618826                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3148046044                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 291528                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.757933                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           103.755352                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1880                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.190476                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.757933                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025332                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025332                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.755352                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025331                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025331                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
@@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5082500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5082500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3905500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3905500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8988000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8988000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8988000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8988000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5130000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5130000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3942000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3942000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9072000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9072000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9072000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9072000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031
 system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           127.992738                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           127.988451                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6122                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             21.942652                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   127.992738                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.062496                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.062496                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   127.988451                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.062494                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.062494                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
@@ -290,97 +290,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          279
 system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14885000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14885000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14885000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14885000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14885000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14885000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15024500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15024500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15024500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15024500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15024500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15024500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043587                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.043587                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.043587                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          184.488660                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          184.465722                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              373                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002681                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   128.011543                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.477117                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003907                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001724                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.994443                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.471279                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003906                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001723                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005629                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          373                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011383                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4022                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4022                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          373                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           95                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           95                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14595500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4987500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     19583000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3832500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      3832500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     14595500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     14595500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4987500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4987500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     14595500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      8820000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     23415500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     14595500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      8820000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     23415500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          279                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          374                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          279                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          279                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           95                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           95                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997326                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996416                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076                       # average overall miss latency
@@ -395,55 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          373                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           95                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           95                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11259000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3847500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15106500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2956500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2956500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11259000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     18063000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11259000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6804000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     18063000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997326                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3102500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3102500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     11815500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     11815500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4037500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4037500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11815500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     18955500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11815500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7140000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     18955500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996416                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            374                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           374                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           95                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          336                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               894                       # Packet count per connected master and slave (bytes)
@@ -468,10 +478,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        418500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        252000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 373                       # Transaction distribution
 system.membus.trans_dist::ReadResp                373                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           373                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          892                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 7408970f9..7c57b2554 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20287000                       # Number of ticks simulated
-final_tick                                   20287000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20091000                       # Number of ticks simulated
+final_tick                                   20091000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140405                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140306                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1100341704                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292772                       # Number of bytes of host memory used
+host_inst_rate                                 125803                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125723                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              976523768                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293292                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           14272                       # Nu
 system.physmem.num_reads::cpu.inst                223                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            703504707                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            268152019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               971656726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       703504707                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          703504707                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           703504707                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           268152019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              971656726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            710367826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            270768006                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               981135832                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       710367826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          710367826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           710367826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           270768006                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              981135832                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           308                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         308                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20198000                       # Total gap between requests
+system.physmem.totGap                        20003000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       243                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        62                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -187,77 +187,77 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      427.707317                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     281.056415                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.596590                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      430.829268                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     282.802413                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.088769                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             10     24.39%     24.39% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255            6     14.63%     39.02% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            4      9.76%     48.78% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511            2      4.88%     53.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7     17.07%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      4.88%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      9.76%     85.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6     14.63%     68.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      9.76%     78.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      7.32%     85.37% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023            3      7.32%     92.68% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            3      7.32%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
-system.physmem.totQLat                        1763250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7538250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1567250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7342250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5724.84                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5088.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24474.84                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         971.66                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23838.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         981.14                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      971.66                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      981.14                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.59                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.59                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.67                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.67                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.26                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        258                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.77                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        65577.92                       # Average gap between requests
+system.physmem.avgGap                        64944.81                       # Average gap between requests
 system.physmem.pageHitRate                      83.77                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                    780000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10555830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 240000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12721485                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              803.504500                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         765250                       # Time in different power states
+system.physmem_0.actBackEnergy               10605420                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 196500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12727575                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              803.889152                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         536250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        14968250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15041250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1185600                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   1201200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10492560                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 300000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13287405                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              838.851326                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         458000                       # Time in different power states
+system.physmem_1.actBackEnergy               10489995                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 299250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13299690                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              839.892011                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         457000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14875250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14871250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                     791                       # Number of BP lookups
+system.cpu.branchPred.lookups                     793                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               397                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups                  563                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                      58                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             10.301954                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     136                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                     138                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -276,10 +276,10 @@ system.cpu.dtb.data_hits                          816                       # DT
 system.cpu.dtb.data_misses                         13                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
 system.cpu.dtb.data_accesses                      829                       # DTB accesses
-system.cpu.itb.fetch_hits                         969                       # ITB hits
+system.cpu.itb.fetch_hits                         971                       # ITB hits
 system.cpu.itb.fetch_misses                        13                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     982                       # ITB accesses
+system.cpu.itb.fetch_accesses                     984                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +293,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            40574                       # number of cpu cycles simulated
+system.cpu.numCycles                            40182                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2585                       # Number of instructions committed
 system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                           594                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              15.695938                       # CPI: cycles per instruction
-system.cpu.ipc                               0.063711                       # IPC: instructions per cycle
-system.cpu.tickCycles                            5391                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           35183                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              15.544294                       # CPI: cycles per instruction
+system.cpu.ipc                               0.064332                       # IPC: instructions per cycle
+system.cpu.tickCycles                            5392                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           34790                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.342007                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            48.329975                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    48.342007                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011802                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011802                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    48.329975                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011799                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011799                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
@@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data          104                       # n
 system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          104                       # number of overall misses
 system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4962000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4962000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      3282500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3282500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      8244500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      8244500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      8244500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      8244500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4723000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4723000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3258500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3258500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7981500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7981500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7981500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7981500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          502                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          502                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
@@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.130653
 system.cpu.dcache.demand_miss_rate::total     0.130653                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.130653                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.130653                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 79274.038462                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 79274.038462                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76745.192308                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76745.192308                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4628250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4628250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2009000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2009000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6637250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6637250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6637250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6637250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4442000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4442000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2017500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2017500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6459500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6459500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6459500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6459500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.115538                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115538                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
@@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.106784
 system.cpu.dcache.demand_mshr_miss_rate::total     0.106784                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.106784                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.106784                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           117.949271                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 746                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           117.935175                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 748                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.345291                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.354260                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   117.949271                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.057592                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2161                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2161                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          746                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             746                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           746                       # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total             746                       # number of overall hits
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 system.cpu.icache.demand_misses::total            223                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
 system.cpu.icache.overall_misses::total           223                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17117250                       # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst          969                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total          969                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.230134                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610                       # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 76758.968610                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76758.968610                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16978500                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst          971                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229660                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::cpu.inst     0.229660                       # miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76136.771300                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76136.771300                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -481,97 +481,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          223
 system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16684250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16684250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16684250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16684250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16684250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16684250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.230134                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.230134                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574                       # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          145.900805                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   118.086871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    27.813934                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.tag_accesses             2772                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2772                       # Number of data accesses
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 system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          223                       # number of demand (read+write) misses
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 system.cpu.l2cache.demand_misses::total           308                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1982000                       # number of ReadExReq miss cycles
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.overall_accesses::total          308                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -580,55 +585,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          223                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           58                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          223                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          223                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           58                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           58                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          223                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          308                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     13669750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3841250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     17511000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1642000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1642000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     13669750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5483250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     19153000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     13669750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5483250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     19153000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1707000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1707000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14191000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14191000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3774000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3774000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14191000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5481000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14191000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5481000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19672000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          223                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           58                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          446                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               616                       # Packet count per connected master and slave (bytes)
@@ -649,14 +659,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            308                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        383750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        143250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        334500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                281                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           281                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          616                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    616                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19712                       # Cumulative packet size per connected master and slave (bytes)
@@ -672,9 +682,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 308                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              360000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              359500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            1638500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              8.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            1638750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              8.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 493ed4968..ee80959b5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    12774000                       # Number of ticks simulated
-final_tick                                   12774000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12591500                       # Number of ticks simulated
+final_tick                                   12591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38054                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38045                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              203548685                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224448                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  74456                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74426                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              392441951                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293552                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           11968                       # Nu
 system.physmem.num_reads::cpu.inst                187                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   272                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            936903084                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            425865038                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1362768123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       936903084                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          936903084                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           936903084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           425865038                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1362768123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            950482468                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            432037486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1382519954                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       950482468                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          950482468                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           950482468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           432037486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1382519954                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           272                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         272                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        12677500                       # Total gap between requests
+system.physmem.totGap                        12495000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -92,8 +92,8 @@ system.physmem.writePktSize::5                      0                       # Wr
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       156                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                        82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -187,9 +187,9 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           36                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      394.666667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     235.952583                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.320824                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      398.222222                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     237.741650                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.174986                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             12     33.33%     33.33% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255            5     13.89%     47.22% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            3      8.33%     55.56% # Bytes accessed per row activation
@@ -200,37 +200,37 @@ system.physmem.bytesPerActivate::768-895            2      5.56%     83.33% # By
 system.physmem.bytesPerActivate::896-1023            1      2.78%     86.11% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            5     13.89%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
-system.physmem.totQLat                        1960500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7060500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1676750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   6776750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7207.72                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6164.52                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25957.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1362.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24914.52                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1382.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1362.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1382.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.65                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.65                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.80                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.80                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.71                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        226                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.09                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        46608.46                       # Average gap between requests
+system.physmem.avgGap                        45937.50                       # Average gap between requests
 system.physmem.pageHitRate                      83.09                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    585000                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                    592800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
 system.physmem_0.actBackEnergy                5478840                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  21750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                  6699315                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              832.600901                       # Core power per rank (mW)
+system.physmem_0.totalEnergy                  6707115                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              833.570297                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          260000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
@@ -238,48 +238,48 @@ system.physmem_0.memoryStateTime::ACT         7777500                       # Ti
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    787800                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                    795600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
 system.physmem_1.actBackEnergy                5200965                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy                 265500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                  6961470                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              865.181917                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         428500                       # Time in different power states
+system.physmem_1.totalEnergy                  6969270                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              866.151313                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         708000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          260000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT         7371500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1106                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               562                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               228                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  735                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     214                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1086                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               546                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               229                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  723                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     206                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             29.115646                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     201                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             28.492393                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     197                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  9                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          705                       # DTB read hits
-system.cpu.dtb.read_misses                         25                       # DTB read misses
+system.cpu.dtb.read_hits                          688                       # DTB read hits
+system.cpu.dtb.read_misses                         18                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      730                       # DTB read accesses
-system.cpu.dtb.write_hits                         367                       # DTB write hits
-system.cpu.dtb.write_misses                        19                       # DTB write misses
+system.cpu.dtb.read_accesses                      706                       # DTB read accesses
+system.cpu.dtb.write_hits                         353                       # DTB write hits
+system.cpu.dtb.write_misses                        17                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     386                       # DTB write accesses
-system.cpu.dtb.data_hits                         1072                       # DTB hits
-system.cpu.dtb.data_misses                         44                       # DTB misses
+system.cpu.dtb.write_accesses                     370                       # DTB write accesses
+system.cpu.dtb.data_hits                         1041                       # DTB hits
+system.cpu.dtb.data_misses                         35                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1116                       # DTB accesses
-system.cpu.itb.fetch_hits                         947                       # ITB hits
+system.cpu.dtb.data_accesses                     1076                       # DTB accesses
+system.cpu.itb.fetch_hits                         931                       # ITB hits
 system.cpu.itb.fetch_misses                        26                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     973                       # ITB accesses
+system.cpu.itb.fetch_accesses                     957                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,236 +293,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            25549                       # number of cpu cycles simulated
+system.cpu.numCycles                            25184                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4412                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           6683                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1106                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                415                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1538                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     502                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               4404                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           6508                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        1086                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                403                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1405                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     504                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1107                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          1109                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                       947                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   152                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               7337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.910863                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.331734                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                       931                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   153                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples               7199                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.904014                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.325149                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     6194     84.42%     84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       50      0.68%     85.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      126      1.72%     86.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       86      1.17%     87.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      137      1.87%     89.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       59      0.80%     90.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       69      0.94%     91.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       62      0.85%     92.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      554      7.55%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     6086     84.54%     84.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       49      0.68%     85.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      124      1.72%     86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       82      1.14%     88.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      134      1.86%     89.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       58      0.81%     90.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       66      0.92%     91.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       57      0.79%     92.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      543      7.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 7337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.043289                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.261576                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5200                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   911                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                       995                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    54                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    177                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  159                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                 7199                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.043123                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.258418                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5197                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   794                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                       972                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    58                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    178                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  158                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    76                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   5779                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   271                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    177                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5279                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     611                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            290                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                       960                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    20                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5531                       # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts                   5639                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   276                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    178                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     5280                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     486                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            288                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                       942                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                    25                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   5401                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands                3966                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6277                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6270                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                     13                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RenamedOperands                3881                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  6093                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             6086                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 6                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2198                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     2113                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       117                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  895                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 472                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4768                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                       109                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                  882                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 453                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 2                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       4674                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      3966                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                23                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2386                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1238                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      3880                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                15                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            2292                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1214                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          7337                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.540548                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.288327                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7199                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.538964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.280196                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                5813     79.23%     79.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 503      6.86%     86.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 359      4.89%     90.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 255      3.48%     94.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 198      2.70%     97.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 113      1.54%     98.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  62      0.85%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  21      0.29%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  13      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5699     79.16%     79.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 500      6.95%     86.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 351      4.88%     90.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 251      3.49%     94.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 194      2.69%     97.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 116      1.61%     98.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  57      0.79%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  21      0.29%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  10      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            7337                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7199                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      11     18.97%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     22     37.93%     56.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    25     43.10%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6     11.76%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     22     43.14%     54.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    23     45.10%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2817     71.03%     71.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  757     19.09%     90.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 391      9.86%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2765     71.26%     71.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  738     19.02%     90.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 376      9.69%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   3966                       # Type of FU issued
-system.cpu.iq.rate                           0.155231                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          58                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014624                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              15337                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              7157                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3670                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   3880                       # Type of FU issued
+system.cpu.iq.rate                           0.154066                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          51                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013144                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              15012                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              6969                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3584                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   4017                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   3924                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          480                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          467                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation            3                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          178                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation            4                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          159                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            24                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    177                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     538                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5114                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    178                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     422                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     4                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                5018                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                28                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   895                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  472                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                   882                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  453                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents              3                       # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents              4                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             21                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          167                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  188                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3845                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   731                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               121                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          168                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  189                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  3751                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   707                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               129                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           340                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1117                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      655                       # Number of branches executed
-system.cpu.iew.exec_stores                        386                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.150495                       # Inst execution rate
-system.cpu.iew.wb_sent                           3743                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3676                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1745                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2262                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           338                       # number of nop insts executed
+system.cpu.iew.exec_refs                         1077                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      639                       # Number of branches executed
+system.cpu.iew.exec_stores                        370                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.148944                       # Inst execution rate
+system.cpu.iew.wb_sent                           3648                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3590                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1708                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2182                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.143880                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.771441                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.142551                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.782768                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2526                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2428                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               154                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         6873                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.374800                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.238011                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               155                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples         6748                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.381743                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.245988                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         6022     87.62%     87.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          192      2.79%     90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          299      4.35%     94.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          111      1.62%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           72      1.05%     97.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           55      0.80%     98.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           33      0.48%     98.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           20      0.29%     99.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           69      1.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5894     87.34%     87.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          193      2.86%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          303      4.49%     94.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          109      1.62%     96.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           72      1.07%     97.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           56      0.83%     98.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           33      0.49%     98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           20      0.30%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           68      1.01%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         6873                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6748                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,101 +568,101 @@ system.cpu.commit.op_class_0::MemWrite            294     11.41%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                    69                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        11659                       # The number of ROB reads
-system.cpu.rob.rob_writes                       10686                       # The number of ROB writes
+system.cpu.commit.bw_lim_events                    68                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        11437                       # The number of ROB reads
+system.cpu.rob.rob_writes                       10476                       # The number of ROB writes
 system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18212                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           17985                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                              10.703393                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.703393                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.093428                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.093428                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4655                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2832                       # number of integer regfile writes
+system.cpu.cpi                              10.550482                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        10.550482                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.094782                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.094782                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4532                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2777                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            46.039302                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 743                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            45.864197                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 731                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.741176                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.600000                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    46.039302                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011240                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011240                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    45.864197                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011197                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011197                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1969                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1969                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          525                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             525                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          218                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            218                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           743                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              743                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          743                       # number of overall hits
-system.cpu.dcache.overall_hits::total             743                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          123                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           123                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          199                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            199                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          199                       # number of overall misses
-system.cpu.dcache.overall_misses::total           199                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8172750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8172750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5678000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5678000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13850750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13850750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13850750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13850750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          648                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          648                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses              1937                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1937                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          518                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             518                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data           731                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              731                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          731                       # number of overall hits
+system.cpu.dcache.overall_hits::total             731                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          195                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            195                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          195                       # number of overall misses
+system.cpu.dcache.overall_misses::total           195                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7589500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7589500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5666500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5666500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13256000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13256000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13256000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13256000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          632                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          632                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          942                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          942                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          942                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          942                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.189815                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.189815                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.258503                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.258503                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.211253                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.211253                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.211253                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.211253                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69601.758794                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69601.758794                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          145                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data          926                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          926                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          926                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          926                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180380                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180380                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.210583                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.210583                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.210583                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.210583                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67979.487179                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67979.487179                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          139                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          114                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          114                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          114                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          114                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           53                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           53                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          110                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          110                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          110                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          110                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
@@ -671,193 +671,198 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4793500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4793500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1841500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1841500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6635000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6635000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.094136                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.094136                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4809500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4809500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1851000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1851000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6660500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6660500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6660500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6660500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096519                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096519                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090234                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090234                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090234                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090234                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091793                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091793                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091793                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091793                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        77125                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        77125                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            91.893913                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 694                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse            91.507771                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 679                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               187                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.711230                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.631016                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    91.893913                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.044870                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.044870                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    91.507771                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.044682                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.044682                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          187                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.091309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2081                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2081                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          694                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             694                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           694                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              694                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          694                       # number of overall hits
-system.cpu.icache.overall_hits::total             694                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          253                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           253                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          253                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            253                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          253                       # number of overall misses
-system.cpu.icache.overall_misses::total           253                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     18914999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     18914999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     18914999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     18914999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     18914999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     18914999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          947                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          947                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          947                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          947                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          947                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          947                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.267159                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.267159                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.267159                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.267159                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.267159                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.267159                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74762.841897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74762.841897                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          126                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              2049                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst          679                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             679                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::total     18724999                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.270677                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.270677                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::total 74305.551587                       # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 74305.551587                       # average overall miss latency
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+system.cpu.icache.blocked_cycles::no_mshrs          125                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           63                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    62.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           66                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           66                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           66                       # number of overall MSHR hits
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 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          187                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14404999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14404999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14404999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14404999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14404999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14404999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.197466                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.197466                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.197466                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.197466                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.197466                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.197466                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14173499                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.200859                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.200859                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.200859                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75794.112299                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75794.112299                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75794.112299                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          121.236486                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          120.686426                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              248                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    92.076745                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    29.159741                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002810                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000890                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003700                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    91.663709                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    29.022716                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002797                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000886                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003683                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           48                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007568                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2448                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2448                       # Number of data accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          187                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          248                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           24                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           24                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          187                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          187                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           61                       # number of ReadSharedReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          187                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data           85                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           272                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          187                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          272                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14216750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4732500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18949250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1816000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1816000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     14216750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6548500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20765250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     14216750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6548500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20765250                       # number of overall miss cycles
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+system.cpu.l2cache.ReadCleanReq_miss_latency::total     13892000                       # number of ReadCleanReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4718000                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data      6531500                       # number of overall miss cycles
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           24                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          187                       # number of demand (read+write) accesses
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 system.cpu.l2cache.demand_accesses::total          272                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          187                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data           85                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          272                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -866,55 +871,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          248                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           24                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           24                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          187                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          187                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           61                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           61                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          272                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11881250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3969500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15850750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1520000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1520000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11881250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5489500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17370750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11881250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5489500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17370750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1573500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1573500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     12022000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     12022000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4108000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4108000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12022000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5681500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17703500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12022000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5681500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17703500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           61                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          374                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               544                       # Packet count per connected master and slave (bytes)
@@ -935,14 +945,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            272                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        318750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        139500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 248                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        280500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                248                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           248                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          544                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    544                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
@@ -958,9 +968,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 272                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              341000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              337000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            1440250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            1441250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 19e3fb417..7e5bf1bcb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000048                       # Number of seconds simulated
-sim_ticks                                       47840                       # Number of ticks simulated
-final_tick                                      47840                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000047                       # Number of seconds simulated
+sim_ticks                                       47487                       # Number of ticks simulated
+final_tick                                      47487                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35814                       # Simulator instruction rate (inst/s)
-host_op_rate                                    35808                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 664620                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 449364                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  68488                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68466                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1261208                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449476                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,36 +21,36 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          626                       #
 system.mem_ctrls.num_reads::total                 626                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          622                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                622                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    837458194                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             837458194                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    832107023                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            832107023                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1669565217                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1669565217                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    843683534                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             843683534                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    838292585                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            838292585                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1681976120                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1681976120                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         626                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        622                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       626                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      622                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  24704                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   15360                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   23360                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  24640                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   15424                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   23424                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   40064                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                39808                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    240                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   225                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    241                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   227                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                29                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                25                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                30                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                24                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                51                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6                53                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                57                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                70                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                63                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 4                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               24                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               14                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               26                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               16                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               31                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::13               68                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14               10                       # Per bank write bursts
@@ -58,22 +58,22 @@ system.mem_ctrls.perBankRdBursts::15                1                       # Pe
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                29                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                24                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                30                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                23                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                51                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                46                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                73                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9                 4                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               20                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               14                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               33                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               58                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                52                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                63                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9                 3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               22                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               16                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12               32                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               61                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               10                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         47801                       # Total gap between requests
+system.mem_ctrls.totGap                         47448                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  622                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     386                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     385                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,11 +135,11 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     21                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     24                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     25                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     25                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                     25                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                     23                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::22                     23                       # What write queue length does an incoming req see
@@ -149,11 +149,11 @@ system.mem_ctrls.wrQLenPdf::25                     23                       # Wh
 system.mem_ctrls.wrQLenPdf::26                     23                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::27                     23                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     22                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                     22                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          109                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    438.605505                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   303.845174                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   335.937991                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           14     12.84%     12.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           30     27.52%     40.37% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           12     11.01%     51.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           11     10.09%     61.47% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            6      5.50%     66.97% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            9      8.26%     75.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            9      8.26%     83.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            4      3.67%     87.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           14     12.84%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          109                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          113                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    424.212389                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   291.141419                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   329.481775                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           17     15.04%     15.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           29     25.66%     40.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           14     12.39%     53.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            9      7.96%     61.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            9      7.96%     69.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           10      8.85%     77.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            8      7.08%     84.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      3.54%     88.50% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           13     11.50%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          113                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples           22                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.863636                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     16.473921                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      4.443245                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             3     13.64%     13.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15             5     22.73%     36.36% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17             9     40.91%     77.27% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             4     18.18%     95.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean             17                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     16.622974                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      4.396969                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             2      9.09%      9.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15             7     31.82%     40.91% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17             7     31.82%     72.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             5     22.73%     95.45% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::34-35             1      4.55%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total            22                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples           22                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.590909                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.555699                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.140555                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.636364                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.592012                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.292670                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16               17     77.27%     77.27% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                2      9.09%     86.36% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                3     13.64%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      4.55%     81.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                3     13.64%     95.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20                1      4.55%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            22                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         4080                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   11414                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       1930                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        10.57                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         3756                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   11071                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       1925                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         9.76                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   29.57                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       516.39                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       488.29                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    837.46                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    832.11                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   28.76                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       518.88                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       493.27                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    843.68                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    838.29                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         7.85                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.03                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    3.81                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         7.91                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.05                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    3.85                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.93                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      289                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     349                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 74.87                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                87.91                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         38.30                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    81.48                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   249480                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   138600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 2009280                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                1575936                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen                      24.54                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      294                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     342                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 76.36                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                86.58                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         38.02                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.54                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   257040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   142800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 2046720                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                1638144                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             30369600                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              1545600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               38939856                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            828.930858                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         2928                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             30869604                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              1107000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               39112668                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            832.609588                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE         1942                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         43008                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         43739                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   574560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   319200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2758080                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                2208384                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                   597240                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   331800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2733120                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                2156544                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             31087116                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               916200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               40914900                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            870.974540                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1359                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             31287528                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               740400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               40897992                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            870.614612                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1080                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         44071                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         44350                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -300,7 +301,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            47840                       # number of cpu cycles simulated
+system.cpu.numCycles                            47487                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -319,7 +320,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      47840                       # Number of busy cycles
+system.cpu.num_busy_cycles                      47487                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total          3295
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              13.523376                      
-system.ruby.latency_hist::gmean              5.183572                      
-system.ruby.latency_hist::stdev             25.409311                      
-system.ruby.latency_hist                 |        3181     96.57%     96.57% |          93      2.82%     99.39% |          16      0.49%     99.88% |           1      0.03%     99.91% |           2      0.06%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              13.416211                      
+system.ruby.latency_hist::gmean              5.177559                      
+system.ruby.latency_hist::stdev             25.037672                      
+system.ruby.latency_hist                 |        3186     96.72%     96.72% |          90      2.73%     99.45% |          15      0.46%     99.91% |           0      0.00%     99.91% |           2      0.06%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  3294                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total              2668
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples            626                      
-system.ruby.miss_latency_hist::mean         58.373802                      
-system.ruby.miss_latency_hist::gmean        53.319163                      
-system.ruby.miss_latency_hist::stdev        30.235728                      
-system.ruby.miss_latency_hist            |         513     81.95%     81.95% |          93     14.86%     96.81% |          16      2.56%     99.36% |           1      0.16%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         57.809904                      
+system.ruby.miss_latency_hist::gmean        52.994493                      
+system.ruby.miss_latency_hist::stdev        29.424898                      
+system.ruby.miss_latency_hist            |         518     82.75%     82.75% |          90     14.38%     97.12% |          15      2.40%     99.52% |           0      0.00%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total              626                      
 system.ruby.Directory.incomplete_times            625                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.521739                      
+system.ruby.network.routers0.percent_links_utilized     6.570219                      
 system.ruby.network.routers0.msg_count.Control::2          626                      
 system.ruby.network.routers0.msg_count.Data::2          622                      
 system.ruby.network.routers0.msg_count.Response_Data::4          626                      
@@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2         5008
 system.ruby.network.routers0.msg_bytes.Data::2        44784                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers1.percent_links_utilized     6.521739                      
+system.ruby.network.routers1.percent_links_utilized     6.570219                      
 system.ruby.network.routers1.msg_count.Control::2          626                      
 system.ruby.network.routers1.msg_count.Data::2          622                      
 system.ruby.network.routers1.msg_count.Response_Data::4          626                      
@@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2         5008
 system.ruby.network.routers1.msg_bytes.Data::2        44784                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.percent_links_utilized     6.521739                      
+system.ruby.network.routers2.percent_links_utilized     6.570219                      
 system.ruby.network.routers2.msg_count.Control::2          626                      
 system.ruby.network.routers2.msg_count.Data::2          622                      
 system.ruby.network.routers2.msg_count.Response_Data::4          626                      
@@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control            15024
 system.ruby.network.msg_byte.Data              134352                      
 system.ruby.network.msg_byte.Response_Data       135216                      
 system.ruby.network.msg_byte.Writeback_Control        14928                      
-system.ruby.network.routers0.throttle0.link_utilization     6.538462                      
+system.ruby.network.routers0.throttle0.link_utilization     6.587066                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers0.throttle1.link_utilization     6.505017                      
+system.ruby.network.routers0.throttle1.link_utilization     6.553373                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2          626                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2          622                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2         5008                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        44784                      
-system.ruby.network.routers1.throttle0.link_utilization     6.505017                      
+system.ruby.network.routers1.throttle0.link_utilization     6.553373                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2          626                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2          622                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2         5008                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        44784                      
-system.ruby.network.routers1.throttle1.link_utilization     6.538462                      
+system.ruby.network.routers1.throttle1.link_utilization     6.587066                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          626                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.throttle0.link_utilization     6.538462                      
+system.ruby.network.routers2.throttle0.link_utilization     6.587066                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.throttle1.link_utilization     6.505017                      
+system.ruby.network.routers2.throttle1.link_utilization     6.553373                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2          626                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2          622                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2         5008                      
@@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total             622                       # de
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples              415                      
-system.ruby.LD.latency_hist::mean           33.055422                      
-system.ruby.LD.latency_hist::gmean          15.599823                      
-system.ruby.LD.latency_hist::stdev          34.047272                      
-system.ruby.LD.latency_hist              |         375     90.36%     90.36% |          33      7.95%     98.31% |           6      1.45%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           33.036145                      
+system.ruby.LD.latency_hist::gmean          15.653569                      
+system.ruby.LD.latency_hist::stdev          33.343638                      
+system.ruby.LD.latency_hist              |         375     90.36%     90.36% |          35      8.43%     98.80% |           4      0.96%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total                415                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total            170
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          245                      
-system.ruby.LD.miss_latency_hist::mean      53.910204                      
-system.ruby.LD.miss_latency_hist::gmean     48.970543                      
-system.ruby.LD.miss_latency_hist::stdev     30.013250                      
-system.ruby.LD.miss_latency_hist         |         205     83.67%     83.67% |          33     13.47%     97.14% |           6      2.45%     99.59% |           0      0.00%     99.59% |           0      0.00%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      53.877551                      
+system.ruby.LD.miss_latency_hist::gmean     49.256670                      
+system.ruby.LD.miss_latency_hist::stdev     28.665419                      
+system.ruby.LD.miss_latency_hist         |         205     83.67%     83.67% |          35     14.29%     97.96% |           4      1.63%     99.59% |           0      0.00%     99.59% |           0      0.00%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           245                      
 system.ruby.ST.latency_hist::bucket_size           32                      
 system.ruby.ST.latency_hist::max_bucket           319                      
 system.ruby.ST.latency_hist::samples              294                      
-system.ruby.ST.latency_hist::mean           17.248299                      
-system.ruby.ST.latency_hist::gmean           6.615603                      
-system.ruby.ST.latency_hist::stdev          28.817235                      
-system.ruby.ST.latency_hist              |         210     71.43%     71.43% |          74     25.17%     96.60% |           8      2.72%     99.32% |           0      0.00%     99.32% |           1      0.34%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
+system.ruby.ST.latency_hist::mean           17.955782                      
+system.ruby.ST.latency_hist::gmean           6.677068                      
+system.ruby.ST.latency_hist::stdev          30.544793                      
+system.ruby.ST.latency_hist              |         210     71.43%     71.43% |          73     24.83%     96.26% |           7      2.38%     98.64% |           0      0.00%     98.64% |           3      1.02%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
 system.ruby.ST.latency_hist::total                294                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total            210
 system.ruby.ST.miss_latency_hist::bucket_size           32                      
 system.ruby.ST.miss_latency_hist::max_bucket          319                      
 system.ruby.ST.miss_latency_hist::samples           84                      
-system.ruby.ST.miss_latency_hist::mean      52.869048                      
-system.ruby.ST.miss_latency_hist::gmean     47.773810                      
-system.ruby.ST.miss_latency_hist::stdev     33.671260                      
-system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |          74     88.10%     88.10% |           8      9.52%     97.62% |           0      0.00%     97.62% |           1      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00%
+system.ruby.ST.miss_latency_hist::mean      55.345238                      
+system.ruby.ST.miss_latency_hist::gmean     49.345449                      
+system.ruby.ST.miss_latency_hist::stdev     36.232680                      
+system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |          73     86.90%     86.90% |           7      8.33%     95.24% |           0      0.00%     95.24% |           3      3.57%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00%
 system.ruby.ST.miss_latency_hist::total            84                      
 system.ruby.IFETCH.latency_hist::bucket_size           32                      
 system.ruby.IFETCH.latency_hist::max_bucket          319                      
 system.ruby.IFETCH.latency_hist::samples         2585                      
-system.ruby.IFETCH.latency_hist::mean        9.964023                      
-system.ruby.IFETCH.latency_hist::gmean       4.224377                      
-system.ruby.IFETCH.latency_hist::stdev      21.618756                      
-system.ruby.IFETCH.latency_hist          |        2288     88.51%     88.51% |         234      9.05%     97.56% |          49      1.90%     99.46% |           3      0.12%     99.57% |           2      0.08%     99.65% |           7      0.27%     99.92% |           1      0.04%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           1      0.04%    100.00%
+system.ruby.IFETCH.latency_hist::mean        9.750097                      
+system.ruby.IFETCH.latency_hist::gmean       4.211373                      
+system.ruby.IFETCH.latency_hist::stdev      20.913083                      
+system.ruby.IFETCH.latency_hist          |        2288     88.51%     88.51% |         240      9.28%     97.79% |          46      1.78%     99.57% |           2      0.08%     99.65% |           2      0.08%     99.73% |           6      0.23%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           1      0.04%    100.00%
 system.ruby.IFETCH.latency_hist::total           2585                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -538,18 +539,18 @@ system.ruby.IFETCH.hit_latency_hist::total         2288
 system.ruby.IFETCH.miss_latency_hist::bucket_size           32                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.miss_latency_hist::samples          297                      
-system.ruby.IFETCH.miss_latency_hist::mean    63.612795                      
-system.ruby.IFETCH.miss_latency_hist::gmean    58.999958                      
-system.ruby.IFETCH.miss_latency_hist::stdev    28.587258                      
-system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         234     78.79%     78.79% |          49     16.50%     95.29% |           3      1.01%     96.30% |           2      0.67%     96.97% |           7      2.36%     99.33% |           1      0.34%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    61.750842                      
+system.ruby.IFETCH.miss_latency_hist::gmean    57.437802                      
+system.ruby.IFETCH.miss_latency_hist::stdev    27.433554                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         240     80.81%     80.81% |          46     15.49%     96.30% |           2      0.67%     96.97% |           2      0.67%     97.64% |           6      2.02%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          297                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples          626                      
-system.ruby.Directory.miss_mach_latency_hist::mean    58.373802                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    53.319163                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    30.235728                      
-system.ruby.Directory.miss_mach_latency_hist |         513     81.95%     81.95% |          93     14.86%     96.81% |          16      2.56%     99.36% |           1      0.16%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    57.809904                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    52.994493                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    29.424898                      
+system.ruby.Directory.miss_mach_latency_hist |         518     82.75%     82.75% |          90     14.38%     97.12% |          15      2.40%     99.52% |           0      0.00%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total          626                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          245                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    53.910204                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    48.970543                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    30.013250                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |         205     83.67%     83.67% |          33     13.47%     97.14% |           6      2.45%     99.59% |           0      0.00%     99.59% |           0      0.00%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    53.877551                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    49.256670                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    28.665419                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |         205     83.67%     83.67% |          35     14.29%     97.96% |           4      1.63%     99.59% |           0      0.00%     99.59% |           0      0.00%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          245                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           32                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples           84                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    52.869048                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.773810                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    33.671260                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |          74     88.10%     88.10% |           8      9.52%     97.62% |           0      0.00%     97.62% |           1      1.19%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    55.345238                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    49.345449                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    36.232680                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |          73     86.90%     86.90% |           7      8.33%     95.24% |           0      0.00%     95.24% |           3      3.57%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total           84                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           32                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          297                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    63.612795                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    58.999958                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    28.587258                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         234     78.79%     78.79% |          49     16.50%     95.29% |           3      1.01%     96.30% |           2      0.67%     96.97% |           7      2.36%     99.33% |           1      0.34%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    61.750842                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    57.437802                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    27.433554                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         240     80.81%     80.81% |          46     15.49%     96.30% |           2      0.67%     96.97% |           2      0.67%     97.64% |           6      2.02%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          297                      
 system.ruby.Directory_Controller.GETX             626      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX             622      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 364bc6f05..7411927e4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    16524500                       # Number of ticks simulated
 final_tick                                   16524500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 396950                       # Simulator instruction rate (inst/s)
-host_op_rate                                   396157                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2535599202                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290048                       # Number of bytes of host memory used
+host_inst_rate                                 374183                       # Simulator instruction rate (inst/s)
+host_op_rate                                   373424                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2390351512                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 291260                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
@@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            47.433873                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            47.431392                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 627                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                82                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              7.646341                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    47.433873                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011581                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011581                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    47.431392                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011580                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           82                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
@@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           82
 system.cpu.dcache.demand_mshr_misses::total           82                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           82                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2942500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2942500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1444500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1444500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4387000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      4387000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4387000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      4387000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2970000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2970000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1458000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1458000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4428000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      4428000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4428000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      4428000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.132530                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.132530                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
@@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.115656
 system.cpu.dcache.demand_mshr_miss_rate::total     0.115656                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.115656                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            80.042941                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            80.038009                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2423                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               163                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             14.865031                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    80.042941                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.039083                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.039083                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    80.038009                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.039081                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.039081                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          163                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
@@ -290,91 +290,96 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          163
 system.cpu.icache.demand_mshr_misses::total          163                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          163                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      8721000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total      8721000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst      8721000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total      8721000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst      8721000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total      8721000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      8802500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total      8802500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst      8802500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total      8802500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst      8802500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total      8802500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.063032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.063032                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.063032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          107.153052                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          107.126637                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              218                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    80.161341                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    26.991711                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    80.141583                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    26.985054                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002446                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003270                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003269                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          218                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.006653                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2205                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2205                       # Number of data accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          163                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          163                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           55                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           55                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          163                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data           82                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           245                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          163                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           82                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          245                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      8558000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2887500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     11445500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1417500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      1417500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst      8558000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total      8558000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      2887500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      2887500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst      8558000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      4305000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     12863000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst      8558000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      4305000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     12863000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          163                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          218                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          163                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          163                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           55                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           55                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          163                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data           82                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          245                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          163                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data           82                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          245                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816                       # average overall miss latency
@@ -389,55 +394,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          218                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          163                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          163                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           55                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           55                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data           82                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          245                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          245                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      6601500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2227500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      8829000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1093500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1093500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      6601500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3321000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total      9922500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      6601500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3321000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total      9922500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1147500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1147500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst      6928000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total      6928000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2337500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2337500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      6928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3485000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     10413000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      6928000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3485000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     10413000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            218                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           218                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           55                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          326                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          164                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               490                       # Packet count per connected master and slave (bytes)
@@ -462,10 +472,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        244500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        123000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 218                       # Transaction distribution
 system.membus.trans_dist::ReadResp                218                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           218                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          490                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    490                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        15680                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index b37232811..e5ff065c1 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    30323500                       # Number of ticks simulated
-final_tick                                   30323500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    29934500                       # Number of ticks simulated
+final_tick                                   29934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 117134                       # Simulator instruction rate (inst/s)
-host_op_rate                                   137081                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              770805796                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310084                       # Number of bytes of host memory used
+host_inst_rate                                 115469                       # Simulator instruction rate (inst/s)
+host_op_rate                                   135130                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              750106498                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310152                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           19520                       # Nu
 system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            643725164                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            244826620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               888551783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       643725164                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          643725164                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           643725164                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           244826620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              888551783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            652090397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            248008151                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               900098548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       652090397                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          652090397                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           652090397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           248008151                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              900098548                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        30232000                       # Total gap between requests
+system.physmem.totGap                        29844000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -186,51 +186,51 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      402.285714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     286.758489                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.986232                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              7     11.11%     11.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     30.16%     41.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13     20.63%     61.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      7.94%     69.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.76%     74.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      6.35%     80.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.17%     84.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.59%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     14.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
-system.physmem.totQLat                        2542750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10436500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      408.774194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     286.680005                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.685266                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              8     12.90%     12.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           18     29.03%     41.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     17.74%     59.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      6.45%     66.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      8.06%     74.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.84%     79.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.84%     83.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.61%     85.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
+system.physmem.totQLat                        2214000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10107750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6039.79                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5258.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24789.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         888.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24008.91                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         900.10                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      888.55                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      900.10                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.94                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       6.94                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        349                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        350                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.90                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        71809.98                       # Average gap between requests
-system.physmem.pageHitRate                      82.90                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        70888.36                       # Average gap between requests
+system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1942200                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                   1973400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
 system.physmem_0.actBackEnergy               16099650                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  48750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20036940                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              848.348875                       # Core power per rank (mW)
+system.physmem_0.totalEnergy                 20068140                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              849.669860                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          12500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
@@ -241,14 +241,14 @@ system.physmem_1.preEnergy                      70125                       # En
 system.physmem_1.readEnergy                    694200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15437025                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 630000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 18485550                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              782.664197                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        2433750                       # Time in different power states
+system.physmem_1.actBackEnergy               15748245                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 357000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 18523770                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              784.282403                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1650750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21873250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22328250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    1918                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1150                       # Number of conditional branches predicted
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            60647                       # number of cpu cycles simulated
+system.cpu.numCycles                            59869                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4605                       # Number of instructions committed
 system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                          1116                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              13.169815                       # CPI: cycles per instruction
-system.cpu.ipc                               0.075931                       # IPC: instructions per cycle
-system.cpu.tickCycles                           10567                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           50080                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              13.000869                       # CPI: cycles per instruction
+system.cpu.ipc                               0.076918                       # IPC: instructions per cycle
+system.cpu.tickCycles                           10574                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           49295                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.373507                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            86.493580                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.136986                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.373507                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021087                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021087                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.493580                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021117                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021117                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
@@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data          182                       # n
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7248241                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7248241                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5053500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5053500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     12301741                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     12301741                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     12301741                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     12301741                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6956000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6956000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5019500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5019500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     11975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     11975500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11975500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1165                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1165                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.087584
 system.cpu.dcache.demand_miss_rate::total     0.087584                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.087584                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.087584                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67591.983516                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67591.983516                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65799.450549                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65799.450549                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6562258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6562258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3179250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3179250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9741508                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9741508                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9741508                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9741508                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6353000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6353000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3198000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3198000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9551000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9551000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088412                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088412                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
@@ -499,27 +499,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070260
 system.cpu.dcache.demand_mshr_miss_rate::total     0.070260                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070260                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.070260                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.448164                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           161.765243                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1909                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.928571                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.448164                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078832                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078832                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.765243                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078987                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078987                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4784                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4784                       # Number of data accesses
@@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst          322                       # n
 system.cpu.icache.demand_misses::total            322                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          322                       # number of overall misses
 system.cpu.icache.overall_misses::total           322                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23879500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23879500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23879500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23879500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23879500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23879500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     23594000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     23594000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     23594000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     23594000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     23594000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     23594000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         2231                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         2231                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         2231                       # number of demand (read+write) accesses
@@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.144330
 system.cpu.icache.demand_miss_rate::total     0.144330                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.144330                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.144330                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74159.937888                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74159.937888                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73273.291925                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73273.291925                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -573,106 +573,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          322
 system.cpu.icache.demand_mshr_misses::total          322                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          322                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23261500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23261500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23261500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23261500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23261500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23261500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23272000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23272000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23272000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23272000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23272000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23272000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.144330                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.144330                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.144330                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          195.068888                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          195.411120                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 41                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.103175                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.108466                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   153.992766                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    41.076122                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004699                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001254                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005953                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.281002                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    41.130118                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004708                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001255                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          253                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4165                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4165                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses             4181                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4181                       # Number of data accesses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           17                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           17                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           22                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           22                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
 system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          305                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           81                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          386                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          305                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          305                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           81                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           81                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          305                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          124                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          124                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22761000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6225250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28986250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3136250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3136250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22761000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9361500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32122500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22761000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9361500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32122500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          322                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          103                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          425                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3133500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3133500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22610500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22610500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5960500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5960500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22610500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9094000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31704500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22610500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9094000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31704500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          322                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          322                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          103                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          103                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          322                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          468                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          322                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          468                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.947205                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.786408                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.908235                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.947205                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.947205                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.786408                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.786408                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.947205                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.849315                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.916667                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947205                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -681,89 +687,95 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          305                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           73                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          378                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          305                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          305                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           73                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           73                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          305                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          116                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          421                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          116                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18938500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4780750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23719250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2598750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2598750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18938500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7379500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26318000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18938500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7379500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26318000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.708738                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889412                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2703500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2703500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19560500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19560500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4700500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4700500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19560500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7404000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26964500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19560500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7404000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26964500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.947205                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.708738                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.708738                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.899573                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            425                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          322                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          103                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          646                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               938                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20608                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              29952                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          468                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          471                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                468    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                471    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            468                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            471                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        550500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        240992                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 378                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        483000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        222992                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                378                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           378                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          842                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    842                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26944                       # Cumulative packet size per connected master and slave (bytes)
@@ -779,9 +791,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 421                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              490500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              491000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2238000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              7.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2236500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 725976bdf..80e232875 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    17398000                       # Number of ticks simulated
-final_tick                                   17398000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    17226500                       # Number of ticks simulated
+final_tick                                   17226500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57922                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67825                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              219380871                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310080                       # Number of bytes of host memory used
+host_inst_rate                                  55427                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64904                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              207866253                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 311436                       # Number of bytes of host memory used
 host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              7680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7744                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                25344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                120                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                121                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   396                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1015289114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            441430049                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1456719163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1015289114                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1015289114                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1015289114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           441430049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1456719163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1021681711                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            449539953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1471221664                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1021681711                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1021681711                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1021681711                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           449539953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1471221664                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           396                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         396                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        17318000                       # Total gap between requests
+system.physmem.totGap                        17159000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
@@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           59                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      410.033898                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     279.539573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.305882                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              9     15.25%     15.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           16     27.12%     42.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            8     13.56%     55.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            9     15.25%     71.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      3.39%     74.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.39%     77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.39%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      3.39%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     15.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             59                       # Bytes accessed per row activation
-system.physmem.totQLat                        3886750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11311750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      395.354839                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     263.720067                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     338.958245                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             11     17.74%     17.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     30.65%     48.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6      9.68%     58.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8     12.90%     70.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.84%     75.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.23%     79.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      3.23%     82.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      3.23%     85.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
+system.physmem.totQLat                        3039250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10464250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1980000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9815.03                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7674.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28565.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1456.72                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26424.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1471.22                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1456.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1471.22                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.38                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.38                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.88                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        331                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.59                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43732.32                       # Average gap between requests
+system.physmem.avgGap                        43330.81                       # Average gap between requests
 system.physmem.pageHitRate                      83.59                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     287280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     156750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2051400                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                     302400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     165000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2090400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10748205                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  71250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14332005                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              905.226907                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          62750                       # Time in different power states
+system.physmem_0.actBackEnergy               10797795                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 14404965                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              909.404356                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          69250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15263500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        16109250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     143640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      78375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    741000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     151200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      82500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    748800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10299330                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 465000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12744465                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              804.955945                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         732000                       # Time in different power states
+system.physmem_1.actBackEnergy               10359180                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 412500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 12771300                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              806.650876                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         820250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14594250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14680750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2567                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1598                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    2576                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1602                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               469                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2080                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     778                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 2087                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     781                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             37.403846                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     334                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             37.422137                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     336                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 70                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -496,178 +496,178 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            34797                       # number of cpu cycles simulated
+system.cpu.numCycles                            34454                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7703                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12168                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2567                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1112                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4777                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles               7709                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12205                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2576                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1117                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4748                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     987                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           251                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           17                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      2007                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   300                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13242                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.084202                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.460827                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2016                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   303                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13219                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.088585                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.463952                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10620     80.20%     80.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      274      2.07%     82.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      209      1.58%     83.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      222      1.68%     85.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      233      1.76%     87.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      323      2.44%     89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      137      1.03%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      162      1.22%     91.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1062      8.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10589     80.10%     80.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      274      2.07%     82.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      212      1.60%     83.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      221      1.67%     85.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      236      1.79%     87.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      324      2.45%     89.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      139      1.05%     90.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      161      1.22%     91.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1063      8.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13242                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.073771                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.349685                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6338                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4330                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2103                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   133                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                13219                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.074766                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.354240                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6369                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4276                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2102                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   134                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    338                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  384                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   164                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11850                       # Number of instructions handled by decode
+system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  11852                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   468                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    338                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6554                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     6584                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     692                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2396                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2012                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1250                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11194                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                    171                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    132                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1066                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               11323                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 51655                       # Number of register rename lookups that rename has made
+system.cpu.rename.serializeStallCycles           2356                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2013                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1236                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11200                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                    168                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    130                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   1064                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               11331                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 51672                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups            12441                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5829                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 42                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             36                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       409                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2284                       # Number of loads inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                     5837                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 43                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       422                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2287                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1689                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                38                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               34                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10118                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      10125                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8189                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4786                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        12366                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      8202                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                55                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4793                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        12371                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              9                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13242                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.618411                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.365218                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13219                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.620471                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.365465                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10034     75.77%     75.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1166      8.81%     84.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 746      5.63%     90.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 448      3.38%     93.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 359      2.71%     96.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 279      2.11%     98.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10002     75.66%     75.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1166      8.82%     84.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 755      5.71%     90.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 451      3.41%     93.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 357      2.70%     96.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 278      2.10%     98.41% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 131      0.99%     99.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  62      0.47%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  17      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  63      0.48%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  16      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13242                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13219                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       9      5.20%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     84     48.55%     53.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    80     46.24%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      5.26%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     84     49.12%     54.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    78     45.61%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4931     60.21%     60.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    6      0.07%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     60.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1952     23.84%     84.16% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1297     15.84%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4937     60.19%     60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.07%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1959     23.88%     84.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1297     15.81%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8189                       # Type of FU issued
-system.cpu.iq.rate                           0.235336                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021126                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29748                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14841                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7422                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8202                       # Type of FU issued
+system.cpu.iq.rate                           0.238057                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         171                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020849                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29750                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14855                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7430                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  99                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                128                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           32                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8319                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8330                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      43                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               24                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1257                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1260                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          751                       # Number of stores squashed
@@ -677,56 +677,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads           32                       #
 system.cpu.iew.lsq.thread0.cacheBlocked             4                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                    338                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     662                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    13                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10173                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               130                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2284                       # Number of dispatched load instructions
+system.cpu.iew.iewBlockCycles                     660                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10180                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               127                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2287                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1689                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     10                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     2                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            111                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          233                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  344                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7858                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1841                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               331                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          234                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  345                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7868                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1843                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               334                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             9                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3070                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1431                       # Number of branches executed
+system.cpu.iew.exec_refs                         3072                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1434                       # Number of branches executed
 system.cpu.iew.exec_stores                       1229                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.225824                       # Inst execution rate
-system.cpu.iew.wb_sent                           7567                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7454                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3520                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6887                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.228362                       # Inst execution rate
+system.cpu.iew.wb_sent                           7574                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7462                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3524                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6897                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.214214                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.511108                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.216579                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.510947                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4794                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4801                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               314                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.433570                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.280415                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12382                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.434340                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.281233                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10350     83.44%     83.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          890      7.18%     90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          420      3.39%     94.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          213      1.72%     95.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          118      0.95%     96.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          211      1.70%     98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           49      0.40%     98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           36      0.29%     99.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          117      0.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10327     83.40%     83.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          891      7.20%     90.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          421      3.40%     94.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          214      1.73%     95.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          114      0.92%     96.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          212      1.71%     98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           49      0.40%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           39      0.31%     99.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          115      0.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12382                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22302                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21197                       # The number of ROB writes
-system.cpu.timesIdled                             195                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21555                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   115                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        22289                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21210                       # The number of ROB writes
+system.cpu.timesIdled                             194                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           21235                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.577744                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.577744                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.131965                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.131965                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     7744                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    4257                       # number of integer regfile writes
+system.cpu.cpi                               7.503049                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.503049                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.133279                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.133279                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     7752                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4259                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        32                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                     28092                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     3277                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    3176                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                     28119                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     3280                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    3175                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.050512                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2159                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.687075                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.080084                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2156                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.767123                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.050512                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021253                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021253                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.080084                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021260                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021260                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5463                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5463                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1539                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1539                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          598                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            598                       # number of WriteReq hits
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5466                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5466                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1537                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1537                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          597                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            597                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2137                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2137                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2137                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2137                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          182                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           182                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          315                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          315                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data          2134                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2134                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2134                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2134                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          186                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           186                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          316                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          316                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          497                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            497                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          497                       # number of overall misses
-system.cpu.dcache.overall_misses::total           497                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10876493                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10876493                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22731000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22731000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       144500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       144500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33607493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33607493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33607493                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33607493                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1721                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1721                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          502                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            502                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          502                       # number of overall misses
+system.cpu.dcache.overall_misses::total           502                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10668000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10668000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22567500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22567500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       142000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       142000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33235500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33235500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33235500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33235500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1723                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1723                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2634                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2634                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2634                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2634                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.105752                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.105752                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.345016                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.345016                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2636                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2636                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2636                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2636                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.107951                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.107951                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.346112                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.346112                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.188686                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.188686                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.188686                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.188686                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67620.710262                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67620.710262                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          125                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.190440                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.190440                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.190440                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.190440                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66206.175299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66206.175299                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          126                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    62.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           63                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           77                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          273                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          273                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           81                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          274                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          274                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          350                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          350                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          350                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          350                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          355                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          355                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          355                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          355                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -895,82 +895,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6879255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6879255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3390500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3390500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10269755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10269755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10269755                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10269755                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.061011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.061011                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6685000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6685000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3406500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3406500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10091500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10091500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10091500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10091500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.060940                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.060940                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055809                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.055809                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055809                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.055809                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055766                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.055766                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055766                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.055766                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           149.166565                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1613                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           149.175552                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1623                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               293                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.505119                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.539249                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   149.166565                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072835                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072835                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   149.175552                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.072840                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.072840                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.142578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4307                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4307                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1613                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1613                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1613                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1613                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1613                       # number of overall hits
-system.cpu.icache.overall_hits::total            1613                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          394                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           394                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          394                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            394                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          394                       # number of overall misses
-system.cpu.icache.overall_misses::total           394                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28003250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28003250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28003250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28003250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28003250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28003250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2007                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2007                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2007                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2007                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2007                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2007                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.196313                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.196313                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.196313                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::cpu.inst     0.196313                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.196313                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71074.238579                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71074.238579                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              4325                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst         1623                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total            1623                       # number of overall hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst     27030000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     27030000                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total     27030000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2016                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2016                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2016                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2016                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2016                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2016                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.194940                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.194940                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.194940                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.194940                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68778.625954                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68778.625954                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68778.625954                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68778.625954                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68778.625954                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          456                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
@@ -979,118 +979,124 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    91.200000
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          101                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          101                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          101                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          101                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          101                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          101                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          100                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          100                       # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_hits::total          100                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          100                       # number of overall MSHR hits
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 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          293                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          293                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          293                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          293                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          293                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22179000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22179000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145989                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145989                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145989                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.145989                       # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total     0.145989                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21572000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21572000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21572000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145337                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145337                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145337                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73624.573379                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 73624.573379                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73624.573379                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.073007                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          186.076752                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              354                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.110169                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.074126                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    45.998881                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004275                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001404                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005678                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.018845                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.057907                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010803                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3916                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3916                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
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-system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           18                       # number of ReadCleanReq hits
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 system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
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 system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          276                       # number of ReadReq misses
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 system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
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 system.cpu.l2cache.overall_misses::total          401                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21706000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6539250                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3346500                       # number of ReadExReq miss cycles
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           42                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          293                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          147                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          440                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          293                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          147                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          440                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.941980                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.790476                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.902010                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.941980                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.850340                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.938567                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.938567                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.800000                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.800000                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.938567                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.857143                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.911364                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.941980                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.850340                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.938567                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.857143                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.911364                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        79086                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        79086                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76154.545455                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75845.238095                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75845.238095                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76154.545455                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77091.269841                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76448.877805                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76154.545455                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77091.269841                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76448.877805                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1099,89 +1105,94 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           78                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          354                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          120                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          275                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          275                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           79                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           79                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          121                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          396                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          120                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          121                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          396                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18264000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5236000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23500000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2824500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2824500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18264000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8060500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26324500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18264000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8060500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26324500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.941980                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.742857                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889447                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2922500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2922500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18192500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18192500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5250500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5250500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8173000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26365500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18192500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8173000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26365500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.941980                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.816327                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.938567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.938567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.752381                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.752381                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.938567                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.823129                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.900000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.941980                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.816327                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.938567                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.823129                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.900000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        67250                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        67250                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            398                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           397                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          293                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          105                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          586                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               880                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               879                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28096                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          440                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                440    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                441    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            440                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         220000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            441                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        493000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        239245                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 354                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        439500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        221495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                354                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           354                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          792                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    792                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25344                       # Cumulative packet size per connected master and slave (bytes)
@@ -1197,9 +1208,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 396                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              497000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2092000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.0                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              485500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2095750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 835d1798d..65214b87e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    17788000                       # Number of ticks simulated
-final_tick                                   17788000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    17777000                       # Number of ticks simulated
+final_tick                                   17777000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23007                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26942                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               89104120                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300104                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  63568                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74435                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              246000775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307848                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst                271                       # Nu
 system.physmem.num_reads::cpu.data                108                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.l2cache.prefetcher           27                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   406                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            975039352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            388576568                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     97144142                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1460760063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       975039352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          975039352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           975039352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           388576568                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     97144142                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1460760063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            975642684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            388817011                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     97204253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1461663948                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       975642684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          975642684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           975642684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           388817011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     97204253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1461663948                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           407                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         407                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        17774500                       # Total gap between requests
+system.physmem.totGap                        17763500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -94,8 +94,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       224                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
@@ -204,65 +204,65 @@ system.physmem.bytesPerActivate::768-895            3      5.08%     79.66% # By
 system.physmem.bytesPerActivate::896-1023            2      3.39%     83.05% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     16.95%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             59                       # Bytes accessed per row activation
-system.physmem.totQLat                        3111242                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10742492                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3256492                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10887742                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2035000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7644.33                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        8001.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26394.33                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1464.36                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26751.21                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1465.26                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1464.36                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1465.26                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.44                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.44                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.45                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.45                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.77                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        340                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.54                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43671.99                       # Average gap between requests
+system.physmem.avgGap                        43644.96                       # Average gap between requests
 system.physmem.pageHitRate                      83.54                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     294840                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     160875                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                   2043600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10829430                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  29250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14375115                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              905.162692                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         243500                       # Time in different power states
+system.physmem_0.actBackEnergy               10756755                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  63750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 14336940                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              905.538607                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         334000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15368000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15275500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    795600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10100115                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 639750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12751230                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              805.383231                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1024000                       # Time in different power states
+system.physmem_1.actBackEnergy               10156545                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 590250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 12758160                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              805.820938                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         942000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14302250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14384250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2340                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1388                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               507                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  838                       # Number of BTB lookups
+system.cpu.branchPred.lookups                    2336                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1386                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               508                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  837                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     442                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             52.744630                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     290                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 55                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             52.807646                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     289                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 56                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,84 +381,84 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            35577                       # number of cpu cycles simulated
+system.cpu.numCycles                            35555                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6129                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          11284                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2340                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                732                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          7521                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1057                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  129                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles               6172                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          11259                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2336                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                731                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          7501                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1059                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           303                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          320                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      3831                       # Number of cache lines fetched
+system.cpu.fetch.IcacheWaitRetryStallCycles          318                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      3825                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   176                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14930                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.882251                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.211921                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              14978                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.878021                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.210560                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     8724     58.43%     58.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     2462     16.49%     74.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      522      3.50%     78.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                     3222     21.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     8782     58.63%     58.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     2458     16.41%     75.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      521      3.48%     78.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                     3217     21.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14930                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.065773                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.317171                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5843                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3543                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5049                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   128                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    367                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                14978                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.065701                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.316664                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5920                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3520                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5039                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   131                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    368                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  329                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   164                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   9870                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1626                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    367                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6916                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     964                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1980                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4098                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   605                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   8889                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                   403                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
+system.cpu.decode.DecodedInsts                   9859                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  1620                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    368                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6989                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     960                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1965                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4095                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   8880                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                   409                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                    15                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      1                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                      9                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    531                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9240                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 40319                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             9768                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                    527                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9231                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 40283                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             9759                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3746                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3737                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             28                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       299                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 1806                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1281                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1277                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       8360                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8347                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  39                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      7147                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               189                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3021                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         7902                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      7144                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               184                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3008                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         7841                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14930                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.478701                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.863585                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14978                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.476966                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.861224                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10739     71.93%     71.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1936     12.97%     84.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1601     10.72%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 607      4.07%     99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                  47      0.31%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10780     71.97%     71.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1947     13.00%     84.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1601     10.69%     95.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 605      4.04%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                  45      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            4                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14930                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14978                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     420     29.23%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     29.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    467     32.50%     61.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   550     38.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     411     28.90%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    464     32.63%     61.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   547     38.47%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4466     62.49%     62.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1589     22.23%     84.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1084     15.17%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4467     62.53%     62.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1588     22.23%     84.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1081     15.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   7147                       # Type of FU issued
-system.cpu.iq.rate                           0.200888                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                        1437                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.201063                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30806                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             11411                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         6546                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   7144                       # Type of FU issued
+system.cpu.iq.rate                           0.200928                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                        1422                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.199048                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30828                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             11385                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         6550                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  44                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8556                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8538                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      28                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               10                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread0.squashedLoads          779                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          343                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          339                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    367                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     358                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     8                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                8413                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    368                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     356                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                8400                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts                  1806                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1281                       # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts                 1277                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     6                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             66                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             67                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          294                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  360                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  6739                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1406                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               408                       # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts                  361                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  6741                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1404                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               403                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            14                       # number of nop insts executed
-system.cpu.iew.exec_refs                         2430                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1270                       # Number of branches executed
-system.cpu.iew.exec_stores                       1024                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.189420                       # Inst execution rate
-system.cpu.iew.wb_sent                           6605                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          6562                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2976                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      5371                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         2427                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1272                       # Number of branches executed
+system.cpu.iew.exec_stores                       1023                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.189594                       # Inst execution rate
+system.cpu.iew.wb_sent                           6608                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          6566                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2973                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      5368                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.184445                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.554087                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.184672                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.553838                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2578                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2565                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               346                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        14390                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.373732                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.023936                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               347                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        14437                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.372515                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.021269                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11747     81.63%     81.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1377      9.57%     91.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          605      4.20%     95.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          294      2.04%     97.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          168      1.17%     98.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           77      0.54%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           46      0.32%     99.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           32      0.22%     99.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           44      0.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11787     81.64%     81.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1388      9.61%     91.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          602      4.17%     95.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          293      2.03%     97.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          168      1.16%     98.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           78      0.54%     99.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           45      0.31%     99.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           33      0.23%     99.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           43      0.30%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        14390                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14437                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -654,121 +654,121 @@ system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                    44                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22145                       # The number of ROB reads
-system.cpu.rob.rob_writes                       16457                       # The number of ROB writes
-system.cpu.timesIdled                             212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20647                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                    43                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        22180                       # The number of ROB reads
+system.cpu.rob.rob_writes                       16432                       # The number of ROB writes
+system.cpu.timesIdled                             214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20577                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.747605                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.747605                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.129072                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.129072                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     6713                       # number of integer regfile reads
+system.cpu.cpi                               7.742814                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.742814                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.129152                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.129152                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     6717                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    3745                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                     23953                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     2889                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    2609                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                     23956                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     2895                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    2607                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 1                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            84.188922                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            84.382295                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1915                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.507042                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.485915                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    84.188922                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.164431                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.164431                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    84.382295                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.164809                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.164809                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.275391                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4696                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4696                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1176                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1176                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4692                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4692                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1173                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1173                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          722                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            722                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1898                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1898                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1898                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1898                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          166                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           166                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          1895                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1895                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1895                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1895                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          167                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           167                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          191                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          191                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          357                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            357                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          357                       # number of overall misses
-system.cpu.dcache.overall_misses::total           357                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9257492                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9257492                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7277250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7277250                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       126000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       126000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16534742                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16534742                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16534742                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16534742                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1342                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1342                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          358                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            358                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          358                       # number of overall misses
+system.cpu.dcache.overall_misses::total           358                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9199500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9199500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      7245500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      7245500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       125000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       125000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16445000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16445000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16445000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16445000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1340                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1340                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2255                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2255                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2255                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2255                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.123696                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.123696                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2253                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2253                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2253                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2253                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.124627                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.124627                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.209200                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.209200                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.158315                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.158315                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.158315                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.158315                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55768.024096                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55768.024096                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        63000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        63000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46315.803922                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46315.803922                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46315.803922                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46315.803922                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.158899                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.158899                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.158899                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.158899                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45935.754190                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45935.754190                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          717                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          731                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    39.833333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    40.611111                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           64                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          150                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          150                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          214                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          214                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          214                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          214                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          215                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          215                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          215                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          215                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           41                       # number of WriteReq MSHR misses
@@ -777,120 +777,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          143
 system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5795755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5795755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2367750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2367750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8163505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8163505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8163505                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8163505                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5829500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5829500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2385500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2385500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8215000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8215000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8215000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8215000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076119                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076119                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044907                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063415                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063415                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063415                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063415                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56821.127451                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56821.127451                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        57750                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        57750                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57087.447552                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57087.447552                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57087.447552                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57087.447552                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063471                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063471                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063471                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063471                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                42                       # number of replacements
-system.cpu.icache.tags.tagsinuse           136.057531                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                3467                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           136.424572                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                3459                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               295                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             11.752542                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             11.725424                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   136.057531                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.265737                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.265737                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   136.424572                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.266454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.266454                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          253                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          162                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.494141                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              7955                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             7955                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         3467                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            3467                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          3467                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             3467                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         3467                       # number of overall hits
-system.cpu.icache.overall_hits::total            3467                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          363                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           363                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          363                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            363                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          363                       # number of overall misses
-system.cpu.icache.overall_misses::total           363                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     21749991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     21749991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     21749991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     21749991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     21749991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     21749991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         3830                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         3830                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         3830                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         3830                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         3830                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         3830                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094778                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.094778                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.094778                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.094778                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.094778                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.094778                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59917.330579                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 59917.330579                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 59917.330579                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 59917.330579                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 59917.330579                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 59917.330579                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         8313                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              7941                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             7941                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         3459                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            3459                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          3459                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             3459                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         3459                       # number of overall hits
+system.cpu.icache.overall_hits::total            3459                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           364                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
+system.cpu.icache.overall_misses::total           364                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     21691493                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     21691493                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     21691493                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     21691493                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     21691493                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     21691493                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         3823                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         3823                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         3823                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         3823                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         3823                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         3823                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.095213                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.095213                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.095213                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.095213                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.095213                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.095213                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59592.013736                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59592.013736                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8521                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           33                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                90                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                89                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    92.366667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    95.741573                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           33                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           67                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           67                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           67                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           67                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           67                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           68                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           68                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           68                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          296                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          296                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          296                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     18653743                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     18653743                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     18653743                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     18653743                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     18653743                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     18653743                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.077285                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.077285                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.077285                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.077285                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.077285                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.077285                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63019.402027                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63019.402027                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63019.402027                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 63019.402027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63019.402027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 63019.402027                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     18899993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     18899993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     18899993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     18899993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     18899993                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     18899993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.077426                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.077426                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.077426                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued          112                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified          112                       # number of prefetch candidates identified
@@ -899,94 +899,100 @@ system.cpu.l2cache.prefetcher.pfInCache             0                       # nu
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          192.560599                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 42                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          193.028614                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 74                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              364                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.115385                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.203297                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.350778                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    45.044062                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     9.165759                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008444                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002749                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000559                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.011753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.716720                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    45.124038                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     9.187855                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002754                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000561                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.011782                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.000977                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021240                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             7429                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            7429                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           23                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           19                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             42                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses             7941                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            7941                       # Number of data accesses
 system.cpu.l2cache.ReadExReq_hits::cpu.data           11                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           11                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           23                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           23                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           19                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           19                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           23                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           30                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total              53                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           23                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           30                       # number of overall hits
 system.cpu.l2cache.overall_hits::total             53                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          273                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           83                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          356                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           30                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           30                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          273                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          273                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           83                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           83                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          273                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          113                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           386                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          273                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          113                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          386                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18354000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5568750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     23922750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2253750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2253750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     18354000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7822500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     26176500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     18354000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7822500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     26176500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          296                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          102                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          398                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2251000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2251000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     18451000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     18451000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5549000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5549000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     18451000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7800000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     26251000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     18451000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7800000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     26251000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           41                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           41                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          296                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          296                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          102                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          102                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          296                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          143                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          439                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          296                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          143                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.922297                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.813725                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.894472                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.731707                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.731707                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.922297                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.922297                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.813725                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.813725                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.922297                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.790210                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.879271                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.922297                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.790210                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.879271                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67230.769231                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67093.373494                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67198.735955                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        75125                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        75125                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67230.769231                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69225.663717                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67814.766839                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67230.769231                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69225.663717                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67814.766839                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -995,22 +1001,24 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          272                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           78                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher           48                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.HardPFReq_mshr_misses::total           48                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           30                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           30                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          272                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          272                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           78                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           78                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          272                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          108                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          380                       # number of demand (read+write) MSHR misses
@@ -1018,27 +1026,29 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst          272
 system.cpu.l2cache.overall_mshr_misses::cpu.data          108                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher           48                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15994000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4617750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20611750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1641917                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1641917                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2002750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2002750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15994000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6620500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     22614500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15994000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6620500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1641917                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24256417                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.918919                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.879397                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1697924                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1697924                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2071000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2071000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     16769500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     16769500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4788500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4788500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16769500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6859500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23629000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16769500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6859500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1697924                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     25326924                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.731707                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.731707                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.918919                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.918919                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.918919                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.755245                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.865604                       # mshr miss rate for demand accesses
@@ -1046,54 +1056,57 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.918919
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.755245                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.974943                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58801.470588                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59201.923077                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58890.714286                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58801.470588                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61300.925926                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59511.842105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58801.470588                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61300.925926                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56673.871495                       # average overall mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            398                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           32                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFReq           64                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           41                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          296                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          102                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          623                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          285                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               876                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               908                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18880                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              27968                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                          64                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          503                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.127237                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.333570                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          546                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.117216                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.321973                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                439     87.28%     87.28% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                 64     12.72%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                482     88.28%     88.28% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                 64     11.72%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            503                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         219500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        496999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        228995                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 377                       # Transaction distribution
+system.cpu.toL2Bus.snoop_fanout::total            546                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         241000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        442999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        215495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                375                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                30                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               30                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           377                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          812                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    812                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25920                       # Cumulative packet size per connected master and slave (bytes)
@@ -1109,9 +1122,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 407                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              508443                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              510442                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2142008                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2136258                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index eccfa92c7..85d747802 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25816500                       # Number of ticks simulated
 final_tick                                   25816500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77759                       # Simulator instruction rate (inst/s)
-host_op_rate                                    90742                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              439383785                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301384                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 428411                       # Simulator instruction rate (inst/s)
+host_op_rate                                   499438                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2416370273                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308620                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5391                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            82.896193                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            82.893462                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1786                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             12.666667                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    82.896193                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.893462                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020238                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020238                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
@@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          141
 system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4571000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4571000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2300500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2300500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6871500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6871500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6871500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6871500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4620000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4620000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2322000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2322000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6942000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6942000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6942000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6942000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098790                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098790                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
@@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074016
 system.cpu.dcache.demand_mshr_miss_rate::total     0.074016                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.074016                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           114.417529                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           114.412880                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4365                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               241                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             18.112033                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   114.417529                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.055868                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.055868                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   114.412880                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.055866                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.055866                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          240                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
@@ -384,100 +384,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          241
 system.cpu.icache.demand_mshr_misses::total          241                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          241                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          241                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12227000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12227000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12227000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12227000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12227000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12227000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12347500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12347500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12347500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12347500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12347500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12347500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052323                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052323                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052323                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.052323                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052323                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.052323                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          153.834298                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          153.810302                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.699770                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    48.134528                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003226                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.682127                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    48.128175                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003225                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001469                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004695                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004694                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.009369                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3406                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3406                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           16                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           16                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           16                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           16                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           16                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total              32                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           16                       # number of overall hits
 system.cpu.l2cache.overall_hits::total             32                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          225                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           82                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          307                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          225                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          225                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           82                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           82                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          125                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           350                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          125                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          350                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11818000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4305000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     16123000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2257500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2257500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     11818000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     11818000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4305000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4305000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     11818000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      6562500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     18380500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     11818000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      6562500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     18380500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          241                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           98                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          339                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          241                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          241                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           98                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           98                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          241                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          382                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          241                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          382                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.933610                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.836735                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.905605                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.933610                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.933610                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.836735                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.836735                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.933610                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.886525                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.916230                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.933610                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.886525                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916230                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286                       # average overall miss latency
@@ -492,55 +498,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          225                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           82                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          307                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          225                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          225                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           82                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           82                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          225                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          125                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          125                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9112500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3321000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12433500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1741500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1741500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9112500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5062500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14175000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9112500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5062500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14175000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.836735                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.905605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1827500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1827500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst      9568000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total      9568000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3485000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3485000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5312500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14880500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9568000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5312500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14880500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.933610                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.836735                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.836735                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.916230                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.916230                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          241                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           98                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          482                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               764                       # Packet count per connected master and slave (bytes)
@@ -548,27 +559,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              24448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          382                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          383                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                382    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                383    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            382                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         191000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            383                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         191500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        361500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 307                       # Transaction distribution
 system.membus.trans_dist::ReadResp                307                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           307                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          700                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    700                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        22400                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 8ffb75804..5213b7cc0 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000023                       # Number of seconds simulated
-sim_ticks                                    22762000                       # Number of ticks simulated
-final_tick                                   22762000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000022                       # Number of seconds simulated
+sim_ticks                                    22403000                       # Number of ticks simulated
+final_tick                                   22403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   3472                       # Simulator instruction rate (inst/s)
-host_op_rate                                     3472                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               15849922                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223436                       # Number of bytes of host memory used
-host_seconds                                     1.44                       # Real time elapsed on the host
+host_inst_rate                                  79030                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79012                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              354943993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292784                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4986                       # Number of instructions simulated
 sim_ops                                          4986                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21120                       # Nu
 system.physmem.num_reads::cpu.inst                330                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   471                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            927862227                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            396450224                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1324312451                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       927862227                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          927862227                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           927862227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           396450224                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1324312451                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            942730884                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            402803196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1345534080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       942730884                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          942730884                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           942730884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           402803196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1345534080                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           471                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         471                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        22674500                       # Total gap between requests
+system.physmem.totGap                        22316000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -92,9 +92,9 @@ system.physmem.writePktSize::5                      0                       # Wr
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       277                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          104                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      262.153846                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.184943                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     253.583818                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             28     26.92%     26.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           35     33.65%     60.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           18     17.31%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           10      9.62%     87.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      2.88%     90.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      1.92%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      0.96%     93.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.96%     94.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      5.77%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            104                       # Bytes accessed per row activation
-system.physmem.totQLat                        5218000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  14049250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      260.876190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.828028                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     254.099908                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             30     28.57%     28.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           33     31.43%     60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           19     18.10%     78.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           10      9.52%     87.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      2.86%     90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      1.90%     92.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      0.95%     93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.95%     94.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      5.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            105                       # Bytes accessed per row activation
+system.physmem.totQLat                        4348750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13180000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2355000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11078.56                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9233.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29828.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1324.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27983.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1345.53                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1324.31                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1345.53                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.35                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.35                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.51                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.51                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.74                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.71                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        356                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        48141.19                       # Average gap between requests
+system.physmem.avgGap                        47380.04                       # Average gap between requests
 system.physmem.pageHitRate                      75.58                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    491400                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                    538200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                9465705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                1196250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12369120                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              781.248697                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE        1950500                       # Time in different power states
+system.physmem_0.actBackEnergy                9525555                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                1143750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12423270                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              784.668877                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE        2113750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        13375750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        13462250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     514080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     280500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2184000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     521640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     284625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2191800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10729395                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                  87750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 14812845                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              935.597347                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         284750                       # Time in different power states
+system.physmem_1.actBackEnergy               10738800                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  87000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 14840985                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              936.635216                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         103500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15222250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        15234500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2110                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1371                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               423                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1629                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     525                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2126                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1379                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               429                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1641                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     514                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.228361                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     280                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             31.322364                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     281                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 67                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -279,236 +279,236 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.numCycles                            45525                       # number of cpu cycles simulated
+system.cpu.numCycles                            44807                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8934                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12895                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2110                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                805                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4920                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     864                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.PendingTrapStallCycles           192                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2026                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   263                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14478                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.890662                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.186824                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               8961                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12993                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2126                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                795                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4908                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     876                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles           194                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2040                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14501                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.896007                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.195594                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11164     77.11%     77.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1470     10.15%     87.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      124      0.86%     88.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      160      1.11%     89.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      283      1.95%     91.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       94      0.65%     91.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      128      0.88%     92.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      113      0.78%     93.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      942      6.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11177     77.08%     77.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1470     10.14%     87.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      121      0.83%     88.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      160      1.10%     89.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      283      1.95%     91.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       95      0.66%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      127      0.88%     92.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      112      0.77%     93.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      956      6.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14478                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.046348                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.283251                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8487                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2706                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2773                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   121                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    391                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  174                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                14501                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.047448                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.289977                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8511                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2687                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2777                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   129                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    397                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  172                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    43                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11880                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   172                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    391                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8645                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     502                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1002                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2724                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1214                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11398                       # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts                  12008                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   170                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    397                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8669                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     506                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            996                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2735                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1198                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11509                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    231                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    967                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                6879                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13412                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13162                       # Number of integer rename lookups
+system.cpu.rename.LQFullEvents                    229                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    954                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                6966                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13566                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13315                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3282                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3597                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 13                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts              9                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       290                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2474                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1168                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                     3684                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 14                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       296                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2503                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1169                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       8940                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       9007                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8204                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                35                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3964                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1790                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      8237                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                38                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4031                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1845                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14478                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.566653                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.310295                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.568030                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.308332                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11167     77.13%     77.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1314      9.08%     86.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 734      5.07%     91.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 423      2.92%     94.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 344      2.38%     96.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 310      2.14%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 102      0.70%     99.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  57      0.39%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  27      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11165     76.99%     76.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1330      9.17%     86.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 739      5.10%     91.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 423      2.92%     94.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 353      2.43%     96.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 304      2.10%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 105      0.72%     99.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  58      0.40%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  24      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14478                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14501                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       9      4.59%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    129     65.82%     70.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       7      3.57%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    131     66.84%     70.41% # attempts to use FU when none available
 system.cpu.iq.fu_full::MemWrite                    58     29.59%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4822     58.78%     58.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2303     28.07%     86.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1072     13.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4840     58.76%     58.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2319     28.15%     87.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1071     13.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8204                       # Type of FU issued
-system.cpu.iq.rate                           0.180209                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   8237                       # Type of FU issued
+system.cpu.iq.rate                           0.183833                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         196                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023891                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31113                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             12922                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7408                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.023795                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31205                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             13056                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7426                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8398                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8431                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               82                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               83                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1342                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1371                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          267                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          268                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            23                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    391                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     464                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10483                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               162                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2474                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1168                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    397                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     472                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     7                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10561                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               155                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2503                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1169                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 11                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    12                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     9                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             96                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          348                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  444                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7875                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2160                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               329                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             98                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          354                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  452                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7898                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2175                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               339                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1532                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3217                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1365                       # Number of branches executed
-system.cpu.iew.exec_stores                       1057                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.172982                       # Inst execution rate
-system.cpu.iew.wb_sent                           7509                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7410                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2869                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4254                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1543                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3228                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1368                       # Number of branches executed
+system.cpu.iew.exec_stores                       1053                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.176267                       # Inst execution rate
+system.cpu.iew.wb_sent                           7529                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7428                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2859                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4251                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.162768                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.674424                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.165778                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.672548                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4860                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4937                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               9                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               382                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13623                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.412758                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.228786                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               388                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13632                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.412485                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.223639                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11456     84.09%     84.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          871      6.39%     90.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          510      3.74%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          252      1.85%     96.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          148      1.09%     97.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          178      1.31%     98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           65      0.48%     98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           40      0.29%     99.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          103      0.76%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11448     83.98%     83.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          886      6.50%     90.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          511      3.75%     94.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          255      1.87%     96.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          161      1.18%     97.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          164      1.20%     98.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           65      0.48%     98.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           40      0.29%     99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13623                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13632                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5623                       # Number of instructions committed
 system.cpu.commit.committedOps                   5623                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite            901     16.02%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5623                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   103                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        23990                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21831                       # The number of ROB writes
-system.cpu.timesIdled                             267                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           31047                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        24077                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22001                       # The number of ROB writes
+system.cpu.timesIdled                             266                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           30306                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4986                       # Number of Instructions Simulated
 system.cpu.committedOps                          4986                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               9.130566                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         9.130566                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.109522                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.109522                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10639                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5201                       # number of integer regfile writes
+system.cpu.cpi                               8.986562                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.986562                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.111277                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.111277                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10682                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5223                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     165                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                     167                       # number of misc regfile reads
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.212769                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2418                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            91.242537                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2427                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.148936                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.212766                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.212769                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022269                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022269                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.242537                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022276                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022276                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5997                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5997                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1862                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1862                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              6025                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             6025                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1871                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1871                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          556                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            556                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2418                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2418                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2418                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2418                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          165                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           165                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2427                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2427                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2427                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2427                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          170                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           170                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          345                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          345                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          510                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            510                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          510                       # number of overall misses
-system.cpu.dcache.overall_misses::total           510                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     12038750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     12038750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24387249                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24387249                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36425999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36425999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36425999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36425999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2027                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2027                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          515                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            515                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          515                       # number of overall misses
+system.cpu.dcache.overall_misses::total           515                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11738500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11738500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     24073999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     24073999                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     35812499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     35812499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     35812499                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     35812499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2041                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2041                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2928                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2928                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2928                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2928                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081401                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081401                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2942                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2942                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2942                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2942                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083293                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.083293                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.382908                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.382908                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.174180                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.174180                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.174180                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.174180                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71423.527451                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71423.527451                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          611                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.175051                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.175051                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.175051                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.175051                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        69050                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        69050                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69538.833010                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69538.833010                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          615                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.909091                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           74                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           79                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          295                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          295                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          369                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          369                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          369                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          369                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
@@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          141
 system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7833500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7833500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4084749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4084749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11918249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11918249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11918249                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11918249                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044894                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044894                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7586500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7586500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4094999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4094999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11681499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11681499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11681499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11681499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044586                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044586                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048156                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.048156                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048156                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.048156                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.047927                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.047927                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.047927                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.047927                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83368.131868                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83368.131868                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81899.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81899.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82847.510638                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82847.510638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82847.510638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82847.510638                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           158.205778                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1577                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           158.208729                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1588                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               333                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.735736                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.768769                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   158.205778                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077249                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077249                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   158.208729                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077250                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          316                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.154297                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4385                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4385                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1577                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1577                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1577                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1577                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1577                       # number of overall hits
-system.cpu.icache.overall_hits::total            1577                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          449                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           449                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          449                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            449                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          449                       # number of overall misses
-system.cpu.icache.overall_misses::total           449                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34003000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34003000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34003000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34003000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34003000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34003000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2026                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2026                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2026                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2026                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2026                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2026                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.221619                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.221619                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.221619                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.221619                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.221619                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.221619                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75730.512249                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75730.512249                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              4413                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4413                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1588                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1588                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1588                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1588                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1588                       # number of overall hits
+system.cpu.icache.overall_hits::total            1588                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          452                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           452                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          452                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            452                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          452                       # number of overall misses
+system.cpu.icache.overall_misses::total           452                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     33055000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     33055000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     33055000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     33055000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     33055000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     33055000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2040                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2040                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2040                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2040                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2040                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2040                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.221569                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.221569                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.221569                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.221569                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.221569                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.221569                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73130.530973                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73130.530973                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73130.530973                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73130.530973                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73130.530973                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73130.530973                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -741,115 +741,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          116                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          116                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          116                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          116                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          116                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          116                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          119                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          119                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          119                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          119                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          119                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          119                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          333                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          333                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          333                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          333                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          333                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          333                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26389500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26389500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26389500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26389500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26389500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26389500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.164363                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.164363                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.164363                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.164363                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.164363                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.164363                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25884000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25884000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25884000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25884000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25884000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25884000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163235                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.163235                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.163235                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77729.729730                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 77729.729730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 77729.729730                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          218.150435                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          218.239575                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 20                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              421                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.007126                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.047506                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.168468                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.981967                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004888                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001769                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006657                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.142310                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    58.097265                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004887                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001773                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006660                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012848                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4263                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4263                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses             4399                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4399                       # Number of data accesses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            3                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          330                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          421                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          330                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          330                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           91                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           91                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          330                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           471                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          330                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          141                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          471                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26025000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7738500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     33763500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4034000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4034000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     26025000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11772500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     37797500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     26025000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11772500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     37797500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          333                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          424                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25353000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25353000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7446500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7446500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25353000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11465500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst     25353000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11465500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36818500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          333                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          333                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          474                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          333                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          474                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.990991                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.992925                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.990991                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.990991                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990991                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.993671                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990991                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.993671                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        80680                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        80680                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        80380                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        80380                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76827.272727                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76827.272727                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81829.670330                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81829.670330                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.272727                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81315.602837                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78170.912951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.272727                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81315.602837                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78170.912951                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -858,83 +863,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          330                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          421                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          330                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          330                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           91                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           91                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          330                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          471                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          330                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          471                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     21894000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6598000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     28492000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3411000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3411000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     21894000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10009000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     31903000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     21894000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10009000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     31903000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.992925                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3519000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3519000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22053000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22053000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6536500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6536500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22053000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10055500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32108500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22053000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10055500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32108500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.990991                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.993671                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.993671                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        68220                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        68220                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        70380                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        70380                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66827.272727                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71829.670330                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71829.670330                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71315.602837                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68170.912951                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71315.602837                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68170.912951                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          666                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          333                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           91                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          683                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               965                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21312                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              30336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          474                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          491                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                474    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                491    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            474                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         237000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        569000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        233500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 421                       # Transaction distribution
+system.cpu.toL2Bus.snoop_fanout::total            491                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         245500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        499500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                421                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           421                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          942                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    942                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30144                       # Cumulative packet size per connected master and slave (bytes)
@@ -950,9 +961,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 471                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              598000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              582000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2506000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2503500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 8476aa73a..c6923a4b0 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000115                       # Number of seconds simulated
-sim_ticks                                      115467                       # Number of ticks simulated
-final_tick                                     115467                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      115089                       # Number of ticks simulated
+final_tick                                     115089                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66709                       # Simulator instruction rate (inst/s)
-host_op_rate                                    66698                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1369179                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 449556                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  64252                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64242                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1314462                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449728                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5624                       # Number of instructions simulated
 sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1470                       #
 system.mem_ctrls.num_reads::total                1470                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1466                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1466                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    814778248                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             814778248                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    812561165                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            812561165                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1627339413                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1627339413                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    817454318                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             817454318                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    815229952                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            815229952                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1632684270                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1632684270                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1470                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1466                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1470                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1466                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  59456                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   34624                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   60800                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  58496                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   35584                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   59392                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   94080                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                93824                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    541                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   491                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    556                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   513                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                34                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                32                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 7                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 3                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                13                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                88                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                66                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9               248                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10              103                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               46                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12              103                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               45                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14              158                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               15                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                36                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6                12                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7                78                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                64                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9               241                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               97                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               44                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12              115                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               43                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14              165                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               13                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                33                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 7                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 3                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                13                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                76                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                60                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9               249                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10              103                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               47                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12              114                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               44                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14              182                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15               16                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6                11                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                66                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                59                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9               245                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               98                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               45                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12              118                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               43                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14              186                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15               14                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        115396                       # Total gap between requests
+system.mem_ctrls.totGap                        115018                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1466                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     929                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     914                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,26 +135,26 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                     13                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                     17                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     62                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     60                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                     11                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                     15                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     55                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     61                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     58                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     59                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     58                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
@@ -184,89 +184,89 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          362                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    330.077348                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   218.964738                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   303.831296                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           84     23.20%     23.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255          104     28.73%     51.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           58     16.02%     67.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           36      9.94%     77.90% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           19      5.25%     83.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           10      2.76%     85.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            9      2.49%     88.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            5      1.38%     89.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           37     10.22%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          362                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           57                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.105263                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.953786                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.697116                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             1      1.75%      1.75% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            25     43.86%     45.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            25     43.86%     89.47% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             5      8.77%     98.25% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      1.75%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            57                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           57                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.666667                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.637263                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.023533                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               37     64.91%     64.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                6     10.53%     75.44% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18               11     19.30%     94.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                2      3.51%     98.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20                1      1.75%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            57                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        12340                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   29991                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4645                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        13.28                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          343                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    339.965015                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   217.922152                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   320.777927                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           88     25.66%     25.66% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           98     28.57%     54.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           42     12.24%     66.47% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           32      9.33%     75.80% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           16      4.66%     80.47% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           13      3.79%     84.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            8      2.33%     86.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            5      1.46%     88.05% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           41     11.95%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          343                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           56                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.125000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.967614                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      2.737368                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             2      3.57%      3.57% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            19     33.93%     37.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            27     48.21%     85.71% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             7     12.50%     98.21% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      1.79%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            56                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           56                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.571429                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.541189                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.041976                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               41     73.21%     73.21% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                3      5.36%     78.57% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                8     14.29%     92.86% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                3      5.36%     98.21% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20                1      1.79%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            56                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        12397                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   29763                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4570                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        13.56                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   32.28                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       514.92                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       526.56                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    814.78                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    812.56                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   32.56                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       508.27                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       516.05                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    817.45                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    815.23                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         8.14                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.02                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    4.11                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         8.00                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     3.97                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    4.03                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.24                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      618                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     892                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 66.52                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                91.49                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         39.30                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    79.31                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   559440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   310800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1684800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                1327104                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen                      25.10                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      631                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     861                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 69.04                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                90.35                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         39.18                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    79.91                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   544320                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   302400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1522560                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                1202688                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             54116712                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             18087600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               83206296                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            761.516108                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        29701                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             49529808                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             22111200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               82332816                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            753.521892                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        36376                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         76066                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         69262                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  2079000                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                  1155000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 9372480                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                7993728                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                  1988280                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                  1104600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 9397440                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                8076672                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             74259144                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               418800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy              102397992                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            937.161297                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          278                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             74119608                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               541200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy              102347640                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            936.700469                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1449                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT        105360                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        105142                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -288,7 +288,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.numCycles                           115467                       # number of cpu cycles simulated
+system.cpu.numCycles                           115089                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5624                       # Number of instructions committed
@@ -307,7 +307,7 @@ system.cpu.num_mem_refs                          2034                       # nu
 system.cpu.num_load_insts                        1132                       # Number of load instructions
 system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     115467                       # Number of busy cycles
+system.cpu.num_busy_cycles                     115089                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               883                       # Number of branches fetched
@@ -362,10 +362,10 @@ system.ruby.outstanding_req_hist::total          7659
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                7658                      
-system.ruby.latency_hist::mean              14.077958                      
-system.ruby.latency_hist::gmean              5.242569                      
-system.ruby.latency_hist::stdev             26.858459                      
-system.ruby.latency_hist                 |        7322     95.61%     95.61% |         283      3.70%     99.31% |          37      0.48%     99.79% |           6      0.08%     99.87% |           9      0.12%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              14.028598                      
+system.ruby.latency_hist::gmean              5.234161                      
+system.ruby.latency_hist::stdev             27.167008                      
+system.ruby.latency_hist                 |        7344     95.90%     95.90% |         261      3.41%     99.31% |          37      0.48%     99.79% |           4      0.05%     99.84% |           9      0.12%     99.96% |           3      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  7658                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -377,17 +377,17 @@ system.ruby.hit_latency_hist::total              6188
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1470                      
-system.ruby.miss_latency_hist::mean         60.710884                      
-system.ruby.miss_latency_hist::gmean        54.957755                      
-system.ruby.miss_latency_hist::stdev        32.665540                      
-system.ruby.miss_latency_hist            |        1134     77.14%     77.14% |         283     19.25%     96.39% |          37      2.52%     98.91% |           6      0.41%     99.32% |           9      0.61%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         60.453741                      
+system.ruby.miss_latency_hist::gmean        54.500138                      
+system.ruby.miss_latency_hist::stdev        34.320124                      
+system.ruby.miss_latency_hist            |        1156     78.64%     78.64% |         261     17.76%     96.39% |          37      2.52%     98.91% |           4      0.27%     99.18% |           9      0.61%     99.80% |           3      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1470                      
 system.ruby.Directory.incomplete_times           1469                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6188                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1470                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         7658                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.356795                      
+system.ruby.network.routers0.percent_links_utilized     6.377673                      
 system.ruby.network.routers0.msg_count.Control::2         1470                      
 system.ruby.network.routers0.msg_count.Data::2         1466                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1470                      
@@ -396,7 +396,7 @@ system.ruby.network.routers0.msg_bytes.Control::2        11760
 system.ruby.network.routers0.msg_bytes.Data::2       105552                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4       105840                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        11728                      
-system.ruby.network.routers1.percent_links_utilized     6.356795                      
+system.ruby.network.routers1.percent_links_utilized     6.377673                      
 system.ruby.network.routers1.msg_count.Control::2         1470                      
 system.ruby.network.routers1.msg_count.Data::2         1466                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1470                      
@@ -405,7 +405,7 @@ system.ruby.network.routers1.msg_bytes.Control::2        11760
 system.ruby.network.routers1.msg_bytes.Data::2       105552                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4       105840                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        11728                      
-system.ruby.network.routers2.percent_links_utilized     6.356795                      
+system.ruby.network.routers2.percent_links_utilized     6.377673                      
 system.ruby.network.routers2.msg_count.Control::2         1470                      
 system.ruby.network.routers2.msg_count.Data::2         1466                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1470                      
@@ -422,32 +422,32 @@ system.ruby.network.msg_byte.Control            35280
 system.ruby.network.msg_byte.Data              316656                      
 system.ruby.network.msg_byte.Response_Data       317520                      
 system.ruby.network.msg_byte.Writeback_Control        35184                      
-system.ruby.network.routers0.throttle0.link_utilization     6.363723                      
+system.ruby.network.routers0.throttle0.link_utilization     6.384624                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1470                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1466                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       105840                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        11728                      
-system.ruby.network.routers0.throttle1.link_utilization     6.349866                      
+system.ruby.network.routers0.throttle1.link_utilization     6.370722                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1470                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1466                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11760                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2       105552                      
-system.ruby.network.routers1.throttle0.link_utilization     6.349866                      
+system.ruby.network.routers1.throttle0.link_utilization     6.370722                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1470                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1466                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11760                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2       105552                      
-system.ruby.network.routers1.throttle1.link_utilization     6.363723                      
+system.ruby.network.routers1.throttle1.link_utilization     6.384624                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1470                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1466                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       105840                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        11728                      
-system.ruby.network.routers2.throttle0.link_utilization     6.363723                      
+system.ruby.network.routers2.throttle0.link_utilization     6.384624                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1470                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1466                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       105840                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        11728                      
-system.ruby.network.routers2.throttle1.link_utilization     6.349866                      
+system.ruby.network.routers2.throttle1.link_utilization     6.370722                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1470                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1466                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11760                      
@@ -462,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket            9                       #
 system.ruby.delayVCHist.vnet_2::samples          1466                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2           |        1466    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::total            1466                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist::bucket_size           32                      
-system.ruby.LD.latency_hist::max_bucket           319                      
+system.ruby.LD.latency_hist::bucket_size           64                      
+system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1132                      
-system.ruby.LD.latency_hist::mean           35.492049                      
-system.ruby.LD.latency_hist::gmean          16.147834                      
-system.ruby.LD.latency_hist::stdev          37.303839                      
-system.ruby.LD.latency_hist              |         465     41.08%     41.08% |         518     45.76%     86.84% |         124     10.95%     97.79% |           3      0.27%     98.06% |           3      0.27%     98.32% |          12      1.06%     99.38% |           2      0.18%     99.56% |           0      0.00%     99.56% |           3      0.27%     99.82% |           2      0.18%    100.00%
+system.ruby.LD.latency_hist::mean           35.838339                      
+system.ruby.LD.latency_hist::gmean          16.062923                      
+system.ruby.LD.latency_hist::stdev          41.117345                      
+system.ruby.LD.latency_hist              |         998     88.16%     88.16% |         109      9.63%     97.79% |          13      1.15%     98.94% |           2      0.18%     99.12% |           7      0.62%     99.73% |           3      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1132                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -477,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean               3
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
 system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         465    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist::total            465                      
-system.ruby.LD.miss_latency_hist::bucket_size           32                      
-system.ruby.LD.miss_latency_hist::max_bucket          319                      
+system.ruby.LD.miss_latency_hist::bucket_size           64                      
+system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          667                      
-system.ruby.LD.miss_latency_hist::mean      58.143928                      
-system.ruby.LD.miss_latency_hist::gmean     52.206801                      
-system.ruby.LD.miss_latency_hist::stdev     33.349415                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |         518     77.66%     77.66% |         124     18.59%     96.25% |           3      0.45%     96.70% |           3      0.45%     97.15% |          12      1.80%     98.95% |           2      0.30%     99.25% |           0      0.00%     99.25% |           3      0.45%     99.70% |           2      0.30%    100.00%
+system.ruby.LD.miss_latency_hist::mean      58.731634                      
+system.ruby.LD.miss_latency_hist::gmean     51.741753                      
+system.ruby.LD.miss_latency_hist::stdev     39.915394                      
+system.ruby.LD.miss_latency_hist         |         533     79.91%     79.91% |         109     16.34%     96.25% |          13      1.95%     98.20% |           2      0.30%     98.50% |           7      1.05%     99.55% |           3      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           667                      
 system.ruby.ST.latency_hist::bucket_size           32                      
 system.ruby.ST.latency_hist::max_bucket           319                      
 system.ruby.ST.latency_hist::samples              901                      
-system.ruby.ST.latency_hist::mean           14.748058                      
-system.ruby.ST.latency_hist::gmean           5.824702                      
-system.ruby.ST.latency_hist::stdev          24.783906                      
-system.ruby.ST.latency_hist              |         684     75.92%     75.92% |         183     20.31%     96.23% |          29      3.22%     99.45% |           0      0.00%     99.45% |           2      0.22%     99.67% |           2      0.22%     99.89% |           0      0.00%     99.89% |           0      0.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           14.653718                      
+system.ruby.ST.latency_hist::gmean           5.820052                      
+system.ruby.ST.latency_hist::stdev          24.674998                      
+system.ruby.ST.latency_hist              |         684     75.92%     75.92% |         188     20.87%     96.78% |          26      2.89%     99.67% |           0      0.00%     99.67% |           0      0.00%     99.67% |           1      0.11%     99.78% |           1      0.11%     99.89% |           0      0.00%     99.89% |           0      0.00%     99.89% |           1      0.11%    100.00%
 system.ruby.ST.latency_hist::total                901                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -503,18 +503,18 @@ system.ruby.ST.hit_latency_hist::total            684
 system.ruby.ST.miss_latency_hist::bucket_size           32                      
 system.ruby.ST.miss_latency_hist::max_bucket          319                      
 system.ruby.ST.miss_latency_hist::samples          217                      
-system.ruby.ST.miss_latency_hist::mean      51.778802                      
-system.ruby.ST.miss_latency_hist::gmean     47.157588                      
-system.ruby.ST.miss_latency_hist::stdev     27.288529                      
-system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |         183     84.33%     84.33% |          29     13.36%     97.70% |           0      0.00%     97.70% |           2      0.92%     98.62% |           2      0.92%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      51.387097                      
+system.ruby.ST.miss_latency_hist::gmean     47.001474                      
+system.ruby.ST.miss_latency_hist::stdev     27.408897                      
+system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |         188     86.64%     86.64% |          26     11.98%     98.62% |           0      0.00%     98.62% |           0      0.00%     98.62% |           1      0.46%     99.08% |           1      0.46%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00%
 system.ruby.ST.miss_latency_hist::total           217                      
-system.ruby.IFETCH.latency_hist::bucket_size           64                      
-system.ruby.IFETCH.latency_hist::max_bucket          639                      
+system.ruby.IFETCH.latency_hist::bucket_size           32                      
+system.ruby.IFETCH.latency_hist::max_bucket          319                      
 system.ruby.IFETCH.latency_hist::samples         5625                      
-system.ruby.IFETCH.latency_hist::mean        9.661156                      
-system.ruby.IFETCH.latency_hist::gmean       4.110524                      
-system.ruby.IFETCH.latency_hist::stdev      22.183687                      
-system.ruby.IFETCH.latency_hist          |        5472     97.28%     97.28% |         127      2.26%     99.54% |          18      0.32%     99.86% |           4      0.07%     99.93% |           3      0.05%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean        9.539378                      
+system.ruby.IFETCH.latency_hist::gmean       4.106431                      
+system.ruby.IFETCH.latency_hist::stdev      21.247440                      
+system.ruby.IFETCH.latency_hist          |        5039     89.58%     89.58% |         435      7.73%     97.32% |         121      2.15%     99.47% |           5      0.09%     99.56% |           8      0.14%     99.70% |          15      0.27%     99.96% |           1      0.02%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00%
 system.ruby.IFETCH.latency_hist::total           5625                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -523,21 +523,21 @@ system.ruby.IFETCH.hit_latency_hist::mean            3
 system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
 system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        5039    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist::total         5039                      
-system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
-system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
+system.ruby.IFETCH.miss_latency_hist::bucket_size           32                      
+system.ruby.IFETCH.miss_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.miss_latency_hist::samples          586                      
-system.ruby.IFETCH.miss_latency_hist::mean    66.940273                      
-system.ruby.IFETCH.miss_latency_hist::gmean    61.663848                      
-system.ruby.IFETCH.miss_latency_hist::stdev    32.593558                      
-system.ruby.IFETCH.miss_latency_hist     |         433     73.89%     73.89% |         127     21.67%     95.56% |          18      3.07%     98.63% |           4      0.68%     99.32% |           3      0.51%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    65.771331                      
+system.ruby.IFETCH.miss_latency_hist::gmean    61.076979                      
+system.ruby.IFETCH.miss_latency_hist::stdev    28.360902                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         435     74.23%     74.23% |         121     20.65%     94.88% |           5      0.85%     95.73% |           8      1.37%     97.10% |          15      2.56%     99.66% |           1      0.17%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          586                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1470                      
-system.ruby.Directory.miss_mach_latency_hist::mean    60.710884                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    54.957755                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    32.665540                      
-system.ruby.Directory.miss_mach_latency_hist |        1134     77.14%     77.14% |         283     19.25%     96.39% |          37      2.52%     98.91% |           6      0.41%     99.32% |           9      0.61%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    60.453741                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    54.500138                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    34.320124                      
+system.ruby.Directory.miss_mach_latency_hist |        1156     78.64%     78.64% |         261     17.76%     96.39% |          37      2.52%     98.91% |           4      0.27%     99.18% |           9      0.61%     99.80% |           3      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1470                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -565,29 +565,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    7
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev          nan                      
 system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            1                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          667                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    58.143928                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    52.206801                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    33.349415                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         518     77.66%     77.66% |         124     18.59%     96.25% |           3      0.45%     96.70% |           3      0.45%     97.15% |          12      1.80%     98.95% |           2      0.30%     99.25% |           0      0.00%     99.25% |           3      0.45%     99.70% |           2      0.30%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    58.731634                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    51.741753                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    39.915394                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |         533     79.91%     79.91% |         109     16.34%     96.25% |          13      1.95%     98.20% |           2      0.30%     98.50% |           7      1.05%     99.55% |           3      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          667                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           32                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          217                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    51.778802                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.157588                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    27.288529                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         183     84.33%     84.33% |          29     13.36%     97.70% |           0      0.00%     97.70% |           2      0.92%     98.62% |           2      0.92%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    51.387097                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.001474                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    27.408897                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         188     86.64%     86.64% |          26     11.98%     98.62% |           0      0.00%     98.62% |           0      0.00%     98.62% |           1      0.46%     99.08% |           1      0.46%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          217                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           32                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          586                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    66.940273                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    61.663848                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    32.593558                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         433     73.89%     73.89% |         127     21.67%     95.56% |          18      3.07%     98.63% |           4      0.68%     99.32% |           3      0.51%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    65.771331                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    61.076979                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    28.360902                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         435     74.23%     74.23% |         121     20.65%     94.88% |           5      0.85%     95.73% |           8      1.37%     97.10% |          15      2.56%     99.66% |           1      0.17%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          586                      
 system.ruby.Directory_Controller.GETX            1470      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1466      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 4f23a8939..7140a68cc 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30902500                       # Number of ticks simulated
 final_tick                                   30902500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 544856                       # Simulator instruction rate (inst/s)
-host_op_rate                                   544118                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2985748792                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288768                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 339265                       # Simulator instruction rate (inst/s)
+host_op_rate                                   338999                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1861147916                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 289452                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5624                       # Number of instructions simulated
 sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -108,14 +108,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5625                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.155054                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            86.152837                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1896                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.839416                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.155054                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021034                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021034                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.152837                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021033                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021033                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          137
 system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4654500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4654500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2675000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2675000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7329500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7329500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7329500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7329500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4698000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4698000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2700000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2700000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7398000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7398000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7398000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7398000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
@@ -202,24 +202,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388
 system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           129.101534                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           129.096971                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5331                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               295                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             18.071186                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   129.101534                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.063038                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.063038                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   129.096971                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063036                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063036                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          282                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
@@ -276,97 +276,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          295
 system.cpu.icache.demand_mshr_misses::total          295                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          295                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          295                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15699000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     15699000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15699000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     15699000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15699000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     15699000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15846500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15846500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15846500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15846500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052435                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.052435                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.052435                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          183.714965                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          183.690355                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 15                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              380                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.005263                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.039474                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.257719                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    53.457246                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.238740                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    53.451615                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003975                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001631                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005607                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005606                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          380                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011597                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3886                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3886                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses             3990                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3990                       # Number of data accesses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          293                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          380                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          293                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          293                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           87                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           87                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          293                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           430                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          293                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          137                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          430                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15383000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4567500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     19950500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2625000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2625000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     15383000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     15383000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4567500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4567500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     15383000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      7192500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     22575500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     15383000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      7192500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     22575500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          295                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          382                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          295                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          295                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           87                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           87                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          295                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          137                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          432                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          295                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          432                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993220                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.994764                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.993220                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.993220                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993220                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.995370                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993220                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995370                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791                       # average overall miss latency
@@ -381,83 +386,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          293                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          380                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          293                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          293                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           87                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           87                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          293                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          430                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11866500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3523500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15390000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2025000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2025000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11866500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5548500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17415000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11866500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5548500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17415000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994764                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2125000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2125000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     12453000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     12453000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3697500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3697500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12453000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5822500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     18275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12453000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5822500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     18275500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.993220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.995370                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995370                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            382                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           382                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           13                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          590                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           87                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          603                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          274                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               864                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               877                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18880                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              27648                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          432                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          445                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                432    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                445    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            432                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         216000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            445                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         222500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        442500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        205500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 380                       # Transaction distribution
 system.membus.trans_dist::ReadResp                380                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           380                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          860                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    860                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        27520                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index dd15d3497..8f334ebb7 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20101000                       # Number of ticks simulated
-final_tick                                   20101000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19998000                       # Number of ticks simulated
+final_tick                                   19998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29548                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29545                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              102528509                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221532                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  99740                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99716                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              344211505                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290580                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21952                       # Nu
 system.physmem.num_reads::cpu.inst                343                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   444                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1092084971                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            321576041                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1413661012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1092084971                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1092084971                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1092084971                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           321576041                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1413661012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1097709771                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            323232323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1420942094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1097709771                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1097709771                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1097709771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           323232323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1420942094                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           444                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         444                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        19960500                       # Total gap between requests
+system.physmem.totGap                        19858500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       142                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       141                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
@@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           78                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      332.307692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     193.606609                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.258819                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.430832                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     340.544877                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             29     37.18%     37.18% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255           17     21.79%     58.97% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            7      8.97%     67.95% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511            4      5.13%     73.08% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639            4      5.13%     78.21% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::640-767            3      3.85%     82.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      1.28%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            4      5.13%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.56%     84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.85%     88.46% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            9     11.54%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             78                       # Bytes accessed per row activation
-system.physmem.totQLat                        3861750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12186750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3950250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12275250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8697.64                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        8896.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27447.64                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1413.66                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27646.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1420.94                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1413.66                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1420.94                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.04                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.10                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,44 +220,44 @@ system.physmem.readRowHits                        357                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.41                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        44956.08                       # Average gap between requests
+system.physmem.avgGap                        44726.35                       # Average gap between requests
 system.physmem.pageHitRate                      80.41                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     461160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     251625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2511600                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                   2519400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10794375                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy               10796085                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 15068130                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              951.571203                       # Core power per rank (mW)
+system.physmem_0.totalEnergy                 15077640                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              952.021468                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15316250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15318750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    288600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                7470990                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                2946000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 11827875                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.063003                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        6720750                       # Time in different power states
+system.physmem_1.actBackEnergy                7492365                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                2927250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 11830500                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              747.228802                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        6597250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        10486250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        10517250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2330                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1881                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    2331                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1883                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               415                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1929                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     660                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1931                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     661                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.214619                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     219                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             34.230968                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     218                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -279,178 +279,178 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            40203                       # number of cpu cycles simulated
+system.cpu.numCycles                            39997                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7819                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13492                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2330                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles               7837                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13501                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2331                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                879                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4287                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                          4391                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     863                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           153                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      1828                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   299                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              12714                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.061192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.469867                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              12836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.051807                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.461524                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10352     81.42%     81.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      189      1.49%     82.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      216      1.70%     84.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      152      1.20%     85.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      247      1.94%     87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      139      1.09%     88.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      253      1.99%     90.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      114      0.90%     91.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1052      8.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10473     81.59%     81.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      190      1.48%     83.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      215      1.67%     84.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      153      1.19%     85.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      248      1.93%     87.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      135      1.05%     88.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      253      1.97%     90.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      115      0.90%     91.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1054      8.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                12714                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.057956                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.335597                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7212                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3139                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1951                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                12836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.058279                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.337550                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7233                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3240                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1952                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   129                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    282                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  336                       # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved                  335                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   150                       # Number of times decode detected a branch misprediction
 system.cpu.decode.DecodedInsts                  11562                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   472                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    282                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7370                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     950                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            627                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.IdleCycles                     7391                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     953                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            624                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      1916                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1569                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11201                       # Number of instructions processed by rename
+system.cpu.rename.UnblockCycles                  1670                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11195                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                     25                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1508                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9631                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18130                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18104                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                   1610                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9626                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 18124                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            18098                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     4633                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4628                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       361                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2014                       # Number of loads inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       362                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2015                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1832                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               29                       # Number of conflicting stores.
 system.cpu.iq.iqInstsAdded                      10320                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  63                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9105                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      9101                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                75                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined            4591                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3348                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined         3358                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         12714                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.716140                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.547958                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         12836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.709022                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.537942                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9591     75.44%     75.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 944      7.42%     82.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 633      4.98%     87.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 463      3.64%     91.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 426      3.35%     94.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 301      2.37%     97.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 240      1.89%     99.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  71      0.56%     99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  45      0.35%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9696     75.54%     75.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 959      7.47%     83.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 638      4.97%     87.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 461      3.59%     91.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 440      3.43%     95.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 291      2.27%     97.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 236      1.84%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  68      0.53%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  47      0.37%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           12714                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12836                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      11      4.37%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    122     48.41%     52.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   119     47.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      11      4.38%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    121     48.21%     52.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   119     47.41%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5535     60.79%     60.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     60.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1910     20.98%     81.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1658     18.21%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5531     60.77%     60.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     60.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1910     20.99%     81.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1658     18.22%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9105                       # Type of FU issued
-system.cpu.iq.rate                           0.226476                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         252                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.027677                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31189                       # Number of integer instruction queue reads
+system.cpu.iq.FU_type_0::total                   9101                       # Type of FU issued
+system.cpu.iq.rate                           0.227542                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         251                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.027579                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31302                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             14945                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8271                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses         8267                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9323                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9318                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               80                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1053                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1054                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          786                       # Number of stores squashed
@@ -460,56 +460,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads            1                       #
 system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                    282                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     870                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    73                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewBlockCycles                     869                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    77                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts               10383                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                18                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2014                       # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts                  2015                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1832                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 54                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    62                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    66                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          276                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  345                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8701                       # Number of executed instructions
+system.cpu.iew.iewExecutedInsts                  8700                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  1776                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               404                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts               401                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
 system.cpu.iew.exec_refs                         3330                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1363                       # Number of branches executed
 system.cpu.iew.exec_stores                       1554                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.216427                       # Inst execution rate
-system.cpu.iew.wb_sent                           8428                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8298                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4465                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7078                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.217516                       # Inst execution rate
+system.cpu.iew.wb_sent                           8425                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8294                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4459                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7044                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.206403                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.630828                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.207366                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.633021                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            4593                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               276                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12003                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.482546                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.346027                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12125                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.477691                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.335541                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9841     81.99%     81.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          848      7.06%     89.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          522      4.35%     93.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          225      1.87%     95.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          168      1.40%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          120      1.00%     97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          110      0.92%     98.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           59      0.49%     99.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          110      0.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9949     82.05%     82.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          859      7.08%     89.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          524      4.32%     93.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          226      1.86%     95.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          182      1.50%     96.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          108      0.89%     97.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          109      0.90%     98.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           59      0.49%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          109      0.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12003                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12125                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -555,60 +555,60 @@ system.cpu.commit.op_class_0::MemWrite           1046     18.06%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   110                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22278                       # The number of ROB reads
+system.cpu.commit.bw_lim_events                   109                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        22401                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21482                       # The number of ROB writes
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27489                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           27161                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.941126                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.941126                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.144069                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.144069                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               6.905559                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.905559                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.144811                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.144811                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    13740                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7173                       # number of integer regfile writes
+system.cpu.int_regfile_writes                    7170                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            63.843132                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2276                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            63.810933                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2272                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             22.313725                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             22.274510                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    63.843132                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.015587                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.015587                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    63.810933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015579                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015579                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1556                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1556                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          720                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            720                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2276                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2276                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2276                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2276                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          111                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           111                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          326                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          326                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
-system.cpu.dcache.overall_misses::total           437                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8814500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8814500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     30924496                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     30924496                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     39738996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     39738996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     39738996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     39738996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_hits::cpu.data         1553                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1553                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          719                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            719                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2272                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2272                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          327                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          327                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          441                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            441                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          441                       # number of overall misses
+system.cpu.dcache.overall_misses::total           441                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8777500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8777500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     32490996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     32490996                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     41268496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     41268496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     41268496                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     41268496                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1667                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1667                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
@@ -617,38 +617,38 @@ system.cpu.dcache.demand_accesses::cpu.data         2713                       #
 system.cpu.dcache.demand_accesses::total         2713                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data         2713                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2713                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.066587                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.066587                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.311663                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.311663                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.161076                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.161076                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.161076                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.161076                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 90935.917620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 90935.917620                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          623                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068386                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.068386                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.312620                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.312620                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.162551                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.162551                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.162551                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.162551                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 93579.356009                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 93579.356009                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          627                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   103.833333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   104.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          279                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          279                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          335                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          335                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          335                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          335                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          280                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          280                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          339                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          339                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
@@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          102
 system.cpu.dcache.demand_mshr_misses::total          102                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          102                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4529750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4529750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4417498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4417498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8947248                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8947248                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8947248                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8947248                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4552000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4552000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4551498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4551498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9103498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9103498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9103498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9103498                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032993                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032993                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
@@ -673,27 +673,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037597
 system.cpu.dcache.demand_mshr_miss_rate::total     0.037597                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037597                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.037597                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.362964                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           169.178952                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1389                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               349                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.979943                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.362964                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082697                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082697                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   169.178952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082607                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082607                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          165                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.170410                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4005                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4005                       # Number of data accesses
@@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst          439                       # n
 system.cpu.icache.demand_misses::total            439                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          439                       # number of overall misses
 system.cpu.icache.overall_misses::total           439                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31975250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31975250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31975250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31975250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31975250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31975250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31700000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31700000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31700000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31700000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31700000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31700000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1828                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1828                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1828                       # number of demand (read+write) accesses
@@ -727,17 +727,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.240153
 system.cpu.icache.demand_miss_rate::total     0.240153                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.240153                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.240153                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72836.560364                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72836.560364                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          487                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72209.567198                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72209.567198                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          485                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    97.400000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           97                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -753,106 +753,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          350
 system.cpu.icache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26127750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26127750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26127750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26127750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26127750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26127750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26208500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26208500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26208500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26208500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26208500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26208500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.191466                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.191466                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.191466                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.954316                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          199.713481                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              397                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.017632                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.205981                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.748335                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005133                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000969                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006102                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.994608                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.718873                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005127                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000968                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006095                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          198                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012115                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4060                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4060                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            6                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              7                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            6                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            6                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data            1                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total            1                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            6                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               7                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            6                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              7                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           54                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          398                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          344                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          344                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           54                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           54                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          101                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           445                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          445                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25715250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4463750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     30179000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4367500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4367500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25715250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      8831250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34546500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25715250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      8831250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34546500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          350                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          405                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4478000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4478000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25621500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25621500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4458500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4458500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25621500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8936500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34558000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25621500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8936500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34558000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          350                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          350                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           55                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           55                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          350                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          102                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          350                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          102                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.982857                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981818                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.982716                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.982857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.982857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.981818                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.981818                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982857                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.990196                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.984513                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982857                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.990196                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.984513                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -861,55 +867,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          344                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          398                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          344                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          344                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           54                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           54                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          445                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          445                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     21441250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3792250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25233500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3785500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3785500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     21441250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7577750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     29019000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     21441250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7577750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     29019000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.982716                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4008000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4008000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22191500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22191500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3918500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3918500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22191500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7926500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30118000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22191500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7926500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30118000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.982857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.981818                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.984513                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.984513                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            405                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           404                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           47                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          350                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           55                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          699                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          204                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               903                       # Packet count per connected master and slave (bytes)
@@ -930,14 +941,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            452                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         226000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        589250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        165750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        523500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        153000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 397                       # Transaction distribution
 system.membus.trans_dist::ReadResp                397                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               47                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           397                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          888                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    888                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28416                       # Cumulative packet size per connected master and slave (bytes)
@@ -953,9 +964,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 444                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              555000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              550500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2341000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2342500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 51b100b5f..3da0fac46 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000096                       # Number of seconds simulated
-sim_ticks                                       95989                       # Number of ticks simulated
-final_tick                                      95989                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000095                       # Number of seconds simulated
+sim_ticks                                       95241                       # Number of ticks simulated
+final_tick                                      95241                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73101                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73087                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1316740                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 448980                       # Number of bytes of host memory used
+host_inst_rate                                  71470                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71456                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1277340                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449880                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1289                       #
 system.mem_ctrls.num_reads::total                1289                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1285                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1285                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    859431810                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             859431810                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    856764838                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            856764838                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1716196648                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1716196648                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    866181581                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             866181581                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    863493663                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            863493663                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1729675245                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1729675245                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1289                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1285                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1289                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1285                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  44736                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   37760                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   45312                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  43328                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   39168                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   43904                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   82496                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                82240                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    590                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   557                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    612                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   580                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                30                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                32                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                16                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                 8                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5               111                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5               113                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6               121                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7               141                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                57                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7               123                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                59                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                34                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               12                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               59                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12               23                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               63                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               15                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               11                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               58                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12               21                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               61                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               11                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                8                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                31                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1                15                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                32                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1                16                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 8                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5               111                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6               120                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7               148                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                59                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9                37                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               12                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               59                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               23                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               58                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15                8                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6               113                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7               127                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                65                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9                35                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               11                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               56                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12               22                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               66                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               14                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15                9                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         95925                       # Total gap between requests
+system.mem_ctrls.totGap                         95177                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1285                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     699                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     677                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      8                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      9                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     36                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     45                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     47                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     44                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     42                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -184,92 +184,92 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          230                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    387.339130                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   262.668395                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   318.441590                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           45     19.57%     19.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           51     22.17%     41.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           39     16.96%     58.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           22      9.57%     68.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           23     10.00%     78.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            5      2.17%     80.43% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           12      5.22%     85.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            9      3.91%     89.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           24     10.43%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          230                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           43                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.186047                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.978763                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.231215                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            22     51.16%     51.16% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            14     32.56%     83.72% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             5     11.63%     95.35% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             1      2.33%     97.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      2.33%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            43                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           43                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.465116                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.435760                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.031615                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               35     81.40%     81.40% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                1      2.33%     83.72% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                2      4.65%     88.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                5     11.63%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            43                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8743                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   22024                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3495                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.51                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          241                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    353.991701                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   236.521382                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   306.711183                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           49     20.33%     20.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           67     27.80%     48.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           30     12.45%     60.58% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           30     12.45%     73.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           18      7.47%     80.50% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            7      2.90%     83.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            9      3.73%     87.14% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023           14      5.81%     92.95% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           17      7.05%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          241                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           42                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.047619                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.828866                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.297837                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             1      2.38%      2.38% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            18     42.86%     45.24% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            17     40.48%     85.71% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             5     11.90%     97.62% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      2.38%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            42                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           42                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.333333                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.313589                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.845841                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               35     83.33%     83.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                3      7.14%     90.48% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                1      2.38%     92.86% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                3      7.14%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            42                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                         8633                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   21496                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3385                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        12.75                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.51                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       466.05                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       472.05                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    859.43                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    856.76                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.75                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       454.93                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       460.98                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    866.18                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    863.49                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         7.33                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     3.64                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    3.69                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         7.16                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     3.55                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    3.60                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.98                       # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      25.53                       # Average write queue length when enqueuing
 system.mem_ctrls.readRowHits                      496                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     676                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 70.96                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                92.86                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         37.27                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    82.13                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                  1035720                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   575400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5229120                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                4271616                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.writeRowHits                     621                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 73.26                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                88.09                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         36.98                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    80.82                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                  1141560                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   634200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5079360                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                4178304                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             59194044                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              4292400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               80701020                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            861.316185                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         6799                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             60945084                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              2754600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               80835828                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            862.782607                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE         4199                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3120                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         83841                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         86387                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   672840                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   373800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 3257280                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                2716416                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                   680400                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   378000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 3194880                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                2768256                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             56250108                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              6873000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               76246164                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            813.795884                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        11133                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             57004560                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              6211200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               76340016                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            814.797592                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE        10140                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3120                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         79453                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         80556                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            95989                       # number of cpu cycles simulated
+system.cpu.numCycles                            95241                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5327                       # Number of instructions committed
@@ -288,7 +288,7 @@ system.cpu.num_mem_refs                          1401                       # nu
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.999990                       # Number of idle cycles
-system.cpu.num_busy_cycles               95988.000010                       # Number of busy cycles
+system.cpu.num_busy_cycles               95240.000010                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.999990                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000010                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
@@ -343,10 +343,10 @@ system.ruby.outstanding_req_hist::total          6759
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                6758                      
-system.ruby.latency_hist::mean              13.203759                      
-system.ruby.latency_hist::gmean              5.149407                      
-system.ruby.latency_hist::stdev             25.345890                      
-system.ruby.latency_hist                 |        6535     96.70%     96.70% |         182      2.69%     99.39% |          30      0.44%     99.84% |           2      0.03%     99.87% |           8      0.12%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              13.093075                      
+system.ruby.latency_hist::gmean              5.137326                      
+system.ruby.latency_hist::stdev             25.295268                      
+system.ruby.latency_hist                 |        6551     96.94%     96.94% |         168      2.49%     99.42% |          27      0.40%     99.82% |           4      0.06%     99.88% |           3      0.04%     99.93% |           5      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  6758                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -358,17 +358,17 @@ system.ruby.hit_latency_hist::total              5469
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1289                      
-system.ruby.miss_latency_hist::mean         56.496509                      
-system.ruby.miss_latency_hist::gmean        50.965481                      
-system.ruby.miss_latency_hist::stdev        32.440273                      
-system.ruby.miss_latency_hist            |        1066     82.70%     82.70% |         182     14.12%     96.82% |          30      2.33%     99.15% |           2      0.16%     99.30% |           8      0.62%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         55.916214                      
+system.ruby.miss_latency_hist::gmean        50.341721                      
+system.ruby.miss_latency_hist::stdev        32.999000                      
+system.ruby.miss_latency_hist            |        1082     83.94%     83.94% |         168     13.03%     96.97% |          27      2.09%     99.07% |           4      0.31%     99.38% |           3      0.23%     99.61% |           5      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1289                      
 system.ruby.Directory.incomplete_times           1288                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         5469                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1289                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         6758                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.703893                      
+system.ruby.network.routers0.percent_links_utilized     6.756544                      
 system.ruby.network.routers0.msg_count.Control::2         1289                      
 system.ruby.network.routers0.msg_count.Data::2         1285                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1289                      
@@ -377,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2        10312
 system.ruby.network.routers0.msg_bytes.Data::2        92520                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers1.percent_links_utilized     6.703893                      
+system.ruby.network.routers1.percent_links_utilized     6.756544                      
 system.ruby.network.routers1.msg_count.Control::2         1289                      
 system.ruby.network.routers1.msg_count.Data::2         1285                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1289                      
@@ -386,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2        10312
 system.ruby.network.routers1.msg_bytes.Data::2        92520                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.percent_links_utilized     6.703893                      
+system.ruby.network.routers2.percent_links_utilized     6.756544                      
 system.ruby.network.routers2.msg_count.Control::2         1289                      
 system.ruby.network.routers2.msg_count.Data::2         1285                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1289                      
@@ -403,32 +403,32 @@ system.ruby.network.msg_byte.Control            30936
 system.ruby.network.msg_byte.Data              277560                      
 system.ruby.network.msg_byte.Response_Data       278424                      
 system.ruby.network.msg_byte.Writeback_Control        30840                      
-system.ruby.network.routers0.throttle0.link_utilization     6.712227                      
+system.ruby.network.routers0.throttle0.link_utilization     6.764944                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers0.throttle1.link_utilization     6.695559                      
+system.ruby.network.routers0.throttle1.link_utilization     6.748144                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1289                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1285                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        10312                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        92520                      
-system.ruby.network.routers1.throttle0.link_utilization     6.695559                      
+system.ruby.network.routers1.throttle0.link_utilization     6.748144                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1289                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1285                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        10312                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        92520                      
-system.ruby.network.routers1.throttle1.link_utilization     6.712227                      
+system.ruby.network.routers1.throttle1.link_utilization     6.764944                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.throttle0.link_utilization     6.712227                      
+system.ruby.network.routers2.throttle0.link_utilization     6.764944                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.throttle1.link_utilization     6.695559                      
+system.ruby.network.routers2.throttle1.link_utilization     6.748144                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1289                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1285                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        10312                      
@@ -446,10 +446,10 @@ system.ruby.delayVCHist.vnet_2::total            1285                       # de
 system.ruby.LD.latency_hist::bucket_size           32                      
 system.ruby.LD.latency_hist::max_bucket           319                      
 system.ruby.LD.latency_hist::samples              715                      
-system.ruby.LD.latency_hist::mean           30.924476                      
-system.ruby.LD.latency_hist::gmean          13.876278                      
-system.ruby.LD.latency_hist::stdev          34.776798                      
-system.ruby.LD.latency_hist              |         320     44.76%     44.76% |         330     46.15%     90.91% |          50      6.99%     97.90% |           2      0.28%     98.18% |           3      0.42%     98.60% |           6      0.84%     99.44% |           1      0.14%     99.58% |           0      0.00%     99.58% |           2      0.28%     99.86% |           1      0.14%    100.00%
+system.ruby.LD.latency_hist::mean           29.991608                      
+system.ruby.LD.latency_hist::gmean          13.799155                      
+system.ruby.LD.latency_hist::stdev          30.436552                      
+system.ruby.LD.latency_hist              |         320     44.76%     44.76% |         332     46.43%     91.19% |          50      6.99%     98.18% |           5      0.70%     98.88% |           4      0.56%     99.44% |           4      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total                715                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -461,18 +461,18 @@ system.ruby.LD.hit_latency_hist::total            320
 system.ruby.LD.miss_latency_hist::bucket_size           32                      
 system.ruby.LD.miss_latency_hist::max_bucket          319                      
 system.ruby.LD.miss_latency_hist::samples          395                      
-system.ruby.LD.miss_latency_hist::mean      53.546835                      
-system.ruby.LD.miss_latency_hist::gmean     47.987716                      
-system.ruby.LD.miss_latency_hist::stdev     32.331244                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |         330     83.54%     83.54% |          50     12.66%     96.20% |           2      0.51%     96.71% |           3      0.76%     97.47% |           6      1.52%     98.99% |           1      0.25%     99.24% |           0      0.00%     99.24% |           2      0.51%     99.75% |           1      0.25%    100.00%
+system.ruby.LD.miss_latency_hist::mean      51.858228                      
+system.ruby.LD.miss_latency_hist::gmean     47.506026                      
+system.ruby.LD.miss_latency_hist::stdev     24.651585                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |         332     84.05%     84.05% |          50     12.66%     96.71% |           5      1.27%     97.97% |           4      1.01%     98.99% |           4      1.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           395                      
-system.ruby.ST.latency_hist::bucket_size           32                      
-system.ruby.ST.latency_hist::max_bucket           319                      
+system.ruby.ST.latency_hist::bucket_size           64                      
+system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              673                      
-system.ruby.ST.latency_hist::mean           17.843982                      
-system.ruby.ST.latency_hist::gmean           6.493774                      
-system.ruby.ST.latency_hist::stdev          27.592771                      
-system.ruby.ST.latency_hist              |         494     73.40%     73.40% |         145     21.55%     94.95% |          28      4.16%     99.11% |           1      0.15%     99.26% |           2      0.30%     99.55% |           3      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           18.735513                      
+system.ruby.ST.latency_hist::gmean           6.548753                      
+system.ruby.ST.latency_hist::stdev          31.370836                      
+system.ruby.ST.latency_hist              |         639     94.95%     94.95% |          25      3.71%     98.66% |           8      1.19%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                673                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -481,21 +481,21 @@ system.ruby.ST.hit_latency_hist::mean               3
 system.ruby.ST.hit_latency_hist::gmean       3.000000                      
 system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         494    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist::total            494                      
-system.ruby.ST.miss_latency_hist::bucket_size           32                      
-system.ruby.ST.miss_latency_hist::max_bucket          319                      
+system.ruby.ST.miss_latency_hist::bucket_size           64                      
+system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          179                      
-system.ruby.ST.miss_latency_hist::mean      58.810056                      
-system.ruby.ST.miss_latency_hist::gmean     54.709109                      
-system.ruby.ST.miss_latency_hist::stdev     23.983086                      
-system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |         145     81.01%     81.01% |          28     15.64%     96.65% |           1      0.56%     97.21% |           2      1.12%     98.32% |           3      1.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      62.162011                      
+system.ruby.ST.miss_latency_hist::gmean     56.471067                      
+system.ruby.ST.miss_latency_hist::stdev     33.641225                      
+system.ruby.ST.miss_latency_hist         |         145     81.01%     81.01% |          25     13.97%     94.97% |           8      4.47%     99.44% |           0      0.00%     99.44% |           0      0.00%     99.44% |           1      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           179                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         5370                      
-system.ruby.IFETCH.latency_hist::mean       10.262756                      
-system.ruby.IFETCH.latency_hist::gmean       4.383388                      
-system.ruby.IFETCH.latency_hist::stdev      22.342607                      
-system.ruby.IFETCH.latency_hist          |        5246     97.69%     97.69% |         101      1.88%     99.57% |          16      0.30%     99.87% |           1      0.02%     99.89% |           5      0.09%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean       10.135940                      
+system.ruby.IFETCH.latency_hist::gmean       4.369076                      
+system.ruby.IFETCH.latency_hist::stdev      22.541685                      
+system.ruby.IFETCH.latency_hist          |        5260     97.95%     97.95% |          88      1.64%     99.59% |          11      0.20%     99.80% |           4      0.07%     99.87% |           3      0.06%     99.93% |           4      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           5370                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -507,18 +507,18 @@ system.ruby.IFETCH.hit_latency_hist::total         4655
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          715                      
-system.ruby.IFETCH.miss_latency_hist::mean    57.546853                      
-system.ruby.IFETCH.miss_latency_hist::gmean    51.762329                      
-system.ruby.IFETCH.miss_latency_hist::stdev    34.218674                      
-system.ruby.IFETCH.miss_latency_hist     |         591     82.66%     82.66% |         101     14.13%     96.78% |          16      2.24%     99.02% |           1      0.14%     99.16% |           5      0.70%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    56.594406                      
+system.ruby.IFETCH.miss_latency_hist::gmean    50.506398                      
+system.ruby.IFETCH.miss_latency_hist::stdev    36.435131                      
+system.ruby.IFETCH.miss_latency_hist     |         605     84.62%     84.62% |          88     12.31%     96.92% |          11      1.54%     98.46% |           4      0.56%     99.02% |           3      0.42%     99.44% |           4      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          715                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1289                      
-system.ruby.Directory.miss_mach_latency_hist::mean    56.496509                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    50.965481                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    32.440273                      
-system.ruby.Directory.miss_mach_latency_hist |        1066     82.70%     82.70% |         182     14.12%     96.82% |          30      2.33%     99.15% |           2      0.16%     99.30% |           8      0.62%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    55.916214                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    50.341721                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    32.999000                      
+system.ruby.Directory.miss_mach_latency_hist |        1082     83.94%     83.94% |         168     13.03%     96.97% |          27      2.09%     99.07% |           4      0.31%     99.38% |           3      0.23%     99.61% |           5      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1289                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -549,26 +549,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           32                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          319                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          395                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    53.546835                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    47.987716                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    32.331244                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         330     83.54%     83.54% |          50     12.66%     96.20% |           2      0.51%     96.71% |           3      0.76%     97.47% |           6      1.52%     98.99% |           1      0.25%     99.24% |           0      0.00%     99.24% |           2      0.51%     99.75% |           1      0.25%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    51.858228                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    47.506026                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    24.651585                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         332     84.05%     84.05% |          50     12.66%     96.71% |           5      1.27%     97.97% |           4      1.01%     98.99% |           4      1.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          395                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           32                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          319                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          179                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    58.810056                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    54.709109                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    23.983086                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         145     81.01%     81.01% |          28     15.64%     96.65% |           1      0.56%     97.21% |           2      1.12%     98.32% |           3      1.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    62.162011                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    56.471067                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    33.641225                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |         145     81.01%     81.01% |          25     13.97%     94.97% |           8      4.47%     99.44% |           0      0.00%     99.44% |           0      0.00%     99.44% |           1      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          179                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          715                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    57.546853                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    51.762329                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    34.218674                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         591     82.66%     82.66% |         101     14.13%     96.78% |          16      2.24%     99.02% |           1      0.14%     99.16% |           5      0.70%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    56.594406                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    50.506398                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    36.435131                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         605     84.62%     84.62% |          88     12.31%     96.92% |          11      1.54%     98.46% |           4      0.56%     99.02% |           3      0.42%     99.44% |           4      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          715                      
 system.ruby.Directory_Controller.GETX            1289      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1285      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index f6a7e842c..fd8319ed7 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    27800500                       # Number of ticks simulated
 final_tick                                   27800500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 510787                       # Simulator instruction rate (inst/s)
-host_op_rate                                   510102                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2658808340                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289420                       # Number of bytes of host memory used
+host_inst_rate                                 428112                       # Simulator instruction rate (inst/s)
+host_op_rate                                   427631                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2229390537                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290104                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
@@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5370                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            82.114550                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            82.112122                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1253                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              9.281481                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    82.114550                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.112122                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020047                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020047                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2847000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2847000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4333500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4333500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7180500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7180500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7180500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7180500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2874000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2874000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4374000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4374000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7248000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7248000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7248000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7248000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
@@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262
 system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           117.036911                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           117.032289                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5114                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               257                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             19.898833                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   117.036911                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.057147                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.057147                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   117.032289                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.057145                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.057145                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          257                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
@@ -258,100 +258,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          257
 system.cpu.icache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          257                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          257                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13666000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     13666000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13666000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     13666000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13666000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     13666000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13794500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13794500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13794500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13794500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13794500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13794500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.047850                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.047850                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.047850                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          142.175920                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          142.153744                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   116.512586                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    25.663334                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003556                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   116.494223                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    25.659521                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003555                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004339                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004338                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.009399                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3525                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3525                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data            1                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total            1                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          255                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          308                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           81                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           81                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          255                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          255                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           53                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           53                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          255                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           389                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          255                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          389                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     13388000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2782500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     16170500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4252500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      4252500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     13388000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     13388000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      2782500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      2782500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     13388000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      7035000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     20423000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     13388000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      7035000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     20423000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          257                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          311                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           81                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           81                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          257                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          257                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           54                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           54                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          257                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          135                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          392                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          257                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          135                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          392                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992218                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.990354                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.992218                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.992218                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.981481                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992218                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.992347                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992218                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.992347                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347                       # average overall miss latency
@@ -366,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          255                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          308                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           81                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           81                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          255                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          255                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           53                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           53                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          255                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          389                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          255                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          389                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10327500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2146500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12474000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3280500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3280500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10327500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5427000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15754500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10327500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5427000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15754500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.990354                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3442500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3442500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     10838000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     10838000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2252500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2252500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10838000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5695000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16533000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10838000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5695000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16533000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.992218                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.981481                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.992347                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.992347                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            311                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           311                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           81                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           81                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          257                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           54                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          514                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          270                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               784                       # Packet count per connected master and slave (bytes)
@@ -439,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        385500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        202500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 308                       # Transaction distribution
 system.membus.trans_dist::ReadResp                308                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                81                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               81                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           308                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          778                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    778                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        24896                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 66fb99cb1..ef02c087f 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21143500                       # Number of ticks simulated
-final_tick                                   21143500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21012000                       # Number of ticks simulated
+final_tick                                   21012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30354                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54988                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              119268705                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303472                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  49067                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88883                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              191585973                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310932                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17600                       # Nu
 system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            832407123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            426797834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1259204957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       832407123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          832407123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           832407123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           426797834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1259204957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            837616600                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            429468875                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1267085475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       837616600                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          837616600                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           837616600                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           429468875                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1267085475                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           417                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         417                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21095000                       # Total gap between requests
+system.physmem.totGap                        20963500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       244                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,137 +186,137 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          100                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      237.440000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     159.807528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     245.488436                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             35     35.00%     35.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           31     31.00%     66.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           16     16.00%     82.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            6      6.00%     88.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      2.00%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      3.00%     93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.00%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.00%     96.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            4      4.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            100                       # Bytes accessed per row activation
-system.physmem.totQLat                        5105750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12924500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           99                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      239.838384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     160.844462                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     248.938264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             34     34.34%     34.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           32     32.32%     66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           15     15.15%     81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      5.05%     86.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.02%     88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      4.04%     92.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.01%     93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.02%     95.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            4      4.04%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             99                       # Bytes accessed per row activation
+system.physmem.totQLat                        3956500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11775250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2085000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12244.00                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9488.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30994.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1262.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28238.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1270.13                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1262.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1270.13                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.86                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.86                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.92                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        307                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        308                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.62                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   73.86                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        50587.53                       # Average gap between requests
-system.physmem.pageHitRate                      73.62                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     181440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                      99000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    936000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        50272.18                       # Average gap between requests
+system.physmem.pageHitRate                      73.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    951600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
 system.physmem_0.actBackEnergy               10792665                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 13058475                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              824.789199                       # Core power per rank (mW)
+system.physmem_0.totalEnergy                 13085760                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              826.512553                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        15314750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     438480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     239250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1513200                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     430920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     235125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1521000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10696905                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 116250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 14021205                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              885.596400                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         102500                       # Time in different power states
+system.physmem_1.actBackEnergy               10315575                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 450750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13970490                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              882.393179                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         973750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15223750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14667250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    3414                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3414                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    3416                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3416                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               534                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2533                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     863                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 2538                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     864                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.070272                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             34.042553                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     247                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            42288                       # number of cpu cycles simulated
+system.cpu.numCycles                            42025                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              12201                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15496                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3414                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1110                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9718                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1201                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   55                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1161                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles              11194                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15490                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3416                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1111                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9646                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1195                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   51                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1127                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                      2164                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   280                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              23748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.168519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.673732                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2165                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   282                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              22628                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.226003                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.725670                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    19483     82.04%     82.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      236      0.99%     83.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      173      0.73%     83.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      257      1.08%     84.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      208      0.88%     85.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      228      0.96%     86.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      337      1.42%     88.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      205      0.86%     88.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2621     11.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18363     81.15%     81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      236      1.04%     82.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      174      0.77%     82.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      258      1.14%     84.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      208      0.92%     85.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      227      1.00%     86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      337      1.49%     87.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      205      0.91%     88.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2620     11.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                23748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.080732                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.366440                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11953                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  7408                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3332                       # Number of cycles decode is running
+system.cpu.fetch.rateDist::total                22628                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.081285                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.368590                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    10919                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  7328                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3329                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                   455                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    600                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  25703                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                    600                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    12221                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2293                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            795                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3474                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  4365                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  24179                       # Number of instructions processed by rename
+system.cpu.decode.SquashCycles                    597                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  25699                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                    597                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11189                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2276                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            782                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3470                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  4314                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24173                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                     93                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   4214                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               27545                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 59275                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            33508                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                   4163                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               27542                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 59265                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            33505                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    16482                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    16479                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             29                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                      1507                       # count of insts added to the skid buffer
@@ -324,109 +324,109 @@ system.cpu.memDep0.insertedLoads                 2438                       # Nu
 system.cpu.memDep0.insertedStores                1611                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21419                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      21416                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17882                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                79                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11697                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        16508                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     17876                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                80                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11694                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        16519                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         23748                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.752990                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.715169                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         22628                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.789995                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.748596                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               18623     78.42%     78.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1142      4.81%     83.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 888      3.74%     86.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 640      2.69%     89.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 832      3.50%     93.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 584      2.46%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 601      2.53%     98.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 314      1.32%     99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                 124      0.52%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               17504     77.36%     77.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1142      5.05%     82.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 891      3.94%     86.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 637      2.82%     89.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 831      3.67%     92.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 584      2.58%     95.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 600      2.65%     98.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 315      1.39%     99.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                 124      0.55%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           23748                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           22628                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     173     77.58%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     31     13.90%     91.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    19      8.52%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     174     77.68%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     31     13.84%     91.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    19      8.48%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14368     80.35%     80.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.39% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2121     11.86%     92.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14362     80.34%     80.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2121     11.87%     92.29% # Type of FU issued
 system.cpu.iq.FU_type_0::MemWrite                1379      7.71%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17882                       # Type of FU issued
-system.cpu.iq.rate                           0.422862                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         223                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012471                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              59806                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             33148                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16353                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17876                       # Type of FU issued
+system.cpu.iq.rate                           0.425366                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012531                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              58676                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             33142                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16350                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  8                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18098                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  18093                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads              235                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
@@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads             0                       # Nu
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    600                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1925                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    68                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21444                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    597                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1916                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    66                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21441                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts                  2438                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1611                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    60                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    58                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          569                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  694                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16910                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1967                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               972                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          565                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  690                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16903                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1966                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               973                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3249                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1660                       # Number of branches executed
+system.cpu.iew.exec_refs                         3248                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1659                       # Number of branches executed
 system.cpu.iew.exec_stores                       1282                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.399877                       # Inst execution rate
-system.cpu.iew.wb_sent                          16617                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16357                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10994                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     17115                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.402213                       # Inst execution rate
+system.cpu.iew.wb_sent                          16611                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16354                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10992                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     17112                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.386800                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.642361                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.389149                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.642356                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           11696                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           11693                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               587                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        21784                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.447438                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.339216                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               584                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        20667                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.471621                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.370778                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        18538     85.10%     85.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1010      4.64%     89.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          544      2.50%     92.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          738      3.39%     95.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          369      1.69%     97.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          141      0.65%     97.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          113      0.52%     98.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           72      0.33%     98.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          259      1.19%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        17422     84.30%     84.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1008      4.88%     89.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          544      2.63%     91.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          740      3.58%     95.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          368      1.78%     97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          141      0.68%     97.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          113      0.55%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           72      0.35%     98.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          259      1.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        21784                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        20667                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -536,100 +536,100 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   259                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        42968                       # The number of ROB reads
-system.cpu.rob.rob_writes                       44876                       # The number of ROB writes
+system.cpu.rob.rob_reads                        41848                       # The number of ROB reads
+system.cpu.rob.rob_writes                       44866                       # The number of ROB writes
 system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18540                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           19397                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.860223                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.860223                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.127223                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.127223                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    21328                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13105                       # number of integer regfile writes
+system.cpu.cpi                               7.811338                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.811338                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.128019                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.128019                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    21318                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13103                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                      8064                       # number of cc regfile reads
+system.cpu.cc_regfile_reads                      8054                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                     5036                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    7485                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7483                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            82.313704                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2393                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            82.324603                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2390                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.971631                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.950355                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    82.313704                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020096                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020096                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.324603                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020099                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020099                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5351                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5351                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1536                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1536                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5349                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5349                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1533                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1533                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          857                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            857                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2393                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2393                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2393                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2393                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          134                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           134                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2390                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2390                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2390                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2390                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          136                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           136                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           78                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           78                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          212                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            212                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          212                       # number of overall misses
-system.cpu.dcache.overall_misses::total           212                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11119000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11119000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      6761250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      6761250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17880250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17880250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17880250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17880250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1670                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1670                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          214                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            214                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          214                       # number of overall misses
+system.cpu.dcache.overall_misses::total           214                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10515500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10515500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      6241000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      6241000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16756500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16756500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16756500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16756500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1669                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1669                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2605                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2605                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080240                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.080240                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2604                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2604                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2604                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2604                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081486                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.081486                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.083422                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.083422                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.081382                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081382                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.081382                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081382                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 84340.801887                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 84340.801887                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          236                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.082181                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.082181                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.082181                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.082181                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77319.852941                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77319.852941                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80012.820513                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80012.820513                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 78301.401869                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 78301.401869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 78301.401869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 78301.401869                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          241                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    47.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.200000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           70                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           70                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           70                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           70                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           72                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           72                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           72                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           72                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           78                       # number of WriteReq MSHR misses
@@ -638,82 +638,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          142
 system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5695500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5695500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6612750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6612750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12308250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12308250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12308250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12308250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.038323                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.038323                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5436500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5436500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6163000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6163000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11599500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11599500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.038346                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.038346                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083422                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.054511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.054511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.054511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.054511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.054531                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.054531                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.054531                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.054531                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84945.312500                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84945.312500                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79012.820513                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79012.820513                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81686.619718                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81686.619718                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81686.619718                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81686.619718                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           131.513084                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1796                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           131.388880                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1795                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               276                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.507246                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.503623                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   131.513084                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.064215                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.064215                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   131.388880                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.064155                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.064155                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.134766                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4604                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4604                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1796                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1796                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1796                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1796                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1796                       # number of overall hits
-system.cpu.icache.overall_hits::total            1796                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          368                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           368                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          368                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            368                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          368                       # number of overall misses
-system.cpu.icache.overall_misses::total           368                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28645750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28645750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28645750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28645750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28645750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28645750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2164                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2164                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2164                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2164                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2164                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2164                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.170055                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.170055                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.170055                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.170055                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.170055                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.170055                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77841.711957                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77841.711957                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              4606                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4606                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1795                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1795                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1795                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1795                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1795                       # number of overall hits
+system.cpu.icache.overall_hits::total            1795                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          370                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           370                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          370                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            370                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          370                       # number of overall misses
+system.cpu.icache.overall_misses::total           370                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     27513500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     27513500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     27513500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     27513500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     27513500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     27513500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2165                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2165                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2165                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2165                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.170901                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.170901                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.170901                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.170901                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.170901                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.170901                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74360.810811                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74360.810811                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74360.810811                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74360.810811                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74360.810811                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74360.810811                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -722,115 +722,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           94                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           94                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           94                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           94                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           94                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          276                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          276                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          276                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21933250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21933250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21933250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21933250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21933250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21933250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.127542                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.127542                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.127542                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.127542                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.127542                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.127542                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21617000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21617000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21617000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total     21617000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.127483                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.127483                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.127483                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78322.463768                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78322.463768                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78322.463768                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          163.168393                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          162.995820                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              338                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002959                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.574096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.594298                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000964                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004980                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.424574                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.571246                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004011                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000963                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010315                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
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 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          275                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           64                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          339                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           78                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           78                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          275                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           78                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           78                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.inst          276                       # number of demand (read+write) accesses
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 system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          276                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996377                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997059                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996377                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996377                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997608                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996377                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997608                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77512.820513                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77512.820513                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77061.818182                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77061.818182                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83468.750000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83468.750000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77061.818182                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80197.183099                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78129.496403                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77061.818182                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80197.183099                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78129.496403                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -839,55 +844,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           78                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           78                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          275                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          275                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           64                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           64                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18201750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4837000                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5555250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5555250                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10392250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28594000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18201750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10392250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28594000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997059                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5266000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5266000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18442000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18442000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4712000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4712000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18442000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9978000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     28420000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18442000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9978000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     28420000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996377                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997608                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997608                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        73625                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        73625                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            340                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           78                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           78                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          276                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           64                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          552                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          283                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               835                       # Packet count per connected master and slave (bytes)
@@ -908,14 +918,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            418                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        471250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        239250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 339                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        414000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                338                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                78                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               78                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           339                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
@@ -933,9 +943,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 417                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              504000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              505000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2222500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             10.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2222250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             10.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 6ad7b9146..478e12e63 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000107                       # Number of seconds simulated
-sim_ticks                                      107237                       # Number of ticks simulated
-final_tick                                     107237                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      107256                       # Number of ticks simulated
+final_tick                                     107256                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59170                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107175                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1178869                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 466480                       # Number of bytes of host memory used
+host_inst_rate                                  57113                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103447                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1138055                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 467864                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
@@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1377                       #
 system.mem_ctrls.num_reads::total                1377                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1373                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1373                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    821805907                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             821805907                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    819418671                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            819418671                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1641224577                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1641224577                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    821660327                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             821660327                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    819273514                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            819273514                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1640933841                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1640933841                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1377                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1373                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1377                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1373                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  42624                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   45504                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   42752                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  43264                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   44864                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   43264                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   88128                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                87872                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    711                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   686                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    701                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   674                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                57                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                56                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 6                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                10                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                51                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                57                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                42                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                64                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                27                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9               134                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10              126                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               22                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                12                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                54                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                56                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6                43                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7                70                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                29                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9               129                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10              124                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               21                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12                2                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               28                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14                7                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               32                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               34                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14                8                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               31                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                50                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 6                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                10                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                52                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                55                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                44                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                66                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                28                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9               133                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                11                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                54                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                54                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6                41                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                72                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                30                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9               129                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10              129                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               22                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               21                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                2                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               30                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14                7                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15               33                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               36                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14                8                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15               32                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        107133                       # Total gap between requests
+system.mem_ctrls.totGap                        107152                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1373                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     666                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     676                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -135,14 +135,14 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                     10                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     43                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::23                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                     41                       # What write queue length does an incoming req see
@@ -184,92 +184,93 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          272                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    306.823529                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   199.088320                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   295.785748                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           71     26.10%     26.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           86     31.62%     57.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           34     12.50%     70.22% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           20      7.35%     77.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           17      6.25%     83.82% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            9      3.31%     87.13% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           11      4.04%     91.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      1.10%     92.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           21      7.72%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          272                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          276                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    306.782609                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   194.488181                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   303.473845                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           80     28.99%     28.99% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           80     28.99%     57.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           33     11.96%     69.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           22      7.97%     77.90% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           18      6.52%     84.42% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            7      2.54%     86.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            7      2.54%     89.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      1.45%     90.94% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           25      9.06%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          276                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples           41                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.121951                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.902045                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.325621                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             2      4.88%      4.88% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            18     43.90%     48.78% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            18     43.90%     92.68% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             2      4.88%     97.56% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.243902                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     16.023325                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.314970                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             1      2.44%      2.44% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            16     39.02%     41.46% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            18     43.90%     85.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             5     12.20%     97.56% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::34-35             1      2.44%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total            41                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples           41                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.292683                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.274345                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.813754                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               36     87.80%     87.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                3      7.32%     95.12% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                2      4.88%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.487805                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.459950                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.003044                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               32     78.05%     78.05% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                2      4.88%     82.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                3      7.32%     90.24% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                4      9.76%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            41                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         9844                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   22498                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3330                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        14.78                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         9573                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   22417                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3380                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        14.16                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   33.78                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       397.47                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       398.67                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    821.81                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    819.42                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   33.16                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       403.37                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       403.37                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    821.66                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    819.27                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         6.22                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     3.11                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    3.11                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         6.30                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     3.15                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    3.15                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.04                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      427                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     625                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 64.11                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                90.98                       # Row buffer hit rate for writes
+system.mem_ctrls.avgWrQLen                      25.88                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      443                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     622                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 65.53                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                88.98                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         38.96                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    77.75                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   695520                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   386400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 3219840                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                2623104                       # Energy for write commands per rank (pJ)
+system.mem_ctrls.pageHitRate                    77.45                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   703080                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   390600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 3319680                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                2685312                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             57895812                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             10101000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               81532956                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            803.454502                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        16443                       # Time in different power states
+system.mem_ctrls_0.actBackEnergy             57105108                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             10794600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               81609660                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            804.210371                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        17627                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          3380                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         81669                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         80485                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1270080                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   705600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 4605120                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                3784320                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy                  1292760                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   718200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 4630080                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                3805056                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_1.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             62916372                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              5697000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               85589772                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            843.431798                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         9164                       # Time in different power states
+system.mem_ctrls_1.actBackEnergy             62793936                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              5804400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               85655712                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            844.081594                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         9408                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          3380                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         89065                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         88844                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                   16                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                           107237                       # number of cpu cycles simulated
+system.cpu.numCycles                           107256                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5381                       # Number of instructions committed
@@ -290,7 +291,7 @@ system.cpu.num_mem_refs                          1988                       # nu
 system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.999991                       # Number of idle cycles
-system.cpu.num_busy_cycles               107236.000009                       # Number of busy cycles
+system.cpu.num_busy_cycles               107255.000009                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.999991                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000009                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
@@ -345,10 +346,10 @@ system.ruby.outstanding_req_hist::total          8852
 system.ruby.latency_hist::bucket_size              64                      
 system.ruby.latency_hist::max_bucket              639                      
 system.ruby.latency_hist::samples                8852                      
-system.ruby.latency_hist::mean              11.114437                      
-system.ruby.latency_hist::gmean              4.638310                      
-system.ruby.latency_hist::stdev             22.979355                      
-system.ruby.latency_hist                 |        8594     97.09%     97.09% |         215      2.43%     99.51% |          29      0.33%     99.84% |           6      0.07%     99.91% |           6      0.07%     99.98% |           2      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::mean              11.116584                      
+system.ruby.latency_hist::gmean              4.640695                      
+system.ruby.latency_hist::stdev             22.790037                      
+system.ruby.latency_hist                 |        8597     97.12%     97.12% |         214      2.42%     99.54% |          29      0.33%     99.86% |           4      0.05%     99.91% |           5      0.06%     99.97% |           3      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist::total                  8852                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
@@ -360,17 +361,17 @@ system.ruby.hit_latency_hist::total              7475
 system.ruby.miss_latency_hist::bucket_size           64                      
 system.ruby.miss_latency_hist::max_bucket          639                      
 system.ruby.miss_latency_hist::samples           1377                      
-system.ruby.miss_latency_hist::mean         55.163399                      
-system.ruby.miss_latency_hist::gmean        49.389540                      
-system.ruby.miss_latency_hist::stdev        33.124416                      
-system.ruby.miss_latency_hist            |        1119     81.26%     81.26% |         215     15.61%     96.88% |          29      2.11%     98.98% |           6      0.44%     99.42% |           6      0.44%     99.85% |           2      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::mean         55.177197                      
+system.ruby.miss_latency_hist::gmean        49.553011                      
+system.ruby.miss_latency_hist::stdev        32.253276                      
+system.ruby.miss_latency_hist            |        1122     81.48%     81.48% |         214     15.54%     97.02% |          29      2.11%     99.13% |           4      0.29%     99.42% |           5      0.36%     99.78% |           3      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1377                      
 system.ruby.Directory.incomplete_times           1376                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1377                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8852                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.411034                      
+system.ruby.network.routers0.percent_links_utilized     6.409898                      
 system.ruby.network.routers0.msg_count.Control::2         1377                      
 system.ruby.network.routers0.msg_count.Data::2         1373                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1377                      
@@ -379,7 +380,7 @@ system.ruby.network.routers0.msg_bytes.Control::2        11016
 system.ruby.network.routers0.msg_bytes.Data::2        98856                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers1.percent_links_utilized     6.411034                      
+system.ruby.network.routers1.percent_links_utilized     6.409898                      
 system.ruby.network.routers1.msg_count.Control::2         1377                      
 system.ruby.network.routers1.msg_count.Data::2         1373                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1377                      
@@ -388,7 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2        11016
 system.ruby.network.routers1.msg_bytes.Data::2        98856                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.percent_links_utilized     6.411034                      
+system.ruby.network.routers2.percent_links_utilized     6.409898                      
 system.ruby.network.routers2.msg_count.Control::2         1377                      
 system.ruby.network.routers2.msg_count.Data::2         1373                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1377                      
@@ -405,32 +406,32 @@ system.ruby.network.msg_byte.Control            33048
 system.ruby.network.msg_byte.Data              296568                      
 system.ruby.network.msg_byte.Response_Data       297432                      
 system.ruby.network.msg_byte.Writeback_Control        32952                      
-system.ruby.network.routers0.throttle0.link_utilization     6.418494                      
+system.ruby.network.routers0.throttle0.link_utilization     6.417357                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers0.throttle1.link_utilization     6.403573                      
+system.ruby.network.routers0.throttle1.link_utilization     6.402439                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1377                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1373                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11016                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        98856                      
-system.ruby.network.routers1.throttle0.link_utilization     6.403573                      
+system.ruby.network.routers1.throttle0.link_utilization     6.402439                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1377                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1373                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11016                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        98856                      
-system.ruby.network.routers1.throttle1.link_utilization     6.418494                      
+system.ruby.network.routers1.throttle1.link_utilization     6.417357                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.throttle0.link_utilization     6.418494                      
+system.ruby.network.routers2.throttle0.link_utilization     6.417357                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.throttle1.link_utilization     6.403573                      
+system.ruby.network.routers2.throttle1.link_utilization     6.402439                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1377                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1373                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11016                      
@@ -445,13 +446,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket            9                       #
 system.ruby.delayVCHist.vnet_2::samples          1373                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2           |        1373    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::total            1373                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist::bucket_size           32                      
-system.ruby.LD.latency_hist::max_bucket           319                      
+system.ruby.LD.latency_hist::bucket_size           64                      
+system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1045                      
-system.ruby.LD.latency_hist::mean           24.819139                      
-system.ruby.LD.latency_hist::gmean          10.890845                      
-system.ruby.LD.latency_hist::stdev          28.082269                      
-system.ruby.LD.latency_hist              |         546     52.25%     52.25% |         414     39.62%     91.87% |          77      7.37%     99.23% |           1      0.10%     99.33% |           2      0.19%     99.52% |           4      0.38%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::mean           24.565550                      
+system.ruby.LD.latency_hist::gmean          10.818925                      
+system.ruby.LD.latency_hist::stdev          28.664875                      
+system.ruby.LD.latency_hist              |         965     92.34%     92.34% |          74      7.08%     99.43% |           4      0.38%     99.81% |           1      0.10%     99.90% |           0      0.00%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1045                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
@@ -460,21 +461,21 @@ system.ruby.LD.hit_latency_hist::mean               3
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
 system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         546    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist::total            546                      
-system.ruby.LD.miss_latency_hist::bucket_size           32                      
-system.ruby.LD.miss_latency_hist::max_bucket          319                      
+system.ruby.LD.miss_latency_hist::bucket_size           64                      
+system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          499                      
-system.ruby.LD.miss_latency_hist::mean      48.693387                      
-system.ruby.LD.miss_latency_hist::gmean     44.641812                      
-system.ruby.LD.miss_latency_hist::stdev     23.667547                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |         414     82.97%     82.97% |          77     15.43%     98.40% |           1      0.20%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean      48.162325                      
+system.ruby.LD.miss_latency_hist::gmean     44.026667                      
+system.ruby.LD.miss_latency_hist::stdev     25.587548                      
+system.ruby.LD.miss_latency_hist         |         419     83.97%     83.97% |          74     14.83%     98.80% |           4      0.80%     99.60% |           1      0.20%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           499                      
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              935                      
-system.ruby.ST.latency_hist::mean           16.765775                      
-system.ruby.ST.latency_hist::gmean           6.381495                      
-system.ruby.ST.latency_hist::stdev          28.609452                      
-system.ruby.ST.latency_hist              |         895     95.72%     95.72% |          35      3.74%     99.47% |           1      0.11%     99.57% |           2      0.21%     99.79% |           1      0.11%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::mean           16.914439                      
+system.ruby.ST.latency_hist::gmean           6.394076                      
+system.ruby.ST.latency_hist::stdev          28.735394                      
+system.ruby.ST.latency_hist              |         895     95.72%     95.72% |          33      3.53%     99.25% |           3      0.32%     99.57% |           2      0.21%     99.79% |           1      0.11%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                935                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
@@ -486,18 +487,18 @@ system.ruby.ST.hit_latency_hist::total            681
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          254                      
-system.ruby.ST.miss_latency_hist::mean      53.673228                      
-system.ruby.ST.miss_latency_hist::gmean     48.282634                      
-system.ruby.ST.miss_latency_hist::stdev     33.823763                      
-system.ruby.ST.miss_latency_hist         |         214     84.25%     84.25% |          35     13.78%     98.03% |           1      0.39%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::mean      54.220472                      
+system.ruby.ST.miss_latency_hist::gmean     48.633946                      
+system.ruby.ST.miss_latency_hist::stdev     33.614512                      
+system.ruby.ST.miss_latency_hist         |         214     84.25%     84.25% |          33     12.99%     97.24% |           3      1.18%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           254                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6864                      
-system.ruby.IFETCH.latency_hist::mean        8.263112                      
-system.ruby.IFETCH.latency_hist::gmean       3.900453                      
-system.ruby.IFETCH.latency_hist::stdev      20.209679                      
-system.ruby.IFETCH.latency_hist          |        6731     98.06%     98.06% |         102      1.49%     99.55% |          22      0.32%     99.87% |           3      0.04%     99.91% |           5      0.07%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::mean        8.284237                      
+system.ruby.IFETCH.latency_hist::gmean       3.905930                      
+system.ruby.IFETCH.latency_hist::stdev      19.803554                      
+system.ruby.IFETCH.latency_hist          |        6729     98.03%     98.03% |         107      1.56%     99.59% |          22      0.32%     99.91% |           1      0.01%     99.93% |           4      0.06%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6864                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
@@ -509,10 +510,10 @@ system.ruby.IFETCH.hit_latency_hist::total         6241
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          623                      
-system.ruby.IFETCH.miss_latency_hist::mean    60.987159                      
-system.ruby.IFETCH.miss_latency_hist::gmean    54.083593                      
-system.ruby.IFETCH.miss_latency_hist::stdev    38.003932                      
-system.ruby.IFETCH.miss_latency_hist     |         490     78.65%     78.65% |         102     16.37%     95.02% |          22      3.53%     98.56% |           3      0.48%     99.04% |           5      0.80%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::mean    61.219904                      
+system.ruby.IFETCH.miss_latency_hist::gmean    54.926300                      
+system.ruby.IFETCH.miss_latency_hist::stdev    35.218812                      
+system.ruby.IFETCH.miss_latency_hist     |         488     78.33%     78.33% |         107     17.17%     95.51% |          22      3.53%     99.04% |           1      0.16%     99.20% |           4      0.64%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          623                      
 system.ruby.RMW_Read.latency_hist::bucket_size            4                      
 system.ruby.RMW_Read.latency_hist::max_bucket           39                      
@@ -540,10 +541,10 @@ system.ruby.RMW_Read.miss_latency_hist::total            1
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1377                      
-system.ruby.Directory.miss_mach_latency_hist::mean    55.163399                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    49.389540                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    33.124416                      
-system.ruby.Directory.miss_mach_latency_hist |        1119     81.26%     81.26% |         215     15.61%     96.88% |          29      2.11%     98.98% |           6      0.44%     99.42% |           6      0.44%     99.85% |           2      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::mean    55.177197                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    49.553011                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    32.253276                      
+system.ruby.Directory.miss_mach_latency_hist |        1122     81.48%     81.48% |         214     15.54%     97.02% |          29      2.11%     99.13% |           4      0.29%     99.42% |           5      0.36%     99.78% |           3      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1377                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -571,29 +572,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    7
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev          nan                      
 system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            1                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          499                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    48.693387                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    44.641812                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    23.667547                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         414     82.97%     82.97% |          77     15.43%     98.40% |           1      0.20%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    48.162325                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    44.026667                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    25.587548                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |         419     83.97%     83.97% |          74     14.83%     98.80% |           4      0.80%     99.60% |           1      0.20%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total          499                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          254                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    53.673228                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    48.282634                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    33.823763                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |         214     84.25%     84.25% |          35     13.78%     98.03% |           1      0.39%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    54.220472                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    48.633946                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    33.614512                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |         214     84.25%     84.25% |          33     12.99%     97.24% |           3      1.18%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist::total          254                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          623                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    60.987159                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    54.083593                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    38.003932                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         490     78.65%     78.65% |         102     16.37%     95.02% |          22      3.53%     98.56% |           3      0.48%     99.04% |           5      0.80%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    61.219904                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    54.926300                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    35.218812                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         488     78.33%     78.33% |         107     17.17%     95.51% |          22      3.53%     99.04% |           1      0.16%     99.20% |           4      0.64%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          623                      
 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size            4                      
 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket           39                      
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 5185b356a..ef7ce3c79 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28358500                       # Number of ticks simulated
 final_tick                                   28358500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97635                       # Simulator instruction rate (inst/s)
-host_op_rate                                   176805                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              514168344                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251928                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 304372                       # Simulator instruction rate (inst/s)
+host_op_rate                                   550952                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1601632215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308112                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       9748                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            80.793450                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            80.791087                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1854                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               134                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.835821                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    80.793450                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.019725                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.019725                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    80.791087                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.019724                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.019724                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
@@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          134
 system.cpu.dcache.demand_mshr_misses::total          134                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          134                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2942500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2942500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4226500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4226500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7169000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7169000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7169000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7169000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2970000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2970000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4266000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4266000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7236000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7236000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7236000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7236000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052232                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052232                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084492                       # mshr miss rate for WriteReq accesses
@@ -187,24 +187,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067404
 system.cpu.dcache.demand_mshr_miss_rate::total     0.067404                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067404                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.067404                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           105.544338                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           105.540319                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6636                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               228                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             29.105263                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   105.544338                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.051535                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.051535                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   105.540319                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.051533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.051533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          228                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
@@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          228
 system.cpu.icache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          228                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          228                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12156500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12156500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12156500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12156500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12270500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12270500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12270500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12270500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12270500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12270500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.033217                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.033217                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.033217                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          134.026823                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          134.006917                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.552484                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    28.474338                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.536457                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    28.470460                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003221                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004090                       # Average percentage of cache occupancy
@@ -297,61 +297,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008606                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3257                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3257                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          227                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          282                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           79                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           79                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          227                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          227                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           55                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           55                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           361                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          227                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          361                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11918000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2887500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     14805500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4147500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      4147500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     11918000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     11918000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      2887500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      2887500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     11918000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      7035000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     18953000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     11918000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      7035000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     18953000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          228                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          283                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           79                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           79                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          228                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          228                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           55                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           55                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          228                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          134                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          362                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          228                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          134                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          362                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995614                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.996466                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.995614                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.995614                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995614                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997238                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995614                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997238                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042                       # average overall miss latency
@@ -366,55 +371,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          227                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          282                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          227                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          227                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           55                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           55                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          227                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          361                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          227                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          361                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9193500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2227500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11421000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3199500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3199500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5427000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14620500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9193500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5427000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14620500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.996466                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3357500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3357500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst      9648000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total      9648000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2337500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2337500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9648000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5695000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9648000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5695000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15343000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.995614                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997238                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997238                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            283                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           79                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          228                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           55                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          456                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          268                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               724                       # Packet count per connected master and slave (bytes)
@@ -439,10 +449,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        342000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        201000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 282                       # Transaction distribution
 system.membus.trans_dist::ReadResp                282                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           282                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          722                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total          722                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    722                       # Packet count per connected master and slave (bytes)
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index c8bb95af1..95258693a 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,49 +1,49 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    25499500                       # Number of ticks simulated
-final_tick                                   25499500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    24760000                       # Number of ticks simulated
+final_tick                                   24760000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60058                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60053                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              120151989                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226048                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  82189                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82182                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              159657472                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295960                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                       12744                       # Number of instructions simulated
 sim_ops                                         12744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             40704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             40576                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             22144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        40704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           40704                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                636                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                62720                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        40576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           40576                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                634                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                346                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   982                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1596266593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            868409184                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2464675778                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1596266593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1596266593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1596266593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           868409184                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2464675778                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           982                       # Number of read requests accepted
+system.physmem.num_reads::total                   980                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1638772213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            894345719                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2533117932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1638772213                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1638772213                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1638772213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           894345719                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2533117932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           980                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         982                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         980                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    62848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    62720                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     62848                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     62720                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  86                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 152                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  79                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 155                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  88                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        25359500                       # Total gap between requests
+system.physmem.totGap                        24609000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     982                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     980                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,13 +90,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       342                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       327                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       346                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       324                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          220                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.836364                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     169.810990                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     284.156672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             81     36.82%     36.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           62     28.18%     65.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           22     10.00%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           14      6.36%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           10      4.55%     85.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            7      3.18%     89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            6      2.73%     91.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            6      2.73%     94.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           12      5.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            220                       # Bytes accessed per row activation
-system.physmem.totQLat                       12877000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  31289500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4910000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13113.03                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          211                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      289.971564                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.051447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     289.757171                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             69     32.70%     32.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           60     28.44%     61.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           22     10.43%     71.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           12      5.69%     77.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           14      6.64%     83.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           12      5.69%     89.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      1.42%     91.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            8      3.79%     94.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11      5.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            211                       # Bytes accessed per row activation
+system.physmem.totQLat                       12705250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  31080250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4900000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12964.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31863.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2464.68                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31714.54                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2533.12                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2464.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2533.12                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          19.26                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      19.26                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          19.79                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      19.79                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.46                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.43                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        752                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        761                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.58                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   77.65                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        25824.34                       # Average gap between requests
-system.physmem.pageHitRate                      76.58                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     929880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     507375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   4547400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        25111.22                       # Average gap between requests
+system.physmem.pageHitRate                      77.65                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     861840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     470250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   4539600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16092810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  54750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 23657895                       # Total energy per rank (pJ)
-system.physmem_0.averagePower             1001.657370                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         688500                       # Time in different power states
+system.physmem_0.actBackEnergy               16083405                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  63000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 23543775                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              996.825615                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2652000                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   2878200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15503715                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 591000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 21359100                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              903.085461                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         888000                       # Time in different power states
+system.physmem_1.actBackEnergy               15819210                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 295500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 21605295                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              914.703429                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         407500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21996000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22446250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    7477                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4177                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1616                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5400                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     850                       # Number of BTB hits
+system.cpu.branchPred.lookups                    7026                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3965                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1425                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 5143                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     872                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             15.740741                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                    1012                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 79                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             16.955085                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                    1033                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4911                       # DTB read hits
-system.cpu.dtb.read_misses                        100                       # DTB read misses
+system.cpu.dtb.read_hits                         4832                       # DTB read hits
+system.cpu.dtb.read_misses                         93                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     5011                       # DTB read accesses
-system.cpu.dtb.write_hits                        2106                       # DTB write hits
-system.cpu.dtb.write_misses                        69                       # DTB write misses
+system.cpu.dtb.read_accesses                     4925                       # DTB read accesses
+system.cpu.dtb.write_hits                        2065                       # DTB write hits
+system.cpu.dtb.write_misses                        72                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2175                       # DTB write accesses
-system.cpu.dtb.data_hits                         7017                       # DTB hits
-system.cpu.dtb.data_misses                        169                       # DTB misses
+system.cpu.dtb.write_accesses                    2137                       # DTB write accesses
+system.cpu.dtb.data_hits                         6897                       # DTB hits
+system.cpu.dtb.data_misses                        165                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     7186                       # DTB accesses
-system.cpu.itb.fetch_hits                        5467                       # ITB hits
-system.cpu.itb.fetch_misses                        60                       # ITB misses
+system.cpu.dtb.data_accesses                     7062                       # DTB accesses
+system.cpu.itb.fetch_hits                        5266                       # ITB hits
+system.cpu.itb.fetch_misses                        59                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5527                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5325                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -294,318 +294,318 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            51000                       # number of cpu cycles simulated
+system.cpu.numCycles                            49521                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               1416                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          41297                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        7477                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1862                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         10878                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1697                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  471                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5467                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   803                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              27699                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.490920                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.868697                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               1262                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          39496                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        7026                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1905                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         11647                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1505                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  695                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      5266                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   809                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              28518                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.384950                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.783550                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    20832     75.21%     75.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      522      1.88%     77.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      376      1.36%     78.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      569      2.05%     80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      524      1.89%     82.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      456      1.65%     84.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      499      1.80%     85.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      422      1.52%     87.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     3499     12.63%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    21883     76.73%     76.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      531      1.86%     78.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      405      1.42%     80.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      525      1.84%     81.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      527      1.85%     83.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      419      1.47%     85.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      492      1.73%     86.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      463      1.62%     88.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3273     11.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                27699                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.146608                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.809745                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    36892                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 11130                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5276                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   643                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1210                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  704                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   509                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  33151                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   887                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1210                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    37566                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    5376                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1365                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      5257                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  4377                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  30969                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   146                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                    361                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    477                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   3380                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               23374                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 38597                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            38579                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                28518                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.141879                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.797561                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    38016                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 11989                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5115                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   629                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1147                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  585                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   376                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  32323                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   785                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1147                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    38621                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    5295                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1200                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      5143                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  5490                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  30197                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    57                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                    302                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    566                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   4493                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               22785                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 37650                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            37632                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    14234                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 57                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             43                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2267                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2994                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1466                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                45                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               23                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 2948                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1410                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    13645                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 56                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             44                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      2153                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2897                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1434                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                31                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               21                       # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads                 2813                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      27629                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     22900                       # Number of instructions issued
+system.cpu.iq.iqInstsAdded                      26855                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     22315                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued               102                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           14934                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         8231                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         27699                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.826745                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.538980                       # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined           14161                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         7975                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             17                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         28518                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.782488                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.503369                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               19213     69.36%     69.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                2603      9.40%     78.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1960      7.08%     85.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1418      5.12%     90.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1237      4.47%     95.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 696      2.51%     97.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 372      1.34%     99.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 137      0.49%     99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  63      0.23%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               20180     70.76%     70.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2624      9.20%     79.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1911      6.70%     86.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1348      4.73%     91.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1241      4.35%     95.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 673      2.36%     98.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 344      1.21%     99.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 144      0.50%     99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  53      0.19%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           27699                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           28518                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      27      8.23%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    211     64.33%     72.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    90     27.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      33      9.65%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    224     65.50%     75.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    85     24.85%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7493     65.81%     65.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2715     23.85%     89.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1173     10.30%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7386     65.50%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2741     24.31%     89.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1144     10.15%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  11386                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  11276                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7630     66.27%     66.28% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.29% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.29% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2714     23.57%     89.88% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1165     10.12%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7337     66.46%     66.48% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.49% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.49% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.51% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2570     23.28%     89.79% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1127     10.21%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  11514                       # Type of FU issued
-system.cpu.iq.FU_type::total                    22900      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.449020                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                      160                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                      168                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  328                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.006987                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.007336                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.014323                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              73887                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             42626                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        20089                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total                  11039                       # Type of FU issued
+system.cpu.iq.FU_type::total                    22315      0.00%      0.00% # Type of FU issued
+system.cpu.iq.rate                           0.450617                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                      168                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                      174                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  342                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.007529                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.007797                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.015326                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              73550                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             41081                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19615                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  23202                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22631                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               64                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               87                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1811                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1714                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          601                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           18                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          569                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           281                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               75                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           342                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               63                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1765                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           20                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          545                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1630                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           18                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          500                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           256                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           278                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1210                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    3002                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   780                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               27815                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               312                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  5942                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2876                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     29                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   747                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1147                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    2841                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   538                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               27054                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               353                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5710                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2799                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     37                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   505                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             36                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            144                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1217                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1361                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 21491                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2518                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2502                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           5020                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1409                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            142                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1136                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1278                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 21041                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2537                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2397                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4934                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1274                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                         69                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         67                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    136                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3616                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3607                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  7223                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1734                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1745                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3479                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1098                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1105                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2203                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.421392                       # Inst execution rate
-system.cpu.iew.wb_sent::0                       10180                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                       10330                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   20510                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9974                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                      10135                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  20109                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   5251                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   5302                       # num instructions producing a value
-system.cpu.iew.wb_producers::total              10553                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   7044                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   7008                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              14052                       # num instructions consuming a value
+system.cpu.iew.exec_nop::0                         74                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         74                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    148                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3628                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3464                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  7092                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1676                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1656                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3332                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1091                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1067                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2158                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.424890                       # Inst execution rate
+system.cpu.iew.wb_sent::0                       10100                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9901                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   20001                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9896                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9739                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19635                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   5244                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   5132                       # num instructions producing a value
+system.cpu.iew.wb_producers::total              10376                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6970                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6831                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              13801                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.195569                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.198725                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.394294                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.745457                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.756564                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.750996                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.199834                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.196664                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.396498                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.752367                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.751281                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.751830                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           15019                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           14269                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1130                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        27612                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.462770                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.343029                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1068                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        28453                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.449091                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.311891                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        22639     81.99%     81.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2318      8.39%     90.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1067      3.86%     94.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          382      1.38%     95.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          325      1.18%     96.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          202      0.73%     97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          208      0.75%     98.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7          146      0.53%     98.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          325      1.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23365     82.12%     82.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2421      8.51%     90.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1102      3.87%     94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          384      1.35%     95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          323      1.14%     96.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          209      0.73%     97.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          206      0.72%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7          116      0.41%     98.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          327      1.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        27612                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        28453                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
 system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12778                       # Number of instructions committed
@@ -707,25 +707,25 @@ system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_1::total              6389                       # Class of committed instruction
 system.cpu.commit.op_class::total               12778      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events                   325                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                       130940                       # The number of ROB reads
-system.cpu.rob.rob_writes                       58397                       # The number of ROB writes
-system.cpu.timesIdled                             389                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           23301                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   327                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                       131668                       # The number of ROB reads
+system.cpu.rob.rob_writes                       56750                       # The number of ROB writes
+system.cpu.timesIdled                             392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           21003                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
 system.cpu.committedInsts::total                12744                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::total                  12744                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0                            8.003766                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            8.003766                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.001883                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.124941                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.124941                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.249882                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    26966                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   15368                       # number of integer regfile writes
+system.cpu.cpi::0                            7.771657                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            7.771657                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.885829                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.128673                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.128673                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.257345                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    26413                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14990                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
@@ -733,289 +733,294 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           213.719872                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                5036                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           213.559941                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4863                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.554913                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.054913                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   213.719872                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052178                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052178                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   213.559941                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.052139                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.052139                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.084473                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             12454                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            12454                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         4006                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            4006                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1030                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1030                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          5036                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             5036                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         5036                       # number of overall hits
-system.cpu.dcache.overall_hits::total            5036                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          318                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           318                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          700                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          700                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1018                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1018                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1018                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1018                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     26557000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     26557000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     48843926                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     48843926                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     75400926                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     75400926                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     75400926                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     75400926                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         4324                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         4324                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses             12116                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            12116                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3840                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3840                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1023                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1023                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4863                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4863                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4863                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4863                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          707                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          707                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1022                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1022                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1022                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1022                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24108500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24108500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     53981926                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     53981926                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     78090426                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     78090426                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     78090426                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     78090426                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         4155                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         4155                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         6054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         6054                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         6054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         6054                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.073543                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.073543                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.404624                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.404624                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.168153                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.168153                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.168153                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.168153                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74067.707269                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74067.707269                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5713                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5885                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5885                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5885                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5885                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075812                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.075812                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.408671                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.408671                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173662                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173662                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173662                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173662                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76534.920635                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76534.920635                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76353.502122                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76353.502122                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76409.418787                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76409.418787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76409.418787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76409.418787                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6161                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               130                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               133                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.946154                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.323308                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          116                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          116                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          556                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          556                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          672                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          672                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          144                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          144                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          114                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          114                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          562                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          562                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          676                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          676                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          676                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          676                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          201                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          201                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          145                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total          346                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          346                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18304750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     18304750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     11840493                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     11840493                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30145243                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     30145243                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30145243                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     30145243                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046716                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046716                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057152                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057152                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057152                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.057152                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17596000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17596000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12625989                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     12625989                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30221989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     30221989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30221989                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     30221989                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048375                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048375                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058794                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.058794                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058794                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.058794                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87542.288557                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87542.288557                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87075.786207                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87075.786207                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87346.789017                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 87346.789017                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87346.789017                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 87346.789017                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements::0              8                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            8                       # number of replacements
-system.cpu.icache.tags.tagsinuse           322.759154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4537                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.111285                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           319.520873                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4318                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               636                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.789308                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   322.759154                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.157597                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.157597                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          630                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          243                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.307617                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11558                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11558                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4537                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4537                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4537                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4537                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4537                       # number of overall hits
-system.cpu.icache.overall_hits::total            4537                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          923                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           923                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          923                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            923                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          923                       # number of overall misses
-system.cpu.icache.overall_misses::total           923                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     70921745                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     70921745                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     70921745                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     70921745                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     70921745                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     70921745                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5460                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5460                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5460                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5460                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.169048                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.169048                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.169048                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.169048                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.169048                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.169048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76838.293608                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76838.293608                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         3978                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   319.520873                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.156016                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.156016                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          628                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.306641                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11148                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11148                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4318                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4318                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4318                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4318                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4318                       # number of overall hits
+system.cpu.icache.overall_hits::total            4318                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          938                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           938                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          938                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            938                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          938                       # number of overall misses
+system.cpu.icache.overall_misses::total           938                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     69872996                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     69872996                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     69872996                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     69872996                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     69872996                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     69872996                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5256                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5256                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5256                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5256                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.178463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.178463                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.178463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.178463                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.178463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.178463                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74491.466951                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74491.466951                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74491.466951                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74491.466951                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74491.466951                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74491.466951                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3812                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                87                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                79                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    45.724138                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    48.253165                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          285                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          285                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          285                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          285                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          285                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          638                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          638                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51664496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     51664496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51664496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     51664496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51664496                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     51664496                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116850                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116850                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116850                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80978.833856                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 80978.833856                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 80978.833856                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          302                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          302                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          302                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          302                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          302                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          302                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          636                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          636                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          636                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          636                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          636                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          636                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51565998                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     51565998                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51565998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     51565998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51565998                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     51565998                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.121005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.121005                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.121005                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81078.613208                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 81078.613208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 81078.613208                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          444.038251                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              838                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002387                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          440.180388                       # Cycle average of tags in use
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+system.cpu.l2cache.tags.sampled_refs              835                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.011976                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   323.497640                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   120.540612                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009872                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003679                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.013551                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          838                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          301                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          537                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025574                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8854                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8854                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   320.217581                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   119.962806                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009772                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024          835                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025482                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8900                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8900                       # Number of data accesses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          636                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     51000750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     18093750                       # number of ReadReq miss cycles
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-system.cpu.l2cache.demand_accesses::total          984                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data          346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          984                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996865                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997619                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996865                       # miss rate for demand accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997967                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80189.858491                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89573.019802                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81197.916667                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80189.858491                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86087.427746                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82267.820774                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80189.858491                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86087.427746                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82267.820774                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997963                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85527.586207                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85527.586207                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79787.066246                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79787.066246                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85997.512438                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85997.512438                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79787.066246                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85800.578035                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81910.204082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79787.066246                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85800.578035                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81910.204082                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1024,101 +1029,107 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          636                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          982                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_miss_latency::total     68514000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996865                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997619                       # mshr miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996865                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997967                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030                       # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000                       # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997963                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75527.586207                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75527.586207                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69787.066246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75997.512438                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75997.512438                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75800.578035                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71910.204082                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75800.578035                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71910.204082                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq          144                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp          144                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1276                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp           837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict            8                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq          145                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp          145                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          636                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          201                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1280                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1968                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1972                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              62976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              62848                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          984                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          990                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                984    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                990    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            984                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         492000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1076750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        574250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 838                       # Transaction distribution
-system.membus.trans_dist::ReadResp                838                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               144                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              144                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   62848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total            990                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         495000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        954000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        519000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp                835                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               145                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              145                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           835                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1960                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1960                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   62720                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               982                       # Request fanout histogram
+system.membus.snoop_fanout::samples               980                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     982    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     980    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 982                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             1219500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 980                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             1192500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               4.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            5224000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            5223750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index eba0d2782..85270cbb1 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    27482500                       # Number of ticks simulated
-final_tick                                   27482500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    27401500                       # Number of ticks simulated
+final_tick                                   27401500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  15220                       # Simulator instruction rate (inst/s)
-host_op_rate                                    15220                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               28973949                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223564                       # Number of bytes of host memory used
-host_seconds                                     0.95                       # Real time elapsed on the host
+host_inst_rate                                  94035                       # Simulator instruction rate (inst/s)
+host_op_rate                                    94027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              178462571                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293360                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           22016                       # Nu
 system.physmem.num_reads::cpu.inst                344                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                148                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   492                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            801091604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            344655690                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1145747294                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       801091604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          801091604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           801091604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           344655690                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1145747294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            803459665                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            345674507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1149134171                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       803459665                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          803459665                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           803459665                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           345674507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1149134171                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           492                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         492                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        27431000                       # Total gap between requests
+system.physmem.totGap                        27350000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       131                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -187,72 +187,71 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           71                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      404.732394                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     270.110571                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.824701                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             13     18.31%     18.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     25.35%     43.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      405.633803                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     274.142926                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     337.087748                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     16.90%     16.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     26.76%     43.66% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            9     12.68%     56.34% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511            7      9.86%     66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7      9.86%     76.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.41%     77.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            8     11.27%     77.46% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895            4      5.63%     83.10% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023            2      2.82%     85.92% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     14.08%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             71                       # Bytes accessed per row activation
-system.physmem.totQLat                        3613750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12838750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3217000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12442000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2460000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7345.02                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6538.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26095.02                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1145.75                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25288.62                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1149.13                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1145.75                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1149.13                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           8.95                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.95                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           8.98                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       8.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.53                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        412                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.74                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        55754.07                       # Average gap between requests
+system.physmem.avgGap                        55589.43                       # Average gap between requests
 system.physmem.pageHitRate                      83.74                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     302400                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     165000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2059200                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                   2067000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               15743115                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 361500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20156895                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              853.427679                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         520250                       # Time in different power states
+system.physmem_0.actBackEnergy               15796980                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 314250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 20171310                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              854.037999                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         440750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22332250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        22411750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     226800                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     123750                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                   1318200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15564420                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 518250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 19277100                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              816.177825                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        2637000                       # Time in different power states
+system.physmem_1.actBackEnergy               15639660                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 452250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 19286340                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              816.569039                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        2456000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        22058500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22168500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    8538                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              5461                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1059                       # Number of conditional branches incorrect
+system.cpu.branchPred.lookups                    8543                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              5466                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1058                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups                 5976                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                    3053                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
@@ -261,232 +260,232 @@ system.cpu.branchPred.usedRAS                     609                       # Nu
 system.cpu.branchPred.RASInCorrect                166                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            54966                       # number of cpu cycles simulated
+system.cpu.numCycles                            54804                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              14246                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          40057                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        8538                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles              14234                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          40091                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        8543                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               3662                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         15957                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                         15933                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    2311                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1048                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          1045                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      6438                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   569                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              32422                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.235488                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.378208                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      6440                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   572                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              32383                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.238026                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.380017                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    20898     64.46%     64.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     5494     16.95%     81.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      685      2.11%     83.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      505      1.56%     85.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      819      2.53%     87.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      909      2.80%     90.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      334      1.03%     91.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      371      1.14%     92.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2407      7.42%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    20844     64.37%     64.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     5506     17.00%     81.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      683      2.11%     83.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      516      1.59%     85.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      807      2.49%     87.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      911      2.81%     90.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      334      1.03%     91.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      372      1.15%     92.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2410      7.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                32422                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.155332                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.728760                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11347                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 12433                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      6847                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   640                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                32383                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.155883                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.731534                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11354                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 12386                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      6823                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   665                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                   1155                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  30502                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  30509                       # Number of instructions handled by decode
 system.cpu.rename.SquashCycles                   1155                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11955                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1146                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9859                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      6898                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1409                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  27684                       # Number of instructions processed by rename
+system.cpu.rename.IdleCycles                    11949                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1145                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9839                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      6913                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1382                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  27687                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   1012                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents                    986                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands               25054                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 51692                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            42838                       # Number of integer rename lookups
+system.cpu.rename.RenameLookups                 51693                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            42839                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
 system.cpu.rename.UndoneMaps                    11235                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                767                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            786                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      3842                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3673                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2348                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.serializingInsts                766                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            785                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      3795                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3676                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2349                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      23655                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      23661                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 726                       # Number of non-speculative instructions added to the IQ
 system.cpu.iq.iqInstsIssued                     21924                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            9945                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         6501                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            9951                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         6530                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            251                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         32422                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.676208                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.425800                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         32383                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.677022                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.427893                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               24009     74.05%     74.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3087      9.52%     83.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1572      4.85%     88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1483      4.57%     93.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 954      2.94%     95.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 709      2.19%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 413      1.27%     99.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 155      0.48%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               23977     74.04%     74.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3084      9.52%     83.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1575      4.86%     88.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1484      4.58%     93.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 922      2.85%     95.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 733      2.26%     98.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 411      1.27%     99.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 157      0.48%     99.88% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  40      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           32422                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           32383                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     111     49.33%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     49.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     49     21.78%     71.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    65     28.89%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     111     49.55%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     49.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     49     21.88%     71.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    64     28.57%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 16300     74.35%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3501     15.97%     90.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2123      9.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 16295     74.32%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3505     15.99%     90.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2124      9.69%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                  21924                       # Type of FU issued
-system.cpu.iq.rate                           0.398865                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         225                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010263                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              76549                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             34352                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        20244                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.rate                           0.400044                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010217                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              76509                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             34365                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        20239                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  22149                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22148                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               34                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1448                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1451                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           26                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          900                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          901                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                   1155                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1147                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     7                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               25507                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               203                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3673                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2348                       # Number of dispatched store instructions
+system.cpu.iew.iewBlockCycles                    1144                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     9                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               25514                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               200                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3676                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2349                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                726                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     2                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             26                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            259                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          935                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            260                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          934                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                 1194                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20914                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3347                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1010                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                 20912                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3349                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1012                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1126                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5371                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4427                       # Number of branches executed
+system.cpu.iew.exec_nop                          1127                       # number of nop insts executed
+system.cpu.iew.exec_refs                         5373                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4424                       # Number of branches executed
 system.cpu.iew.exec_stores                       2024                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.380490                       # Inst execution rate
-system.cpu.iew.wb_sent                          20501                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         20244                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9848                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     12670                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.381578                       # Inst execution rate
+system.cpu.iew.wb_sent                          20497                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         20239                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9852                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     12795                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.368300                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.777269                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.369298                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.769988                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           10287                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10294                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1059                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        30361                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.499391                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.308685                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1058                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        30320                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.500066                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.312560                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23816     78.44%     78.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3429     11.29%     89.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1193      3.93%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          637      2.10%     95.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          331      1.09%     96.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          224      0.74%     97.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          397      1.31%     98.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           62      0.20%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          272      0.90%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23779     78.43%     78.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3460     11.41%     89.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1176      3.88%     93.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          592      1.95%     95.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          324      1.07%     96.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          261      0.86%     97.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          394      1.30%     98.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           63      0.21%     99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          271      0.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        30361                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        30320                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -532,36 +531,36 @@ system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   272                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        54715                       # The number of ROB reads
-system.cpu.rob.rob_writes                       52974                       # The number of ROB writes
+system.cpu.commit.bw_lim_events                   271                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        54682                       # The number of ROB reads
+system.cpu.rob.rob_writes                       52990                       # The number of ROB writes
 system.cpu.timesIdled                             200                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           22544                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           22421                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               3.807564                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.807564                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.262635                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.262635                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    33408                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   18606                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    7133                       # number of misc regfile reads
+system.cpu.cpi                               3.796342                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.796342                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.263411                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.263411                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    33404                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   18604                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    7136                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            98.556611                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            98.713941                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                4125                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             28.061224                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    98.556611                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024062                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024062                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    98.713941                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024100                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024100                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              9489                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             9489                       # Number of data accesses
+system.cpu.dcache.tags.tag_accesses              9491                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             9491                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         3086                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            3086                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
@@ -572,64 +571,64 @@ system.cpu.dcache.demand_hits::cpu.data          4119                       # nu
 system.cpu.dcache.demand_hits::total             4119                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data         4119                       # number of overall hits
 system.cpu.dcache.overall_hits::total            4119                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          137                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           137                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          138                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           138                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          546                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            546                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          546                       # number of overall misses
-system.cpu.dcache.overall_misses::total           546                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9397000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9397000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     27538481                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     27538481                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36935481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36935481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36935481                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36935481                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3223                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3223                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          547                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            547                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          547                       # number of overall misses
+system.cpu.dcache.overall_misses::total           547                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9332000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9332000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     27213977                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     27213977                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     36545977                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     36545977                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     36545977                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     36545977                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3224                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3224                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4665                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4665                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4665                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4665                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.042507                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.042507                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         4666                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4666                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4666                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4666                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.042804                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.042804                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117042                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117042                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117042                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67647.401099                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67647.401099                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1052                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.117231                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117231                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117231                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117231                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67623.188406                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67623.188406                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66537.841076                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66537.841076                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66811.658135                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66811.658135                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66811.658135                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66811.658135                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1080                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    47.818182                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    41.538462                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           72                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           73                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          398                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          398                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          398                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          398                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          399                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          399                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          399                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          399                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
@@ -638,199 +637,204 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          148
 system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5143250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5143250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6389250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6389250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11532500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11532500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11532500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11532500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020168                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020168                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5162500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5162500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6419500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6419500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11582000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11582000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11582000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11582000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020161                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020161                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031726                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.031726                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031726                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031726                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031719                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031719                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79423.076923                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79423.076923                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77343.373494                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77343.373494                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78256.756757                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78256.756757                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78256.756757                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78256.756757                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           190.975563                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                5904                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           191.519539                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5908                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.063584                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.075145                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   190.975563                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.093250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.093250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   191.519539                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.093515                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.168945                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             13222                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            13222                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         5904                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5904                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5904                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5904                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5904                       # number of overall hits
-system.cpu.icache.overall_hits::total            5904                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          534                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           534                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          534                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            534                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          534                       # number of overall misses
-system.cpu.icache.overall_misses::total           534                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     37367000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     37367000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     37367000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     37367000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     37367000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     37367000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6438                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6438                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6438                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6438                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6438                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6438                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082945                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.082945                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.082945                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::cpu.inst     0.082945                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.082945                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69975.655431                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69975.655431                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs           57                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses             13226                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            13226                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         5908                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5908                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total           532                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     36225500                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst         6440                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082609                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::cpu.inst     0.082609                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::cpu.inst     0.082609                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.082609                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68093.045113                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68093.045113                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68093.045113                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68093.045113                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68093.045113                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68093.045113                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          188                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          188                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          188                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          188                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          188                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          188                       # number of overall MSHR hits
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 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          346                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          346                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          346                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          346                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          346                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          346                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26526250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26526250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26526250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26526250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26526250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26526250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.053743                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.053743                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.053743                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.053743                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.053743                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.053743                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26213500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26213500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26213500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total     26213500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.053727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.053727                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.053727                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75761.560694                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75761.560694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75761.560694                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          224.896195                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          225.494304                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              408                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.004902                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   190.368376                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    34.527819                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005810                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006863                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   190.884921                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    34.609384                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005825                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001056                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006882                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012451                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4443                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4443                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           65                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          409                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          344                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          344                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           65                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           65                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          148                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           492                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          148                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          492                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26158750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5078750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31237500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6304750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6304750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     26158750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11383500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     37542250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     26158750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11383500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     37542250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          346                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           65                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          411                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6293500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6293500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25673000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25673000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5066000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5066000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25673000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11359500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     37032500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25673000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11359500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     37032500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          346                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          346                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           65                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           65                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          346                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          148                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          494                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          346                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          148                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          494                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994220                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.995134                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994220                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994220                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994220                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.995951                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994220                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995951                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75825.301205                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75825.301205                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74630.813953                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74630.813953                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77938.461538                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77938.461538                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74630.813953                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76753.378378                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75269.308943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74630.813953                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76753.378378                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75269.308943                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -839,55 +843,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          344                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          409                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          344                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          344                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           65                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           65                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          492                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          492                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     21861250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4272750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     26134000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5278250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5278250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     21861250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9551000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     31412250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     21861250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9551000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     31412250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995134                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5463500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5463500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22233000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22233000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4426000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4426000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22233000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32122500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22233000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9889500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32122500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.995951                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65825.301205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65825.301205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64630.813953                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68092.307692                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68092.307692                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66820.945946                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65289.634146                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66820.945946                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65289.634146                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            411                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           410                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          346                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           65                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          295                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               987                       # Packet count per connected master and slave (bytes)
@@ -908,14 +917,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            494                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         247000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        587750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        245000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 409                       # Transaction distribution
+system.cpu.toL2Bus.respLayer0.occupancy        519000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                408                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           409                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          983                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    983                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31424                       # Cumulative packet size per connected master and slave (bytes)
@@ -931,9 +940,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 492                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              608000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              593500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2599750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2604000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              9.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 56b893c5d..625747903 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000041                       # Nu
 sim_ticks                                    41368500                       # Number of ticks simulated
 final_tick                                   41368500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 311873                       # Simulator instruction rate (inst/s)
-host_op_rate                                   311783                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              850451247                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289340                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 372083                       # Simulator instruction rate (inst/s)
+host_op_rate                                   371955                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1014555487                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290028                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                      15207                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            97.991492                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            97.989824                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                3535                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             25.615942                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    97.991492                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.023924                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.023924                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    97.989824                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.023923                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.023923                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
@@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2835500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2835500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4547500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4547500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7383000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7383000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7383000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7383000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2862000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2862000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4590000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4590000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7452000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7452000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
@@ -188,24 +188,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633
 system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           153.777491                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           153.774107                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs               14928                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               280                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             53.314286                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   153.777491                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.075087                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.075087                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   153.774107                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.075085                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.075085                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          280                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
@@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          280
 system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14896500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14896500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14896500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14896500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15036500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15036500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15036500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15036500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15036500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15036500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.018411                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.018411                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.018411                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          184.625818                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          184.609803                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   153.105687                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.520131                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   153.092235                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.517568                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004672                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005634                       # Average percentage of cache occupancy
@@ -298,61 +298,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          275
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010101                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          331                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           53                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           53                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           416                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          416                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14595500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2782500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17378000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4462500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      4462500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     14595500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     14595500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      2782500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      2782500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     14595500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      7245000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     21840500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     14595500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      7245000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     21840500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          280                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          333                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          280                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          280                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           53                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           53                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.993994                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.992857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992857                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.995215                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992857                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995215                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923                       # average overall miss latency
@@ -367,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          331                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           53                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           53                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          416                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          416                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11259000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2146500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13405500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3442500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3442500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11259000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5589000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16848000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11259000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5589000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16848000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993994                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3612500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3612500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     11815500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     11815500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2252500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2252500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11815500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17680500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11815500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5865000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17680500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.992857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.995215                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            333                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           333                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           85                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          280                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           53                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          560                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               836                       # Packet count per connected master and slave (bytes)
@@ -440,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        420000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        207000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 331                       # Transaction distribution
 system.membus.trans_dist::ReadResp                331                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               85                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           331                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          832                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    832                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index fd1fa8729..bc3ca9120 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.147041                       # Number of seconds simulated
-sim_ticks                                147041219500                       # Number of ticks simulated
-final_tick                               147041219500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                147041221500                       # Number of ticks simulated
+final_tick                               147041221500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 770569                       # Simulator instruction rate (inst/s)
-host_op_rate                                   774399                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1250931150                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 437476                       # Number of bytes of host memory used
-host_seconds                                   117.55                       # Real time elapsed on the host
+host_inst_rate                                1077194                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1082547                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1748701394                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 444972                       # Number of bytes of host memory used
+host_seconds                                    84.09                       # Real time elapsed on the host
 sim_insts                                    90576862                       # Number of instructions simulated
 sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,7 +147,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        294082439                       # number of cpu cycles simulated
+system.cpu.numCycles                        294082443                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90576862                       # Number of instructions committed
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs                      27220755                       # nu
 system.cpu.num_load_insts                    22475911                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               294082438.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               294082442.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          18732305                       # Number of branches fetched
@@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   91054081                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            942702                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3565.593917                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3565.593910                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       54410415000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593917                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle       54410415500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593910                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.870506                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.870506                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       946795
 system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10361087000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10361087000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1147270000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1147270000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       118500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       118500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11508357000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11508357000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11508475500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11508475500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10811180000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10811180000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1170574500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1170574500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       120000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       120000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11981754500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11981754500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11981874500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11981874500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
@@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.940168                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.940168                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        39500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        39500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.067359                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.067359                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.154003                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.154003                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        40000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        40000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 2                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.120567                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           510.120565                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           107830173                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               599                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          180016.983306                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.120567                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.120565                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.249082                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.249082                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
@@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst          599                       # n
 system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
 system.cpu.icache.overall_misses::total           599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     32032000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     32032000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     32032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     32032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     32032000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     32032000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32034000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32034000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32034000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32034000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32034000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32034000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    107830772                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    107830772                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    107830772                       # number of demand (read+write) accesses
@@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000006
 system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53475.792988                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53475.792988                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53475.792988                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53475.792988                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53475.792988                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53475.792988                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53479.131886                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53479.131886                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          599
 system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31133500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     31133500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     31133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31133500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     31133500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31435000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     31435000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31435000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     31435000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31435000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     31435000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51975.792988                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51975.792988                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51975.792988                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51975.792988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51975.792988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51975.792988                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9567.852356                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1827177                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         9567.852238                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1827433                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15323                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           119.244078                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           119.260784                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8879.446284                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   494.172984                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   194.233089                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  8879.446176                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   494.172976                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   194.233086                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.270979                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015081                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.005928                       # Average percentage of cache occupancy
@@ -451,78 +451,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          105
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1468                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15179780                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15179780                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       899974                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         899996                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         15181828                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15181828                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks       942334                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       942334                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           22                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           22                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       899974                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       899974                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       932035                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          932057                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       932035                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         932057                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          577                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          215                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          792                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          577                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          577                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          215                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          215                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          577                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14763                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total         15340                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          577                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14763                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15340                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30303500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     11289500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     41593000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    764020500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    764020500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     30303500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     30304500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     30304500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     11289500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     11289500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30304500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data    775310000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    805613500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     30303500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total    805614500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30304500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    775310000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    805613500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::total    805614500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks       942334                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       942334                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          599                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          599                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::total       900189                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.963272                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000239                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000879                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.963272                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.963272                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000239                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000239                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963272                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015593                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.016192                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963272                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016192                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.064125                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.302326                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.064125                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52520.797227                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52520.797227                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52509.302326                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52509.302326                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520.797227                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.103570                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.064125                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52517.242503                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520.797227                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.103570                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52517.242503                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -531,84 +537,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          577                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          215                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          792                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          577                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          577                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          215                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          215                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          577                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14763                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total        15340                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          577                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14763                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15340                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23368500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8707500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     32076000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    589194000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    589194000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23368500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    597901500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    621270000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23368500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    597901500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    621270000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000239                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000879                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    618540500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    618540500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     24534500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     24534500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      9139500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      9139500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24534500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    627680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    652214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24534500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    627680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    652214500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.963272                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000239                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000239                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015593                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016192                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016192                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42517.218862                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42517.218862                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42520.797227                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42520.797227                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42509.302326                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42509.302326                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42520.797227                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42517.103570                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42517.242503                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       942334                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          256                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46609                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46609                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1198                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2835930                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2837128                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          599                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       900189                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1199                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2836185                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2837384                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        38336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          120942784                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1889731                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1890101                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1889731    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1890101    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1889731                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1887199500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1890101                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1887384500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        898500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1420197000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
 system.membus.trans_dist::ReadResp                792                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           792                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        30680                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  30680                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
@@ -624,9 +636,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15340                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15603500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            15604500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           76963500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           76964500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index ebb41442e..37bdd5ca5 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,79 +1,73 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000108                       # Number of seconds simulated
-sim_ticks                                   107944000                       # Number of ticks simulated
-final_tick                                  107944000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   107900000                       # Number of ticks simulated
+final_tick                                  107900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128828                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128828                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               13989470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239356                       # Number of bytes of host memory used
-host_seconds                                     7.72                       # Real time elapsed on the host
-sim_insts                                      994048                       # Number of instructions simulated
-sim_ops                                        994048                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 161691                       # Simulator instruction rate (inst/s)
+host_op_rate                                   161690                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               17527940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308804                       # Number of bytes of host memory used
+host_seconds                                     6.16                       # Real time elapsed on the host
+sim_insts                                      995346                       # Number of instructions simulated
+sim_ops                                        995346                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            23168                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             5120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst             5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              576                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                42816                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                42944                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        23168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         5120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           29056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst         5440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           29184                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               362                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                80                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 9                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   669                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           214629808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           100200104                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            47432002                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            11858000                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             4150300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7707700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             2964500                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7707700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               396650115                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      214629808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       47432002                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        4150300                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        2964500                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          269176610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          214629808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          100200104                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           47432002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           11858000                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            4150300                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7707700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            2964500                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7707700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              396650115                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           670                       # Number of read requests accepted
+system.physmem.num_reads::total                   671                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           214717331                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           100240964                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            50417053                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11862836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7710843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             5338276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7710843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               397998146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      214717331                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       50417053                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        5338276                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          270472660                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          214717331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          100240964                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           50417053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11862836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7710843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            5338276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7710843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              397998146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           672                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         670                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         672                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    42880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    43008                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     42880                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     43008                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             76                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 115                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             75                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  27                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  66                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
@@ -105,14 +99,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       107916000                       # Total gap between requests
+system.physmem.totGap                       107872000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     670                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     672                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -120,11 +114,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       188                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -216,319 +210,319 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          148                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.702703                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.430987                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     234.776821                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             43     29.05%     29.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           39     26.35%     55.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           25     16.89%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           19     12.84%     85.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6      4.05%     89.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            6      4.05%     93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      3.38%     96.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      1.35%     97.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            3      2.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            148                       # Bytes accessed per row activation
-system.physmem.totQLat                        6539750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  19102250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      3350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9760.82                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          149                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      269.744966                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.953250                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     233.682770                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             43     28.86%     28.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           40     26.85%     55.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           25     16.78%     72.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           17     11.41%     83.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            8      5.37%     89.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            7      4.70%     93.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      2.68%     96.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.34%     97.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            3      2.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            149                       # Bytes accessed per row activation
+system.physmem.totQLat                        7242000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  19842000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      3360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10776.79                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28510.82                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         397.24                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29526.79                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         398.59                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      397.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      398.59                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.10                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.10                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.11                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.39                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.38                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        511                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        512                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.27                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.19                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161068.66                       # Average gap between requests
-system.physmem.pageHitRate                      76.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2761200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                       160523.81                       # Average gap between requests
+system.physmem.pageHitRate                      76.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     710640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     387750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2776800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               39247065                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy               26461500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 76167750                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              750.559832                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE       46478250                       # Time in different power states
+system.physmem_0.actBackEnergy               34825860                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               30339750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 75652080                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              745.478401                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE       52910500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        54316750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        47852500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     385560                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     210375                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                   2067000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               30855240                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               33814500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 73943955                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              728.745214                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE       59727000                       # Time in different power states
+system.physmem_1.actBackEnergy               31297275                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               33426750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 73998240                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              729.280213                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE       59054500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        42022000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        42666000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups                  81450                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            78581                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1205                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               78182                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  75500                       # Number of BTB hits
+system.cpu0.branchPred.lookups                  81516                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            78639                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect             1206                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups               78220                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  75547                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            96.569543                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                    747                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.BTBHitPct            96.582715                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                    751                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          215889                       # number of cpu cycles simulated
+system.cpu0.numCycles                          215801                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             20419                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        481443                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      81450                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             76247                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       165590                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   2709                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.icacheStallCycles             19984                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        481810                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      81516                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             76298                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       165347                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   2711                       # Number of cycles fetch has spent squashing
 system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         2214                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     7225                       # Number of cache lines fetched
+system.cpu0.fetch.PendingTrapStallCycles         2206                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     7238                       # Number of cache lines fetched
 system.cpu0.fetch.IcacheSquashes                  649                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            189580                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.539524                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.227640                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples            188895                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.550676                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.226315                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   32064     16.91%     16.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   77818     41.05%     57.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     818      0.43%     58.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1146      0.60%     59.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     623      0.33%     59.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   72992     38.50%     97.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     703      0.37%     98.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     447      0.24%     98.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2969      1.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   31263     16.55%     16.55% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   77878     41.23%     57.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     817      0.43%     58.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1146      0.61%     58.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     622      0.33%     59.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   73043     38.67%     97.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     702      0.37%     98.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     447      0.24%     98.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2977      1.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              189580                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.377277                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.230049                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   15778                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                19697                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   152079                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  672                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  1354                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                469796                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  1354                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   16409                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   2266                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         15970                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   152076                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                 1505                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                466337                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                    21                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents                  1001                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             319451                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               929999                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          702902                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               305355                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   14096                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               900                       # count of serializing insts renamed
+system.cpu0.fetch.rateDist::total              188895                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.377737                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.232659                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   15795                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                18848                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   152228                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  669                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  1355                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                470263                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  1355                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   16424                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2157                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         15249                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   152226                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                 1484                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                466822                       # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents                    20                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                     9                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents                   991                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands             319803                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               930944                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          703631                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               305659                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   14144                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               901                       # count of serializing insts renamed
 system.cpu0.rename.tempSerializingInsts           908                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     4587                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              148758                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              75265                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            72519                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           72258                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    390345                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.skidInsts                     4515                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              148895                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              75333                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            72583                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           72320                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    390748                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqNonSpecInstsAdded                967                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   386997                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued               24                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          13187                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        11208                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqInstsIssued                   387435                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued               23                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          13210                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11146                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved           408                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       189580                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.041339                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.140292                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples       188895                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.051060                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.134423                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              35140     18.54%     18.54% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4258      2.25%     20.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              73622     38.83%     59.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              73334     38.68%     98.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1646      0.87%     99.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                901      0.48%     99.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                423      0.22%     99.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                182      0.10%     99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 74      0.04%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              34285     18.15%     18.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4265      2.26%     20.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              73704     39.02%     59.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              73391     38.85%     98.28% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1671      0.88%     99.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                904      0.48%     99.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                416      0.22%     99.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                183      0.10%     99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 76      0.04%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         189580                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         188895                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     91     32.73%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     32.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    84     30.22%     62.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  103     37.05%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     90     32.14%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     32.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    85     30.36%     62.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  105     37.50%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               164205     42.43%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              148197     38.29%     80.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              74595     19.28%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               164414     42.44%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              148348     38.29%     80.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              74673     19.27%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                386997                       # Type of FU issued
-system.cpu0.iq.rate                          1.792574                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        278                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000718                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads            963876                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           404550                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       385100                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                387435                       # Type of FU issued
+system.cpu0.iq.rate                          1.795335                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        280                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000723                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            964068                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           404976                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       385522                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                387275                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                387715                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           71895                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           71972                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2491                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2476                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread0.memOrderViolation           53                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1625                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores         1617                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu0.iew.lsq.thread0.cacheBlocked            9                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  1354                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   2232                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   35                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             464248                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              186                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               148758                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               75265                       # Number of dispatched store instructions
+system.cpu0.iew.iewSquashCycles                  1355                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   2123                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   37                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             464714                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              184                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               148895                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               75333                       # Number of dispatched store instructions
 system.cpu0.iew.iewDispNonSpecInsts               846                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents            53                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           333                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1104                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1437                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               385946                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               147890                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1051                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.predictedTakenIncorrect           331                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1113                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1444                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               386358                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               148024                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1077                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        72936                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      222349                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   76534                       # Number of branches executed
-system.cpu0.iew.exec_stores                     74459                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.787706                       # Inst execution rate
-system.cpu0.iew.wb_sent                        385475                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       385100                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   228400                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   231722                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        72999                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      222560                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   76623                       # Number of branches executed
+system.cpu0.iew.exec_stores                     74536                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.790344                       # Inst execution rate
+system.cpu0.iew.wb_sent                        385902                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       385522                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   228646                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   231982                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.783787                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.985664                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.786470                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.985620                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts          13801                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts          13812                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1205                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       186928                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.409398                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.152220                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1206                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       186239                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.420760                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.150366                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        35407     18.94%     18.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        75555     40.42%     59.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         1920      1.03%     60.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          633      0.34%     60.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          494      0.26%     60.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        71651     38.33%     99.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          511      0.27%     99.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          263      0.14%     99.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          494      0.26%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        34563     18.56%     18.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        75593     40.59%     59.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         1959      1.05%     60.20% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          634      0.34%     60.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          503      0.27%     60.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        71729     38.51%     99.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          522      0.28%     99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          250      0.13%     99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       186928                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              450384                       # Number of instructions committed
-system.cpu0.commit.committedOps                450384                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       186239                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              450840                       # Number of instructions committed
+system.cpu0.commit.committedOps                450840                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        219907                       # Number of memory references committed
-system.cpu0.commit.loads                       146267                       # Number of loads committed
+system.cpu0.commit.refs                        220135                       # Number of memory references committed
+system.cpu0.commit.loads                       146419                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     75527                       # Number of branches committed
+system.cpu0.commit.branches                     75603                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   303686                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   303990                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        72259     16.04%     16.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          158134     35.11%     51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass        72335     16.04%     16.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          158286     35.11%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.15% # Class of committed instruction
@@ -557,625 +551,625 @@ system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.15%
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         146351     32.49%     83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         73640     16.35%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         146503     32.50%     83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         73716     16.35%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           450384                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events                  494                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                      649458                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     931043                       # The number of ROB writes
+system.cpu0.commit.op_class_0::total           450840                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events                  486                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                      649244                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     931981                       # The number of ROB writes
 system.cpu0.timesIdled                            314                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          26309                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     378041                       # Number of Instructions Simulated
-system.cpu0.committedOps                       378041                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.571073                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.571073                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.751090                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.751090                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  690199                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 311415                       # number of integer regfile writes
+system.cpu0.idleCycles                          26906                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     378421                       # Number of Instructions Simulated
+system.cpu0.committedOps                       378421                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.570267                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.570267                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.753565                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.753565                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  690917                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 311762                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 224240                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 224455                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          140.939988                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             148370                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          141.011743                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             148491                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              171                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           867.660819                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           868.368421                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   140.939988                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275273                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.275273                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.011743                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275414                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.275414                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.330078                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           598524                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          598524                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        75399                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          75399                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        73059                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         73059                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           599051                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          599051                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        75429                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          75429                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        73130                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         73130                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       148458                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          148458                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       148458                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         148458                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          514                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          514                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          539                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          539                       # number of WriteReq misses
+system.cpu0.dcache.demand_hits::cpu0.data       148559                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          148559                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       148559                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         148559                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          540                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          540                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          544                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          544                       # number of WriteReq misses
 system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
 system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1053                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1053                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1053                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1053                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17626915                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     17626915                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     36442515                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     36442515                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       680000                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       680000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     54069430                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     54069430                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     54069430                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     54069430                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        75913                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        75913                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        73598                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        73598                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_misses::cpu0.data         1084                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1084                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1084                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1084                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16932500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     16932500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35823993                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     35823993                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       460000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       460000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     52756493                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     52756493                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     52756493                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     52756493                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        75969                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        75969                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        73674                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        73674                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       149511                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       149511                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       149511                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       149511                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006771                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.006771                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007324                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007324                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data       149643                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       149643                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       149643                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       149643                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007108                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.007108                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007384                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007384                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007043                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.007043                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007043                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.007043                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1036                       # number of cycles access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007244                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.007244                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007244                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.007244                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1048                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               13                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               16                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    79.692308                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          330                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          330                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          362                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          362                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          692                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          692                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          692                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          692                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          184                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          184                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          177                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          177                       # number of WriteReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          369                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          369                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          726                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          726                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          726                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          726                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          361                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          361                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          361                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          361                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6770753                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6770753                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8530978                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8530978                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       646500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       646500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15301731                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     15301731                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15301731                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     15301731                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002424                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002424                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002405                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002405                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          358                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          358                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          358                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          358                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6813000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6813000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8643000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8643000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       439000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       439000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     15456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15456000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     15456000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002409                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002409                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002375                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002375                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002415                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002415                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002415                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002415                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002392                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002392                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002392                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002392                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              323                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          240.188663                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               6428                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          240.334366                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               6439                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              614                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.469055                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.486971                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   240.188663                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.469118                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.469118                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   240.334366                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.469403                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.469403                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.568359                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             7839                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            7839                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         6428                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           6428                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         6428                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            6428                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         6428                       # number of overall hits
-system.cpu0.icache.overall_hits::total           6428                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          797                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          797                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          797                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           797                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          797                       # number of overall misses
-system.cpu0.icache.overall_misses::total          797                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40514746                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     40514746                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     40514746                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     40514746                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     40514746                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     40514746                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         7225                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         7225                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         7225                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         7225                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         7225                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         7225                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110311                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.110311                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110311                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.110311                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110311                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.110311                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 50834.060226                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 50834.060226                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses             7852                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            7852                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst         6439                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           6439                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         6439                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            6439                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         6439                       # number of overall hits
+system.cpu0.icache.overall_hits::total           6439                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          799                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          799                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          799                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           799                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          799                       # number of overall misses
+system.cpu0.icache.overall_misses::total          799                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40829000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     40829000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     40829000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     40829000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     40829000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     40829000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         7238                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         7238                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         7238                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         7238                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         7238                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         7238                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110390                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.110390                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110390                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.110390                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110390                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.110390                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51100.125156                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51100.125156                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            2                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          182                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          182                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          182                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          182                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          182                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          182                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          184                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          184                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          184                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          184                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          184                       # number of overall MSHR hits
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          615                       # number of ReadReq MSHR misses
 system.cpu0.icache.ReadReq_mshr_misses::total          615                       # number of ReadReq MSHR misses
 system.cpu0.icache.demand_mshr_misses::cpu0.inst          615                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.demand_mshr_misses::total          615                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          615                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          615                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31043001                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     31043001                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31043001                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     31043001                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31043001                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     31043001                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.085121                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085121                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.085121                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.085121                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.085121                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.085121                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31621000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     31621000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31621000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     31621000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31621000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     31621000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084968                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.084968                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.084968                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  52261                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            48386                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1341                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               44394                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  43169                       # Number of BTB hits
+system.cpu1.branchPred.lookups                  53963                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            50167                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             1346                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               46229                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  44971                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            97.240618                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    906                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct            97.278764                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                    927                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          162232                       # number of cpu cycles simulated
+system.cpu1.numCycles                          162372                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             31153                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        288417                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      52261                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             44075                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       122623                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   2833                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.icacheStallCycles             29926                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        299894                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      53963                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             45898                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       123960                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   2845                       # Number of cycles fetch has spent squashing
 system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles         1159                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    21623                       # Number of cache lines fetched
+system.cpu1.fetch.PendingTrapStallCycles         1155                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines                    20576                       # Number of cache lines fetched
 system.cpu1.fetch.IcacheSquashes                  472                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            156364                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.844523                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.218152                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::samples            156476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.916550                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.231802                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   56063     35.85%     35.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   50599     32.36%     68.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    6236      3.99%     72.20% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3531      2.26%     74.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     937      0.60%     75.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   32564     20.83%     95.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1222      0.78%     96.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     843      0.54%     97.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    4369      2.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   52995     33.87%     33.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   51987     33.22%     67.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    5834      3.73%     70.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3448      2.20%     73.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     958      0.61%     73.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   34873     22.29%     95.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1256      0.80%     96.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     838      0.54%     97.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    4287      2.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              156364                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.322137                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.777806                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   18077                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                54814                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    78767                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 3280                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  1416                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                271927                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  1416                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   18807                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  25020                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         13667                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    79411                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                18033                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                268621                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                 15397                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                    31                       # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total              156476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.332342                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.846956                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   18007                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                50929                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    83026                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 3082                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1422                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                283749                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1422                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   18719                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  22929                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13387                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    84356                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                15653                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                280426                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                 13898                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands             189765                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               514915                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          401460                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               175087                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   14678                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1212                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1278                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    22640                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               74986                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              35614                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            35483                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           30428                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    223482                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               6146                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   225009                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               16                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          13593                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        10743                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           680                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       156364                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.439008                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.385420                       # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands             198372                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               540599                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          420692                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               183271                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   15101                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1203                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1280                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    20103                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               79058                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              37890                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            37399                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           32713                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    233810                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               5671                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   234514                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued               46                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          14000                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        11968                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           653                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       156476                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.498722                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.383815                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              59519     38.06%     38.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              20894     13.36%     51.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              35016     22.39%     73.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              34585     22.12%     95.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3417      2.19%     98.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1600      1.02%     99.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                882      0.56%     99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                240      0.15%     99.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                211      0.13%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              56669     36.22%     36.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              19562     12.50%     48.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              37085     23.70%     72.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              36801     23.52%     95.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3420      2.19%     98.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1602      1.02%     99.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                884      0.56%     99.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                239      0.15%     99.86% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                214      0.14%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         156364                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         156476                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     92     27.88%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    29      8.79%     36.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  209     63.33%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     87     24.58%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     24.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    58     16.38%     40.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  209     59.04%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               110922     49.30%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               79078     35.14%     84.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              35009     15.56%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               114757     48.93%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               82569     35.21%     84.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              37188     15.86%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                225009                       # Type of FU issued
-system.cpu1.iq.rate                          1.386958                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        330                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001467                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            606728                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           243255                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       223369                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                234514                       # Type of FU issued
+system.cpu1.iq.rate                          1.444301                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        354                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001510                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            625904                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           253521                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       232777                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                225339                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                234868                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           30296                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           32465                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2626                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2830                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           34                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1552                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1669                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  1416                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   7338                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   47                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             266019                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              165                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                74986                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               35614                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1143                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    24                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  1422                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   6958                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             277649                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              222                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                79058                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               37890                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1130                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            34                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           453                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         1125                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1578                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               223948                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                74035                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1061                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           481                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1587                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               233397                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                77941                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1117                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        36391                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      108940                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   45914                       # Number of branches executed
-system.cpu1.iew.exec_stores                     34905                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.380418                       # Inst execution rate
-system.cpu1.iew.wb_sent                        223649                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       223369                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   126652                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   133295                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        38168                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      115010                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   47577                       # Number of branches executed
+system.cpu1.iew.exec_stores                     37069                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.437421                       # Inst execution rate
+system.cpu1.iew.wb_sent                        233106                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       232777                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   132706                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   139339                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.376849                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.950163                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.433603                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.952397                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts          14380                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           5466                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1341                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       153714                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.636819                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.057713                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts          14853                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5018                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1346                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       153761                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.708866                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.078798                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        64759     42.13%     42.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        42554     27.68%     69.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5173      3.37%     73.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         6281      4.09%     77.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1529      0.99%     78.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        30355     19.75%     98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          785      0.51%     98.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          966      0.63%     99.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8         1312      0.85%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        61362     39.91%     39.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        44235     28.77%     68.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5219      3.39%     72.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         5854      3.81%     75.88% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1519      0.99%     76.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        32513     21.15%     98.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          819      0.53%     98.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          953      0.62%     99.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8         1287      0.84%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       153714                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              251602                       # Number of instructions committed
-system.cpu1.commit.committedOps                251602                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       153761                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              262757                       # Number of instructions committed
+system.cpu1.commit.committedOps                262757                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        106422                       # Number of memory references committed
-system.cpu1.commit.loads                        72360                       # Number of loads committed
-system.cpu1.commit.membars                       4751                       # Number of memory barriers committed
-system.cpu1.commit.branches                     44778                       # Number of branches committed
+system.cpu1.commit.refs                        112449                       # Number of memory references committed
+system.cpu1.commit.loads                        76228                       # Number of loads committed
+system.cpu1.commit.membars                       4303                       # Number of memory barriers committed
+system.cpu1.commit.branches                     46487                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   173320                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   181057                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        35567     14.14%     14.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          104862     41.68%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead          77111     30.65%     86.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         34062     13.54%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass        37276     14.19%     14.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          108729     41.38%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead          80531     30.65%     86.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         36221     13.78%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           251602                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                 1312                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                      417798                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     534614                       # The number of ROB writes
+system.cpu1.commit.op_class_0::total           262757                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events                 1287                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                      429498                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     557934                       # The number of ROB writes
 system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           5868                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       46290                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     211284                       # Number of Instructions Simulated
-system.cpu1.committedOps                       211284                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.767839                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.767839                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.302357                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.302357                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  386957                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 181537                       # number of integer regfile writes
+system.cpu1.idleCycles                           5896                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       46085                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     221178                       # Number of Instructions Simulated
+system.cpu1.committedOps                       221178                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.734124                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.734124                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.362168                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.362168                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  405088                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 189742                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 110600                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 116634                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           25.579817                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              40184                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           25.592984                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              42361                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1435.142857                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1512.892857                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.579817                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.049961                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.049961                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.592984                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.049986                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.049986                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           311400                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          311400                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        43257                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          43257                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        33840                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         33840                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        77097                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           77097                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        77097                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          77097                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          466                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          466                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          153                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          153                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          619                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           619                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          619                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          619                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      9865731                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      9865731                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3999011                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3999011                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       673507                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       673507                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     13864742                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     13864742                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     13864742                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     13864742                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        43723                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        43723                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        33993                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        33993                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.tags.tag_accesses           326938                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          326938                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        44990                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          44990                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        35982                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         35982                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        80972                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           80972                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        80972                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          80972                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          461                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          461                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          170                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          170                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          631                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           631                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          631                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          631                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8707500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      8707500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      4222000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      4222000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       652500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       652500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     12929500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     12929500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     12929500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     12929500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        45451                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        45451                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        36152                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        36152                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.SwapReq_accesses::cpu1.data           69                       # number of SwapReq accesses(hits+misses)
 system.cpu1.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        77716                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        77716                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        77716                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        77716                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.010658                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.010658                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004501                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004501                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.826087                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.826087                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007965                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.007965                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007965                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.007965                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::cpu1.data        81603                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        81603                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        81603                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        81603                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.010143                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.010143                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004702                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.004702                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.811594                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007733                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.007733                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007733                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.007733                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1184,106 +1178,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          299                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          299                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           45                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           45                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          344                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          344                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          344                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          344                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          167                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          303                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          303                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           62                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           62                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          365                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          365                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          365                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          365                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           57                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          275                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          275                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          275                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1943270                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1943270                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1707489                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1707489                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       587993                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       587993                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3650759                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3650759                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3650759                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3650759                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003820                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003820                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003177                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003177                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.826087                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.826087                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273                       # average overall mshr miss latency
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1924500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1924500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1959500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1959500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       596500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       596500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3884000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3884000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3884000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3884000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003476                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003476                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002987                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002987                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003260                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003260                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003260                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003260                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              385                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           83.683741                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              21045                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              497                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            42.344064                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           85.488179                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              19990                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              500                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.980000                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    83.683741                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.163445                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.163445                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          112                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    85.488179                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.166969                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.166969                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          115                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.218750                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            22120                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           22120                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        21045                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          21045                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        21045                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           21045                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        21045                       # number of overall hits
-system.cpu1.icache.overall_hits::total          21045                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          578                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          578                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          578                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           578                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          578                       # number of overall misses
-system.cpu1.icache.overall_misses::total          578                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14251747                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     14251747                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     14251747                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     14251747                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     14251747                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     14251747                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        21623                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        21623                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        21623                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        21623                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        21623                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        21623                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.026731                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.026731                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.026731                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.026731                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.026731                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.026731                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 24657.001730                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 24657.001730                       # average overall miss latency
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.224609                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses            21076                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           21076                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        19990                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          19990                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        19990                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           19990                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        19990                       # number of overall hits
+system.cpu1.icache.overall_hits::total          19990                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          586                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          586                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          586                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           586                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          586                       # number of overall misses
+system.cpu1.icache.overall_misses::total          586                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14253000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     14253000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     14253000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     14253000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     14253000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     14253000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        20576                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        20576                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        20576                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        20576                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        20576                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        20576                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028480                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.028480                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028480                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.028480                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028480                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.028480                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24322.525597                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24322.525597                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs          114                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
@@ -1292,410 +1286,410 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs           57
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           81                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           81                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           81                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           81                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          497                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          497                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          497                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          497                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          497                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          497                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11245503                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     11245503                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11245503                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     11245503                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11245503                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     11245503                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022985                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022985                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022985                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.022985                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022985                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.022985                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           86                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           86                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           86                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          500                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          500                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          500                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          500                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          500                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          500                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11778500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     11778500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11778500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     11778500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11778500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     11778500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024300                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024300                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024300                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst        23557                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total        23557                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst        23557                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total        23557                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst        23557                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total        23557                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  51309                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            47950                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1280                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               43975                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  43053                       # Number of BTB hits
+system.cpu2.branchPred.lookups                  40179                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            36730                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             1284                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               32851                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  31814                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.903354                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                    886                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct            96.843323                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                    891                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          161860                       # number of cpu cycles simulated
+system.cpu2.numCycles                          162000                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             31583                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        282068                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      51309                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             43939                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       125716                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   2717                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles             38502                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        208114                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      40179                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             32705                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       119095                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   2725                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1207                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    22884                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  412                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            159877                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.764281                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.167875                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles         1151                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    29772                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  430                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            160123                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.299713                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            1.967894                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   59518     37.23%     37.23% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   51095     31.96%     69.19% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    7306      4.57%     73.76% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3438      2.15%     75.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     997      0.62%     76.53% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   31616     19.78%     96.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1254      0.78%     97.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     769      0.48%     97.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3884      2.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   78817     49.22%     49.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   43234     27.00%     76.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                   10666      6.66%     82.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3447      2.15%     85.04% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                    1063      0.66%     85.70% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   17019     10.63%     96.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1193      0.75%     97.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     770      0.48%     97.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3914      2.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              159877                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.316996                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.742667                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   17468                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                61085                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    76240                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 3716                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  1358                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                267722                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  1358                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   18170                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  29188                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         12834                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    77782                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                20535                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                264399                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                 18336                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                    25                       # Number of times rename has blocked due to LQ full
+system.cpu2.fetch.rateDist::total              160123                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.248019                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.284654                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   17927                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                88037                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    47537                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5250                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  1362                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                193193                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  1362                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   18611                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  44936                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         13295                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    49321                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                32588                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                189743                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                 29082                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                    12                       # Number of times rename has blocked due to LQ full
 system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands             185298                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               503121                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          392507                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               170476                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   14822                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1180                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1243                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    25168                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               73362                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              34382                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            35300                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           29228                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    218628                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               6983                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   220497                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               53                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          13773                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        12313                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           622                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       159877                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.379166                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.379581                       # Number of insts issued each cycle
+system.cpu2.rename.RenamedOperands             129905                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               340650                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          270570                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               115581                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   14324                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1221                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1285                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    37412                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               47453                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              19802                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            23979                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           14667                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    152040                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded              10334                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   157175                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          13577                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        11994                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           781                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       160123                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.981589                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.305622                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              63376     39.64%     39.64% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              23374     14.62%     54.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              33553     20.99%     75.25% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              33206     20.77%     96.02% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3423      2.14%     98.16% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1623      1.02%     99.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                877      0.55%     99.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                230      0.14%     99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                215      0.13%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              83163     51.94%     51.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              32837     20.51%     72.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              19129     11.95%     84.39% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              18742     11.70%     96.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3350      2.09%     98.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1588      0.99%     99.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                888      0.55%     99.73% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                222      0.14%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                204      0.13%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         159877                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         160123                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     86     23.69%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     23.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    68     18.73%     42.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     85     23.42%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     23.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    69     19.01%     42.42% # attempts to use FU when none available
 system.cpu2.iq.fu_full::MemWrite                  209     57.58%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               108751     49.32%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               78120     35.43%     84.75% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              33626     15.25%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu                82729     52.63%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     52.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               55347     35.21%     87.85% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              19099     12.15%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                220497                       # Type of FU issued
-system.cpu2.iq.rate                          1.362270                       # Inst issue rate
+system.cpu2.iq.FU_type_0::total                157175                       # Type of FU issued
+system.cpu2.iq.rate                          0.970216                       # Inst issue rate
 system.cpu2.iq.fu_busy_cnt                        363                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001646                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            601287                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           239427                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       218768                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fu_busy_rate                  0.002310                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            474890                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           175995                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       155491                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                220860                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                157538                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           28926                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           14398                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2863                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2822                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1691                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1616                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  1358                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   8128                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   61                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             261616                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              204                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                73362                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               34382                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1094                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    39                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  1362                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                  11555                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   80                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             187117                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              206                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                47453                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               19802                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1131                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    44                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            43                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           455                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         1045                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1500                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               219377                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                72164                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1120                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            44                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           462                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         1028                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1490                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               156065                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                46210                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1110                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        36005                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      105679                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   45327                       # Number of branches executed
-system.cpu2.iew.exec_stores                     33515                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.355350                       # Inst execution rate
-system.cpu2.iew.wb_sent                        219089                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       218768                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   123331                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   129941                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        24743                       # number of nop insts executed
+system.cpu2.iew.exec_refs                       65197                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   33975                       # Number of branches executed
+system.cpu2.iew.exec_stores                     18987                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.963364                       # Inst execution rate
+system.cpu2.iew.wb_sent                        155796                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       155491                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                    82775                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                    89322                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.351588                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.949131                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.959821                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.926703                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          14642                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           6361                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1280                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       157221                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.570534                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.031430                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts          14525                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           9553                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1284                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       157478                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.095639                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.783689                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        69336     44.10%     44.10% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        41971     26.70%     70.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5151      3.28%     74.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         7156      4.55%     78.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1534      0.98%     79.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        28975     18.43%     98.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          827      0.53%     98.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7          961      0.61%     99.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8         1310      0.83%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        92218     58.56%     58.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        30640     19.46%     78.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         5207      3.31%     81.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3        10311      6.55%     87.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1532      0.97%     88.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        14554      9.24%     98.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          759      0.48%     98.57% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          956      0.61%     99.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8         1301      0.83%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       157221                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              246921                       # Number of instructions committed
-system.cpu2.commit.committedOps                246921                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       157478                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              172539                       # Number of instructions committed
+system.cpu2.commit.committedOps                172539                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        103190                       # Number of memory references committed
-system.cpu2.commit.loads                        70499                       # Number of loads committed
-system.cpu2.commit.membars                       5644                       # Number of memory barriers committed
-system.cpu2.commit.branches                     44296                       # Number of branches committed
+system.cpu2.commit.refs                         62817                       # Number of memory references committed
+system.cpu2.commit.loads                        44631                       # Number of loads committed
+system.cpu2.commit.membars                       8825                       # Number of memory barriers committed
+system.cpu2.commit.branches                     32966                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   169605                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   117894                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        35083     14.21%     14.21% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu          103004     41.72%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          76143     30.84%     86.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         32691     13.24%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass        23742     13.76%     13.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu           77155     44.72%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     58.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          53456     30.98%     89.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         18186     10.54%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           246921                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                 1310                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                      416888                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     525783                       # The number of ROB writes
-system.cpu2.timesIdled                            205                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           1983                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       46662                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     206194                       # Number of Instructions Simulated
-system.cpu2.committedOps                       206194                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.784989                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.784989                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.273903                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.273903                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  376797                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 176595                       # number of integer regfile writes
+system.cpu2.commit.op_class_0::total           172539                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events                 1301                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                      342655                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     376773                       # The number of ROB writes
+system.cpu2.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           1877                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       46457                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     139972                       # Number of Instructions Simulated
+system.cpu2.committedOps                       139972                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.157374                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.157374                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.864025                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.864025                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  255225                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 121437                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 107278                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                  66781                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           24.051885                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              38880                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           23.055357                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              24315                       # Total number of references to valid blocks.
 system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1340.689655                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           838.448276                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    24.051885                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.046976                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.046976                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.055357                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045030                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.045030                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           303893                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          303893                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42781                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42781                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        32487                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         32487                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        75268                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           75268                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        75268                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          75268                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          440                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          440                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          133                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          133                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           57                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          573                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           573                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          573                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          573                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7341783                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      7341783                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2962762                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2962762                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       594005                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       594005                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     10304545                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     10304545                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     10304545                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     10304545                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        43221                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        43221                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        32620                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        32620                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        75841                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        75841                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        75841                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        75841                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010180                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.010180                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004077                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.004077                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.802817                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007555                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.007555                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007555                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.007555                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127                       # average overall miss latency
+system.cpu2.dcache.tags.tag_accesses           200189                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          200189                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        31354                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          31354                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        17953                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         17953                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           17                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        49307                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           49307                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        49307                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          49307                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          441                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          441                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          151                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          151                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           65                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          592                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           592                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          592                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          592                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      6519500                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      6519500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3142000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3142000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       710000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       710000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      9661500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      9661500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      9661500                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      9661500                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        31795                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        31795                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        18104                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        18104                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           82                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           82                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        49899                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        49899                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        49899                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        49899                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.013870                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.013870                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.008341                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.008341                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.792683                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.792683                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.011864                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.011864                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.011864                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.011864                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14783.446712                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 14783.446712                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20807.947020                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 20807.947020                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10923.076923                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 10923.076923                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 16320.101351                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 16320.101351                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1704,106 +1698,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          285                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           31                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          316                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          316                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          316                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          316                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          155                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          102                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          257                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          257                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          257                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1424773                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1424773                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1555988                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1555988                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       508495                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       508495                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2980761                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      2980761                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2980761                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      2980761                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003586                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003586                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003127                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003127                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003389                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003389                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003389                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003389                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9192.083871                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9192.083871                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  8920.964912                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  8920.964912                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          267                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          267                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           54                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           54                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          321                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          321                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          321                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          321                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          174                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data           97                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total           97                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           65                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           65                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1675000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1675000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1750000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1750000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       645000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       645000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3425000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3425000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3425000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3425000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.005473                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.005473                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.005358                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.005358                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.792683                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.792683                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005431                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.005431                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005431                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.005431                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9626.436782                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9626.436782                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18041.237113                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18041.237113                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  9923.076923                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  9923.076923                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12638.376384                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12638.376384                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12638.376384                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12638.376384                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.tags.replacements              384                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           78.035025                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              22324                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              494                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            45.190283                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.replacements              387                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           74.683777                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              29208                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              496                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            58.887097                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    78.035025                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.152412                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.152412                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.683777                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.145867                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.145867                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          109                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            23378                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           23378                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        22324                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          22324                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        22324                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           22324                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        22324                       # number of overall hits
-system.cpu2.icache.overall_hits::total          22324                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          560                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          560                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          560                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           560                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          560                       # number of overall misses
-system.cpu2.icache.overall_misses::total          560                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8454990                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      8454990                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      8454990                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      8454990                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      8454990                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      8454990                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        22884                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        22884                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        22884                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        22884                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        22884                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        22884                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024471                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.024471                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024471                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.024471                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024471                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.024471                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 15098.196429                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 15098.196429                       # average overall miss latency
+system.cpu2.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.212891                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses            30268                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           30268                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst        29208                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          29208                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        29208                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           29208                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        29208                       # number of overall hits
+system.cpu2.icache.overall_hits::total          29208                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          564                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          564                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          564                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           564                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          564                       # number of overall misses
+system.cpu2.icache.overall_misses::total          564                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7822000                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      7822000                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      7822000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      7822000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      7822000                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      7822000                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        29772                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        29772                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        29772                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        29772                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        29772                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        29772                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.018944                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.018944                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.018944                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.018944                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.018944                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.018944                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.794326                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13868.794326                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13868.794326                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 13868.794326                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13868.794326                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 13868.794326                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1812,409 +1806,409 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           66                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           66                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           66                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           66                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          494                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          494                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          494                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          494                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          494                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          494                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6668508                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      6668508                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6668508                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      6668508                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6668508                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      6668508                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021587                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021587                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021587                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.021587                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021587                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.021587                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          496                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          496                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          496                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          496                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          496                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          496                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6709500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      6709500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6709500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      6709500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6709500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      6709500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.016660                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.016660                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.016660                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  49957                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            46526                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1263                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               42773                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  41661                       # Number of BTB hits
+system.cpu3.branchPred.lookups                  59537                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            56113                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             1261                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               52336                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  51268                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            97.400229                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                    886                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct            97.959340                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                    894                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          161075                       # number of cpu cycles simulated
+system.cpu3.numCycles                          161647                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             32422                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        272949                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      49957                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             42547                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       124988                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   2685                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.icacheStallCycles             26901                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        335954                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      59537                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             52162                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       130682                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   2681                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1170                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    23669                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  411                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            159935                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.706625                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.149562                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles         1202                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                    18139                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  423                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            160153                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             2.097707                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.240976                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   61940     38.73%     38.73% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   50129     31.34%     70.07% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    7684      4.80%     74.88% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3433      2.15%     77.02% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                    1026      0.64%     77.66% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   29810     18.64%     96.30% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1265      0.79%     97.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     775      0.48%     97.58% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3873      2.42%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   45773     28.58%     28.58% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   56940     35.55%     64.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    4846      3.03%     67.16% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3496      2.18%     69.34% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                    1060      0.66%     70.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   42180     26.34%     96.34% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1201      0.75%     97.09% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     768      0.48%     97.57% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    3889      2.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              159935                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.310147                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.694546                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   17524                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                64435                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    72722                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 3902                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  1342                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                258692                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  1342                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   18198                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  31170                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         12771                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    73832                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                22612                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                255419                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                 19775                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                    23                       # Number of times rename has blocked due to LQ full
+system.cpu3.fetch.rateDist::total              160153                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.368315                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       2.078319                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   16971                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                42083                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    97172                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 2577                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1340                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                322134                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1340                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   17645                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  17747                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         12855                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    98257                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                12299                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                318864                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                 10783                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
 system.cpu3.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands             178600                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               483471                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          377749                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               164114                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   14486                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1167                       # count of serializing insts renamed
+system.cpu3.rename.RenamedOperands             225541                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               621446                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          481213                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               211532                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   14009                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1171                       # count of serializing insts renamed
 system.cpu3.rename.tempSerializingInsts          1234                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    27248                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               70256                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              32624                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            33902                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           27488                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    210626                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               7365                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   213102                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued               40                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          13428                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        11687                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           617                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       159935                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.332429                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.375890                       # Number of insts issued each cycle
+system.cpu3.rename.skidInsts                    16730                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               92339                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              45060                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            43467                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           39931                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    267326                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               4600                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   267770                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          12807                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        10139                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           551                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       160153                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.671964                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.354316                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              65625     41.03%     41.03% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              24603     15.38%     56.42% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              31869     19.93%     76.34% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              31495     19.69%     96.03% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3384      2.12%     98.15% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1646      1.03%     99.18% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                880      0.55%     99.73% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                234      0.15%     99.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                199      0.12%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              48755     30.44%     30.44% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              16655     10.40%     40.84% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              44376     27.71%     68.55% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              43948     27.44%     95.99% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3484      2.18%     98.17% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1651      1.03%     99.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                861      0.54%     99.74% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                222      0.14%     99.87% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                201      0.13%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         159935                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         160153                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     83     23.71%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     23.71% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    58     16.57%     40.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  209     59.71%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     86     25.67%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.67% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    40     11.94%     37.61% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  209     62.39%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               105687     49.59%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               75490     35.42%     85.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              31925     14.98%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               128178     47.87%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               95149     35.53%     83.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              44443     16.60%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                213102                       # Type of FU issued
-system.cpu3.iq.rate                          1.322999                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        350                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001642                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            586529                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           231462                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       211399                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                267770                       # Type of FU issued
+system.cpu3.iq.rate                          1.656511                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        335                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001251                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            696028                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           284773                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       266078                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                213452                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                268105                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           27230                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           39763                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2740                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2450                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1625                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1547                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  1342                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   8471                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   59                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             252649                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              168                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                70256                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               32624                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1081                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    37                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  1340                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   5357                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   49                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             316296                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              170                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                92339                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               45060                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1094                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            43                       # Number of memory order violations
+system.cpu3.iew.memOrderViolationEvents            40                       # Number of memory order violations
 system.cpu3.iew.predictedTakenIncorrect           466                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         1012                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1478                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               211973                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                69143                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1129                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.predictedNotTakenIncorrect         1001                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1467                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               266621                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                91475                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1149                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        34658                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      100953                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   44015                       # Number of branches executed
-system.cpu3.iew.exec_stores                     31810                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.315989                       # Inst execution rate
-system.cpu3.iew.wb_sent                        211700                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       211399                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   118601                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   125234                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        44370                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      135810                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   53906                       # Number of branches executed
+system.cpu3.iew.exec_stores                     44335                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.649403                       # Inst execution rate
+system.cpu3.iew.wb_sent                        266372                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       266078                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   153535                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   160065                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.312426                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.947035                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.646044                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.959204                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts          14249                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           6748                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1263                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       157342                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.514834                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.009338                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts          13497                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           4049                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1261                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       157643                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.920440                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     2.127029                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        72048     45.79%     45.79% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        40652     25.84%     71.63% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         5170      3.29%     74.91% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         7572      4.81%     79.73% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1532      0.97%     80.70% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        27266     17.33%     98.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          833      0.53%     98.56% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          969      0.62%     99.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8         1300      0.83%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        52663     33.41%     33.41% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        50442     32.00%     65.40% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         5240      3.32%     68.73% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         4903      3.11%     71.84% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1534      0.97%     72.81% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        39716     25.19%     98.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          903      0.57%     98.58% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          957      0.61%     99.18% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8         1285      0.82%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       157342                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              238347                       # Number of instructions committed
-system.cpu3.commit.committedOps                238347                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       157643                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              302744                       # Number of instructions committed
+system.cpu3.commit.committedOps                302744                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                         98515                       # Number of memory references committed
-system.cpu3.commit.loads                        67516                       # Number of loads committed
-system.cpu3.commit.membars                       6034                       # Number of memory barriers committed
-system.cpu3.commit.branches                     42994                       # Number of branches committed
+system.cpu3.commit.refs                        133402                       # Number of memory references committed
+system.cpu3.commit.loads                        89889                       # Number of loads committed
+system.cpu3.commit.membars                       3344                       # Number of memory barriers committed
+system.cpu3.commit.branches                     52826                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   163632                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   208356                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        33784     14.17%     14.17% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu          100014     41.96%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.14% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          73550     30.86%     86.99% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         30999     13.01%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass        43625     14.41%     14.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu          122373     40.42%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          93233     30.80%     85.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         43513     14.37%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           238347                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                 1300                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                      408052                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     507784                       # The number of ROB writes
+system.cpu3.commit.op_class_0::total           302744                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events                 1285                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                      472013                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     634991                       # The number of ROB writes
 system.cpu3.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1140                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       47445                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     198529                       # Number of Instructions Simulated
-system.cpu3.committedOps                       198529                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              0.811342                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.811342                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.232525                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.232525                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  362535                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 170128                       # number of integer regfile writes
+system.cpu3.idleCycles                           1494                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       46809                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     255775                       # Number of Instructions Simulated
+system.cpu3.committedOps                       255775                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              0.631989                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.631989                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.582306                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.582306                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  467282                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 217631                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 102551                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 137439                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           23.026048                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              37058                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           24.171664                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              49547                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1323.500000                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1769.535714                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.026048                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.044973                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.044973                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.171664                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047210                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.047210                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           291822                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          291822                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        41456                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          41456                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        30794                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         30794                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        72250                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           72250                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        72250                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          72250                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          440                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          440                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          137                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          137                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          577                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           577                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          577                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          577                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      7521134                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      7521134                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3020012                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3020012                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       589507                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       589507                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     10541146                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     10541146                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     10541146                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     10541146                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41896                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41896                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        30931                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        30931                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        72827                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        72827                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        72827                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        72827                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010502                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.010502                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004429                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.004429                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.794118                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007923                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.007923                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007923                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.007923                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882                       # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses           381069                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          381069                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        51168                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          51168                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        43290                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         43290                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           10                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        94458                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           94458                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        94458                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          94458                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          527                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          527                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          164                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          164                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           49                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           49                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          691                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           691                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          691                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          691                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8076500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      8076500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3222500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3222500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       607500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       607500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     11299000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     11299000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     11299000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     11299000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        51695                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        51695                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        43454                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        43454                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           59                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           59                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        95149                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        95149                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        95149                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        95149                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010194                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.010194                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003774                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.003774                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830508                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.830508                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007262                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.007262                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007262                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.007262                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2223,385 +2217,389 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          288                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          288                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           34                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          322                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          322                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          322                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          322                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          152                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          103                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          255                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          255                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          255                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1429011                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1429011                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1527238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1527238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       508493                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       508493                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2956249                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2956249                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2956249                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2956249                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003628                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003628                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003330                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003330                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003501                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003501                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003501                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003501                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9401.388158                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9401.388158                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  9416.537037                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  9416.537037                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          382                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          382                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           52                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          434                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          434                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          434                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          434                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          145                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          145                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          112                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          112                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           49                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           49                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          257                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          257                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          257                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1368000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1368000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1719500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1719500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       558500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       558500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3087500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3087500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002805                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002805                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002577                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002577                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830508                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.830508                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002701                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.002701                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002701                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.002701                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9434.482759                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9434.482759                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15352.678571                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15352.678571                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11397.959184                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11397.959184                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12013.618677                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12013.618677                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12013.618677                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12013.618677                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.tags.replacements              387                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           75.442206                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              23109                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.replacements              388                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           77.972544                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              17573                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              498                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            46.403614                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            35.287149                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    75.442206                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.147348                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.147348                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          111                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.972544                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.152290                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.152290                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.216797                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            24167                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           24167                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        23109                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          23109                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        23109                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           23109                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        23109                       # number of overall hits
-system.cpu3.icache.overall_hits::total          23109                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          560                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          560                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          560                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           560                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          560                       # number of overall misses
-system.cpu3.icache.overall_misses::total          560                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7349496                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      7349496                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      7349496                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      7349496                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      7349496                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      7349496                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        23669                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        23669                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        23669                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        23669                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        23669                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        23669                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.023660                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.023660                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.023660                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.023660                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.023660                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.023660                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13124.100000                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13124.100000                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            18637                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           18637                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        17573                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          17573                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        17573                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           17573                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        17573                       # number of overall hits
+system.cpu3.icache.overall_hits::total          17573                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          566                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          566                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          566                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           566                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          566                       # number of overall misses
+system.cpu3.icache.overall_misses::total          566                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7887000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7887000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7887000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7887000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7887000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7887000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        18139                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        18139                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        18139                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        18139                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        18139                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        18139                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.031203                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.031203                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.031203                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.031203                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.031203                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.031203                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13934.628975                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13934.628975                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13934.628975                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13934.628975                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13934.628975                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13934.628975                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs           24                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           62                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           62                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           62                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           62                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           68                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           68                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           68                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.demand_mshr_misses::cpu3.inst          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.demand_mshr_misses::total          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          498                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          498                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6152504                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      6152504                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6152504                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      6152504                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6152504                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      6152504                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021040                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021040                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021040                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.021040                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021040                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.021040                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6839000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      6839000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      6839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6839000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      6839000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.027455                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.027455                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.027455                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13732.931727                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 13732.931727                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  421.791819                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1669                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      536                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.113806                       # Average number of references to valid blocks.
+system.l2c.tags.tagsinuse                  422.903421                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       2336                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      538                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.342007                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.783957                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      289.037601                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       57.982294                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       60.100309                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        5.287110                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        5.207527                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.713016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        2.004391                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.675614                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.784815                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      289.208824                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       58.009977                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       62.701446                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        5.295227                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        0.676960                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        5.511844                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.714328                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.004410                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.004413                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000885                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000917                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000957                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000081                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000079                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000031                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000010                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.006436                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          536                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu2.data       0.000010                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000084                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.006453                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          538                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1024     0.008179                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    20118                       # Number of tag accesses
-system.l2c.tags.data_accesses                   20118                       # Number of data accesses
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 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
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 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.591870                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.176000                       # miss rate for ReadCleanReq accesses
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+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.026104                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.225225                       # miss rate for ReadCleanReq accesses
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 system.l2c.demand_miss_rate::cpu0.inst       0.591870                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu3.inst       0.014056                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.290089                       # miss rate for demand accesses
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 system.l2c.overall_miss_rate::cpu0.inst      0.591870                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
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 system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.014056                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.290089                       # miss rate for overall accesses
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-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85032.442748                       # average ReadExReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2610,222 +2608,216 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
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 system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.160966                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014170                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.242793                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_misses::total             672                       # number of overall MSHR misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       456500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       395500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       290997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       417000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1559997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6987500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      1168500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1055000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       955000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total     10166000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     24396000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5728000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       584500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     30708500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5237000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       481500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data        72500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        86500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total      5877500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     24396000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     12224500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      5728000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data      1650000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data      1127500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       584500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data      1041500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     46752000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     24396000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     12224500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      5728000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data      1650000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data      1127500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       584500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data      1041500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     46752000                       # number of overall MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.962025                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.961538                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.216690                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.724138                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.160966                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014170                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.284985                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.285229                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.160966                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014170                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.284985                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        83750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        67900                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        70000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        67900                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 66276.492537                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        67900                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 66276.492537                       # average overall mshr miss latency
+system.l2c.overall_mshr_miss_rate::total     0.285229                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        20750                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20815.789474                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20785.500000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        20850                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.960000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74335.106383                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89884.615385                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 87916.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 79583.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 77603.053435                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67195.842451                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69826.666667                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 68785.714286                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        72500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        86500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69970.238095                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72334.319527                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        82500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86730.769231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 80115.384615                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69571.428571                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72334.319527                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        82500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69571.428571                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                 539                       # Transaction distribution
-system.membus.trans_dist::ReadResp                538                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              276                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               171                       # Transaction distribution
+system.membus.trans_dist::ReadResp                540                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              281                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              75                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               168                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1731                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1731                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   42816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              240                       # Total snoops (count)
-system.membus.snoop_fanout::samples               986                       # Request fanout histogram
+system.membus.trans_dist::ReadSharedReq           541                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1736                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1736                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   42944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              243                       # Total snoops (count)
+system.membus.snoop_fanout::samples               990                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     986    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     990    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 986                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              941000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 990                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              926003                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3702674                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            3714925                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.4                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq               2762                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2761                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp              2768                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             279                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            279                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              401                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             401                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1229                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::CleanEvict             670                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             284                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            284                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              403                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             403                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          2109                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          660                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1469                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          583                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          375                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          988                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          355                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          996                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          352                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5872                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1144                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          366                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1137                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          375                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1136                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          350                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  6560                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39296                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        31808                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        32000                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        31616                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        31744                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31872                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 150464                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1012                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3443                       # Request fanout histogram
+system.toL2Bus.pkt_size::total                 150784                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1022                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             4941                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -2836,29 +2828,29 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   3443    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   4941    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3443                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            1736971                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              1.6                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy            994999                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               4941                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            2489462                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              2.3                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy            921499                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            532769                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy            506002                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            762997                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy            751497                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            438748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            425967                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            744992                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy            748987                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            415244                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy            449462                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            747996                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy            748992                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            406758                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy            400481                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 833acaaf7..6ed919c46 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1398636                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1398593                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              181097192                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299844                       # Number of bytes of host memory used
-host_seconds                                     0.48                       # Real time elapsed on the host
+host_inst_rate                                1750110                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1750047                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              226603798                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303668                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
 sim_insts                                      677333                       # Number of instructions simulated
 sim_ops                                        677333                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -59,255 +59,7 @@ system.physmem.bw_total::cpu2.data            9486130                       # To
 system.physmem.bw_total::cpu3.inst             729702                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu3.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              407903588                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                 423                       # Transaction distribution
-system.membus.trans_dist::ReadResp                423                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              273                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              80                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               412                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              136                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1747                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1747                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        35776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   35776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              1108                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    1108    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                1108                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  366.582953                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      421                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.897862                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.966439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      239.426226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       55.207589                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       59.512205                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        6.721185                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        1.942787                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.935416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        0.965459                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.905646                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.003653                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000842                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000908                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000103                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000030                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005594                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          373                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.006424                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    15456                       # Number of tag accesses
-system.l2c.tags.data_accesses                   15456                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                355                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              282                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               62                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst                3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                80                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                3                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                1                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  559                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            359                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1643                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              82                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.603854                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.173184                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.700000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.008380                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.002786                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.257456                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.975610                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.008380                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.002786                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.008380                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.002786                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq               2179                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2179                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              412                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             412                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          711                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          716                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          696                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          716                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          618                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          718                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          624                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5733                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        22912                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        22912                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        22976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 165888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             2867                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   2867    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               2867                       # Request fanout histogram
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu0.numCycles                          175415                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
@@ -367,54 +119,6 @@ system.cpu0.op_class::MemWrite                  27806     15.85%    100.00% # Cl
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                    175388                       # Class of executed instruction
-system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          222.772732                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           374.563169                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772732                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           175855                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          175855                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          174921                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       174921                       # number of overall hits
-system.cpu0.icache.overall_hits::total         174921                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          150.745705                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs              81882                       # Total number of references to valid blocks.
@@ -481,6 +185,54 @@ system.cpu0.dcache.cache_copies                     0                       # nu
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements              215                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          222.772732                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           374.563169                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772732                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           175855                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          175855                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          174921                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       174921                       # number of overall hits
+system.cpu0.icache.overall_hits::total         174921                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
+system.cpu0.icache.overall_misses::total          467                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       175388                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       175388                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       175388                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       175388                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       175388                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       175388                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002663                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002663                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002663                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002663                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002663                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002663                       # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          173297                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -539,54 +291,6 @@ system.cpu1.op_class::MemWrite                  10149      6.06%    100.00% # Cl
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                    167432                       # Class of executed instruction
-system.cpu1.icache.tags.replacements              278                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           76.752158                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             167074                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           466.687151                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.752158                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149907                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.149907                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           167790                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          167790                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       167074                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         167074                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       167074                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          167074                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       167074                       # number of overall hits
-system.cpu1.icache.overall_hits::total         167074                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          358                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          358                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          358                       # number of overall misses
-system.cpu1.icache.overall_misses::total          358                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       167432                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       167432                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       167432                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       167432                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       167432                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       167432                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
 system.cpu1.dcache.tags.tagsinuse           30.295170                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs              21529                       # Total number of references to valid blocks.
@@ -650,6 +354,54 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements              278                       # number of replacements
+system.cpu1.icache.tags.tagsinuse           76.752158                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             167074                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           466.687151                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.752158                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149907                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.149907                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses           167790                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          167790                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst       167074                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         167074                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       167074                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          167074                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       167074                       # number of overall hits
+system.cpu1.icache.overall_hits::total         167074                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          358                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          358                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          358                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           358                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          358                       # number of overall misses
+system.cpu1.icache.overall_misses::total          358                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       167432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       167432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       167432                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       167432                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       167432                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       167432                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002138                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.002138                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002138                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.002138                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002138                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.002138                       # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          173296                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -708,54 +460,6 @@ system.cpu2.op_class::MemWrite                  17037     10.18%    100.00% # Cl
 system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::total                    167367                       # Class of executed instruction
-system.cpu2.icache.tags.replacements              278                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           74.781471                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             167009                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           466.505587                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781471                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146058                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.146058                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           167725                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          167725                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       167009                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         167009                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       167009                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          167009                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       167009                       # number of overall hits
-system.cpu2.icache.overall_hits::total         167009                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          358                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          358                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          358                       # number of overall misses
-system.cpu2.icache.overall_misses::total          358                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       167367                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       167367                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       167367                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       167367                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       167367                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       167367                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
 system.cpu2.dcache.tags.tagsinuse           29.575165                       # Cycle average of tags in use
 system.cpu2.dcache.tags.total_refs              35457                       # Total number of references to valid blocks.
@@ -820,6 +524,54 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.icache.tags.replacements              278                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           74.781471                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             167009                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs           466.505587                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781471                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146058                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.146058                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses           167725                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          167725                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst       167009                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         167009                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       167009                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          167009                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       167009                       # number of overall hits
+system.cpu2.icache.overall_hits::total         167009                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          358                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          358                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          358                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           358                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          358                       # number of overall misses
+system.cpu2.icache.overall_misses::total          358                       # number of overall misses
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       167367                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       167367                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       167367                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       167367                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       167367                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       167367                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002139                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.002139                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002139                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.002139                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002139                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.002139                       # miss rate for overall accesses
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          173297                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -878,54 +630,6 @@ system.cpu3.op_class::MemWrite                  16166      9.66%    100.00% # Cl
 system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::total                    167304                       # Class of executed instruction
-system.cpu3.icache.tags.replacements              279                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           72.874953                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             166945                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              359                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           465.027855                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874953                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142334                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.142334                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           167663                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          167663                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       166945                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         166945                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       166945                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          166945                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       166945                       # number of overall hits
-system.cpu3.icache.overall_hits::total         166945                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          359                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          359                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          359                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           359                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          359                       # number of overall misses
-system.cpu3.icache.overall_misses::total          359                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       167304                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       167304                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       167304                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       167304                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       167304                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       167304                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
 system.cpu3.dcache.tags.tagsinuse           28.848199                       # Cycle average of tags in use
 system.cpu3.dcache.tags.total_refs              33595                       # Total number of references to valid blocks.
@@ -989,5 +693,307 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.tags.replacements              279                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           72.874953                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             166945                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              359                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs           465.027855                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874953                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142334                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.142334                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses           167663                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          167663                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst       166945                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         166945                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       166945                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          166945                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       166945                       # number of overall hits
+system.cpu3.icache.overall_hits::total         166945                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          359                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          359                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          359                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           359                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          359                       # number of overall misses
+system.cpu3.icache.overall_misses::total          359                       # number of overall misses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       167304                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       167304                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       167304                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       167304                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       167304                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       167304                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002146                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.002146                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002146                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.002146                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002146                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.002146                       # miss rate for overall accesses
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                  366.582953                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       2271                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      421                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     5.394299                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks       0.966439                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      239.426226                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       55.207589                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       59.512205                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        6.721185                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst        1.942787                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        0.935416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        0.965459                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.905646                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.003653                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.000842                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000908                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000103                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000030                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.005594                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          373                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.006424                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    23864                       # Number of tag accesses
+system.l2c.tags.data_accesses                   23864                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
+system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst           185                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst           296                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           355                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           358                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total              1194                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            3                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                   1220                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                80                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          282                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           62                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst            3                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst            1                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total             348                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data            7                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data            1                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data            1                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total             75                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                 3                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst                3                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                1                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
+system.l2c.overall_misses::total                  559                       # number of overall misses
+system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              82                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          358                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          358                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          359                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1542                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data           10                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data           10                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data           10                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total          101                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.975610                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.603854                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.173184                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.008380                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.002786                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.225681                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.700000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.100000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.100000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.742574                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.008380                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.002786                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.008380                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.002786                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadResp                423                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              273                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              80                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               412                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              136                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           423                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1747                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1747                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        35776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   35776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              1108                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    1108    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                1108                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadResp              2179                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict            1051                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              412                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             412                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          1542                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          637                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          712                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          696                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          618                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          997                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          624                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  6784                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29888                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        22912                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        22912                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        22976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total                 165888                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                               0                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             3918                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   3918    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total               3918                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 67fefac90..89934d478 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,91 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000260                       # Number of seconds simulated
-sim_ticks                                   260037500                       # Number of ticks simulated
-final_tick                                  260037500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   260073500                       # Number of ticks simulated
+final_tick                                  260073500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 961598                       # Simulator instruction rate (inst/s)
-host_op_rate                                   961579                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              379344878                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302744                       # Number of bytes of host memory used
-host_seconds                                     0.69                       # Real time elapsed on the host
-sim_insts                                      659142                       # Number of instructions simulated
-sim_ops                                        659142                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1077387                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1077364                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              425087977                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303432                       # Number of bytes of host memory used
+host_seconds                                     0.61                       # Real time elapsed on the host
+sim_insts                                      659129                       # Number of instructions simulated
+sim_ops                                        659129                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst              448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             3904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst              896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data             1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst             3456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data             1408                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.inst               64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         3904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst          896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst         3456                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu3.inst           64                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                 7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                61                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                23                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                14                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data                16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                54                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data                22                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.inst                 1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            70143729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            40609527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             1722828                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3691775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            15013219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             5660722                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              246118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3691775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               140779695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       70143729                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        1722828                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       15013219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         246118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           87125895                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           70143729                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           40609527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            1722828                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3691775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           15013219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            5660722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             246118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3691775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              140779695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst            70134020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            40603906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             3445180                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3937348                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            13288551                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             5413854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              246084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             3691264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               140760208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       70134020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        3445180                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       13288551                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         246084                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           87113835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           70134020                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           40603906                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            3445180                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3937348                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           13288551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            5413854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             246084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            3691264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              140760208                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          520075                       # number of cpu cycles simulated
+system.cpu0.numCycles                          520147                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     157392                       # Number of instructions committed
-system.cpu0.committedOps                       157392                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               108420                       # Number of integer alu accesses
+system.cpu0.committedInsts                     157434                       # Number of instructions committed
+system.cpu0.committedOps                       157434                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               108448                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        25835                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      108420                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        25842                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      108448                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             313418                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110026                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             313502                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            110054                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        73430                       # number of memory refs
-system.cpu0.num_load_insts                      48613                       # Number of load instructions
-system.cpu0.num_store_insts                     24817                       # Number of store instructions
+system.cpu0.num_mem_refs                        73451                       # number of memory refs
+system.cpu0.num_load_insts                      48627                       # Number of load instructions
+system.cpu0.num_store_insts                     24824                       # Number of store instructions
 system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
-system.cpu0.num_busy_cycles              520074.998000                       # Number of busy cycles
+system.cpu0.num_busy_cycles              520146.998000                       # Number of busy cycles
 system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
-system.cpu0.Branches                            26700                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                23427     14.88%     14.88% # Class of executed instruction
-system.cpu0.op_class::IntAlu                    60513     38.43%     53.31% # Class of executed instruction
+system.cpu0.Branches                            26707                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                23434     14.88%     14.88% # Class of executed instruction
+system.cpu0.op_class::IntAlu                    60527     38.43%     53.31% # Class of executed instruction
 system.cpu0.op_class::IntMult                       0      0.00%     53.31% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     53.31% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     53.31% # Class of executed instruction
@@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.31% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.31% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.31% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.31% # Class of executed instruction
-system.cpu0.op_class::MemRead                   48697     30.93%     84.24% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  24817     15.76%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                   48711     30.93%     84.24% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  24824     15.76%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    157454                       # Class of executed instruction
+system.cpu0.op_class::total                    157496                       # Class of executed instruction
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          145.649829                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs              72898                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          145.650768                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs              72919                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           436.514970                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           436.640719                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.649829                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284472                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.284472                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.650768                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284474                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.284474                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           293953                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          293953                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48433                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48433                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24583                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24583                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           294037                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          294037                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        48447                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          48447                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        24590                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         24590                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73016                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73016                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73016                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73016                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        73037                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           73037                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        73037                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          73037                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          170                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
@@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data          353                       #
 system.cpu0.dcache.demand_misses::total           353                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          353                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          353                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4637996                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      4637996                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6976000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      6976000                       # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4613500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total      4613500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6976500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      6976500                       # number of WriteReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       359000                       # number of SwapReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::total       359000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     11613996                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     11613996                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     11613996                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     11613996                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48603                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48603                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24766                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24766                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data     11590000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     11590000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     11590000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     11590000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        48617                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        48617                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        24773                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        24773                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73369                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73369                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73369                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73369                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003498                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003498                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007389                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007389                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        73390                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        73390                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        73390                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        73390                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003497                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.003497                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007387                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007387                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004811                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004811                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004811                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004811                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579                       # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004810                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.004810                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004810                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.004810                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820                       # average WriteReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308                       # average SwapReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          353
 system.cpu0.dcache.demand_mshr_misses::total          353                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          353                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          353                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4372004                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4372004                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6701500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6701500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       320000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       320000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11073504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     11073504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11073504                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     11073504                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003498                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003498                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007389                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007389                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4443500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4443500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6793500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6793500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       333000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       333000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11237000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     11237000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11237000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     11237000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003497                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003497                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007387                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007387                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004811                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004811                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004811                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004811                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004810                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.004810                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004810                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.004810                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          212.581030                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             156988                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          212.583222                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             157030                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           336.162741                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           336.252677                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.581030                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.415197                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.415197                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.583222                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.415202                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.415202                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           157922                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          157922                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       156988                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         156988                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       156988                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          156988                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       156988                       # number of overall hits
-system.cpu0.icache.overall_hits::total         156988                       # number of overall hits
+system.cpu0.icache.tags.tag_accesses           157964                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          157964                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst       157030                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         157030                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       157030                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          157030                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       157030                       # number of overall hits
+system.cpu0.icache.overall_hits::total         157030                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
 system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18041500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     18041500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     18041500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     18041500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     18041500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     18041500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       157455                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       157455                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       157455                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       157455                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       157455                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       157455                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002966                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002966                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002966                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002966                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002966                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002966                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38632.762313                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38632.762313                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18042500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     18042500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     18042500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     18042500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     18042500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     18042500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       157497                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       157497                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       157497                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       157497                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       157497                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       157497                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002965                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002965                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002965                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002965                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002965                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002965                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38634.903640                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38634.903640                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          467
 system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17341000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     17341000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17341000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     17341000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17341000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     17341000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002966                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002966                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002966                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17575500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     17575500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17575500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     17575500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17575500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     17575500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002965                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002965                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002965                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.002965                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002965                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.002965                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          520075                       # number of cpu cycles simulated
+system.cpu1.numCycles                          520147                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     168980                       # Number of instructions committed
-system.cpu1.committedOps                       168980                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               110320                       # Number of integer alu accesses
+system.cpu1.committedInsts                     165571                       # Number of instructions committed
+system.cpu1.committedOps                       165571                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               111555                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        33339                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      110320                       # number of integer instructions
+system.cpu1.num_conditional_control_insts        31016                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      111555                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             270098                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            102062                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads             284333                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            108565                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        53149                       # number of memory refs
-system.cpu1.num_load_insts                      40825                       # Number of load instructions
-system.cpu1.num_store_insts                     12324                       # Number of store instructions
+system.cpu1.num_mem_refs                        56707                       # number of memory refs
+system.cpu1.num_load_insts                      41448                       # Number of load instructions
+system.cpu1.num_store_insts                     15259                       # Number of store instructions
 system.cpu1.num_idle_cycles              67727.001740                       # Number of idle cycles
-system.cpu1.num_busy_cycles              452347.998260                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.869775                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.130225                       # Percentage of idle cycles
-system.cpu1.Branches                            34992                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                25772     15.25%     15.25% # Class of executed instruction
-system.cpu1.op_class::IntAlu                    74368     44.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::IntMult                       0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.25% # Class of executed instruction
-system.cpu1.op_class::MemRead                   56548     33.46%     92.71% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  12324      7.29%    100.00% # Class of executed instruction
+system.cpu1.num_busy_cycles              452419.998260                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.869793                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.130207                       # Percentage of idle cycles
+system.cpu1.Branches                            32668                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                23452     14.16%     14.16% # Class of executed instruction
+system.cpu1.op_class::IntAlu                    74986     45.28%     59.44% # Class of executed instruction
+system.cpu1.op_class::IntMult                       0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.44% # Class of executed instruction
+system.cpu1.op_class::MemRead                   51906     31.34%     90.79% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  15259      9.21%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    169012                       # Class of executed instruction
+system.cpu1.op_class::total                    165603                       # Class of executed instruction
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           25.995164                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              26990                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           899.666667                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           26.035238                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              32753                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1129.413793                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.995164                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050772                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.050772                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.035238                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050850                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.050850                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           212815                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          212815                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        40655                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          40655                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        12144                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         12144                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        52799                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           52799                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        52799                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          52799                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          162                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          108                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          270                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           270                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          270                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          270                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2619475                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      2619475                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1982498                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      1982498                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       237000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       237000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      4601973                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      4601973                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      4601973                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      4601973                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        40817                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        40817                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        12252                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        12252                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        53069                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        53069                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        53069                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        53069                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003969                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.003969                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008815                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.008815                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005088                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005088                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005088                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005088                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4232.142857                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  4232.142857                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444                       # average overall miss latency
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           227042                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          227042                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        41284                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          41284                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        15082                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         15082                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        56366                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           56366                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        56366                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          56366                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          156                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          156                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          109                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          265                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           265                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          265                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          265                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2383000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      2383000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2068000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      2068000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       251500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       251500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      4451000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      4451000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      4451000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      4451000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        41440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        41440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        15191                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        15191                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        56631                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        56631                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        56631                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        56631                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003764                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.003764                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.007175                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.007175                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.833333                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004679                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.004679                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004679                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.004679                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4572.727273                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  4572.727273                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          162                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2358525                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2358525                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1818502                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1818502                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       153000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       153000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4177027                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      4177027                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4177027                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      4177027                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003969                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003969                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008815                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008815                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005088                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.005088                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005088                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.005088                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  2732.142857                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  2732.142857                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          156                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          156                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          109                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          265                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          265                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2227000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2227000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1959000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1959000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       196500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       196500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4186000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      4186000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4186000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      4186000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003764                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003764                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.007175                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.007175                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.833333                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.833333                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004679                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.004679                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004679                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.004679                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3572.727273                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3572.727273                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              280                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           65.697365                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             168647                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           65.699918                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             165238                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           460.784153                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           451.469945                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    65.697365                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.128315                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.128315                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    65.699918                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.128320                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.128320                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           169379                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          169379                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       168647                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         168647                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       168647                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          168647                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       168647                       # number of overall hits
-system.cpu1.icache.overall_hits::total         168647                       # number of overall hits
+system.cpu1.icache.tags.tag_accesses           165970                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          165970                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst       165238                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         165238                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       165238                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          165238                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       165238                       # number of overall hits
+system.cpu1.icache.overall_hits::total         165238                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
 system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5333988                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      5333988                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      5333988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      5333988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      5333988                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      5333988                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       169013                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       169013                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       169013                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       169013                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       169013                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       169013                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002166                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002166                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002166                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002166                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002166                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002166                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14573.737705                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14573.737705                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5351500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      5351500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      5351500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      5351500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      5351500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      5351500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       165604                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       165604                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       165604                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       165604                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       165604                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       165604                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002210                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.002210                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002210                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.002210                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002210                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.002210                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14621.584699                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14621.584699                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          366
 system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      4778012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      4778012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      4778012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      4778012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      4778012                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      4778012                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002166                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002166                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002166                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      4985500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      4985500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      4985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      4985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      4985500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      4985500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002210                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002210                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002210                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.002210                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002210                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.002210                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          520075                       # number of cpu cycles simulated
+system.cpu2.numCycles                          520146                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     164869                       # Number of instructions committed
-system.cpu2.committedOps                       164869                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               110069                       # Number of integer alu accesses
+system.cpu2.committedInsts                     160598                       # Number of instructions committed
+system.cpu2.committedOps                       160598                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               111601                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        31409                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      110069                       # number of integer instructions
+system.cpu2.num_conditional_control_insts        28506                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      111601                       # number of integer instructions
 system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             276820                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            105549                       # number of times the integer registers were written
+system.cpu2.num_int_register_reads             294560                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            113655                       # number of times the integer registers were written
 system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        54829                       # number of memory refs
-system.cpu2.num_load_insts                      40701                       # Number of load instructions
-system.cpu2.num_store_insts                     14128                       # Number of store instructions
-system.cpu2.num_idle_cycles              67985.001739                       # Number of idle cycles
-system.cpu2.num_busy_cycles              452089.998261                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.869278                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.130722                       # Percentage of idle cycles
-system.cpu2.Branches                            33062                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                23842     14.46%     14.46% # Class of executed instruction
-system.cpu2.op_class::IntAlu                    74244     45.02%     59.48% # Class of executed instruction
-system.cpu2.op_class::IntMult                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::MemRead                   52687     31.95%     91.43% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  14128      8.57%    100.00% # Class of executed instruction
+system.cpu2.num_mem_refs                        59264                       # number of memory refs
+system.cpu2.num_load_insts                      41473                       # Number of load instructions
+system.cpu2.num_store_insts                     17791                       # Number of store instructions
+system.cpu2.num_idle_cycles              67981.871041                       # Number of idle cycles
+system.cpu2.num_busy_cycles              452164.128959                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.869302                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.130698                       # Percentage of idle cycles
+system.cpu2.Branches                            30158                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                20943     13.04%     13.04% # Class of executed instruction
+system.cpu2.op_class::IntAlu                    75009     46.70%     59.73% # Class of executed instruction
+system.cpu2.op_class::IntMult                       0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.73% # Class of executed instruction
+system.cpu2.op_class::MemRead                   46887     29.19%     88.92% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  17791     11.08%    100.00% # Class of executed instruction
 system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    164901                       # Class of executed instruction
+system.cpu2.op_class::total                    160630                       # Class of executed instruction
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           27.767003                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              30481                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           27.808310                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              37821                       # Total number of references to valid blocks.
 system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1051.068966                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1304.172414                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.767003                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.054232                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.054232                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.808310                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.054313                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.054313                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           219531                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          219531                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        40534                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          40534                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        13949                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         13949                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        54483                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           54483                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        54483                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          54483                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          159                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          159                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          108                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          267                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           267                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          267                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          267                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2767480                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      2767480                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2022500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2022500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       237000                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       237000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      4789980                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      4789980                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      4789980                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      4789980                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        40693                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        40693                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        14057                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        14057                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        54750                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        54750                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        54750                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        54750                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003907                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003907                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007683                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.007683                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.811594                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004877                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004877                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004877                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004877                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4232.142857                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  4232.142857                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data        17940                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total        17940                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data        17940                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total        17940                       # average overall miss latency
+system.cpu2.dcache.tags.tag_accesses           237265                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          237265                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        41314                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          41314                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        17614                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         17614                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           10                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        58928                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           58928                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        58928                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          58928                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          151                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          110                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          110                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           55                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          261                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           261                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          261                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          261                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2416500                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      2416500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2235500                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      2235500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       248000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       248000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      4652000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      4652000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      4652000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      4652000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        41465                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        41465                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        17724                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        17724                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           65                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        59189                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        59189                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        59189                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        59189                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003642                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.003642                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006206                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.006206                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.846154                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.846154                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004410                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.004410                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004410                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.004410                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4509.090909                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  4509.090909                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          159                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          108                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2514020                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2514020                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1860500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1860500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       153000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       153000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4374520                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      4374520                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4374520                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      4374520                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003907                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003907                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.007683                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.007683                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.811594                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004877                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004877                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004877                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004877                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  2732.142857                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  2732.142857                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          151                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          110                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          110                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           55                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          261                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          261                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          261                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          261                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2265500                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2265500                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      2125500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      2125500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       193000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       193000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4391000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      4391000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4391000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      4391000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003642                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003642                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006206                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.006206                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.846154                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004410                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.004410                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004410                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.004410                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3509.090909                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3509.090909                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              280                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           70.145256                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             164536                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse           70.147178                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             160265                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           449.551913                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs           437.882514                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    70.145256                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.137002                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.137002                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    70.147178                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.137006                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.137006                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           165268                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          165268                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       164536                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         164536                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       164536                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          164536                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       164536                       # number of overall hits
-system.cpu2.icache.overall_hits::total         164536                       # number of overall hits
+system.cpu2.icache.tags.tag_accesses           160997                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          160997                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst       160265                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         160265                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       160265                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          160265                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       160265                       # number of overall hits
+system.cpu2.icache.overall_hits::total         160265                       # number of overall hits
 system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
 system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
 system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
 system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7445997                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      7445997                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      7445997                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      7445997                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      7445997                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      7445997                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       164902                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       164902                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       164902                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       164902                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       164902                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       164902                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 20344.254098                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 20344.254098                       # average overall miss latency
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7437500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      7437500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      7437500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      7437500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      7437500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      7437500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       160631                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       160631                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       160631                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       160631                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       160631                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       160631                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002279                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.002279                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002279                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.002279                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002279                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.002279                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 20321.038251                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 20321.038251                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -844,158 +844,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst          366
 system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6894003                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      6894003                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6894003                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      6894003                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6894003                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      6894003                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7071500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      7071500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      7071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7071500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      7071500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002279                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002279                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002279                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.002279                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002279                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.002279                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          520075                       # number of cpu cycles simulated
+system.cpu3.numCycles                          520146                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     167901                       # Number of instructions committed
-system.cpu3.committedOps                       167901                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               110672                       # Number of integer alu accesses
+system.cpu3.committedInsts                     175526                       # Number of instructions committed
+system.cpu3.committedOps                       175526                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               107877                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        32621                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      110672                       # number of integer instructions
+system.cpu3.num_conditional_control_insts        37833                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      107877                       # number of integer instructions
 system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             274378                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            104026                       # number of times the integer registers were written
+system.cpu3.num_int_register_reads             242346                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes             89400                       # number of times the integer registers were written
 system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        54219                       # number of memory refs
-system.cpu3.num_load_insts                      41000                       # Number of load instructions
-system.cpu3.num_store_insts                     13219                       # Number of store instructions
-system.cpu3.num_idle_cycles              68239.001738                       # Number of idle cycles
-system.cpu3.num_busy_cycles              451835.998262                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.868790                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.131210                       # Percentage of idle cycles
-system.cpu3.Branches                            34277                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                25056     14.92%     14.92% # Class of executed instruction
-system.cpu3.op_class::IntAlu                    74547     44.39%     59.31% # Class of executed instruction
-system.cpu3.op_class::IntMult                       0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.31% # Class of executed instruction
-system.cpu3.op_class::MemRead                   55111     32.82%     92.13% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  13219      7.87%    100.00% # Class of executed instruction
+system.cpu3.num_mem_refs                        46213                       # number of memory refs
+system.cpu3.num_load_insts                      39592                       # Number of load instructions
+system.cpu3.num_store_insts                      6621                       # Number of store instructions
+system.cpu3.num_idle_cycles              68237.870548                       # Number of idle cycles
+system.cpu3.num_busy_cycles              451908.129452                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.868810                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.131190                       # Percentage of idle cycles
+system.cpu3.Branches                            39491                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                30262     17.24%     17.24% # Class of executed instruction
+system.cpu3.op_class::IntAlu                    73148     41.67%     58.90% # Class of executed instruction
+system.cpu3.op_class::IntMult                       0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     58.90% # Class of executed instruction
+system.cpu3.op_class::MemRead                   65527     37.32%     96.23% # Class of executed instruction
+system.cpu3.op_class::MemWrite                   6621      3.77%    100.00% # Class of executed instruction
 system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    167933                       # Class of executed instruction
+system.cpu3.op_class::total                    175558                       # Class of executed instruction
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           26.810589                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              28657                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs           988.172414                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           26.732151                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              15554                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs           518.466667                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    26.810589                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.052364                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.052364                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    26.732151                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.052211                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.052211                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           217093                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          217093                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        40832                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          40832                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        13038                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         13038                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        53870                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           53870                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        53870                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          53870                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          160                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          160                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          108                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           58                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2513476                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      2513476                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2024000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2024000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       244500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       244500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      4537476                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      4537476                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      4537476                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      4537476                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        40992                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        40992                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        13146                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        13146                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        54138                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        54138                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        54138                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        54138                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003903                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003903                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.008215                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.008215                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.816901                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004950                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.004950                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004950                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.004950                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4215.517241                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  4215.517241                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597                       # average overall miss latency
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           185088                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          185088                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        39402                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          39402                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data         6435                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total          6435                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           19                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        45837                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           45837                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        45837                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          45837                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          182                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          182                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           60                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          287                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           287                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          287                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          287                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3223000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      3223000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1728500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      1728500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       276500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       276500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      4951500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      4951500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      4951500                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      4951500                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        39584                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        39584                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data         6540                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total         6540                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           79                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           79                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        46124                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        46124                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        46124                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        46124                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.004598                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.004598                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.016055                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.016055                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.759494                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.759494                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006222                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.006222                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006222                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.006222                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4608.333333                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  4608.333333                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          160                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           58                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2256524                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2256524                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1862000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1862000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       157500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       157500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4118524                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      4118524                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4118524                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      4118524                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003903                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003903                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.008215                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.008215                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004950                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.004950                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004950                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.004950                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  2715.517241                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  2715.517241                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          182                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          182                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           60                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           60                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          287                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          287                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          287                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          287                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      3041000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      3041000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1623500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1623500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       216500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       216500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4664500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      4664500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4664500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      4664500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004598                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004598                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.016055                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.016055                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.759494                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.759494                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.006222                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.006222                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.006222                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.006222                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3608.333333                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3608.333333                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              281                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           67.819588                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             167567                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           67.821849                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             175192                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           456.585831                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs           477.362398                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    67.819588                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.132460                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.132460                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    67.821849                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.132465                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.132465                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           168301                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          168301                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       167567                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         167567                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       167567                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          167567                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       167567                       # number of overall hits
-system.cpu3.icache.overall_hits::total         167567                       # number of overall hits
+system.cpu3.icache.tags.tag_accesses           175926                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          175926                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst       175192                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         175192                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       175192                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          175192                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       175192                       # number of overall hits
+system.cpu3.icache.overall_hits::total         175192                       # number of overall hits
 system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
 system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
 system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
 system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
 system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
 system.cpu3.icache.overall_misses::total          367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5144490                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      5144490                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      5144490                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      5144490                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      5144490                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      5144490                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       167934                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       167934                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       167934                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       167934                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       167934                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       167934                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002185                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002185                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002185                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002185                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002185                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002185                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14017.683924                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14017.683924                       # average overall miss latency
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5136500                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      5136500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      5136500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      5136500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      5136500                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      5136500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       175559                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       175559                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       175559                       # number of demand (read+write) accesses
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+system.cpu3.icache.overall_accesses::cpu3.inst       175559                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       175559                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002090                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.002090                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002090                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.002090                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002090                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.002090                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13995.912807                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13995.912807                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1111,46 +1111,46 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst          367
 system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4586010                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      4586010                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4586010                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      4586010                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4586010                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      4586010                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002185                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002185                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002185                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4769500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      4769500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4769500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      4769500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4769500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      4769500                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002090                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002090                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002090                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.002090                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002090                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.002090                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  349.350598                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                  349.351676                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1716                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.843823                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                            4                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.890412                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      231.950361                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       54.237281                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst        6.226273                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        0.814088                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       47.344433                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        6.154120                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        0.888026                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.845603                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.890425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      231.950289                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       54.237156                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst        6.367865                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        0.832949                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst       47.203910                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        6.135421                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        0.888032                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.845628                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000014                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.003539                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000828                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000095                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000722                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data       0.000013                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000720                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000094                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.inst       0.000014                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
@@ -1159,21 +1159,22 @@ system.l2c.tags.occ_task_id_blocks::1024          429                       # Oc
 system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    15709                       # Number of tag accesses
-system.l2c.tags.data_accesses                   15709                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                352                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                302                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
+system.l2c.tags.tag_accesses                    19677                       # Number of tag accesses
+system.l2c.tags.data_accesses                   19677                       # Number of data accesses
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst           182                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst           352                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           302                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           358                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total              1194                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            3                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                 352                       # number of demand (read+write) hits
@@ -1192,25 +1193,26 @@ system.l2c.overall_hits::cpu2.data                  3                       # nu
 system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
 system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               14                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst               64                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                8                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            17                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            11                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             15                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          285                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           14                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst           64                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst            9                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total             372                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total             78                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst                14                       # number of demand (read+write) misses
@@ -1229,59 +1231,61 @@ system.l2c.overall_misses::cpu2.data               23                       # nu
 system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
 system.l2c.overall_misses::total                  592                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     14963000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      3465000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst       714500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst      3356500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data       420000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       458000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data       103500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       23584500                       # number of ReadReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu0.data      5197500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       744000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       791500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       740000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      7473000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     14963000                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       735000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       797000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       744000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      7473500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     14964000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst       740000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3341500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst       453500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     19499000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data      3465000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data       105000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data       419000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data       104500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total      4093500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     14964000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.data      8662500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst       714500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data       848000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      3356500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1211500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       458000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       843500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        31057500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     14963000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu1.inst       740000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data       840000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      3341500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1216000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       453500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       848500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        31066000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     14964000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.data      8662500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst       714500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data       848000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      3356500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1211500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       458000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       843500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       31057500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu1.inst       740000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data       840000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      3341500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1216000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       453500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       848500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       31066000                       # number of overall miss cycles
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           17                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           11                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           15                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          366                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          366                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          367                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1566                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total          104                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
@@ -1300,15 +1304,6 @@ system.l2c.overall_accesses::cpu2.data             26                       # nu
 system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.038251                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.174863                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.727273                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
@@ -1319,6 +1314,16 @@ system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # m
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.610278                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.038251                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.174863                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.024523                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.237548                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181818                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.727273                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.181818                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.750000                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.038251                       # miss rate for demand accesses
@@ -1337,38 +1342,39 @@ system.l2c.overall_miss_rate::cpu2.data      0.884615                       # mi
 system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data        51750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total        52410                       # average ReadReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52500                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52626.760563                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data        52500                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52630.281690                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data        52500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        52500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        52375                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        52250                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52461.993243                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data        52500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52476.351351                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52461.993243                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data        52500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 52210.937500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 52869.565217                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52476.351351                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1377,107 +1383,98 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           10                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            8                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.inst              8                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             8                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst           61                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data            8                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           16                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           17                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           18                       # number of UpgradeReq MSHR misses
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 system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           14                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          285                       # number of ReadCleanReq MSHR misses
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+system.l2c.ReadCleanReq_mshr_misses::total          354                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data           66                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data            2                       # number of ReadSharedReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst            7                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data           15                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst            7                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11542500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2673000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       283500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data        40500                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::total     17419500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1134000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       649996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       648000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       688500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      3120496                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4009500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       575500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       611500                       # number of ReadExReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.inst     11542500                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu2.data       935500                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total     23187000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.727273                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1194000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       765000                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::total      6053500                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       600000                       # number of ReadCleanReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::total     15052000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      2805000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data        85000                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu0.data      7012500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.data       680000                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu2.data       944500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu3.data       646500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     24335500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     12114000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      7012500                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.data       680000                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu3.data       646500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     24335500                       # number of overall MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1488,68 +1485,79 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.038251                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.226054                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.181818                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.636364                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.730769                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.038251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.640000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.038251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.640000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40536.713287                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40536.713287                       # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        42500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        42500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        42500                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data        43100                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42544.580420                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data        43100                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 42544.580420                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                 430                       # Transaction distribution
 system.membus.trans_dist::ReadResp                430                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1559                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   1559                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
@@ -1565,26 +1573,28 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 914                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              679142                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              665648                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2961502                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2948008                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq               2217                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2217                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp              2225                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict             496                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq              429                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp             429                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          580                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          734                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          368                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  4812                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq          1566                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          659                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1077                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          581                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          848                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          363                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          846                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          362                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          856                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          383                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  5316                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29888                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        23424                       # Cumulative packet size per connected master and slave (bytes)
@@ -1594,8 +1604,8 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        23488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 116032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1029                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             2921                       # Request fanout histogram
+system.toL2Bus.snoops                            1037                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             3986                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -1606,29 +1616,29 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   2921    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   3986    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               2921                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            1466989                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.6                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total               3986                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            1998491                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.8                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy            700500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            503996                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy            503490                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            552488                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy            549000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            431973                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            419983                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            550497                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy            553988                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            423980                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy            412483                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            554490                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy            554487                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            428476                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy            467954                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index e7443957c..4a69b5566 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.010140                       # Number of seconds simulated
-sim_ticks                                    10139920                       # Number of ticks simulated
-final_tick                                   10139920                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.010085                       # Number of seconds simulated
+sim_ticks                                    10084846                       # Number of ticks simulated
+final_tick                                   10084846                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 145167                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 481408                       # Number of bytes of host memory used
-host_seconds                                    69.85                       # Real time elapsed on the host
+host_tick_rate                                 135609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 534216                       # Number of bytes of host memory used
+host_seconds                                    74.37                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39722368                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           39722368                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14274816                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total        14274816                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       620662                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              620662                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       223044                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             223044                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   3917424201                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            3917424201                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1407783888                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1407783888                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   5325208088                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           5325208088                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      620666                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     223044                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    620666                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   223044                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               39325760                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                  396864                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                14138944                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                39722624                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys             14274816                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                   6201                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                  2091                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39539520                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           39539520                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14190848                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total        14190848                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       617805                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              617805                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       221732                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             221732                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   3920686543                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            3920686543                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   1407145731                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           1407145731                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   5327832274                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           5327832274                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      617810                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     221732                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    617810                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   221732                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               39149376                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                  390400                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                14065216                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                39539840                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys             14190848                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                   6100                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                  1940                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             76321                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             76908                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             76950                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             77228                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             77214                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             76769                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             76576                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             76499                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             76472                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             76445                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             76295                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             76401                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             76651                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             76559                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             76484                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             76402                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::10                0                       # Per bank write bursts
@@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0             27303                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1             27584                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2             27647                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3             27851                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4             27807                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5             27671                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6             27568                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7             27490                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             27622                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1             27185                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2             27442                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3             27653                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4             27274                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5             27861                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6             27499                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7             27233                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
@@ -69,29 +69,29 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                      10139879                       # Total gap between requests
+system.mem_ctrls.totGap                      10084812                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                620666                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                617810                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               223044                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                   34202                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                   67883                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                  107442                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                  137013                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                  123761                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                   83967                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                   43765                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                   16432                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               221732                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                   33764                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                   67305                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                  107562                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                  136575                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                  123260                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                   83360                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                   43779                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                   16105                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
@@ -131,35 +131,35 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                    102                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                   1701                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   5412                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   9478                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                  12746                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                  14568                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                  15535                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                  16087                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                  16159                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                  16083                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                  15677                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                  15094                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                  14842                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                  14767                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                  14802                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                  14952                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                  15339                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                   4340                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                   1928                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                    791                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                    311                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                    122                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                     14                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                     28                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                    100                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                   1824                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   5451                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   9639                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                  12681                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                  14370                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                  15508                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                  15925                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                  16112                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                  15973                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                  15537                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                  15061                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                  14828                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                  14675                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                  14690                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                  14838                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                  15284                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                   4187                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                   1849                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    776                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                    270                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                    109                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                     12                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::41                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
@@ -180,165 +180,168 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples       335053                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    159.568976                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   125.655089                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   125.561192                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127       136625     40.78%     40.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255       126781     37.84%     78.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383        44480     13.28%     91.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511        17048      5.09%     96.98% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639         6525      1.95%     98.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         2297      0.69%     99.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895          855      0.26%     99.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023          301      0.09%     99.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151          141      0.04%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total       335053                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples        13793                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      44.545857                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     43.515478                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      9.590118                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19            13      0.09%      0.09% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23            63      0.46%      0.55% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27           253      1.83%      2.39% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31           644      4.67%      7.05% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35          1374      9.96%     17.02% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39          2023     14.67%     31.68% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-43          2256     16.36%     48.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::44-47          2260     16.39%     64.42% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-51          1885     13.67%     78.09% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::52-55          1286      9.32%     87.41% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-59           772      5.60%     93.01% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::60-63           480      3.48%     96.49% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-67           280      2.03%     98.52% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::68-71           112      0.81%     99.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-75            40      0.29%     99.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::76-79            38      0.28%     99.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-83             9      0.07%     99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::84-87             2      0.01%     99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-91             2      0.01%     99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-115            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total         13793                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples        13793                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.016893                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.015738                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.203483                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16            13672     99.12%     99.12% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17               53      0.38%     99.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18               36      0.26%     99.77% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19               22      0.16%     99.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20                9      0.07%     99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22                1      0.01%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total         13793                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                     29132870                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                40807705                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                    3072325                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        47.41                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples       332248                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    160.163733                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   126.016641                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   126.021242                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127       134990     40.63%     40.63% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255       125717     37.84%     78.47% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383        44100     13.27%     91.74% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511        17233      5.19%     96.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639         6597      1.99%     98.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         2403      0.72%     99.64% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895          797      0.24%     99.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023          271      0.08%     99.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151          140      0.04%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total       332248                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples        13719                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      44.587579                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     43.567132                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      9.560965                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-15             1      0.01%      0.01% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-19            10      0.07%      0.08% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-23            52      0.38%      0.46% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-27           254      1.85%      2.31% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::28-31           679      4.95%      7.26% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-35          1331      9.70%     16.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-39          1929     14.06%     31.02% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-43          2366     17.25%     48.27% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::44-47          2213     16.13%     64.40% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-51          1878     13.69%     78.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::52-55          1269      9.25%     87.34% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-59           815      5.94%     93.28% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::60-63           445      3.24%     96.52% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-67           259      1.89%     98.41% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::68-71           126      0.92%     99.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-75            51      0.37%     99.70% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::76-79            25      0.18%     99.88% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-83             8      0.06%     99.94% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::84-87             3      0.02%     99.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-91             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::92-95             1      0.01%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-115            2      0.01%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total         13719                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples        13719                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.019316                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.017844                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.231611                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16            13593     99.08%     99.08% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17               51      0.37%     99.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18               36      0.26%     99.72% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19               22      0.16%     99.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20               11      0.08%     99.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21                4      0.03%     99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22                2      0.01%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total         13719                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                     28969420                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                40591891                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                    3058545                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        47.36                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   66.41                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      3878.31                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      1394.38                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   3917.45                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1407.78                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   66.36                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      3882.00                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      1394.69                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   3920.72                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   1407.15                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        41.19                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    30.30                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   10.89                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       5.50                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.47                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   285829                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  214496                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 46.52                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                97.08                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         12.02                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    59.89                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy               2532486600                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy               1406937000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy              7666913280                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy             2290011264                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy            662145120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy           6909126408                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             21943800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy            21489563472                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           2119.780745                       # Core power per rank (mW)
+system.mem_ctrls.busUtil                        41.22                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    30.33                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   10.90                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       5.49                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      26.46                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   285743                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  213481                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 46.71                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                97.13                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         12.01                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    60.04                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy               2511379080                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy               1395210600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy              7632905280                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy             2278067328                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy            658585200                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy           6872035140                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             21818400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy            21370001028                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower           2119.367180                       # Core power per rank (mW)
 system.mem_ctrls_0.memoryStateTime::IDLE           20                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF        338520                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF        336700                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT       9799109                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT       9746493                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy            662145120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            219079728                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy           5890395600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy             6771620448                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.969581                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE      9799112                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF        338520                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy            658585200                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy            217901880                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy           5858727600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy             6735214680                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            667.969572                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE      9746430                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF        336700                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           99636                       # number of read accesses completed
-system.cpu0.num_writes                          55756                       # number of write accesses completed
-system.cpu1.num_reads                           99812                       # number of read accesses completed
-system.cpu1.num_writes                          55738                       # number of write accesses completed
-system.cpu2.num_reads                           99728                       # number of read accesses completed
-system.cpu2.num_writes                          55111                       # number of write accesses completed
-system.cpu3.num_reads                           99867                       # number of read accesses completed
-system.cpu3.num_writes                          55484                       # number of write accesses completed
-system.cpu4.num_reads                           99170                       # number of read accesses completed
-system.cpu4.num_writes                          55261                       # number of write accesses completed
-system.cpu5.num_reads                          100000                       # number of read accesses completed
-system.cpu5.num_writes                          55396                       # number of write accesses completed
-system.cpu6.num_reads                           99231                       # number of read accesses completed
-system.cpu6.num_writes                          55296                       # number of write accesses completed
-system.cpu7.num_reads                           99263                       # number of read accesses completed
-system.cpu7.num_writes                          55610                       # number of write accesses completed
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          54904                       # number of write accesses completed
+system.cpu1.num_reads                           98267                       # number of read accesses completed
+system.cpu1.num_writes                          54988                       # number of write accesses completed
+system.cpu2.num_reads                           99798                       # number of read accesses completed
+system.cpu2.num_writes                          55147                       # number of write accesses completed
+system.cpu3.num_reads                           98142                       # number of read accesses completed
+system.cpu3.num_writes                          54997                       # number of write accesses completed
+system.cpu4.num_reads                           99042                       # number of read accesses completed
+system.cpu4.num_writes                          55133                       # number of write accesses completed
+system.cpu5.num_reads                           99461                       # number of read accesses completed
+system.cpu5.num_writes                          55195                       # number of write accesses completed
+system.cpu6.num_reads                           99533                       # number of read accesses completed
+system.cpu6.num_writes                          55095                       # number of write accesses completed
+system.cpu7.num_reads                           99126                       # number of read accesses completed
+system.cpu7.num_writes                          55305                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size               2048                       # delay histogram for all message
 system.ruby.delayHist::max_bucket               20479                       # delay histogram for all message
-system.ruby.delayHist::samples                4993549                       # delay histogram for all message
-system.ruby.delayHist::mean                200.268799                       # delay histogram for all message
-system.ruby.delayHist::stdev               576.702096                       # delay histogram for all message
-system.ruby.delayHist                    |     4855621     97.24%     97.24% |      131487      2.63%     99.87% |        6055      0.12%     99.99% |         370      0.01%    100.00% |          13      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                  4993549                       # delay histogram for all message
+system.ruby.delayHist::samples                4974912                       # delay histogram for all message
+system.ruby.delayHist::mean                203.140608                       # delay histogram for all message
+system.ruby.delayHist::stdev               582.111066                       # delay histogram for all message
+system.ruby.delayHist                    |     4834308     97.17%     97.17% |      133920      2.69%     99.87% |        6363      0.13%     99.99% |         304      0.01%    100.00% |          15      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                  4974912                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       626470                      
-system.ruby.outstanding_req_hist::mean      15.998466                      
-system.ruby.outstanding_req_hist::gmean     15.997202                      
-system.ruby.outstanding_req_hist::stdev      0.125833                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          17      0.00%      0.02% |      626349     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        626470                      
+system.ruby.outstanding_req_hist::samples       623553                      
+system.ruby.outstanding_req_hist::mean      15.998456                      
+system.ruby.outstanding_req_hist::gmean     15.997185                      
+system.ruby.outstanding_req_hist::stdev      0.126140                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          19      0.00%      0.02% |      623430     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        623553                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples              626342                      
-system.ruby.latency_hist::mean            2071.919100                      
-system.ruby.latency_hist::gmean           1588.311546                      
-system.ruby.latency_hist::stdev           1228.835712                      
-system.ruby.latency_hist                 |      165846     26.48%     26.48% |      150976     24.10%     50.58% |      148385     23.69%     74.27% |      132690     21.18%     95.46% |       28063      4.48%     99.94% |         382      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                626342                      
+system.ruby.latency_hist::samples              623425                      
+system.ruby.latency_hist::mean            2070.305650                      
+system.ruby.latency_hist::gmean           1615.472448                      
+system.ruby.latency_hist::stdev           1197.783939                      
+system.ruby.latency_hist                 |      158292     25.39%     25.39% |      157674     25.29%     50.68% |      153146     24.57%     75.25% |      128715     20.65%     95.89% |       25317      4.06%     99.95% |         281      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                623425                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples               9                      
+system.ruby.hit_latency_hist::samples               8                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           9    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total                 9                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           8    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                 8                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples         626333                      
-system.ruby.miss_latency_hist::mean       2071.948829                      
-system.ruby.miss_latency_hist::gmean      1588.454694                      
-system.ruby.miss_latency_hist::stdev      1228.819513                      
-system.ruby.miss_latency_hist            |      165837     26.48%     26.48% |      150976     24.10%     50.58% |      148385     23.69%     74.27% |      132690     21.19%     95.46% |       28063      4.48%     99.94% |         382      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           626333                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits            2                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        78425                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78427                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples         623417                      
+system.ruby.miss_latency_hist::mean       2070.332179                      
+system.ruby.miss_latency_hist::gmean      1615.602823                      
+system.ruby.miss_latency_hist::stdev      1197.768731                      
+system.ruby.miss_latency_hist            |      158284     25.39%     25.39% |      157674     25.29%     50.68% |      153146     24.57%     75.25% |      128715     20.65%     95.89% |       25317      4.06%     99.95% |         281      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           623417                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits            1                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78229                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78230                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -351,9 +354,9 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        78414                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78415                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits            2                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        77517                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        77519                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -366,9 +369,9 @@ system.ruby.l1_cntrl1.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl2.L1Dcache.demand_hits            3                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        78001                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78004                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits            1                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        78390                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78391                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -381,9 +384,9 @@ system.ruby.l1_cntrl2.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl2.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl2.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl3.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        78494                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78495                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_hits            0                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        77490                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        77490                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -397,8 +400,8 @@ system.ruby.l1_cntrl3.prefetcher.partial_hits            0
 system.ruby.l1_cntrl3.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl4.L1Dcache.demand_hits            2                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        78222                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78224                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        77712                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77714                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -411,9 +414,9 @@ system.ruby.l1_cntrl4.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl4.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl4.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl5.L1Dcache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        78386                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78386                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits            2                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        77950                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        77952                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -427,8 +430,8 @@ system.ruby.l1_cntrl5.prefetcher.partial_hits            0
 system.ruby.l1_cntrl5.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl6.L1Dcache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        78056                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78056                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78084                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78084                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -442,8 +445,8 @@ system.ruby.l1_cntrl6.prefetcher.partial_hits            0
 system.ruby.l1_cntrl6.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl7.L1Dcache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        78357                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78357                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        78070                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78070                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -456,541 +459,541 @@ system.ruby.l1_cntrl7.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl7.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl7.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l2_cntrl0.L2cache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       626317                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       626338                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits           29                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       623394                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses       623423                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers00.percent_links_utilized     4.037004                      
-system.ruby.network.routers00.msg_count.Control::0        78425                      
-system.ruby.network.routers00.msg_count.Request_Control::2        76893                      
-system.ruby.network.routers00.msg_count.Response_Data::1        78968                      
-system.ruby.network.routers00.msg_count.Response_Control::1        65300                      
-system.ruby.network.routers00.msg_count.Response_Control::2        77769                      
-system.ruby.network.routers00.msg_count.Writeback_Data::0        14808                      
-system.ruby.network.routers00.msg_count.Writeback_Data::1        52104                      
-system.ruby.network.routers00.msg_count.Writeback_Control::0        26089                      
-system.ruby.network.routers00.msg_bytes.Control::0       627400                      
-system.ruby.network.routers00.msg_bytes.Request_Control::2       615144                      
-system.ruby.network.routers00.msg_bytes.Response_Data::1      5685696                      
-system.ruby.network.routers00.msg_bytes.Response_Control::1       522400                      
-system.ruby.network.routers00.msg_bytes.Response_Control::2       622152                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::0      1066176                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::1      3751488                      
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0       208712                      
-system.ruby.network.routers01.percent_links_utilized     4.037019                      
-system.ruby.network.routers01.msg_count.Control::0        78414                      
-system.ruby.network.routers01.msg_count.Request_Control::2        76799                      
-system.ruby.network.routers01.msg_count.Response_Data::1        79002                      
-system.ruby.network.routers01.msg_count.Response_Control::1        65210                      
-system.ruby.network.routers01.msg_count.Response_Control::2        77782                      
-system.ruby.network.routers01.msg_count.Writeback_Data::0        14737                      
-system.ruby.network.routers01.msg_count.Writeback_Data::1        52146                      
-system.ruby.network.routers01.msg_count.Writeback_Control::0        26232                      
-system.ruby.network.routers01.msg_bytes.Control::0       627312                      
-system.ruby.network.routers01.msg_bytes.Request_Control::2       614392                      
-system.ruby.network.routers01.msg_bytes.Response_Data::1      5688144                      
-system.ruby.network.routers01.msg_bytes.Response_Control::1       521680                      
-system.ruby.network.routers01.msg_bytes.Response_Control::2       622256                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::0      1061064                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::1      3754512                      
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0       209856                      
-system.ruby.network.routers02.percent_links_utilized     4.006533                      
-system.ruby.network.routers02.msg_count.Control::0        78001                      
-system.ruby.network.routers02.msg_count.Request_Control::2        76355                      
-system.ruby.network.routers02.msg_count.Response_Data::1        78521                      
-system.ruby.network.routers02.msg_count.Response_Control::1        64835                      
-system.ruby.network.routers02.msg_count.Response_Control::2        77400                      
-system.ruby.network.routers02.msg_count.Writeback_Data::0        14554                      
-system.ruby.network.routers02.msg_count.Writeback_Data::1        51648                      
-system.ruby.network.routers02.msg_count.Writeback_Control::0        25939                      
-system.ruby.network.routers02.msg_bytes.Control::0       624008                      
-system.ruby.network.routers02.msg_bytes.Request_Control::2       610840                      
-system.ruby.network.routers02.msg_bytes.Response_Data::1      5653512                      
-system.ruby.network.routers02.msg_bytes.Response_Control::1       518680                      
-system.ruby.network.routers02.msg_bytes.Response_Control::2       619200                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::0      1047888                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::1      3718656                      
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0       207512                      
-system.ruby.network.routers03.percent_links_utilized     4.041657                      
-system.ruby.network.routers03.msg_count.Control::0        78494                      
-system.ruby.network.routers03.msg_count.Request_Control::2        76865                      
-system.ruby.network.routers03.msg_count.Response_Data::1        79053                      
-system.ruby.network.routers03.msg_count.Response_Control::1        65335                      
-system.ruby.network.routers03.msg_count.Response_Control::2        77870                      
-system.ruby.network.routers03.msg_count.Writeback_Data::0        14768                      
-system.ruby.network.routers03.msg_count.Writeback_Data::1        52223                      
-system.ruby.network.routers03.msg_count.Writeback_Control::0        26323                      
-system.ruby.network.routers03.msg_bytes.Control::0       627952                      
-system.ruby.network.routers03.msg_bytes.Request_Control::2       614920                      
-system.ruby.network.routers03.msg_bytes.Response_Data::1      5691816                      
-system.ruby.network.routers03.msg_bytes.Response_Control::1       522680                      
-system.ruby.network.routers03.msg_bytes.Response_Control::2       622960                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::0      1063296                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::1      3760056                      
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0       210584                      
-system.ruby.network.routers04.percent_links_utilized     4.019913                      
-system.ruby.network.routers04.msg_count.Control::0        78222                      
-system.ruby.network.routers04.msg_count.Request_Control::2        76635                      
-system.ruby.network.routers04.msg_count.Response_Data::1        78766                      
-system.ruby.network.routers04.msg_count.Response_Control::1        65032                      
-system.ruby.network.routers04.msg_count.Response_Control::2        77609                      
-system.ruby.network.routers04.msg_count.Writeback_Data::0        14555                      
-system.ruby.network.routers04.msg_count.Writeback_Data::1        51885                      
-system.ruby.network.routers04.msg_count.Writeback_Control::0        26112                      
-system.ruby.network.routers04.msg_bytes.Control::0       625776                      
-system.ruby.network.routers04.msg_bytes.Request_Control::2       613080                      
-system.ruby.network.routers04.msg_bytes.Response_Data::1      5671152                      
-system.ruby.network.routers04.msg_bytes.Response_Control::1       520256                      
-system.ruby.network.routers04.msg_bytes.Response_Control::2       620872                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::0      1047960                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::1      3735720                      
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0       208896                      
-system.ruby.network.routers05.percent_links_utilized     4.036768                      
-system.ruby.network.routers05.msg_count.Control::0        78384                      
-system.ruby.network.routers05.msg_count.Request_Control::2        76802                      
-system.ruby.network.routers05.msg_count.Response_Data::1        78979                      
-system.ruby.network.routers05.msg_count.Response_Control::1        65382                      
-system.ruby.network.routers05.msg_count.Response_Control::2        77762                      
-system.ruby.network.routers05.msg_count.Writeback_Data::0        14815                      
-system.ruby.network.routers05.msg_count.Writeback_Data::1        52065                      
-system.ruby.network.routers05.msg_count.Writeback_Control::0        26239                      
-system.ruby.network.routers05.msg_bytes.Control::0       627072                      
-system.ruby.network.routers05.msg_bytes.Request_Control::2       614416                      
-system.ruby.network.routers05.msg_bytes.Response_Data::1      5686488                      
-system.ruby.network.routers05.msg_bytes.Response_Control::1       523056                      
-system.ruby.network.routers05.msg_bytes.Response_Control::2       622096                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::0      1066680                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::1      3748680                      
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0       209912                      
-system.ruby.network.routers06.percent_links_utilized     4.013530                      
-system.ruby.network.routers06.msg_count.Control::0        78056                      
-system.ruby.network.routers06.msg_count.Request_Control::2        76406                      
-system.ruby.network.routers06.msg_count.Response_Data::1        78589                      
-system.ruby.network.routers06.msg_count.Response_Control::1        64923                      
-system.ruby.network.routers06.msg_count.Response_Control::2        77431                      
-system.ruby.network.routers06.msg_count.Writeback_Data::0        14695                      
-system.ruby.network.routers06.msg_count.Writeback_Data::1        51730                      
-system.ruby.network.routers06.msg_count.Writeback_Control::0        25933                      
-system.ruby.network.routers06.msg_bytes.Control::0       624448                      
-system.ruby.network.routers06.msg_bytes.Request_Control::2       611248                      
-system.ruby.network.routers06.msg_bytes.Response_Data::1      5658408                      
-system.ruby.network.routers06.msg_bytes.Response_Control::1       519384                      
-system.ruby.network.routers06.msg_bytes.Response_Control::2       619448                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::0      1058040                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::1      3724560                      
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0       207464                      
-system.ruby.network.routers07.percent_links_utilized     4.029978                      
-system.ruby.network.routers07.msg_count.Control::0        78357                      
-system.ruby.network.routers07.msg_count.Request_Control::2        76601                      
-system.ruby.network.routers07.msg_count.Response_Data::1        78907                      
-system.ruby.network.routers07.msg_count.Response_Control::1        65200                      
-system.ruby.network.routers07.msg_count.Response_Control::2        77682                      
-system.ruby.network.routers07.msg_count.Writeback_Data::0        14815                      
-system.ruby.network.routers07.msg_count.Writeback_Data::1        51903                      
-system.ruby.network.routers07.msg_count.Writeback_Control::0        26081                      
-system.ruby.network.routers07.msg_bytes.Control::0       626856                      
-system.ruby.network.routers07.msg_bytes.Request_Control::2       612808                      
-system.ruby.network.routers07.msg_bytes.Response_Data::1      5681304                      
-system.ruby.network.routers07.msg_bytes.Response_Control::1       521600                      
-system.ruby.network.routers07.msg_bytes.Response_Control::2       621456                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::0      1066680                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::1      3737016                      
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0       208648                      
-system.ruby.network.routers08.percent_links_utilized    54.780178                      
-system.ruby.network.routers08.msg_count.Control::0      1247019                      
-system.ruby.network.routers08.msg_count.Request_Control::2       609515                      
-system.ruby.network.routers08.msg_count.Response_Data::1      1465708                      
-system.ruby.network.routers08.msg_count.Response_Control::1      1539449                      
-system.ruby.network.routers08.msg_count.Response_Control::2       621304                      
-system.ruby.network.routers08.msg_count.Writeback_Data::0       117747                      
-system.ruby.network.routers08.msg_count.Writeback_Data::1       415704                      
-system.ruby.network.routers08.msg_count.Writeback_Control::0       208948                      
-system.ruby.network.routers08.msg_bytes.Control::0      9976152                      
-system.ruby.network.routers08.msg_bytes.Request_Control::2      4876120                      
-system.ruby.network.routers08.msg_bytes.Response_Data::1    105530976                      
-system.ruby.network.routers08.msg_bytes.Response_Control::1     12315592                      
-system.ruby.network.routers08.msg_bytes.Response_Control::2      4970432                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::0      8477784                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::1     29930688                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0      1671584                      
-system.ruby.network.routers09.percent_links_utilized    22.762241                      
-system.ruby.network.routers09.msg_count.Control::0       620666                      
-system.ruby.network.routers09.msg_count.Response_Data::1       843706                      
-system.ruby.network.routers09.msg_count.Response_Control::1      1018272                      
-system.ruby.network.routers09.msg_bytes.Control::0      4965328                      
-system.ruby.network.routers09.msg_bytes.Response_Data::1     60746832                      
-system.ruby.network.routers09.msg_bytes.Response_Control::1      8146176                      
-system.ruby.network.routers10.percent_links_utilized    10.983016                      
-system.ruby.network.routers10.msg_count.Control::0      1247019                      
-system.ruby.network.routers10.msg_count.Request_Control::2       613356                      
-system.ruby.network.routers10.msg_count.Response_Data::1      1471359                      
-system.ruby.network.routers10.msg_count.Response_Control::1      1539469                      
-system.ruby.network.routers10.msg_count.Response_Control::2       621304                      
-system.ruby.network.routers10.msg_count.Writeback_Data::0       117747                      
-system.ruby.network.routers10.msg_count.Writeback_Data::1       415704                      
-system.ruby.network.routers10.msg_count.Writeback_Control::0       208948                      
-system.ruby.network.routers10.msg_bytes.Control::0      9976152                      
-system.ruby.network.routers10.msg_bytes.Request_Control::2      4906848                      
-system.ruby.network.routers10.msg_bytes.Response_Data::1    105937848                      
-system.ruby.network.routers10.msg_bytes.Response_Control::1     12315752                      
-system.ruby.network.routers10.msg_bytes.Response_Control::2      4970432                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::0      8477784                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::1     29930688                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0      1671584                      
-system.ruby.network.msg_count.Control         3741057                      
-system.ruby.network.msg_count.Request_Control      1836227                      
-system.ruby.network.msg_count.Response_Data      4411558                      
-system.ruby.network.msg_count.Response_Control      6482320                      
-system.ruby.network.msg_count.Writeback_Data      1600353                      
-system.ruby.network.msg_count.Writeback_Control       626844                      
-system.ruby.network.msg_byte.Control         29928456                      
-system.ruby.network.msg_byte.Request_Control     14689816                      
-system.ruby.network.msg_byte.Response_Data    317632176                      
-system.ruby.network.msg_byte.Response_Control     51858560                      
-system.ruby.network.msg_byte.Writeback_Data    115225416                      
-system.ruby.network.msg_byte.Writeback_Control      5014752                      
-system.ruby.network.routers00.throttle0.link_utilization     4.061181                      
-system.ruby.network.routers00.throttle0.msg_count.Request_Control::2        76893                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::1        78423                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::1        40901                      
-system.ruby.network.routers00.throttle0.msg_bytes.Request_Control::2       615144                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::1      5646456                      
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+system.ruby.network.routers09.throttle1.link_utilization    30.630344                      
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+system.ruby.network.routers10.throttle0.link_utilization     4.073126                      
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+system.ruby.network.routers10.throttle1.link_utilization     4.036477                      
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+system.ruby.network.routers10.throttle2.link_utilization     4.083726                      
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+system.ruby.network.routers10.throttle3.link_utilization     4.034132                      
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+system.ruby.network.routers10.throttle4.link_utilization     4.046690                      
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+system.ruby.network.routers10.throttle5.link_utilization     4.060558                      
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+system.ruby.network.routers10.throttle6.link_utilization     4.066919                      
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+system.ruby.network.routers10.throttle7.link_utilization     4.066701                      
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+system.ruby.network.routers10.throttle8.link_utilization    62.626117                      
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+system.ruby.network.routers10.throttle9.link_utilization    14.920739                      
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+system.ruby.network.routers10.throttle9.msg_count.Response_Data::1       221732                      
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+system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1      3168552                      
 system.ruby.delayVCHist.vnet_0::bucket_size         2048                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket        20479                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       1574320                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean       631.193011                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev      885.262867                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     1436392     91.24%     91.24% |      131487      8.35%     99.59% |        6055      0.38%     99.98% |         370      0.02%    100.00% |          13      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         1574320                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       1568858                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean       640.119386                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev      891.952930                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     1428254     91.04%     91.04% |      133920      8.54%     99.57% |        6363      0.41%     99.98% |         304      0.02%    100.00% |          15      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         1568858                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            8                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           79                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       2805873                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         2.261817                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        4.246713                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     2397962     85.46%     85.46% |      340890     12.15%     97.61% |       58848      2.10%     99.71% |        7632      0.27%     99.98% |         517      0.02%    100.00% |          24      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         2805873                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       2795245                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         2.269717                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        4.251012                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     2388876     85.46%     85.46% |      339265     12.14%     97.60% |       59099      2.11%     99.71% |        7462      0.27%     99.98% |         530      0.02%    100.00% |          12      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         2795245                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples        613356                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.009639                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.138885                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |      610408     99.52%     99.52% |           0      0.00%     99.52% |        2940      0.48%    100.00% |           0      0.00%    100.00% |           8      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total          613356                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples        610809                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.009522                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.137860                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |      607905     99.52%     99.52% |           0      0.00%     99.52% |        2900      0.47%    100.00% |           0      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total          610809                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size         1024                      
 system.ruby.LD.latency_hist::max_bucket         10239                      
-system.ruby.LD.latency_hist::samples           402616                      
-system.ruby.LD.latency_hist::mean         2072.049427                      
-system.ruby.LD.latency_hist::gmean        1588.762336                      
-system.ruby.LD.latency_hist::stdev        1228.569503                      
-system.ruby.LD.latency_hist              |      106527     26.46%     26.46% |       97059     24.11%     50.57% |       95427     23.70%     74.27% |       85360     21.20%     95.47% |       17986      4.47%     99.94% |         257      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             402616                      
+system.ruby.LD.latency_hist::samples           401087                      
+system.ruby.LD.latency_hist::mean         2069.126818                      
+system.ruby.LD.latency_hist::gmean        1613.676021                      
+system.ruby.LD.latency_hist::stdev        1198.428887                      
+system.ruby.LD.latency_hist              |      102022     25.44%     25.44% |      101345     25.27%     50.70% |       98349     24.52%     75.22% |       82950     20.68%     95.91% |       16249      4.05%     99.96% |         172      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total             401087                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples            6                      
+system.ruby.LD.hit_latency_hist::samples            5                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              6                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              5                      
 system.ruby.LD.miss_latency_hist::bucket_size         1024                      
 system.ruby.LD.miss_latency_hist::max_bucket        10239                      
-system.ruby.LD.miss_latency_hist::samples       402610                      
-system.ruby.LD.miss_latency_hist::mean    2072.080261                      
-system.ruby.LD.miss_latency_hist::gmean   1588.910848                      
-system.ruby.LD.miss_latency_hist::stdev   1228.552693                      
-system.ruby.LD.miss_latency_hist         |      106521     26.46%     26.46% |       97059     24.11%     50.57% |       95427     23.70%     74.27% |       85360     21.20%     95.47% |       17986      4.47%     99.94% |         257      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        402610                      
+system.ruby.LD.miss_latency_hist::samples       401082                      
+system.ruby.LD.miss_latency_hist::mean    2069.152575                      
+system.ruby.LD.miss_latency_hist::gmean   1613.802512                      
+system.ruby.LD.miss_latency_hist::stdev   1198.414154                      
+system.ruby.LD.miss_latency_hist         |      102017     25.44%     25.44% |      101345     25.27%     50.70% |       98349     24.52%     75.22% |       82950     20.68%     95.91% |       16249      4.05%     99.96% |         172      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        401082                      
 system.ruby.ST.latency_hist::bucket_size         1024                      
 system.ruby.ST.latency_hist::max_bucket         10239                      
-system.ruby.ST.latency_hist::samples           223726                      
-system.ruby.ST.latency_hist::mean         2071.684565                      
-system.ruby.ST.latency_hist::gmean        1587.500627                      
-system.ruby.ST.latency_hist::stdev        1229.317345                      
-system.ruby.ST.latency_hist              |       59319     26.51%     26.51% |       53917     24.10%     50.61% |       52958     23.67%     74.28% |       47330     21.16%     95.44% |       10077      4.50%     99.94% |         125      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             223726                      
+system.ruby.ST.latency_hist::samples           222338                      
+system.ruby.ST.latency_hist::mean         2072.432207                      
+system.ruby.ST.latency_hist::gmean        1618.718174                      
+system.ruby.ST.latency_hist::stdev        1196.619363                      
+system.ruby.ST.latency_hist              |       56270     25.31%     25.31% |       56329     25.33%     50.64% |       54797     24.65%     75.29% |       45765     20.58%     95.87% |        9068      4.08%     99.95% |         109      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total             222338                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
 system.ruby.ST.hit_latency_hist::samples            3                      
@@ -1000,215 +1003,213 @@ system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |
 system.ruby.ST.hit_latency_hist::total              3                      
 system.ruby.ST.miss_latency_hist::bucket_size         1024                      
 system.ruby.ST.miss_latency_hist::max_bucket        10239                      
-system.ruby.ST.miss_latency_hist::samples       223723                      
-system.ruby.ST.miss_latency_hist::mean    2071.712305                      
-system.ruby.ST.miss_latency_hist::gmean   1587.634133                      
-system.ruby.ST.miss_latency_hist::stdev   1229.302246                      
-system.ruby.ST.miss_latency_hist         |       59316     26.51%     26.51% |       53917     24.10%     50.61% |       52958     23.67%     74.28% |       47330     21.16%     95.44% |       10077      4.50%     99.94% |         125      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        223723                      
-system.ruby.Directory_Controller.Fetch         620666      0.00%      0.00%
-system.ruby.Directory_Controller.Data          223044      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       620662      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       223044      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement       397614      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       620666      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data        223044      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement       397614      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       620662      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack       223044      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load      |       50387     12.51%     12.51% |       50364     12.51%     25.02% |       50179     12.46%     37.49% |       50465     12.53%     50.02% |       50375     12.51%     62.53% |       50436     12.53%     75.06% |       50129     12.45%     87.51% |       50302     12.49%    100.00%
-system.ruby.L1Cache_Controller.Load::total       402637                      
-system.ruby.L1Cache_Controller.Store     |       28042     12.53%     12.53% |       28053     12.54%     25.07% |       27828     12.44%     37.51% |       28030     12.53%     50.04% |       27852     12.45%     62.48% |       27954     12.49%     74.98% |       27928     12.48%     87.46% |       28057     12.54%    100.00%
-system.ruby.L1Cache_Controller.Store::total       223744                      
-system.ruby.L1Cache_Controller.Inv       |       76503     12.54%     12.54% |       76387     12.52%     25.05% |       75991     12.45%     37.51% |       76469     12.53%     50.04% |       76247     12.49%     62.53% |       76392     12.52%     75.05% |       76025     12.46%     87.51% |       76209     12.49%    100.00%
-system.ruby.L1Cache_Controller.Inv::total       610223                      
-system.ruby.L1Cache_Controller.L1_Replacement |      552329     12.49%     12.49% |      554080     12.53%     25.02% |      551001     12.46%     37.48% |      553019     12.51%     49.99% |      552775     12.50%     62.49% |      553813     12.53%     75.02% |      551589     12.47%     87.49% |      552978     12.51%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      4421584                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |         235     12.95%     12.95% |         233     12.84%     25.80% |         206     11.36%     37.16% |         229     12.62%     49.78% |         229     12.62%     62.40% |         224     12.35%     74.75% |         227     12.51%     87.27% |         231     12.73%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         1814                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |         155     11.75%     11.75% |         179     13.57%     25.32% |         158     11.98%     37.30% |         167     12.66%     49.96% |         159     12.05%     62.02% |         186     14.10%     76.12% |         154     11.68%     87.79% |         161     12.21%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total         1319                      
-system.ruby.L1Cache_Controller.Data      |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Data::total           10                      
-system.ruby.L1Cache_Controller.Data_Exclusive |       49564     12.51%     12.51% |       49570     12.51%     25.02% |       49411     12.47%     37.49% |       49662     12.53%     50.02% |       49589     12.51%     62.53% |       49661     12.53%     75.07% |       49353     12.45%     87.52% |       49453     12.48%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total       396263                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |         167     12.66%     12.66% |         162     12.28%     24.94% |         164     12.43%     37.38% |         179     13.57%     50.95% |         170     12.89%     63.84% |         150     11.37%     75.21% |         153     11.60%     86.81% |         174     13.19%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total         1319                      
-system.ruby.L1Cache_Controller.Data_all_Acks |       28690     12.54%     12.54% |       28678     12.54%     25.08% |       28423     12.43%     37.51% |       28648     12.52%     50.03% |       28457     12.44%     62.47% |       28571     12.49%     74.96% |       28547     12.48%     87.44% |       28727     12.56%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total       228741                      
-system.ruby.L1Cache_Controller.Ack       |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Ack::total           10                      
-system.ruby.L1Cache_Controller.Ack_all   |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total           10                      
-system.ruby.L1Cache_Controller.WB_Ack    |       40897     12.52%     12.52% |       40967     12.54%     25.06% |       40490     12.39%     37.45% |       41087     12.58%     50.03% |       40664     12.45%     62.48% |       41053     12.57%     75.05% |       40626     12.44%     87.48% |       40894     12.52%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total       326678                      
-system.ruby.L1Cache_Controller.NP.Load   |       50378     12.51%     12.51% |       50348     12.51%     25.02% |       50170     12.46%     37.48% |       50455     12.53%     50.02% |       50362     12.51%     62.53% |       50427     12.53%     75.06% |       50123     12.45%     87.51% |       50292     12.49%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total       402555                      
-system.ruby.L1Cache_Controller.NP.Store  |       28035     12.53%     12.53% |       28046     12.54%     25.07% |       27823     12.44%     37.51% |       28023     12.53%     50.04% |       27848     12.45%     62.49% |       27949     12.49%     74.98% |       27917     12.48%     87.46% |       28052     12.54%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       223693                      
-system.ruby.L1Cache_Controller.NP.Inv    |         220     12.34%     12.34% |         229     12.84%     25.18% |         209     11.72%     36.90% |         233     13.07%     49.97% |         235     13.18%     63.15% |         247     13.85%     77.01% |         202     11.33%     88.33% |         208     11.67%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         1783                      
-system.ruby.L1Cache_Controller.I.Load    |           7     10.94%     10.94% |          14     21.88%     32.81% |           4      6.25%     39.06% |          10     15.62%     54.69% |           9     14.06%     68.75% |           6      9.38%     78.12% |           6      9.38%     87.50% |           8     12.50%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total           64                      
-system.ruby.L1Cache_Controller.I.Store   |           5     11.63%     11.63% |           6     13.95%     25.58% |           4      9.30%     34.88% |           6     13.95%     48.84% |           3      6.98%     55.81% |           4      9.30%     65.12% |          10     23.26%     88.37% |           5     11.63%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total           43                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |       37358     12.52%     12.52% |       37278     12.50%     25.02% |       37354     12.52%     37.54% |       37224     12.48%     50.02% |       37375     12.53%     62.54% |       37164     12.46%     75.00% |       37269     12.49%     87.49% |       37314     12.51%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total       298336                      
-system.ruby.L1Cache_Controller.S.Inv     |         693     12.90%     12.90% |         679     12.64%     25.54% |         642     11.95%     37.48% |         666     12.40%     49.88% |         649     12.08%     61.96% |         646     12.02%     73.98% |         661     12.30%     86.28% |         737     13.72%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total         5373                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |         154     13.01%     13.01% |         143     12.08%     25.08% |         142     11.99%     37.08% |         159     13.43%     50.51% |         164     13.85%     64.36% |         153     12.92%     77.28% |         139     11.74%     89.02% |         130     10.98%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total         1184                      
-system.ruby.L1Cache_Controller.E.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     60.00%     60.00% |           0      0.00%     60.00% |           2     40.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total            5                      
-system.ruby.L1Cache_Controller.E.Store   |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.E.Store::total            3                      
-system.ruby.L1Cache_Controller.E.Inv     |       23423     12.54%     12.54% |       23271     12.45%     24.99% |       23422     12.53%     37.52% |       23280     12.46%     49.98% |       23423     12.54%     62.52% |       23370     12.51%     75.03% |       23365     12.50%     87.53% |       23299     12.47%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total       186853                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |       26089     12.49%     12.49% |       26232     12.55%     25.04% |       25939     12.41%     37.45% |       26323     12.60%     50.05% |       26112     12.50%     62.55% |       26240     12.56%     75.11% |       25933     12.41%     87.52% |       26081     12.48%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total       208949                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |          45     11.25%     11.25% |          58     14.50%     25.75% |          43     10.75%     36.50% |          53     13.25%     49.75% |          43     10.75%     60.50% |          45     11.25%     71.75% |          50     12.50%     84.25% |          63     15.75%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          400                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |           6     10.71%     10.71% |           8     14.29%     25.00% |           7     12.50%     37.50% |           5      8.93%     46.43% |          10     17.86%     64.29% |           6     10.71%     75.00% |           5      8.93%     83.93% |           9     16.07%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total           56                      
-system.ruby.L1Cache_Controller.M.Load    |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total            1                      
-system.ruby.L1Cache_Controller.M.Inv     |       13143     12.49%     12.49% |       13204     12.55%     25.04% |       13192     12.54%     37.57% |       13169     12.51%     50.09% |       13209     12.55%     62.64% |       13024     12.38%     75.01% |       13141     12.49%     87.50% |       13152     12.50%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total       105234                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |       14808     12.58%     12.58% |       14737     12.52%     25.09% |       14554     12.36%     37.45% |       14768     12.54%     49.99% |       14555     12.36%     62.36% |       14815     12.58%     74.94% |       14695     12.48%     87.42% |       14815     12.58%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       117747                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |          28     10.57%     10.57% |          45     16.98%     27.55% |          23      8.68%     36.23% |          29     10.94%     47.17% |          27     10.19%     57.36% |          50     18.87%     76.23% |          29     10.94%     87.17% |          34     12.83%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total          265                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |          60     12.50%     12.50% |          65     13.54%     26.04% |          56     11.67%     37.71% |          64     13.33%     51.04% |          59     12.29%     63.33% |          62     12.92%     76.25% |          60     12.50%     88.75% |          54     11.25%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total          480                      
-system.ruby.L1Cache_Controller.IS.Inv    |          40     12.27%     12.27% |          42     12.88%     25.15% |          42     12.88%     38.04% |          43     13.19%     51.23% |          36     11.04%     62.27% |          40     12.27%     74.54% |          41     12.58%     87.12% |          42     12.88%    100.00%
-system.ruby.L1Cache_Controller.IS.Inv::total          326                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |      304582     12.48%     12.48% |      306242     12.55%     25.03% |      304848     12.49%     37.52% |      305151     12.51%     50.03% |      305139     12.50%     62.53% |      305447     12.52%     75.05% |      304421     12.48%     87.53% |      304369     12.47%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total      2440199                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |       49564     12.51%     12.51% |       49570     12.51%     25.02% |       49411     12.47%     37.49% |       49662     12.53%     50.02% |       49589     12.51%     62.53% |       49661     12.53%     75.07% |       49353     12.45%     87.52% |       49453     12.48%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total       396263                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |         167     12.66%     12.66% |         162     12.28%     24.94% |         164     12.43%     37.38% |         179     13.57%     50.95% |         170     12.89%     63.84% |         150     11.37%     75.21% |         153     11.60%     86.81% |         174     13.19%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total         1319                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |         614     13.06%     13.06% |         587     12.48%     25.54% |         557     11.85%     37.39% |         577     12.27%     49.66% |         574     12.21%     61.87% |         581     12.36%     74.22% |         582     12.38%     86.60% |         630     13.40%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total         4702                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |      169338     12.50%     12.50% |      169448     12.50%     25.00% |      168164     12.41%     37.41% |      169394     12.50%     49.91% |      169430     12.50%     62.41% |      169994     12.54%     74.96% |      169132     12.48%     87.44% |      170269     12.56%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total      1355169                      
-system.ruby.L1Cache_Controller.IM.Data   |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total           10                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |       28036     12.53%     12.53% |       28049     12.54%     25.07% |       27824     12.44%     37.51% |       28028     12.53%     50.04% |       27847     12.45%     62.48% |       27950     12.49%     74.98% |       27924     12.48%     87.46% |       28055     12.54%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       223713                      
-system.ruby.L1Cache_Controller.SM.Ack    |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total           10                      
-system.ruby.L1Cache_Controller.SM.Ack_all |           2     20.00%     20.00% |           1     10.00%     30.00% |           1     10.00%     40.00% |           1     10.00%     50.00% |           3     30.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total           10                      
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks |          40     12.27%     12.27% |          42     12.88%     25.15% |          42     12.88%     38.04% |          43     13.19%     51.23% |          36     11.04%     62.27% |          40     12.27%     74.54% |          41     12.58%     87.12% |          42     12.88%    100.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total          326                      
-system.ruby.L1Cache_Controller.M_I.Load  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.M_I.Load::total            2                      
-system.ruby.L1Cache_Controller.M_I.Store |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M_I.Store::total            1                      
-system.ruby.L1Cache_Controller.M_I.Inv   |       38961     12.55%     12.55% |       38942     12.54%     25.09% |       38456     12.39%     37.48% |       39054     12.58%     50.06% |       38676     12.46%     62.51% |       39041     12.57%     75.09% |       38589     12.43%     87.52% |       38751     12.48%    100.00%
-system.ruby.L1Cache_Controller.M_I.Inv::total       310470                      
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX |         162     14.10%     14.10% |         130     11.31%     25.41% |         140     12.18%     37.60% |         147     12.79%     50.39% |         159     13.84%     64.23% |         129     11.23%     75.46% |         148     12.88%     88.34% |         134     11.66%    100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total         1149                      
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS |          89     11.37%     11.37% |         106     13.54%     24.90% |          95     12.13%     37.04% |          98     12.52%     49.55% |          90     11.49%     61.05% |         118     15.07%     76.12% |          89     11.37%     87.48% |          98     12.52%    100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total          783                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |        1685     11.79%     11.79% |        1791     12.53%     24.32% |        1802     12.61%     36.93% |        1792     12.54%     49.46% |        1742     12.19%     61.65% |        1766     12.36%     74.01% |        1802     12.61%     86.62% |        1913     13.38%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total        14293                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load |           1     10.00%     10.00% |           2     20.00%     30.00% |           2     20.00%     50.00% |           0      0.00%     50.00% |           2     20.00%     70.00% |           2     20.00%     90.00% |           0      0.00%     90.00% |           1     10.00%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total           10                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::samples       222335                      
+system.ruby.ST.miss_latency_hist::mean    2072.460130                      
+system.ruby.ST.miss_latency_hist::gmean   1618.855581                      
+system.ruby.ST.miss_latency_hist::stdev   1196.603290                      
+system.ruby.ST.miss_latency_hist         |       56267     25.31%     25.31% |       56329     25.34%     50.64% |       54797     24.65%     75.29% |       45765     20.58%     95.87% |        9068      4.08%     99.95% |         109      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        222335                      
+system.ruby.Directory_Controller.Fetch         617810      0.00%      0.00%
+system.ruby.Directory_Controller.Data          221732      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       617805      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       221732      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement       396069      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch       617810      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data        221732      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement       396069      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       617805      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack       221732      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load      |       50630     12.62%     12.62% |       49663     12.38%     25.00% |       50388     12.56%     37.57% |       49765     12.41%     49.97% |       49962     12.46%     62.43% |       50103     12.49%     74.92% |       50413     12.57%     87.49% |       50187     12.51%    100.00%
+system.ruby.L1Cache_Controller.Load::total       401111                      
+system.ruby.L1Cache_Controller.Store     |       27600     12.41%     12.41% |       27856     12.53%     24.94% |       28004     12.59%     37.54% |       27726     12.47%     50.00% |       27753     12.48%     62.49% |       27852     12.53%     75.01% |       27673     12.45%     87.46% |       27886     12.54%    100.00%
+system.ruby.L1Cache_Controller.Store::total       222350                      
+system.ruby.L1Cache_Controller.Inv       |       76146     12.53%     12.53% |       75657     12.45%     24.98% |       76432     12.58%     37.55% |       75459     12.42%     49.97% |       75850     12.48%     62.45% |       76014     12.51%     74.95% |       76119     12.52%     87.48% |       76126     12.52%    100.00%
+system.ruby.L1Cache_Controller.Inv::total       607803                      
+system.ruby.L1Cache_Controller.L1_Replacement |      552196     12.54%     12.54% |      550326     12.50%     25.04% |      552899     12.56%     37.60% |      548553     12.46%     50.06% |      549178     12.47%     62.53% |      548891     12.47%     75.00% |      551846     12.53%     87.53% |      548920     12.47%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      4402809                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |         232     13.19%     13.19% |         234     13.30%     26.49% |         225     12.79%     39.28% |         210     11.94%     51.22% |         213     12.11%     63.33% |         216     12.28%     75.61% |         231     13.13%     88.74% |         198     11.26%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         1759                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |         184     14.76%     14.76% |         144     11.55%     26.30% |         143     11.47%     37.77% |         160     12.83%     50.60% |         162     12.99%     63.59% |         154     12.35%     75.94% |         135     10.83%     86.77% |         165     13.23%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total         1247                      
+system.ruby.L1Cache_Controller.Data      |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.Data::total           11                      
+system.ruby.L1Cache_Controller.Data_Exclusive |       49783     12.61%     12.61% |       48864     12.38%     24.99% |       49581     12.56%     37.56% |       48942     12.40%     49.96% |       49189     12.46%     62.42% |       49331     12.50%     74.92% |       49626     12.57%     87.49% |       49364     12.51%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total       394680                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |         168     13.47%     13.47% |         154     12.35%     25.82% |         157     12.59%     38.41% |         164     13.15%     51.56% |         141     11.31%     62.87% |         150     12.03%     74.90% |         155     12.43%     87.33% |         158     12.67%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total         1247                      
+system.ruby.L1Cache_Controller.Data_all_Acks |       28276     12.43%     12.43% |       28494     12.53%     24.96% |       28649     12.59%     37.55% |       28378     12.47%     50.03% |       28378     12.47%     62.50% |       28465     12.51%     75.01% |       28297     12.44%     87.45% |       28542     12.55%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total       227479                      
+system.ruby.L1Cache_Controller.Ack       |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.Ack::total           11                      
+system.ruby.L1Cache_Controller.Ack_all   |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total           11                      
+system.ruby.L1Cache_Controller.WB_Ack    |       40932     12.51%     12.51% |       40469     12.37%     24.88% |       41392     12.65%     37.53% |       40465     12.37%     49.90% |       40593     12.41%     62.31% |       41093     12.56%     74.87% |       41076     12.55%     87.42% |       41154     12.58%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total       327174                      
+system.ruby.L1Cache_Controller.NP.Load   |       50624     12.62%     12.62% |       49650     12.38%     25.00% |       50379     12.56%     37.57% |       49757     12.41%     49.97% |       49954     12.46%     62.43% |       50092     12.49%     74.92% |       50401     12.57%     87.49% |       50176     12.51%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total       401033                      
+system.ruby.L1Cache_Controller.NP.Store  |       27589     12.41%     12.41% |       27853     12.53%     24.94% |       28000     12.60%     37.53% |       27722     12.47%     50.00% |       27749     12.48%     62.49% |       27841     12.52%     75.01% |       27669     12.45%     87.46% |       27884     12.54%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       222307                      
+system.ruby.L1Cache_Controller.NP.Inv    |         234     14.18%     14.18% |         198     12.00%     26.18% |         204     12.36%     38.55% |         217     13.15%     51.70% |         207     12.55%     64.24% |         208     12.61%     76.85% |         164      9.94%     86.79% |         218     13.21%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         1650                      
+system.ruby.L1Cache_Controller.I.Load    |           6      9.09%      9.09% |          11     16.67%     25.76% |           8     12.12%     37.88% |           8     12.12%     50.00% |           6      9.09%     59.09% |           8     12.12%     71.21% |          11     16.67%     87.88% |           8     12.12%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total           66                      
+system.ruby.L1Cache_Controller.I.Store   |          10     27.78%     27.78% |           3      8.33%     36.11% |           3      8.33%     44.44% |           3      8.33%     52.78% |           3      8.33%     61.11% |           9     25.00%     86.11% |           3      8.33%     94.44% |           2      5.56%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total           36                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |       37124     12.58%     12.58% |       36897     12.51%     25.09% |       36843     12.49%     37.58% |       36860     12.49%     50.07% |       36970     12.53%     62.61% |       36689     12.44%     75.04% |       36882     12.50%     87.54% |       36746     12.46%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total       295011                      
+system.ruby.L1Cache_Controller.S.Inv     |         743     13.54%     13.54% |         675     12.30%     25.83% |         689     12.55%     38.39% |         684     12.46%     50.85% |         663     12.08%     62.93% |         649     11.82%     74.75% |         686     12.50%     87.25% |         700     12.75%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total         5489                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |         149     13.41%     13.41% |         132     11.88%     25.29% |         139     12.51%     37.80% |         149     13.41%     51.22% |         136     12.24%     63.46% |         146     13.14%     76.60% |         106      9.54%     86.14% |         154     13.86%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total         1111                      
+system.ruby.L1Cache_Controller.E.Load    |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total            2                      
+system.ruby.L1Cache_Controller.E.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.E.Store::total            2                      
+system.ruby.L1Cache_Controller.E.Inv     |       23229     12.57%     12.57% |       22892     12.39%     24.96% |       23105     12.50%     37.46% |       23121     12.51%     49.98% |       23143     12.52%     62.50% |       23004     12.45%     74.95% |       23259     12.59%     87.54% |       23027     12.46%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total       184780                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |       26480     12.65%     12.65% |       25896     12.37%     25.02% |       26409     12.61%     37.63% |       25762     12.30%     49.94% |       25986     12.41%     62.35% |       26263     12.54%     74.89% |       26302     12.56%     87.45% |       26267     12.55%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total       209365                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |          64     13.53%     13.53% |          68     14.38%     27.91% |          60     12.68%     40.59% |          56     11.84%     52.43% |          51     10.78%     63.21% |          52     10.99%     74.21% |          58     12.26%     86.47% |          64     13.53%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          473                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |          10     16.95%     16.95% |           8     13.56%     30.51% |           6     10.17%     40.68% |           3      5.08%     45.76% |           8     13.56%     59.32% |          11     18.64%     77.97% |           7     11.86%     89.83% |           6     10.17%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total           59                      
+system.ruby.L1Cache_Controller.M.Load    |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total            3                      
+system.ruby.L1Cache_Controller.M.Store   |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total            1                      
+system.ruby.L1Cache_Controller.M.Inv     |       13045     12.57%     12.57% |       13205     12.72%     25.29% |       12928     12.45%     37.74% |       12932     12.46%     50.20% |       13051     12.57%     62.77% |       12938     12.46%     75.23% |       12814     12.34%     87.58% |       12896     12.42%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total       103809                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |       14456     12.27%     12.27% |       14574     12.37%     24.64% |       14984     12.72%     37.36% |       14704     12.48%     49.84% |       14607     12.40%     62.23% |       14831     12.59%     74.82% |       14776     12.54%     87.36% |       14889     12.64%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       117821                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |          27     11.25%     11.25% |          30     12.50%     23.75% |          39     16.25%     40.00% |          30     12.50%     52.50% |          32     13.33%     65.83% |          24     10.00%     75.83% |          31     12.92%     88.75% |          27     11.25%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total          240                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |          68     14.59%     14.59% |          47     10.09%     24.68% |          53     11.37%     36.05% |          58     12.45%     48.50% |          61     13.09%     61.59% |          55     11.80%     73.39% |          50     10.73%     84.12% |          74     15.88%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total          466                      
+system.ruby.L1Cache_Controller.IS.Inv    |          33     10.09%     10.09% |          43     13.15%     23.24% |          34     10.40%     33.64% |          48     14.68%     48.32% |          39     11.93%     60.24% |          40     12.23%     72.48% |          48     14.68%     87.16% |          42     12.84%    100.00%
+system.ruby.L1Cache_Controller.IS.Inv::total          327                      
+system.ruby.L1Cache_Controller.IS.L1_Replacement |      306619     12.62%     12.62% |      302229     12.44%     25.06% |      305593     12.58%     37.64% |      302624     12.46%     50.10% |      302601     12.46%     62.56% |      301776     12.42%     74.98% |      305829     12.59%     87.57% |      301854     12.43%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total      2429125                      
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |       49783     12.61%     12.61% |       48864     12.38%     24.99% |       49581     12.56%     37.56% |       48942     12.40%     49.96% |       49189     12.46%     62.42% |       49331     12.50%     74.92% |       49626     12.57%     87.49% |       49364     12.51%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total       394680                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |         168     13.47%     13.47% |         154     12.35%     25.82% |         157     12.59%     38.41% |         164     13.15%     51.56% |         141     11.31%     62.87% |         150     12.03%     74.90% |         155     12.43%     87.33% |         158     12.67%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total         1247                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |         646     13.38%     13.38% |         598     12.39%     25.77% |         612     12.68%     38.44% |         608     12.59%     51.04% |         589     12.20%     63.24% |         579     11.99%     75.23% |         580     12.01%     87.24% |         616     12.76%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total         4828                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |      167368     12.39%     12.39% |      170598     12.63%     25.03% |      168931     12.51%     37.54% |      168454     12.47%     50.01% |      168878     12.51%     62.52% |      169186     12.53%     75.05% |      167951     12.44%     87.48% |      169010     12.52%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total      1350376                      
+system.ruby.L1Cache_Controller.IM.Data   |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total           11                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |       27597     12.41%     12.41% |       27853     12.53%     24.94% |       28003     12.60%     37.54% |       27722     12.47%     50.01% |       27750     12.48%     62.49% |       27846     12.52%     75.01% |       27669     12.45%     87.46% |       27884     12.54%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       222324                      
+system.ruby.L1Cache_Controller.SM.Ack    |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total           11                      
+system.ruby.L1Cache_Controller.SM.Ack_all |           0      0.00%      0.00% |           3     27.27%     27.27% |           0      0.00%     27.27% |           2     18.18%     45.45% |           1      9.09%     54.55% |           1      9.09%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total           11                      
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks |          33     10.09%     10.09% |          43     13.15%     23.24% |          34     10.40%     33.64% |          48     14.68%     48.32% |          39     11.93%     60.24% |          40     12.23%     72.48% |          48     14.68%     87.16% |          42     12.84%    100.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total          327                      
+system.ruby.L1Cache_Controller.M_I.Inv   |       38841     12.47%     12.47% |       38621     12.40%     24.86% |       39453     12.66%     37.53% |       38426     12.33%     49.86% |       38725     12.43%     62.29% |       39149     12.57%     74.85% |       39128     12.56%     87.41% |       39222     12.59%    100.00%
+system.ruby.L1Cache_Controller.M_I.Inv::total       311565                      
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX |         141     13.48%     13.48% |         136     13.00%     26.48% |         126     12.05%     38.53% |         124     11.85%     50.38% |         130     12.43%     62.81% |         140     13.38%     76.20% |         142     13.58%     89.77% |         107     10.23%    100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total         1046                      
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS |         106     14.68%     14.68% |          89     12.33%     27.01% |          84     11.63%     38.64% |          99     13.71%     52.35% |          93     12.88%     65.24% |          88     12.19%     77.42% |          78     10.80%     88.23% |          85     11.77%    100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total          722                      
+system.ruby.L1Cache_Controller.M_I.WB_Ack |        1848     13.34%     13.34% |        1624     11.72%     25.06% |        1730     12.49%     37.55% |        1817     13.12%     50.67% |        1645     11.87%     62.54% |        1717     12.39%     74.94% |        1730     12.49%     87.43% |        1742     12.57%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total        13853                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     14.29%     14.29% |           0      0.00%     14.29% |           0      0.00%     14.29% |           2     28.57%     42.86% |           1     14.29%     57.14% |           3     42.86%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total            7                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Store |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           1     25.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total            4                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv |          23     12.50%     12.50% |          20     10.87%     23.37% |          28     15.22%     38.59% |          24     13.04%     51.63% |          19     10.33%     61.96% |          24     13.04%     75.00% |          26     14.13%     89.13% |          20     10.87%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total          184                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |       39212     12.55%     12.55% |       39176     12.54%     25.09% |       38688     12.38%     37.48% |       39295     12.58%     50.06% |       38922     12.46%     62.52% |       39287     12.58%     75.09% |       38824     12.43%     87.52% |       38981     12.48%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total       312385                      
-system.ruby.L2Cache_Controller.L1_GETS         404349      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         226057      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX          16561      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old       317938      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement         6824      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean      4940882      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        620662      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         620658      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data         217651      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean       199372      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               3831      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all         190668      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock           1319      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock       619985      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       398766      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       221900      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old       308113      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX           10      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX          604      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX_old            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement         1242      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         2573      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS            4      0.00%      0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv |          21     11.48%     11.48% |          23     12.57%     24.04% |          19     10.38%     34.43% |          31     16.94%     51.37% |          22     12.02%     63.39% |          26     14.21%     77.60% |          20     10.93%     88.52% |          21     11.48%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total          183                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |       39084     12.47%     12.47% |       38845     12.40%     24.87% |       39662     12.66%     37.53% |       38648     12.33%     49.87% |       38948     12.43%     62.30% |       39376     12.57%     74.86% |       39346     12.56%     87.42% |       39412     12.58%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total       313321                      
+system.ruby.L2Cache_Controller.L1_GETS         402675      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         224636      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX          15857      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old       318841      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement         6494      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean      4974808      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        617805      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         617799      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data         216590      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean       200031      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               3820      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all         188587      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock           1247      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock       617014      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       397247      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       220563      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old       309284      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTX          544      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTX_old            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement         1161      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         2646      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS            9      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETX            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement         5399      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean         8887      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS         1319      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX         1814      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX        14293      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX_old          864      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean       602549      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETS           16      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETX           22      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old         2197      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       620658      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETS           70      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETX           61      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old         6155      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data       216395      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean       199302      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all       186852      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           2585      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         2573      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.L1_PUTX_old            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack           1246      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all         1242      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETS         2506      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETX         1362      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_PUTX_old          291      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean      2164243      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data       396259      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETS           12      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETX            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L1_PUTX_old            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean        13776      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data         2506      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETS         1516      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETX          804      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_PUTX_old          310      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean      1208415      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       221897      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_PUTX            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock           10      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS          132      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX           72      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX          992      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement         5141      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean         8700      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS         1247      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX         1759      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX        13853      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old          788      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement            9      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean       600145      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETS           23      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETX           21      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old         2121      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       617799      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data_clean            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETS           48      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETX           73      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old         6058      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data       215422      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean       199947      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all       184776      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           2654      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         2646      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack           1166      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all         1161      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETS         2571      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETX         1408      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_PUTX_old          278      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean      2181712      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data       394672      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETS            7      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETX            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean        14929      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data         2571      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETS         1372      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETX          722      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_PUTX_old          300      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean      1221486      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       220562      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_PUTX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean           46      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS          139      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX           68      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX          875      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean       937127      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock       619975      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETS            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETX            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX          668      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean         3309      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data         1048      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean           49      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock          222      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.L1_PUTX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data          201      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean           21      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean       942368      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock       617003      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_GETS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_GETX            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX          583      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean         2761      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data          953      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean           59      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock          235      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data          211      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean           24      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_SB.L1_PUTX            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_SB.L2_Replacement          175      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock         1097      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock         1012      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index 565004605..528acac96 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.007434                       # Number of seconds simulated
-sim_ticks                                     7434347                       # Number of ticks simulated
-final_tick                                    7434347                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.007450                       # Number of seconds simulated
+sim_ticks                                     7449950                       # Number of ticks simulated
+final_tick                                    7449950                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  60462                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 481612                       # Number of bytes of host memory used
-host_seconds                                   122.96                       # Real time elapsed on the host
+host_tick_rate                                  57472                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 537872                       # Number of bytes of host memory used
+host_seconds                                   129.63                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39396928                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           39396928                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14155776                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total        14155776                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       615577                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              615577                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       221184                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             221184                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   5299312502                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            5299312502                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1904104826                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1904104826                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   7203417328                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           7203417328                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      615577                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     221184                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    615577                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   221184                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               38921664                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                  475264                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                14074624                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                39396928                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys             14155776                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                   7426                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                  1246                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39430656                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           39430656                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14218432                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total        14218432                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       616104                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              616104                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       222163                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             222163                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   5292741025                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            5292741025                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   1908527171                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           1908527171                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   7201268196                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           7201268196                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      616105                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     222163                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    616105                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   222163                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               38949632                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                  481088                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                14133568                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                39430720                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys             14218432                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                   7517                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                  1302                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             76166                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             75916                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             76401                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             76284                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             75567                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             76286                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             75866                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             75665                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             75571                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             76259                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             76117                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             76093                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             76223                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             75989                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             76244                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             76092                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::10                0                       # Per bank write bursts
@@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0             27493                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1             27659                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2             27618                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3             27743                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4             27329                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5             27461                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6             27226                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7             27387                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             27477                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1             27606                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2             27738                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3             27573                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4             27439                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5             27783                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6             27594                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7             27627                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
@@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                       7434244                       # Total gap between requests
+system.mem_ctrls.totGap                       7449899                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                615577                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                616105                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               221184                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                   31005                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                   21298                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                   21020                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                   21014                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                   21010                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                   20998                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                   20995                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                   20996                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8                   21008                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9                   21051                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10                  21087                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11                  21106                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12                  21092                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13                  21036                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14                  21043                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15                  20930                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16                  20829                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17                  20806                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18                  21402                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19                  23417                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20                  20537                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21                  20504                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22                  20662                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23                  21143                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24                  19571                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25                  18774                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26                  17341                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27                  14959                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28                  11156                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29                   6941                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30                   2864                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31                    556                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               222163                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                   30549                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                   21596                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                   21192                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                   21113                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                   21031                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                   21028                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                   20998                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                   21010                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::8                   21064                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::9                   21087                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::10                  21110                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::11                  21124                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::12                  21122                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::13                  21081                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::14                  21079                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::15                  20997                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::16                  20881                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::17                  20859                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::18                  21404                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::19                  23415                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::20                  20541                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::21                  20538                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::22                  20723                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::23                  21180                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::24                  19536                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::25                  18735                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::26                  17250                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::27                  14907                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::28                  11091                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::29                   6921                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::30                   2899                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::31                    527                       # What read queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
@@ -131,48 +131,48 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                   1617                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                   1729                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                   3115                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   4520                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   5913                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                   7334                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                   8308                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                   9365                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                  10303                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                  11243                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                  12929                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                  44516                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                  21633                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                  13629                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                  13641                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                  13638                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                  13639                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                  13642                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                   1705                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    952                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                    833                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                    785                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                    713                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                    634                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                    580                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                    508                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                    452                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                    397                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                    345                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                   1517                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                   1598                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                   2949                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   4414                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   5799                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                   7205                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                   8259                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                   9290                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                  10245                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                  11149                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                  13077                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                  45268                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                  22379                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                  13802                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                  13611                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                  13661                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                  13631                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                  13563                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                   1725                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                    967                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    857                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                    772                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                    726                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                    646                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                    591                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                    516                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                    455                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                    392                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                    347                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::44                    294                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                    238                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                    193                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                    149                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48                    120                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49                     95                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50                     78                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52                     37                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53                     20                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54                     14                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                    243                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                    207                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                    163                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::48                    136                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::49                    110                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::50                     80                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::51                     63                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::52                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::53                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::54                     20                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::55                     18                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::56                     13                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
@@ -180,1234 +180,1246 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples       217198                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    243.992818                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   202.467078                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   149.850896                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        27585     12.70%     12.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        89029     40.99%     53.69% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383        57738     26.58%     80.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511        26133     12.03%     92.31% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639        10701      4.93%     97.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         4012      1.85%     99.08% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         1375      0.63%     99.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023          429      0.20%     99.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151          196      0.09%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total       217198                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples        13269                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      45.830432                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     16.164450                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7              23      0.17%      0.17% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15             33      0.25%      0.42% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23           115      0.87%      1.29% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31          4764     35.90%     37.19% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39          1332     10.04%     47.23% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47           205      1.54%     48.78% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55           710      5.35%     54.13% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63          5419     40.84%     94.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71           323      2.43%     97.40% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79            65      0.49%     97.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87           134      1.01%     98.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95           141      1.06%     99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103            3      0.02%     99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::120-127            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::160-167            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total         13269                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples        13269                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.573668                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.530150                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.283732                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16            10393     78.33%     78.33% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17              435      3.28%     81.60% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18             1077      8.12%     89.72% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19              911      6.87%     96.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20              245      1.85%     98.43% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21              113      0.85%     99.28% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22               39      0.29%     99.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23               18      0.14%     99.71% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24               19      0.14%     99.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25                5      0.04%     99.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26                1      0.01%     99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27                6      0.05%     99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29                1      0.01%     99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31                1      0.01%     99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32                3      0.02%     99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33                1      0.01%     99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35                1      0.01%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total         13269                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                     69684050                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                81238919                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                    3040755                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                       114.58                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples       217927                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    243.578079                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   202.332515                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   149.225070                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        27531     12.63%     12.63% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        89928     41.27%     53.90% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383        57630     26.44%     80.34% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511        26331     12.08%     92.43% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639        10616      4.87%     97.30% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         3910      1.79%     99.09% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         1341      0.62%     99.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023          442      0.20%     99.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151          198      0.09%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total       217927                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples        13336                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      45.632648                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     42.604910                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     16.181876                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-7              22      0.16%      0.16% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-15             23      0.17%      0.34% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23           102      0.76%      1.10% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-31          4874     36.55%     37.65% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-39          1383     10.37%     48.02% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-47           197      1.48%     49.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-55           688      5.16%     54.66% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-63          5373     40.29%     94.95% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-71           322      2.41%     97.36% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-79            76      0.57%     97.93% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87           142      1.06%     99.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-95           129      0.97%     99.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::104-111            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-119            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::144-151            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::168-175            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total         13336                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples        13336                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.559463                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.517273                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.258100                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16            10504     78.76%     78.76% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17              437      3.28%     82.04% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18             1076      8.07%     90.11% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19              871      6.53%     96.64% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20              245      1.84%     98.48% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21               96      0.72%     99.20% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22               44      0.33%     99.53% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23               27      0.20%     99.73% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24               16      0.12%     99.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25                6      0.04%     99.90% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26                4      0.03%     99.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27                4      0.03%     99.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28                3      0.02%     99.98% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30                2      0.01%     99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32                1      0.01%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total         13336                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                     70095683                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                81658855                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                    3042940                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                       115.18                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                  133.58                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      5235.38                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      1893.19                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   5299.31                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1904.10                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                  134.18                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      5228.17                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      1897.14                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   5292.75                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   1908.53                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        55.69                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    40.90                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   14.79                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                      20.94                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      27.75                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   397850                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  213011                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 65.42                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                96.85                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                          8.88                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    73.77                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy               1640640960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                911467200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy              7583122560                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy             2278088064                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy            485166240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy           5062396176                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             16183800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy            17977065000                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           2420.131050                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE          130                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF        248040                       # Time in different power states
+system.mem_ctrls.busUtil                        55.67                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    40.85                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   14.82                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                      20.89                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      27.79                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   397267                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  214223                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 65.28                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                96.99                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                          8.89                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    73.72                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy               1646182440                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                914545800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy              7588501440                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy             2287554048                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy            486183360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy           5073054948                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             16157400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy            18012179436                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower           2419.796272                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE           63                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF        248560                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT       7179981                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT       7195067                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy            485166240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            160523856                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy           4316043600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy             4961733696                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.968979                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE      7180064                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF        248040                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy            486183360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy            160860384                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy           4325091600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy             4972135344                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            667.968984                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE      7195116                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF        248560                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           99085                       # number of read accesses completed
-system.cpu0.num_writes                          54827                       # number of write accesses completed
-system.cpu1.num_reads                          100000                       # number of read accesses completed
-system.cpu1.num_writes                          55173                       # number of write accesses completed
-system.cpu2.num_reads                           99662                       # number of read accesses completed
-system.cpu2.num_writes                          55209                       # number of write accesses completed
+system.cpu0.num_reads                           99288                       # number of read accesses completed
+system.cpu0.num_writes                          55258                       # number of write accesses completed
+system.cpu1.num_reads                           99200                       # number of read accesses completed
+system.cpu1.num_writes                          55136                       # number of write accesses completed
+system.cpu2.num_reads                          100001                       # number of read accesses completed
+system.cpu2.num_writes                          55818                       # number of write accesses completed
 system.cpu3.num_reads                           99361                       # number of read accesses completed
-system.cpu3.num_writes                          55448                       # number of write accesses completed
-system.cpu4.num_reads                           99249                       # number of read accesses completed
-system.cpu4.num_writes                          55511                       # number of write accesses completed
-system.cpu5.num_reads                           99199                       # number of read accesses completed
-system.cpu5.num_writes                          55584                       # number of write accesses completed
-system.cpu6.num_reads                           99773                       # number of read accesses completed
-system.cpu6.num_writes                          55692                       # number of write accesses completed
-system.cpu7.num_reads                           99764                       # number of read accesses completed
-system.cpu7.num_writes                          55297                       # number of write accesses completed
+system.cpu3.num_writes                          55505                       # number of write accesses completed
+system.cpu4.num_reads                           98943                       # number of read accesses completed
+system.cpu4.num_writes                          55417                       # number of write accesses completed
+system.cpu5.num_reads                           99536                       # number of read accesses completed
+system.cpu5.num_writes                          55539                       # number of write accesses completed
+system.cpu6.num_reads                           99984                       # number of read accesses completed
+system.cpu6.num_writes                          55224                       # number of write accesses completed
+system.cpu7.num_reads                           99513                       # number of read accesses completed
+system.cpu7.num_writes                          55026                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       627101                      
-system.ruby.outstanding_req_hist::mean      15.998452                      
-system.ruby.outstanding_req_hist::gmean     15.997188                      
-system.ruby.outstanding_req_hist::stdev      0.125833                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          27      0.00%      0.02% |      626970     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        627101                      
+system.ruby.outstanding_req_hist::samples       627405                      
+system.ruby.outstanding_req_hist::mean      15.998457                      
+system.ruby.outstanding_req_hist::gmean     15.997194                      
+system.ruby.outstanding_req_hist::stdev      0.125784                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          24      0.00%      0.02% |      627277     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        627405                      
 system.ruby.latency_hist::bucket_size            2048                      
 system.ruby.latency_hist::max_bucket            20479                      
-system.ruby.latency_hist::samples              626973                      
-system.ruby.latency_hist::mean            1517.423723                      
-system.ruby.latency_hist::gmean           1021.259356                      
-system.ruby.latency_hist::stdev           1496.123234                      
-system.ruby.latency_hist                 |      474274     75.65%     75.65% |      109211     17.42%     93.06% |       31636      5.05%     98.11% |        9009      1.44%     99.55% |        2159      0.34%     99.89% |         565      0.09%     99.98% |          99      0.02%    100.00% |          20      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                626973                      
+system.ruby.latency_hist::samples              627277                      
+system.ruby.latency_hist::mean            1519.910775                      
+system.ruby.latency_hist::gmean           1025.504888                      
+system.ruby.latency_hist::stdev           1490.760460                      
+system.ruby.latency_hist                 |      473792     75.53%     75.53% |      110236     17.57%     93.11% |       31414      5.01%     98.11% |        9061      1.44%     99.56% |        2199      0.35%     99.91% |         446      0.07%     99.98% |         106      0.02%    100.00% |          13      0.00%    100.00% |           8      0.00%    100.00% |           2      0.00%    100.00%
+system.ruby.latency_hist::total                627277                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples             124                      
+system.ruby.hit_latency_hist::samples              82                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         124    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               124                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          82    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                82                      
 system.ruby.miss_latency_hist::bucket_size         2048                      
 system.ruby.miss_latency_hist::max_bucket        20479                      
-system.ruby.miss_latency_hist::samples         626849                      
-system.ruby.miss_latency_hist::mean       1517.723299                      
-system.ruby.miss_latency_hist::gmean      1022.437850                      
-system.ruby.miss_latency_hist::stdev      1496.119562                      
-system.ruby.miss_latency_hist            |      474150     75.64%     75.64% |      109211     17.42%     93.06% |       31636      5.05%     98.11% |        9009      1.44%     99.55% |        2159      0.34%     99.89% |         565      0.09%     99.98% |          99      0.02%    100.00% |          20      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           626849                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           14                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        78032                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78046                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples         627195                      
+system.ruby.miss_latency_hist::mean       1520.109097                      
+system.ruby.miss_latency_hist::gmean      1026.287427                      
+system.ruby.miss_latency_hist::stdev      1490.756998                      
+system.ruby.miss_latency_hist            |      473710     75.53%     75.53% |      110236     17.58%     93.10% |       31414      5.01%     98.11% |        9061      1.44%     99.56% |        2199      0.35%     99.91% |         446      0.07%     99.98% |         106      0.02%    100.00% |          13      0.00%    100.00% |           8      0.00%    100.00% |           2      0.00%    100.00%
+system.ruby.miss_latency_hist::total           627195                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits            8                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78523                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78531                       # Number of cache demand accesses
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 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           16                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        78433                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78449                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits           15                       # Number of cache demand hits
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-system.ruby.l1_cntrl2.L1Dcache.demand_hits           17                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        78349                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78366                       # Number of cache demand accesses
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 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits           19                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        78457                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78476                       # Number of cache demand accesses
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 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
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-system.ruby.l1_cntrl4.L1Dcache.demand_hits           13                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        78422                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78435                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Dcache.demand_hits            8                       # Number of cache demand hits
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 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        78251                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78272                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits            9                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78469                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78478                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
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 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           12                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        78547                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78559                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits            7                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78282                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78289                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           12                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        78376                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78388                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           11                       # Number of cache demand hits
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-system.ruby.l2_cntrl0.L2cache.demand_hits         4590                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       622265                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       626855                       # Number of cache demand accesses
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 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers00.percent_links_utilized     5.774438                      
-system.ruby.network.routers00.msg_count.Request_Control::0        78032                      
-system.ruby.network.routers00.msg_count.Response_Data::2        76681                      
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-system.ruby.network.routers00.msg_count.Response_Control::2          596                      
-system.ruby.network.routers00.msg_count.Writeback_Data::2        76954                      
-system.ruby.network.routers00.msg_count.Writeback_Control::0       155996                      
-system.ruby.network.routers00.msg_count.Forwarded_Control::0          860                      
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-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2        37152                      
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2       122040                      
-system.ruby.network.routers00.msg_bytes.Response_Control::2         4768                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::2      5540688                      
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0      1247968                      
-system.ruby.network.routers00.msg_bytes.Forwarded_Control::0         6880                      
-system.ruby.network.routers00.msg_bytes.Invalidate_Control::0         1920                      
-system.ruby.network.routers00.msg_bytes.Unblock_Control::2       630632                      
-system.ruby.network.routers01.percent_links_utilized     5.804161                      
-system.ruby.network.routers01.msg_count.Request_Control::0        78433                      
-system.ruby.network.routers01.msg_count.Response_Data::2        76986                      
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2          599                      
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::2         1726                      
-system.ruby.network.routers01.msg_count.Response_Control::2          622                      
-system.ruby.network.routers01.msg_count.Writeback_Data::2        77339                      
-system.ruby.network.routers01.msg_count.Writeback_Control::0       156756                      
-system.ruby.network.routers01.msg_count.Forwarded_Control::0          880                      
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-system.ruby.network.routers01.msg_count.Unblock_Control::2        79225                      
-system.ruby.network.routers01.msg_bytes.Request_Control::0       627464                      
-system.ruby.network.routers01.msg_bytes.Response_Data::2      5542992                      
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2        43128                      
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2       124272                      
-system.ruby.network.routers01.msg_bytes.Response_Control::2         4976                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::2      5568408                      
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0      1254048                      
-system.ruby.network.routers01.msg_bytes.Forwarded_Control::0         7040                      
-system.ruby.network.routers01.msg_bytes.Invalidate_Control::0         1944                      
-system.ruby.network.routers01.msg_bytes.Unblock_Control::2       633800                      
-system.ruby.network.routers02.percent_links_utilized     5.796696                      
-system.ruby.network.routers02.msg_count.Request_Control::0        78349                      
-system.ruby.network.routers02.msg_count.Response_Data::2        76918                      
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2          586                      
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::2         1696                      
-system.ruby.network.routers02.msg_count.Response_Control::2          585                      
-system.ruby.network.routers02.msg_count.Writeback_Data::2        77247                      
-system.ruby.network.routers02.msg_count.Writeback_Control::0       156587                      
-system.ruby.network.routers02.msg_count.Forwarded_Control::0          854                      
-system.ruby.network.routers02.msg_count.Invalidate_Control::0          208                      
-system.ruby.network.routers02.msg_count.Unblock_Control::2        79180                      
-system.ruby.network.routers02.msg_bytes.Request_Control::0       626792                      
-system.ruby.network.routers02.msg_bytes.Response_Data::2      5538096                      
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2        42192                      
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2       122112                      
-system.ruby.network.routers02.msg_bytes.Response_Control::2         4680                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::2      5561784                      
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0      1252696                      
-system.ruby.network.routers02.msg_bytes.Forwarded_Control::0         6832                      
-system.ruby.network.routers02.msg_bytes.Invalidate_Control::0         1664                      
-system.ruby.network.routers02.msg_bytes.Unblock_Control::2       633440                      
-system.ruby.network.routers03.percent_links_utilized     5.805984                      
-system.ruby.network.routers03.msg_count.Request_Control::0        78457                      
-system.ruby.network.routers03.msg_count.Response_Data::2        77073                      
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2          549                      
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-system.ruby.LD.latency_hist              |      305543     75.66%     75.66% |       70250     17.40%     93.06% |       20367      5.04%     98.10% |        5840      1.45%     99.55% |        1389      0.34%     99.89% |         361      0.09%     99.98% |          65      0.02%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.LD.latency_hist              |      304509     75.52%     75.52% |       71031     17.62%     93.14% |       20112      4.99%     98.13% |        5774      1.43%     99.56% |        1417      0.35%     99.91% |         283      0.07%     99.98% |          64      0.02%    100.00% |           9      0.00%    100.00% |           5      0.00%    100.00% |           2      0.00%    100.00%
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-system.ruby.LD.hit_latency_hist::total             98                      
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-system.ruby.LD.miss_latency_hist::stdev   1496.994981                      
-system.ruby.LD.miss_latency_hist         |      305445     75.66%     75.66% |       70250     17.40%     93.06% |       20367      5.04%     98.10% |        5840      1.45%     99.55% |        1389      0.34%     99.89% |         361      0.09%     99.98% |          65      0.02%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.Directory_Controller.I.GETX         78802      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS        143619      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack       220913      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETX        142401      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETS        250755      0.00%      0.00%
-system.ruby.Directory_Controller.S.Memory_Ack          105      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX        221085      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTO_SHARERS          105      0.00%      0.00%
-system.ruby.Directory_Controller.IS.GETX            3      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Unblock       143614      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data       143619      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Ack          100      0.00%      0.00%
-system.ruby.Directory_Controller.SS.GETX            3      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock       250750      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Memory_Data       250755      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock       221198      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data       221203      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Ack           66      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETX            1      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback       221079      0.00%      0.00%
-system.ruby.Directory_Controller.MIS.Dirty_Writeback          105      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load      |       50428     12.48%     12.48% |       50682     12.55%     25.03% |       50615     12.53%     37.56% |       50552     12.51%     50.08% |       50377     12.47%     62.55% |       50216     12.43%     74.98% |       50557     12.52%     87.49% |       50520     12.51%    100.00%
-system.ruby.L1Cache_Controller.Load::total       403947                      
-system.ruby.L1Cache_Controller.Store     |       27645     12.39%     12.39% |       27771     12.44%     24.83% |       27753     12.44%     37.27% |       27971     12.53%     49.80% |       28068     12.58%     62.38% |       28075     12.58%     74.96% |       28004     12.55%     87.50% |       27887     12.50%    100.00%
-system.ruby.L1Cache_Controller.Store::total       223174                      
-system.ruby.L1Cache_Controller.L1_Replacement |     9437024     12.51%     12.51% |     9428542     12.50%     25.01% |     9430070     12.50%     37.51% |     9427922     12.50%     50.01% |     9423979     12.49%     62.50% |     9433022     12.51%     75.01% |     9422446     12.49%     87.50% |     9430776     12.50%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total     75433781                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |         160     12.60%     12.60% |         161     12.68%     25.28% |         194     15.28%     40.55% |         145     11.42%     51.97% |         163     12.83%     64.80% |         138     10.87%     75.67% |         160     12.60%     88.27% |         149     11.73%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         1270                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |         733     12.79%     12.79% |         762     13.29%     26.08% |         712     12.42%     38.50% |         692     12.07%     50.58% |         706     12.32%     62.89% |         717     12.51%     75.40% |         715     12.47%     87.88% |         695     12.12%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total         5732                      
-system.ruby.L1Cache_Controller.Inv       |         240     13.36%     13.36% |         243     13.52%     26.88% |         208     11.57%     38.45% |         215     11.96%     50.42% |         211     11.74%     62.16% |         209     11.63%     73.79% |         218     12.13%     85.92% |         253     14.08%    100.00%
-system.ruby.L1Cache_Controller.Inv::total         1797                      
-system.ruby.L1Cache_Controller.Ack       |         356     11.97%     11.97% |         379     12.75%     24.72% |         377     12.68%     37.40% |         373     12.55%     49.95% |         365     12.28%     62.23% |         398     13.39%     75.61% |         364     12.24%     87.86% |         361     12.14%    100.00%
-system.ruby.L1Cache_Controller.Ack::total         2973                      
-system.ruby.L1Cache_Controller.Data      |       50238     12.49%     12.49% |       50469     12.55%     25.04% |       50418     12.54%     37.57% |       50300     12.51%     50.08% |       50156     12.47%     62.55% |       49994     12.43%     74.98% |       50340     12.52%     87.50% |       50293     12.50%    100.00%
-system.ruby.L1Cache_Controller.Data::total       402208                      
-system.ruby.L1Cache_Controller.Exclusive_Data |       27794     12.37%     12.37% |       27962     12.45%     24.82% |       27928     12.43%     37.25% |       28156     12.53%     49.79% |       28263     12.58%     62.37% |       28254     12.58%     74.94% |       28204     12.56%     87.50% |       28080     12.50%    100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total       224641                      
-system.ruby.L1Cache_Controller.Writeback_Ack |         665     12.82%     12.82% |         665     12.82%     25.64% |         683     13.16%     38.80% |         624     12.03%     50.83% |         614     11.84%     62.66% |         679     13.09%     75.75% |         631     12.16%     87.91% |         627     12.09%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total         5188                      
-system.ruby.L1Cache_Controller.Writeback_Ack_Data |       77086     12.44%     12.44% |       77469     12.51%     24.95% |       77398     12.49%     37.44% |       77574     12.52%     49.97% |       77552     12.52%     62.49% |       77313     12.48%     74.97% |       77638     12.53%     87.50% |       77435     12.50%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data::total       619465                      
-system.ruby.L1Cache_Controller.Writeback_Nack |         247     13.53%     13.53% |         243     13.31%     26.83% |         211     11.56%     38.39% |         220     12.05%     50.44% |         211     11.56%     61.99% |         217     11.88%     73.88% |         226     12.38%     86.25% |         251     13.75%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total         1826                      
-system.ruby.L1Cache_Controller.All_acks  |       27633     12.38%     12.38% |       27766     12.44%     24.83% |       27743     12.43%     37.26% |       27965     12.53%     49.80% |       28063     12.58%     62.38% |       28062     12.58%     74.95% |       28003     12.55%     87.50% |       27882     12.50%    100.00%
-system.ruby.L1Cache_Controller.All_acks::total       223117                      
-system.ruby.L1Cache_Controller.Use_Timeout |       27792     12.37%     12.37% |       27962     12.45%     24.82% |       27928     12.43%     37.25% |       28155     12.53%     49.79% |       28263     12.58%     62.37% |       28254     12.58%     74.94% |       28204     12.56%     87.50% |       28079     12.50%    100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total       224637                      
-system.ruby.L1Cache_Controller.I.Load    |       50399     12.48%     12.48% |       50665     12.55%     25.03% |       50603     12.53%     37.57% |       50491     12.51%     50.07% |       50359     12.47%     62.54% |       50188     12.43%     74.97% |       50544     12.52%     87.49% |       50494     12.51%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       403743                      
-system.ruby.L1Cache_Controller.I.Store   |       27633     12.39%     12.39% |       27766     12.45%     24.83% |       27743     12.43%     37.27% |       27964     12.53%     49.80% |       28062     12.58%     62.38% |       28062     12.58%     74.95% |       27999     12.55%     87.50% |       27879     12.50%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       223108                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |          48     11.03%     11.03% |          61     14.02%     25.06% |          58     13.33%     38.39% |          46     10.57%     48.97% |          52     11.95%     60.92% |          51     11.72%     72.64% |          54     12.41%     85.06% |          65     14.94%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total          435                      
-system.ruby.L1Cache_Controller.S.Load    |           6     11.76%     11.76% |           6     11.76%     23.53% |           5      9.80%     33.33% |           6     11.76%     45.10% |           6     11.76%     56.86% |          11     21.57%     78.43% |           6     11.76%     90.20% |           5      9.80%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total           51                      
-system.ruby.L1Cache_Controller.S.Store   |           0      0.00%      0.00% |           2     12.50%     12.50% |           3     18.75%     31.25% |           2     12.50%     43.75% |           1      6.25%     50.00% |           1      6.25%     56.25% |           4     25.00%     81.25% |           3     18.75%    100.00%
-system.ruby.L1Cache_Controller.S.Store::total           16                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |       50228     12.49%     12.49% |       50453     12.55%     25.04% |       50408     12.54%     37.57% |       50291     12.51%     50.08% |       50143     12.47%     62.55% |       49984     12.43%     74.98% |       50328     12.52%     87.50% |       50277     12.50%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total       402112                      
-system.ruby.L1Cache_Controller.S.Fwd_GETS |          45     11.94%     11.94% |          60     15.92%     27.85% |          56     14.85%     42.71% |          42     11.14%     53.85% |          40     10.61%     64.46% |          39     10.34%     74.80% |          55     14.59%     89.39% |          40     10.61%    100.00%
-system.ruby.L1Cache_Controller.S.Fwd_GETS::total          377                      
-system.ruby.L1Cache_Controller.S.Inv     |           9     12.50%     12.50% |          12     16.67%     29.17% |           6      8.33%     37.50% |           5      6.94%     44.44% |          12     16.67%     61.11% |           8     11.11%     72.22% |           7      9.72%     81.94% |          13     18.06%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total           72                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |         160     10.53%     10.53% |         195     12.83%     23.36% |         185     12.17%     35.53% |         191     12.57%     48.09% |         199     13.09%     61.18% |         192     12.63%     73.82% |         200     13.16%     86.97% |         198     13.03%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total         1520                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total            4                      
-system.ruby.L1Cache_Controller.M_W.L1_Replacement |         465     10.98%     10.98% |         530     12.51%     23.49% |         698     16.48%     39.98% |         505     11.92%     51.90% |         529     12.49%     64.39% |         418      9.87%     74.26% |         568     13.41%     87.67% |         522     12.33%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total         4235                      
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     50.00%     50.00% |           0      0.00%     50.00% |           2     50.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total            4                      
-system.ruby.L1Cache_Controller.M_W.Use_Timeout |         161     10.56%     10.56% |         196     12.86%     23.43% |         185     12.14%     35.56% |         191     12.53%     48.10% |         200     13.12%     61.22% |         192     12.60%     73.82% |         201     13.19%     87.01% |         198     12.99%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total         1524                      
-system.ruby.L1Cache_Controller.MM.Load   |           1      7.69%      7.69% |           2     15.38%     23.08% |           3     23.08%     46.15% |           3     23.08%     69.23% |           0      0.00%     69.23% |           2     15.38%     84.62% |           0      0.00%     84.62% |           2     15.38%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           13                      
-system.ruby.L1Cache_Controller.MM.Store  |           2     18.18%     18.18% |           0      0.00%     18.18% |           4     36.36%     54.55% |           3     27.27%     81.82% |           1      9.09%     90.91% |           1      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MM.Store::total           11                      
-system.ruby.L1Cache_Controller.MM.L1_Replacement |       27592     12.39%     12.39% |       27718     12.44%     24.83% |       27691     12.43%     37.26% |       27923     12.54%     49.80% |       28023     12.58%     62.38% |       28019     12.58%     74.96% |       27957     12.55%     87.51% |       27829     12.49%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total       222752                      
-system.ruby.L1Cache_Controller.MM.Fwd_GETX |          12      9.92%      9.92% |          20     16.53%     26.45% |          26     21.49%     47.93% |          11      9.09%     57.02% |          13     10.74%     67.77% |           8      6.61%     74.38% |          16     13.22%     87.60% |          15     12.40%    100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total          121                      
-system.ruby.L1Cache_Controller.MM.Fwd_GETS |          26     10.92%     10.92% |          28     11.76%     22.69% |          26     10.92%     33.61% |          30     12.61%     46.22% |          26     10.92%     57.14% |          35     14.71%     71.85% |          30     12.61%     84.45% |          37     15.55%    100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total          238                      
-system.ruby.L1Cache_Controller.MM_W.Load |           3      8.82%      8.82% |           5     14.71%     23.53% |           3      8.82%     32.35% |           6     17.65%     50.00% |           3      8.82%     58.82% |           6     17.65%     76.47% |           5     14.71%     91.18% |           3      8.82%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total           34                      
-system.ruby.L1Cache_Controller.MM_W.Store |           2     13.33%     13.33% |           3     20.00%     33.33% |           2     13.33%     46.67% |           1      6.67%     53.33% |           3     20.00%     73.33% |           1      6.67%     80.00% |           1      6.67%     86.67% |           2     13.33%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total           15                      
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      613663     12.48%     12.48% |      608323     12.37%     24.85% |      616946     12.54%     37.39% |      613237     12.47%     49.86% |      617680     12.56%     62.42% |      618886     12.58%     75.01% |      616731     12.54%     87.55% |      612440     12.45%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      4917906                      
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX |          15     16.67%     16.67% |           9     10.00%     26.67% |          17     18.89%     45.56% |           3      3.33%     48.89% |           8      8.89%     57.78% |          13     14.44%     72.22% |          18     20.00%     92.22% |           7      7.78%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total           90                      
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS |          18      8.18%      8.18% |          34     15.45%     23.64% |          35     15.91%     39.55% |          19      8.64%     48.18% |          25     11.36%     59.55% |          28     12.73%     72.27% |          28     12.73%     85.00% |          33     15.00%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total          220                      
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout |       27631     12.38%     12.38% |       27766     12.44%     24.83% |       27743     12.43%     37.26% |       27964     12.53%     49.80% |       28063     12.58%     62.38% |       28062     12.58%     74.95% |       28003     12.55%     87.50% |       27881     12.50%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total       223113                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |     3100083     12.39%     12.39% |     3100594     12.39%     24.78% |     3114295     12.44%     37.22% |     3131272     12.51%     49.73% |     3172501     12.68%     62.41% |     3140503     12.55%     74.95% |     3129364     12.50%     87.46% |     3139161     12.54%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total     25027773                      
-system.ruby.L1Cache_Controller.IM.Ack    |         130     11.00%     11.00% |         152     12.86%     23.86% |         136     11.51%     35.36% |         148     12.52%     47.88% |         143     12.10%     59.98% |         166     14.04%     74.03% |         155     13.11%     87.14% |         152     12.86%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total         1182                      
-system.ruby.L1Cache_Controller.IM.Exclusive_Data |       27633     12.39%     12.39% |       27764     12.44%     24.83% |       27740     12.43%     37.26% |       27963     12.53%     49.80% |       28062     12.58%     62.38% |       28061     12.58%     74.95% |       27999     12.55%     87.50% |       27879     12.50%    100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       223101                      
-system.ruby.L1Cache_Controller.SM.L1_Replacement |           0      0.00%      0.00% |         577     21.47%     21.47% |         301     11.20%     32.66% |         296     11.01%     43.68% |         399     14.84%     58.52% |           0      0.00%     58.52% |         838     31.18%     89.69% |         277     10.31%    100.00%
-system.ruby.L1Cache_Controller.SM.L1_Replacement::total         2688                      
-system.ruby.L1Cache_Controller.SM.Exclusive_Data |           0      0.00%      0.00% |           2     12.50%     12.50% |           3     18.75%     31.25% |           2     12.50%     43.75% |           1      6.25%     50.00% |           1      6.25%     56.25% |           4     25.00%     81.25% |           3     18.75%    100.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data::total           16                      
-system.ruby.L1Cache_Controller.OM.L1_Replacement |       21719     12.56%     12.56% |       21417     12.39%     24.95% |       21539     12.46%     37.42% |       21504     12.44%     49.86% |       22297     12.90%     62.76% |       21631     12.51%     75.27% |       21846     12.64%     87.91% |       20903     12.09%    100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total       172856                      
-system.ruby.L1Cache_Controller.OM.Ack    |         226     12.62%     12.62% |         227     12.67%     25.29% |         241     13.46%     38.75% |         225     12.56%     51.31% |         222     12.40%     63.71% |         232     12.95%     76.66% |         209     11.67%     88.33% |         209     11.67%    100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total         1791                      
-system.ruby.L1Cache_Controller.OM.All_acks |       27633     12.38%     12.38% |       27766     12.44%     24.83% |       27743     12.43%     37.26% |       27965     12.53%     49.80% |       28063     12.58%     62.38% |       28062     12.58%     74.95% |       28003     12.55%     87.50% |       27882     12.50%    100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total       223117                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |     5623066     12.58%     12.58% |     5618674     12.57%     25.16% |     5597949     12.53%     37.69% |     5582657     12.49%     50.18% |     5532156     12.38%     62.56% |     5573338     12.47%     75.04% |     5574560     12.48%     87.51% |     5579104     12.49%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total     44681504                      
-system.ruby.L1Cache_Controller.IS.Data   |       50238     12.49%     12.49% |       50469     12.55%     25.04% |       50418     12.54%     37.57% |       50300     12.51%     50.08% |       50156     12.47%     62.55% |       49994     12.43%     74.98% |       50340     12.52%     87.50% |       50293     12.50%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total       402208                      
-system.ruby.L1Cache_Controller.IS.Exclusive_Data |         161     10.56%     10.56% |         196     12.86%     23.43% |         185     12.14%     35.56% |         191     12.53%     48.10% |         200     13.12%     61.22% |         192     12.60%     73.82% |         201     13.19%     87.01% |         198     12.99%    100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total         1524                      
-system.ruby.L1Cache_Controller.SI.Load   |          17     18.09%     18.09% |           2      2.13%     20.21% |           1      1.06%     21.28% |          46     48.94%     70.21% |           3      3.19%     73.40% |           8      8.51%     81.91% |           1      1.06%     82.98% |          16     17.02%    100.00%
-system.ruby.L1Cache_Controller.SI.Load::total           94                      
-system.ruby.L1Cache_Controller.SI.Store  |           1      6.25%      6.25% |           0      0.00%      6.25% |           0      0.00%      6.25% |           1      6.25%     12.50% |           1      6.25%     18.75% |          10     62.50%     81.25% |           0      0.00%     81.25% |           3     18.75%    100.00%
-system.ruby.L1Cache_Controller.SI.Store::total           16                      
-system.ruby.L1Cache_Controller.SI.Fwd_GETS |         393     13.54%     13.54% |         384     13.23%     26.77% |         337     11.61%     38.39% |         357     12.30%     50.69% |         382     13.16%     63.85% |         357     12.30%     76.15% |         346     11.92%     88.08% |         346     11.92%    100.00%
-system.ruby.L1Cache_Controller.SI.Fwd_GETS::total         2902                      
-system.ruby.L1Cache_Controller.SI.Inv    |         231     13.39%     13.39% |         231     13.39%     26.78% |         202     11.71%     38.49% |         210     12.17%     50.67% |         199     11.54%     62.20% |         201     11.65%     73.86% |         211     12.23%     86.09% |         240     13.91%    100.00%
-system.ruby.L1Cache_Controller.SI.Inv::total         1725                      
-system.ruby.L1Cache_Controller.SI.Writeback_Ack |         663     12.81%     12.81% |         663     12.81%     25.61% |         681     13.15%     38.77% |         621     12.00%     50.76% |         614     11.86%     62.62% |         678     13.10%     75.72% |         630     12.17%     87.89% |         627     12.11%    100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total         5177                      
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data |       49334     12.48%     12.48% |       49558     12.54%     25.02% |       49523     12.53%     37.55% |       49460     12.52%     50.07% |       49330     12.48%     62.55% |       49103     12.42%     74.98% |       49485     12.52%     87.50% |       49409     12.50%    100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total       395202                      
-system.ruby.L1Cache_Controller.OI.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Load::total            1                      
-system.ruby.L1Cache_Controller.OI.Fwd_GETX |           1     25.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETX::total            4                      
-system.ruby.L1Cache_Controller.OI.Fwd_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     42.86%     42.86% |           3     42.86%     85.71% |           1     14.29%    100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETS::total            7                      
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data |         250     12.60%     12.60% |         256     12.90%     25.50% |         257     12.95%     38.46% |         243     12.25%     50.71% |         233     11.74%     62.45% |         254     12.80%     75.25% |         253     12.75%     88.00% |         238     12.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total         1984                      
-system.ruby.L1Cache_Controller.OI.Writeback_Nack |          18     16.82%     16.82% |          13     12.15%     28.97% |          11     10.28%     39.25% |          13     12.15%     51.40% |          12     11.21%     62.62% |          16     14.95%     77.57% |          13     12.15%     89.72% |          11     10.28%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Nack::total          107                      
-system.ruby.L1Cache_Controller.MI.Load   |           2     18.18%     18.18% |           2     18.18%     36.36% |           0      0.00%     36.36% |           0      0.00%     36.36% |           6     54.55%     90.91% |           1      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MI.Load::total           11                      
-system.ruby.L1Cache_Controller.MI.Store  |           7     87.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MI.Store::total            8                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETX |         131     12.51%     12.51% |         131     12.51%     25.02% |         150     14.33%     39.35% |         130     12.42%     51.77% |         139     13.28%     65.04% |         116     11.08%     76.12% |         123     11.75%     87.87% |         127     12.13%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         1047                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETS |         251     12.63%     12.63% |         256     12.88%     25.50% |         258     12.98%     38.48% |         244     12.27%     50.75% |         233     11.72%     62.47% |         255     12.83%     75.30% |         253     12.73%     88.03% |         238     11.97%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total         1988                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data |       27370     12.37%     12.37% |       27525     12.44%     24.81% |       27467     12.42%     37.23% |       27740     12.54%     49.77% |       27850     12.59%     62.36% |       27840     12.58%     74.94% |       27780     12.56%     87.50% |       27661     12.50%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total       221233                      
-system.ruby.L1Cache_Controller.II.Writeback_Ack |           2     18.18%     18.18% |           2     18.18%     36.36% |           2     18.18%     54.55% |           3     27.27%     81.82% |           0      0.00%     81.82% |           1      9.09%     90.91% |           1      9.09%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total           11                      
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data |         132     12.62%     12.62% |         130     12.43%     25.05% |         151     14.44%     39.48% |         131     12.52%     52.01% |         139     13.29%     65.30% |         116     11.09%     76.39% |         120     11.47%     87.86% |         127     12.14%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total         1046                      
-system.ruby.L1Cache_Controller.II.Writeback_Nack |         229     13.32%     13.32% |         230     13.38%     26.70% |         200     11.63%     38.34% |         207     12.04%     50.38% |         199     11.58%     61.95% |         201     11.69%     73.65% |         213     12.39%     86.04% |         240     13.96%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total         1719                      
-system.ruby.L2Cache_Controller.L1_GETS         504171      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         275912      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTO            107      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX         259606      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only       476434      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTS          25911      0.00%      0.00%
-system.ruby.L2Cache_Controller.All_Acks        221202      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data            615574      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA       395202      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA       223217      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack       221184      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock         408438      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock       224639      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement       691372      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       394374      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       218066      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS         3279      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX         1785      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only       391942      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS         3260      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS         2226      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX         1172      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX       222279      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTS         1711      0.00%      0.00%
+system.ruby.ST.miss_latency_hist::samples       224056                      
+system.ruby.ST.miss_latency_hist::mean    1522.834657                      
+system.ruby.ST.miss_latency_hist::gmean   1029.834307                      
+system.ruby.ST.miss_latency_hist::stdev   1493.434693                      
+system.ruby.ST.miss_latency_hist         |      169268     75.55%     75.55% |       39205     17.50%     93.05% |       11302      5.04%     98.09% |        3287      1.47%     99.56% |         782      0.35%     99.91% |         163      0.07%     99.98% |          42      0.02%    100.00% |           4      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        224056                      
+system.ruby.Directory_Controller.GETX          222195      0.00%      0.00%
+system.ruby.Directory_Controller.GETS          393916      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX          222083      0.00%      0.00%
+system.ruby.Directory_Controller.PUTO_SHARERS           88      0.00%      0.00%
+system.ruby.Directory_Controller.Unblock       143328      0.00%      0.00%
+system.ruby.Directory_Controller.Last_Unblock       250580      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock       222184      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback       222163      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       616104      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       222163      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX         80051      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS        143331      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack       221891      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETX        142138      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETS        250585      0.00%      0.00%
+system.ruby.Directory_Controller.S.Memory_Ack           88      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX        222083      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTO_SHARERS           88      0.00%      0.00%
+system.ruby.Directory_Controller.IS.GETX            2      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Unblock       143328      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data       143331      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Ack          114      0.00%      0.00%
+system.ruby.Directory_Controller.SS.GETX            4      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock       250580      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Memory_Data       250584      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock       222184      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data       222189      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Ack           70      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback       222075      0.00%      0.00%
+system.ruby.Directory_Controller.MIS.Dirty_Writeback           88      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load      |       50337     12.48%     12.48% |       50334     12.48%     24.96% |       50658     12.56%     37.52% |       50226     12.45%     49.98% |       50303     12.47%     62.45% |       50420     12.50%     74.95% |       50532     12.53%     87.48% |       50481     12.52%    100.00%
+system.ruby.L1Cache_Controller.Load::total       403291                      
+system.ruby.L1Cache_Controller.Store     |       28208     12.59%     12.59% |       27932     12.46%     25.05% |       28122     12.55%     37.60% |       28217     12.59%     50.19% |       27953     12.47%     62.66% |       28062     12.52%     75.19% |       27780     12.40%     87.58% |       27829     12.42%    100.00%
+system.ruby.L1Cache_Controller.Store::total       224103                      
+system.ruby.L1Cache_Controller.L1_Replacement |     9443995     12.50%     12.50% |     9453005     12.51%     25.00% |     9433466     12.48%     37.49% |     9447264     12.50%     49.99% |     9453992     12.51%     62.50% |     9447610     12.50%     75.00% |     9447185     12.50%     87.50% |     9448753     12.50%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total     75575270                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |         172     13.43%     13.43% |         152     11.87%     25.29% |         173     13.51%     38.80% |         175     13.66%     52.46% |         143     11.16%     63.62% |         143     11.16%     74.79% |         173     13.51%     88.29% |         150     11.71%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         1281                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |         662     11.73%     11.73% |         742     13.15%     24.88% |         690     12.23%     37.10% |         726     12.86%     49.96% |         704     12.47%     62.44% |         735     13.02%     75.46% |         695     12.31%     87.77% |         690     12.23%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total         5644                      
+system.ruby.L1Cache_Controller.Inv       |         227     12.74%     12.74% |         219     12.29%     25.03% |         265     14.87%     39.90% |         212     11.90%     51.80% |         217     12.18%     63.97% |         227     12.74%     76.71% |         205     11.50%     88.22% |         210     11.78%    100.00%
+system.ruby.L1Cache_Controller.Inv::total         1782                      
+system.ruby.L1Cache_Controller.Ack       |         389     13.23%     13.23% |         360     12.24%     25.48% |         373     12.69%     38.16% |         359     12.21%     50.37% |         367     12.48%     62.86% |         348     11.84%     74.69% |         379     12.89%     87.59% |         365     12.41%    100.00%
+system.ruby.L1Cache_Controller.Ack::total         2940                      
+system.ruby.L1Cache_Controller.Data      |       50111     12.48%     12.48% |       50127     12.48%     24.96% |       50476     12.57%     37.53% |       49986     12.45%     49.98% |       50074     12.47%     62.45% |       50206     12.50%     74.96% |       50292     12.52%     87.48% |       50265     12.52%    100.00%
+system.ruby.L1Cache_Controller.Data::total       401537                      
+system.ruby.L1Cache_Controller.Exclusive_Data |       28409     12.59%     12.59% |       28119     12.46%     25.05% |       28290     12.54%     37.59% |       28420     12.59%     50.18% |       28155     12.48%     62.66% |       28261     12.52%     75.18% |       27986     12.40%     87.58% |       28018     12.42%    100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total       225658                      
+system.ruby.L1Cache_Controller.Writeback_Ack |         641     12.65%     12.65% |         619     12.22%     24.87% |         587     11.58%     36.45% |         628     12.39%     48.85% |         671     13.24%     62.09% |         695     13.72%     75.80% |         609     12.02%     87.82% |         617     12.18%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total         5067                      
+system.ruby.L1Cache_Controller.Writeback_Ack_Data |       77592     12.52%     12.52% |       77349     12.48%     24.99% |       77854     12.56%     37.55% |       77513     12.50%     50.06% |       77289     12.47%     62.53% |       77502     12.50%     75.03% |       77405     12.49%     87.51% |       77395     12.49%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data::total       619899                      
+system.ruby.L1Cache_Controller.Writeback_Nack |         231     12.62%     12.62% |         221     12.08%     24.70% |         270     14.75%     39.45% |         217     11.86%     51.31% |         215     11.75%     63.06% |         239     13.06%     76.12% |         208     11.37%     87.49% |         229     12.51%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total         1830                      
+system.ruby.L1Cache_Controller.All_acks  |       28205     12.59%     12.59% |       27927     12.46%     25.05% |       28121     12.55%     37.60% |       28205     12.59%     50.19% |       27950     12.47%     62.67% |       28061     12.52%     75.19% |       27773     12.40%     87.59% |       27814     12.41%    100.00%
+system.ruby.L1Cache_Controller.All_acks::total       224056                      
+system.ruby.L1Cache_Controller.Use_Timeout |       28409     12.59%     12.59% |       28119     12.46%     25.05% |       28289     12.54%     37.59% |       28420     12.59%     50.18% |       28153     12.48%     62.66% |       28260     12.52%     75.18% |       27986     12.40%     87.58% |       28018     12.42%    100.00%
+system.ruby.L1Cache_Controller.Use_Timeout::total       225654                      
+system.ruby.L1Cache_Controller.I.Load    |       50316     12.48%     12.48% |       50322     12.48%     24.96% |       50646     12.56%     37.52% |       50205     12.45%     49.98% |       50279     12.47%     62.45% |       50408     12.50%     74.95% |       50508     12.53%     87.48% |       50472     12.52%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       403156                      
+system.ruby.L1Cache_Controller.I.Store   |       28202     12.59%     12.59% |       27928     12.47%     25.05% |       28118     12.55%     37.60% |       28202     12.59%     50.19% |       27949     12.47%     62.67% |       28059     12.52%     75.19% |       27773     12.40%     87.59% |       27813     12.41%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       224044                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |          60     12.63%     12.63% |          69     14.53%     27.16% |          62     13.05%     40.21% |          57     12.00%     52.21% |          56     11.79%     64.00% |          50     10.53%     74.53% |          62     13.05%     87.58% |          59     12.42%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total          475                      
+system.ruby.L1Cache_Controller.S.Load    |           3      9.68%      9.68% |           4     12.90%     22.58% |           3      9.68%     32.26% |           8     25.81%     58.06% |           3      9.68%     67.74% |           3      9.68%     77.42% |           3      9.68%     87.10% |           4     12.90%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total           31                      
+system.ruby.L1Cache_Controller.S.Store   |           5     26.32%     26.32% |           0      0.00%     26.32% |           3     15.79%     42.11% |           3     15.79%     57.89% |           3     15.79%     73.68% |           2     10.53%     84.21% |           1      5.26%     89.47% |           2     10.53%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total           19                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |       50098     12.48%     12.48% |       50115     12.48%     24.96% |       50464     12.57%     37.53% |       49973     12.45%     49.98% |       50061     12.47%     62.45% |       50192     12.50%     74.95% |       50285     12.53%     87.48% |       50259     12.52%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total       401447                      
+system.ruby.L1Cache_Controller.S.Fwd_GETS |          39     10.92%     10.92% |          61     17.09%     28.01% |          35      9.80%     37.82% |          49     13.73%     51.54% |          47     13.17%     64.71% |          45     12.61%     77.31% |          46     12.89%     90.20% |          35      9.80%    100.00%
+system.ruby.L1Cache_Controller.S.Fwd_GETS::total          357                      
+system.ruby.L1Cache_Controller.S.Inv     |           7     10.29%     10.29% |          12     17.65%     27.94% |           8     11.76%     39.71% |          10     14.71%     54.41% |          10     14.71%     69.12% |          11     16.18%     85.29% |           6      8.82%     94.12% |           4      5.88%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total           68                      
+system.ruby.L1Cache_Controller.O.L1_Replacement |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     57.14%     57.14% |           0      0.00%     57.14% |           1     14.29%     71.43% |           0      0.00%     71.43% |           2     28.57%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total            7                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |         202     12.69%     12.69% |         192     12.06%     24.75% |         165     10.36%     35.11% |         215     13.51%     48.62% |         204     12.81%     61.43% |         199     12.50%     73.93% |         211     13.25%     87.19% |         204     12.81%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total         1592                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total            3                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     57.14%     57.14% |           0      0.00%     57.14% |           1     14.29%     71.43% |           0      0.00%     71.43% |           2     28.57%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total            7                      
+system.ruby.L1Cache_Controller.M_W.L1_Replacement |         548     12.10%     12.10% |         971     21.44%     33.54% |         579     12.78%     46.32% |         280      6.18%     52.51% |         482     10.64%     63.15% |         351      7.75%     70.90% |         809     17.86%     88.76% |         509     11.24%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total         4529                      
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total            5                      
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     50.00%     50.00% |           0      0.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           2     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total            8                      
+system.ruby.L1Cache_Controller.M_W.Use_Timeout |         204     12.73%     12.73% |         192     11.99%     24.72% |         169     10.55%     35.27% |         215     13.42%     48.69% |         205     12.80%     61.49% |         200     12.48%     73.97% |         213     13.30%     87.27% |         204     12.73%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout::total         1602                      
+system.ruby.L1Cache_Controller.MM.Load   |           2     16.67%     16.67% |           1      8.33%     25.00% |           3     25.00%     50.00% |           1      8.33%     58.33% |           1      8.33%     66.67% |           2     16.67%     83.33% |           1      8.33%     91.67% |           1      8.33%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           12                      
+system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
+system.ruby.L1Cache_Controller.MM.Store::total            4                      
+system.ruby.L1Cache_Controller.MM.L1_Replacement |       28154     12.59%     12.59% |       27870     12.46%     25.05% |       28065     12.55%     37.60% |       28158     12.59%     50.19% |       27902     12.48%     62.67% |       28022     12.53%     75.19% |       27717     12.39%     87.59% |       27759     12.41%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total       223647                      
+system.ruby.L1Cache_Controller.MM.Fwd_GETX |          15     10.49%     10.49% |          20     13.99%     24.48% |          17     11.89%     36.36% |          16     11.19%     47.55% |          14      9.79%     57.34% |          10      6.99%     64.34% |          25     17.48%     81.82% |          26     18.18%    100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX::total          143                      
+system.ruby.L1Cache_Controller.MM.Fwd_GETS |          36     13.79%     13.79% |          37     14.18%     27.97% |          37     14.18%     42.15% |          31     11.88%     54.02% |          32     12.26%     66.28% |          28     10.73%     77.01% |          31     11.88%     88.89% |          29     11.11%    100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETS::total          261                      
+system.ruby.L1Cache_Controller.MM_W.Load |           2      8.33%      8.33% |           6     25.00%     33.33% |           4     16.67%     50.00% |           3     12.50%     62.50% |           4     16.67%     79.17% |           3     12.50%     91.67% |           0      0.00%     91.67% |           2      8.33%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total           24                      
+system.ruby.L1Cache_Controller.MM_W.Store |           1      9.09%      9.09% |           3     27.27%     36.36% |           1      9.09%     45.45% |           0      0.00%     45.45% |           0      0.00%     45.45% |           1      9.09%     54.55% |           2     18.18%     72.73% |           3     27.27%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total           11                      
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      618517     12.51%     12.51% |      616680     12.47%     24.98% |      619593     12.53%     37.52% |      616079     12.46%     49.98% |      621287     12.57%     62.55% |      617144     12.48%     75.03% |      615748     12.45%     87.48% |      618786     12.52%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      4943834                      
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX |          16     13.56%     13.56% |          17     14.41%     27.97% |          24     20.34%     48.31% |          20     16.95%     65.25% |          11      9.32%     74.58% |           8      6.78%     81.36% |          17     14.41%     95.76% |           5      4.24%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total          118                      
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS |          26     10.20%     10.20% |          31     12.16%     22.35% |          32     12.55%     34.90% |          38     14.90%     49.80% |          31     12.16%     61.96% |          46     18.04%     80.00% |          26     10.20%     90.20% |          25      9.80%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total          255                      
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout |       28205     12.59%     12.59% |       27927     12.46%     25.05% |       28120     12.55%     37.60% |       28205     12.59%     50.19% |       27948     12.47%     62.67% |       28060     12.52%     75.19% |       27773     12.40%     87.59% |       27814     12.41%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total       224052                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |     3149997     12.52%     12.52% |     3186048     12.66%     25.18% |     3123041     12.41%     37.60% |     3135752     12.46%     50.06% |     3137292     12.47%     62.53% |     3156543     12.55%     75.07% |     3113373     12.37%     87.45% |     3158021     12.55%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total     25160067                      
+system.ruby.L1Cache_Controller.IM.Ack    |         153     13.21%     13.21% |         144     12.44%     25.65% |         157     13.56%     39.21% |         146     12.61%     51.81% |         136     11.74%     63.56% |         131     11.31%     74.87% |         149     12.87%     87.74% |         142     12.26%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total         1158                      
+system.ruby.L1Cache_Controller.IM.Exclusive_Data |       28200     12.59%     12.59% |       27927     12.47%     25.05% |       28118     12.55%     37.60% |       28202     12.59%     50.19% |       27947     12.47%     62.67% |       28059     12.52%     75.19% |       27772     12.40%     87.59% |       27812     12.41%    100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       224037                      
+system.ruby.L1Cache_Controller.SM.L1_Replacement |         798     28.74%     28.74% |           0      0.00%     28.74% |         138      4.97%     33.71% |         597     21.50%     55.20% |         695     25.03%     80.23% |         276      9.94%     90.17% |         135      4.86%     95.03% |         138      4.97%    100.00%
+system.ruby.L1Cache_Controller.SM.L1_Replacement::total         2777                      
+system.ruby.L1Cache_Controller.SM.Exclusive_Data |           5     26.32%     26.32% |           0      0.00%     26.32% |           3     15.79%     42.11% |           3     15.79%     57.89% |           3     15.79%     73.68% |           2     10.53%     84.21% |           1      5.26%     89.47% |           2     10.53%    100.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data::total           19                      
+system.ruby.L1Cache_Controller.OM.L1_Replacement |       22088     12.82%     12.82% |       21719     12.61%     25.43% |       21701     12.60%     38.02% |       20594     11.95%     49.98% |       21388     12.41%     62.39% |       21743     12.62%     75.01% |       21703     12.60%     87.61% |       21346     12.39%    100.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement::total       172282                      
+system.ruby.L1Cache_Controller.OM.Ack    |         236     13.24%     13.24% |         216     12.12%     25.36% |         216     12.12%     37.49% |         213     11.95%     49.44% |         231     12.96%     62.40% |         217     12.18%     74.58% |         230     12.91%     87.49% |         223     12.51%    100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total         1782                      
+system.ruby.L1Cache_Controller.OM.All_acks |       28205     12.59%     12.59% |       27927     12.46%     25.05% |       28121     12.55%     37.60% |       28205     12.59%     50.19% |       27950     12.47%     62.67% |       28061     12.52%     75.19% |       27773     12.40%     87.59% |       27814     12.41%    100.00%
+system.ruby.L1Cache_Controller.OM.All_acks::total       224056                      
+system.ruby.L1Cache_Controller.IS.L1_Replacement |     5573533     12.48%     12.48% |     5549341     12.42%     24.90% |     5589654     12.51%     37.42% |     5595559     12.53%     49.95% |     5594624     12.53%     62.47% |     5573090     12.48%     74.95% |     5617140     12.58%     87.53% |     5571672     12.47%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total     44664613                      
+system.ruby.L1Cache_Controller.IS.Data   |       50111     12.48%     12.48% |       50127     12.48%     24.96% |       50476     12.57%     37.53% |       49986     12.45%     49.98% |       50074     12.47%     62.45% |       50206     12.50%     74.96% |       50292     12.52%     87.48% |       50265     12.52%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total       401537                      
+system.ruby.L1Cache_Controller.IS.Exclusive_Data |         204     12.73%     12.73% |         192     11.99%     24.72% |         169     10.55%     35.27% |         215     13.42%     48.69% |         205     12.80%     61.49% |         200     12.48%     73.97% |         213     13.30%     87.27% |         204     12.73%    100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total         1602                      
+system.ruby.L1Cache_Controller.SI.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           2      4.00%      4.00% |           9     18.00%     22.00% |          16     32.00%     54.00% |           3      6.00%     60.00% |          18     36.00%     96.00% |           2      4.00%    100.00%
+system.ruby.L1Cache_Controller.SI.Load::total           50                      
+system.ruby.L1Cache_Controller.SI.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11     78.57%     78.57% |           1      7.14%     85.71% |           0      0.00%     85.71% |           2     14.29%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SI.Store::total           14                      
+system.ruby.L1Cache_Controller.SI.Fwd_GETS |         359     12.43%     12.43% |         363     12.56%     24.99% |         353     12.22%     37.21% |         354     12.25%     49.46% |         367     12.70%     62.17% |         374     12.95%     75.11% |         351     12.15%     87.26% |         368     12.74%    100.00%
+system.ruby.L1Cache_Controller.SI.Fwd_GETS::total         2889                      
+system.ruby.L1Cache_Controller.SI.Inv    |         220     12.84%     12.84% |         207     12.08%     24.91% |         257     14.99%     39.91% |         202     11.79%     51.69% |         207     12.08%     63.77% |         216     12.60%     76.37% |         199     11.61%     87.98% |         206     12.02%    100.00%
+system.ruby.L1Cache_Controller.SI.Inv::total         1714                      
+system.ruby.L1Cache_Controller.SI.Writeback_Ack |         639     12.63%     12.63% |         618     12.22%     24.85% |         587     11.60%     36.45% |         627     12.39%     48.84% |         670     13.24%     62.09% |         694     13.72%     75.81% |         607     12.00%     87.80% |         617     12.20%    100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack::total         5059                      
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data |       49238     12.48%     12.48% |       49289     12.49%     24.96% |       49620     12.57%     37.54% |       49140     12.45%     49.99% |       49183     12.46%     62.45% |       49282     12.49%     74.94% |       49477     12.54%     87.47% |       49432     12.53%    100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total       394661                      
+system.ruby.L1Cache_Controller.OI.Fwd_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETX::total            3                      
+system.ruby.L1Cache_Controller.OI.Fwd_GETS |           1     11.11%     11.11% |           1     11.11%     22.22% |           2     22.22%     44.44% |           1     11.11%     55.56% |           0      0.00%     55.56% |           2     22.22%     77.78% |           2     22.22%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETS::total            9                      
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data |         201     10.79%     10.79% |         249     13.37%     24.17% |         227     12.19%     36.36% |         252     13.53%     49.89% |         225     12.08%     61.98% |         240     12.89%     74.87% |         235     12.62%     87.49% |         233     12.51%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total         1862                      
+system.ruby.L1Cache_Controller.OI.Writeback_Nack |          12      9.76%      9.76% |          15     12.20%     21.95% |          13     10.57%     32.52% |          16     13.01%     45.53% |           9      7.32%     52.85% |          24     19.51%     72.36% |          11      8.94%     81.30% |          23     18.70%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Nack::total          123                      
+system.ruby.L1Cache_Controller.MI.Load   |          14     77.78%     77.78% |           1      5.56%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           1      5.56%     88.89% |           2     11.11%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.MI.Load::total           18                      
+system.ruby.L1Cache_Controller.MI.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      9.09%      9.09% |          10     90.91%    100.00%
+system.ruby.L1Cache_Controller.MI.Store::total           11                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETX |         135     13.38%     13.38% |         115     11.40%     24.78% |         132     13.08%     37.86% |         138     13.68%     51.54% |         118     11.69%     63.23% |         123     12.19%     75.42% |         129     12.78%     88.21% |         119     11.79%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         1009                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETS |         201     10.82%     10.82% |         249     13.40%     24.22% |         223     12.00%     36.22% |         253     13.62%     49.84% |         224     12.06%     61.89% |         240     12.92%     74.81% |         235     12.65%     87.46% |         233     12.54%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETS::total         1858                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data |       28019     12.60%     12.60% |       27696     12.46%     25.06% |       27875     12.54%     37.59% |       27982     12.58%     50.18% |       27763     12.49%     62.66% |       27857     12.53%     75.19% |       27562     12.39%     87.58% |       27611     12.42%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total       222365                      
+system.ruby.L1Cache_Controller.II.Writeback_Ack |           2     25.00%     25.00% |           1     12.50%     37.50% |           0      0.00%     37.50% |           1     12.50%     50.00% |           1     12.50%     62.50% |           1     12.50%     75.00% |           2     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack::total            8                      
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data |         134     13.25%     13.25% |         115     11.37%     24.63% |         132     13.06%     37.69% |         139     13.75%     51.43% |         118     11.67%     63.11% |         123     12.17%     75.27% |         131     12.96%     88.23% |         119     11.77%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total         1011                      
+system.ruby.L1Cache_Controller.II.Writeback_Nack |         219     12.83%     12.83% |         206     12.07%     24.90% |         257     15.06%     39.95% |         201     11.78%     51.73% |         206     12.07%     63.80% |         215     12.60%     76.39% |         197     11.54%     87.93% |         206     12.07%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total         1707                      
+system.ruby.L2Cache_Controller.L1_GETS         503138      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         276686      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTO            151      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX         258242      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only       474368      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTS          25708      0.00%      0.00%
+system.ruby.L2Cache_Controller.All_Acks        222189      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data            616104      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA       394660      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA       224227      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack       222163      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock         407610      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock       225655      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement       688531      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       393916      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       219009      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETS         3246      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX         1771      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only       391425      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS         3236      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETS         2126      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETX         1155      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX       223374      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTS         1701      0.00%      0.00%
 system.ruby.L2Cache_Controller.ILOX.L1_GETS            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO          107      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTX          107      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETS            6      0.00%      0.00%
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+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock         1341      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L2_Replacement        12721      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only           10      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.Unblock            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.L2_Replacement           14      0.00%      0.00%
+system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only           25      0.00%      0.00%
+system.ruby.L2Cache_Controller.SLSS.Unblock           17      0.00%      0.00%
+system.ruby.L2Cache_Controller.SLSS.L2_Replacement           19      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETS          802      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETX          291      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack       222075      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only          217      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSI.Writeback_Ack           88      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index f687bc41a..3f1fbe27c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.005861                       # Number of seconds simulated
-sim_ticks                                     5861055                       # Number of ticks simulated
-final_tick                                    5861055                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.005821                       # Number of seconds simulated
+sim_ticks                                     5821182                       # Number of ticks simulated
+final_tick                                    5821182                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  95295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 485672                       # Number of bytes of host memory used
-host_seconds                                    61.50                       # Real time elapsed on the host
+host_tick_rate                                  68014                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 539140                       # Number of bytes of host memory used
+host_seconds                                    85.59                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39765312                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           39765312                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0     15548160                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total        15548160                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       621333                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              621333                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       242940                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             242940                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   6784667948                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            6784667948                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   2652792031                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           2652792031                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   9437459979                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           9437459979                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      621339                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     242940                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    621339                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   242940                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               39153536                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                  612160                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                15348928                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                39765696                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys             15548160                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                   9565                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                  3089                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39830912                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           39830912                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0     15373376                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total        15373376                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       622358                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              622358                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       240209                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             240209                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   6842409669                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            6842409669                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   2640937184                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           2640937184                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   9483346853                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           9483346853                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      622368                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     240209                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    622368                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   240209                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               39210944                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                  620416                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                15175936                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                39831552                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys             15373376                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                   9694                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                  3049                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             76254                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             76617                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             76129                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             77015                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             76504                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             76352                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             76489                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             76414                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             76983                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             76321                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             76515                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             76522                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             77021                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             76398                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             76334                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             76577                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::10                0                       # Per bank write bursts
@@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0             29636                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1             29880                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2             29803                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3             30173                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4             29938                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5             30411                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6             29999                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7             29987                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             29953                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1             29528                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2             29532                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3             29603                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4             29785                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5             29746                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6             29543                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7             29434                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
@@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                       5861029                       # Total gap between requests
+system.mem_ctrls.totGap                       5821160                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                621339                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                622368                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               242940                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    9448                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                   13046                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                   16459                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                   19563                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                   24246                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                   30435                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                   36606                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                   40256                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8                   38769                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9                   34745                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10                  30104                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11                  27475                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12                  26332                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13                  25691                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14                  24671                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15                  23610                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16                  22181                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17                  20983                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18                  19870                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19                  19241                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20                  18435                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21                  17866                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22                  16962                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23                  15619                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24                  13591                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25                  10815                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26                   7536                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27                   4396                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28                   1996                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29                    660                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30                    148                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31                     19                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               240209                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                    8340                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                   11906                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                   15620                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                   18559                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                   22953                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                   29117                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                   35827                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                   40200                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::8                   40426                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::9                   36509                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::10                  31650                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::11                  28573                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::12                  27266                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::13                  26251                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::14                  25235                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::15                  24021                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::16                  22472                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::17                  20919                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::18                  19841                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::19                  19049                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::20                  18234                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::21                  17567                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::22                  16593                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::23                  15420                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::24                  13597                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::25                  10982                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::26                   7856                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::27                   4648                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::28                   2127                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::29                    716                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::30                    185                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::31                     15                       # What read queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
@@ -131,1004 +131,991 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                     73                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                    151                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                    586                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   1517                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   2905                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                   4724                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                   6770                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                   8830                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                  11052                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                  13013                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                  14849                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                  16609                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                  15329                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                  15883                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                  16471                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                  16826                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                  16956                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                  17389                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                   9252                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                   7590                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                   6450                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                   5313                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                   4590                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                   3886                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                   3409                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                   2927                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                   2474                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                   2164                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                   1800                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                   1622                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                   1458                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                   1210                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                   1075                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48                    934                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49                    800                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50                    700                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51                    609                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52                    543                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53                    426                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54                    388                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55                    170                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56                     52                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57                     26                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                     50                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                    145                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                    507                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   1367                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   2635                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                   4148                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                   6053                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                   7858                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                   9893                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                  11694                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                  13326                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                  15063                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                  14272                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                  14999                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                  15490                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                  16216                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                  16414                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                  16827                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                   9948                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                   8560                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                   7255                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                   6262                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                   5386                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                   4562                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                   4004                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                   3425                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                   3067                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                   2622                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                   2219                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::44                   2015                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                   1837                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                   1650                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                   1349                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::48                   1177                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::49                   1078                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::50                    952                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::51                    768                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::52                    624                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::53                    554                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::54                    456                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::55                    249                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::56                     81                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::57                     47                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::58                     15                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::59                     10                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::60                     12                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::61                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples       250748                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    217.354922                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   175.083790                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   148.722121                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        50160     20.00%     20.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255       107083     42.71%     62.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383        54285     21.65%     84.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511        23329      9.30%     93.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639         9881      3.94%     97.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         3756      1.50%     99.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         1424      0.57%     99.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023          540      0.22%     99.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151          290      0.12%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total       250748                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples        14683                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      41.663420                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     37.948654                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     17.513815                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7             305      2.08%      2.08% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15             32      0.22%      2.30% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23            27      0.18%      2.48% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31          3189     21.72%     24.20% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39          6160     41.95%     66.15% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47          1671     11.38%     77.53% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55           181      1.23%     78.76% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63           914      6.22%     84.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71          1223      8.33%     93.32% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79           546      3.72%     97.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87           109      0.74%     97.78% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95            91      0.62%     98.40% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103          107      0.73%     99.13% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::104-111           71      0.48%     99.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-119           20      0.14%     99.75% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::120-127           25      0.17%     99.92% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::128-135            9      0.06%     99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::136-143            2      0.01%     99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::144-151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total         14683                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples        14683                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.333651                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.292472                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.288313                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16            13340     90.85%     90.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17              298      2.03%     92.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18              249      1.70%     94.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19              199      1.36%     95.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20              179      1.22%     97.15% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21              145      0.99%     98.14% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22               82      0.56%     98.70% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23               86      0.59%     99.28% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24               47      0.32%     99.60% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25               28      0.19%     99.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26               10      0.07%     99.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27                9      0.06%     99.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28                5      0.03%     99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29                1      0.01%     99.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30                4      0.03%     99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31                1      0.01%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total         14683                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                     62104397                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                73728103                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                    3058870                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                       101.52                       # Average queueing delay per DRAM burst
+system.mem_ctrls.wrQLenPdf::62                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples       249951                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    217.586583                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   175.307455                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   148.799547                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        49763     19.91%     19.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255       106960     42.79%     62.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383        53993     21.60%     84.30% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511        23277      9.31%     93.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639         9836      3.94%     97.55% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         3899      1.56%     99.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         1418      0.57%     99.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023          526      0.21%     99.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151          279      0.11%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total       249951                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples        14538                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      42.137914                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     38.248629                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     18.048368                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-7             307      2.11%      2.11% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-15             22      0.15%      2.26% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23            34      0.23%      2.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-31          3134     21.56%     24.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-39          5983     41.15%     65.21% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-47          1658     11.40%     76.61% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-55           202      1.39%     78.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-63           833      5.73%     83.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-71          1284      8.83%     92.56% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-79           590      4.06%     96.62% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87           132      0.91%     97.53% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-95           100      0.69%     98.22% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::96-103          121      0.83%     99.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::104-111           64      0.44%     99.49% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-119           33      0.23%     99.72% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::120-127           26      0.18%     99.90% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::128-135            8      0.06%     99.95% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143            4      0.03%     99.98% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::144-151            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::152-159            2      0.01%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total         14538                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples        14538                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.310634                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.272693                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.237976                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16            13255     91.17%     91.17% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17              312      2.15%     93.32% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18              225      1.55%     94.87% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19              219      1.51%     96.38% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20              170      1.17%     97.54% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21              124      0.85%     98.40% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22               76      0.52%     98.92% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23               56      0.39%     99.31% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24               38      0.26%     99.57% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25               29      0.20%     99.77% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26               13      0.09%     99.86% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27               10      0.07%     99.92% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28                6      0.04%     99.97% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29                2      0.01%     99.98% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::31                2      0.01%     99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32                1      0.01%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total         14538                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                     62772430                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                74413179                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                    3063355                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                       102.46                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                  120.52                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      6680.29                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      2618.80                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   6784.73                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   2652.79                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                  121.46                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      6735.91                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      2607.02                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   6842.52                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   2640.94                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        72.65                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    52.19                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   20.46                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                      15.37                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      30.05                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   366603                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  234242                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 59.92                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                97.66                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                          6.78                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    70.55                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy               1894029480                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy               1052238600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy              7627626240                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy             2483809920                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy            382437120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy           3990635208                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             12680400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy            17443456968                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           2979.039670                       # Core power per rank (mW)
+system.mem_ctrls.busUtil                        72.99                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    52.62                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   20.37                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                      15.56                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      30.72                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   367791                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  232046                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 60.03                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                97.84                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                          6.75                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    70.58                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy               1887996600                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy               1048887000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy              7639681920                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy             2456438400                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy            379894320                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy           3964067964                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             12588600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy            17389554804                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower           2989.744313                       # Core power per rank (mW)
 system.mem_ctrls_0.memoryStateTime::IDLE           22                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF        195520                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF        194220                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT       5659868                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT       5622174                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy            382437120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            126534528                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy           3402195600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy             3911167248                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.968375                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE      5659812                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF        195520                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy            379894320                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy            125693208                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy           3379575600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy             3885163128                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            667.968356                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE      5622182                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF        194220                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           98982                       # number of read accesses completed
-system.cpu0.num_writes                          55308                       # number of write accesses completed
-system.cpu1.num_reads                          100000                       # number of read accesses completed
-system.cpu1.num_writes                          55392                       # number of write accesses completed
-system.cpu2.num_reads                           99114                       # number of read accesses completed
-system.cpu2.num_writes                          55497                       # number of write accesses completed
-system.cpu3.num_reads                           99168                       # number of read accesses completed
-system.cpu3.num_writes                          55352                       # number of write accesses completed
-system.cpu4.num_reads                           99493                       # number of read accesses completed
-system.cpu4.num_writes                          54983                       # number of write accesses completed
-system.cpu5.num_reads                           99075                       # number of read accesses completed
-system.cpu5.num_writes                          55346                       # number of write accesses completed
-system.cpu6.num_reads                           99096                       # number of read accesses completed
-system.cpu6.num_writes                          54949                       # number of write accesses completed
-system.cpu7.num_reads                           99018                       # number of read accesses completed
-system.cpu7.num_writes                          54930                       # number of write accesses completed
+system.cpu0.num_reads                           99759                       # number of read accesses completed
+system.cpu0.num_writes                          55062                       # number of write accesses completed
+system.cpu1.num_reads                           99676                       # number of read accesses completed
+system.cpu1.num_writes                          56012                       # number of write accesses completed
+system.cpu2.num_reads                           99760                       # number of read accesses completed
+system.cpu2.num_writes                          55397                       # number of write accesses completed
+system.cpu3.num_reads                          100000                       # number of read accesses completed
+system.cpu3.num_writes                          55911                       # number of write accesses completed
+system.cpu4.num_reads                           99280                       # number of read accesses completed
+system.cpu4.num_writes                          54878                       # number of write accesses completed
+system.cpu5.num_reads                           99419                       # number of read accesses completed
+system.cpu5.num_writes                          55605                       # number of write accesses completed
+system.cpu6.num_reads                           99512                       # number of read accesses completed
+system.cpu6.num_writes                          55332                       # number of write accesses completed
+system.cpu7.num_reads                           99101                       # number of read accesses completed
+system.cpu7.num_writes                          55293                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       625828                      
-system.ruby.outstanding_req_hist::mean      15.998460                      
-system.ruby.outstanding_req_hist::gmean     15.997194                      
-system.ruby.outstanding_req_hist::stdev      0.125917                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          20      0.00%      0.02% |      625704     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        625828                      
+system.ruby.outstanding_req_hist::samples       626798                      
+system.ruby.outstanding_req_hist::mean      15.998464                      
+system.ruby.outstanding_req_hist::gmean     15.997200                      
+system.ruby.outstanding_req_hist::stdev      0.125813                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          19      0.00%      0.02% |      626675     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        626798                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples              625700                      
-system.ruby.latency_hist::mean            1198.832377                      
-system.ruby.latency_hist::gmean            899.836581                      
-system.ruby.latency_hist::stdev            764.001734                      
-system.ruby.latency_hist                 |      168514     26.93%     26.93% |      119446     19.09%     46.02% |      111629     17.84%     63.86% |      119695     19.13%     82.99% |       84495     13.50%     96.50% |       20461      3.27%     99.77% |        1425      0.23%     99.99% |          34      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                625700                      
+system.ruby.latency_hist::samples              626670                      
+system.ruby.latency_hist::mean            1188.866103                      
+system.ruby.latency_hist::gmean            895.172071                      
+system.ruby.latency_hist::stdev            753.817957                      
+system.ruby.latency_hist                 |      168975     26.96%     26.96% |      120052     19.16%     46.12% |      115384     18.41%     64.53% |      120399     19.21%     83.75% |       82434     13.15%     96.90% |       18213      2.91%     99.81% |        1198      0.19%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                626670                      
 system.ruby.hit_latency_hist::bucket_size          512                      
 system.ruby.hit_latency_hist::max_bucket         5119                      
-system.ruby.hit_latency_hist::samples            2941                      
-system.ruby.hit_latency_hist::mean        1072.636858                      
-system.ruby.hit_latency_hist::gmean        541.560950                      
-system.ruby.hit_latency_hist::stdev        789.424392                      
-system.ruby.hit_latency_hist             |         996     33.87%     33.87% |         480     16.32%     50.19% |         522     17.75%     67.94% |         531     18.06%     85.99% |         338     11.49%     97.48% |          68      2.31%     99.80% |           6      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2941                      
+system.ruby.hit_latency_hist::samples            2921                      
+system.ruby.hit_latency_hist::mean        1087.767203                      
+system.ruby.hit_latency_hist::gmean        544.065854                      
+system.ruby.hit_latency_hist::stdev        803.453196                      
+system.ruby.hit_latency_hist             |         965     33.04%     33.04% |         498     17.05%     50.09% |         495     16.95%     67.03% |         523     17.90%     84.94% |         350     11.98%     96.92% |          84      2.88%     99.79% |           6      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2921                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples         622759                      
-system.ruby.miss_latency_hist::mean       1199.428339                      
-system.ruby.miss_latency_hist::gmean       901.996890                      
-system.ruby.miss_latency_hist::stdev       763.830861                      
-system.ruby.miss_latency_hist            |      167518     26.90%     26.90% |      118966     19.10%     46.00% |      111107     17.84%     63.84% |      119164     19.13%     82.98% |       84157     13.51%     96.49% |       20393      3.27%     99.77% |        1419      0.23%     99.99% |          34      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           622759                      
-system.ruby.L1Cache.incomplete_times             1274                      
-system.ruby.Directory.incomplete_times         621482                      
+system.ruby.miss_latency_hist::samples         623749                      
+system.ruby.miss_latency_hist::mean       1189.339547                      
+system.ruby.miss_latency_hist::gmean       897.261928                      
+system.ruby.miss_latency_hist::stdev       753.546605                      
+system.ruby.miss_latency_hist            |      168010     26.94%     26.94% |      119554     19.17%     46.10% |      114889     18.42%     64.52% |      119876     19.22%     83.74% |       82084     13.16%     96.90% |       18129      2.91%     99.81% |        1192      0.19%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           623749                      
+system.ruby.L1Cache.incomplete_times             1208                      
+system.ruby.Directory.incomplete_times         622538                      
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           27                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        78075                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78102                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78497                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78524                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           24                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        78760                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78784                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits           19                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        78630                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78649                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits           24                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        78362                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78386                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits           16                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        78235                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78251                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits           23                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        78022                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78045                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_hits           20                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        78633                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78653                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Dcache.demand_hits           25                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        78196                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78221                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Dcache.demand_hits           22                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        78239                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78261                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           23                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        78073                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78096                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits           20                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78117                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78137                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           18                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        78070                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78088                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits           26                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78165                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78191                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           23                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        77974                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        77997                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           31                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        77991                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78022                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.L2cache.demand_hits         1865                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       623660                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       625525                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits         1849                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       624657                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses       626506                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers00.percent_links_utilized     9.730987                      
-system.ruby.network.routers00.msg_count.Request_Control::1        78075                      
-system.ruby.network.routers00.msg_count.Response_Data::4        79609                      
-system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4          237                      
-system.ruby.network.routers00.msg_count.ResponseLocal_Data::4          185                      
-system.ruby.network.routers00.msg_count.Response_Control::4           87                      
-system.ruby.network.routers00.msg_count.Writeback_Data::4        84294                      
-system.ruby.network.routers00.msg_count.Broadcast_Control::1       625529                      
-system.ruby.network.routers00.msg_count.Persistent_Control::3        98738                      
-system.ruby.network.routers00.msg_bytes.Request_Control::1       624600                      
-system.ruby.network.routers00.msg_bytes.Response_Data::4      5731848                      
-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4        17064                      
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4        13320                      
-system.ruby.network.routers00.msg_bytes.Response_Control::4          696                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::4      6069168                      
-system.ruby.network.routers00.msg_bytes.Broadcast_Control::1      5004232                      
-system.ruby.network.routers00.msg_bytes.Persistent_Control::3       789904                      
-system.ruby.network.routers01.percent_links_utilized     9.789650                      
-system.ruby.network.routers01.msg_count.Request_Control::1        78759                      
-system.ruby.network.routers01.msg_count.Response_Data::4        80279                      
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4          250                      
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::4          170                      
-system.ruby.network.routers01.msg_count.Response_Control::4           88                      
-system.ruby.network.routers01.msg_count.Writeback_Data::4        85066                      
-system.ruby.network.routers01.msg_count.Broadcast_Control::1       625528                      
-system.ruby.network.routers01.msg_count.Persistent_Control::3        98848                      
-system.ruby.network.routers01.msg_bytes.Request_Control::1       630072                      
-system.ruby.network.routers01.msg_bytes.Response_Data::4      5780088                      
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4        18000                      
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4        12240                      
-system.ruby.network.routers01.msg_bytes.Response_Control::4          704                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::4      6124752                      
-system.ruby.network.routers01.msg_bytes.Broadcast_Control::1      5004224                      
-system.ruby.network.routers01.msg_bytes.Persistent_Control::3       790784                      
-system.ruby.network.routers02.percent_links_utilized     9.754677                      
-system.ruby.network.routers02.msg_count.Request_Control::1        78362                      
-system.ruby.network.routers02.msg_count.Response_Data::4        79837                      
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4          249                      
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::4          172                      
-system.ruby.network.routers02.msg_count.Response_Control::4           97                      
-system.ruby.network.routers02.msg_count.Writeback_Data::4        84646                      
-system.ruby.network.routers02.msg_count.Broadcast_Control::1       625529                      
-system.ruby.network.routers02.msg_count.Persistent_Control::3        98784                      
-system.ruby.network.routers02.msg_bytes.Request_Control::1       626896                      
-system.ruby.network.routers02.msg_bytes.Response_Data::4      5748264                      
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4        17928                      
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4        12384                      
-system.ruby.network.routers02.msg_bytes.Response_Control::4          776                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::4      6094512                      
-system.ruby.network.routers02.msg_bytes.Broadcast_Control::1      5004232                      
-system.ruby.network.routers02.msg_bytes.Persistent_Control::3       790272                      
-system.ruby.network.routers03.percent_links_utilized     9.724713                      
-system.ruby.network.routers03.msg_count.Request_Control::1        78022                      
-system.ruby.network.routers03.msg_count.Response_Data::4        79535                      
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4          229                      
-system.ruby.network.routers03.msg_count.ResponseLocal_Data::4          170                      
-system.ruby.network.routers03.msg_count.Response_Control::4           85                      
-system.ruby.network.routers03.msg_count.Writeback_Data::4        84220                      
-system.ruby.network.routers03.msg_count.Broadcast_Control::1       625530                      
-system.ruby.network.routers03.msg_count.Persistent_Control::3        98860                      
-system.ruby.network.routers03.msg_bytes.Request_Control::1       624176                      
-system.ruby.network.routers03.msg_bytes.Response_Data::4      5726520                      
-system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4        16488                      
-system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4        12240                      
-system.ruby.network.routers03.msg_bytes.Response_Control::4          680                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::4      6063840                      
-system.ruby.network.routers03.msg_bytes.Broadcast_Control::1      5004240                      
-system.ruby.network.routers03.msg_bytes.Persistent_Control::3       790880                      
-system.ruby.network.routers04.percent_links_utilized     9.738865                      
-system.ruby.network.routers04.msg_count.Request_Control::1        78196                      
-system.ruby.network.routers04.msg_count.Response_Data::4        79670                      
-system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4          267                      
-system.ruby.network.routers04.msg_count.ResponseLocal_Data::4          159                      
+system.ruby.network.routers00.percent_links_utilized     9.725168                      
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-system.ruby.LD.latency_hist              |      108616     26.98%     26.98% |       76986     19.12%     46.11% |       71722     17.82%     63.92% |       76938     19.11%     83.04% |       54198     13.46%     96.50% |       13154      3.27%     99.77% |         917      0.23%     99.99% |          22      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.LD.hit_latency_hist::stdev     783.939123                      
-system.ruby.LD.hit_latency_hist          |         650     34.08%     34.08% |         313     16.41%     50.50% |         343     17.99%     68.48% |         352     18.46%     86.94% |         203     10.64%     97.59% |          43      2.25%     99.84% |           3      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total           1907                      
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-system.ruby.L1Cache.hit_mach_latency_hist::gmean            2                      
-system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         187    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total          187                      
+system.ruby.L1Cache.hit_mach_latency_hist::gmean     2.000000                      
+system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         181    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total          181                      
 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.L1Cache.miss_mach_latency_hist::samples         1274                      
-system.ruby.L1Cache.miss_mach_latency_hist::mean  1137.938776                      
-system.ruby.L1Cache.miss_mach_latency_hist::gmean   742.704975                      
-system.ruby.L1Cache.miss_mach_latency_hist::stdev   774.705868                      
-system.ruby.L1Cache.miss_mach_latency_hist |         360     28.26%     28.26% |         260     20.41%     48.67% |         251     19.70%     68.37% |         206     16.17%     84.54% |         148     11.62%     96.15% |          45      3.53%     99.69% |           4      0.31%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total         1274                      
+system.ruby.L1Cache.miss_mach_latency_hist::samples         1208                      
+system.ruby.L1Cache.miss_mach_latency_hist::mean  1138.897351                      
+system.ruby.L1Cache.miss_mach_latency_hist::gmean   755.701841                      
+system.ruby.L1Cache.miss_mach_latency_hist::stdev   765.191756                      
+system.ruby.L1Cache.miss_mach_latency_hist |         353     29.22%     29.22% |         218     18.05%     47.27% |         246     20.36%     67.63% |         213     17.63%     85.26% |         142     11.75%     97.02% |          32      2.65%     99.67% |           4      0.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_mach_latency_hist::total         1208                      
 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size          512                      
 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket         5119                      
-system.ruby.L2Cache.hit_mach_latency_hist::samples         2754                      
-system.ruby.L2Cache.hit_mach_latency_hist::mean  1145.334423                      
-system.ruby.L2Cache.hit_mach_latency_hist::gmean   792.182169                      
-system.ruby.L2Cache.hit_mach_latency_hist::stdev   763.134229                      
-system.ruby.L2Cache.hit_mach_latency_hist |         809     29.38%     29.38% |         480     17.43%     46.80% |         522     18.95%     65.76% |         531     19.28%     85.04% |         338     12.27%     97.31% |          68      2.47%     99.78% |           6      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total         2754                      
+system.ruby.L2Cache.hit_mach_latency_hist::samples         2740                      
+system.ruby.L2Cache.hit_mach_latency_hist::mean  1159.491241                      
+system.ruby.L2Cache.hit_mach_latency_hist::gmean   787.913705                      
+system.ruby.L2Cache.hit_mach_latency_hist::stdev   777.910979                      
+system.ruby.L2Cache.hit_mach_latency_hist |         784     28.61%     28.61% |         498     18.18%     46.79% |         495     18.07%     64.85% |         523     19.09%     83.94% |         350     12.77%     96.72% |          84      3.07%     99.78% |           6      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total         2740                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.Directory.miss_mach_latency_hist::samples       621485                      
-system.ruby.Directory.miss_mach_latency_hist::mean  1199.554388                      
-system.ruby.Directory.miss_mach_latency_hist::gmean   902.356250                      
-system.ruby.Directory.miss_mach_latency_hist::stdev   763.803957                      
-system.ruby.Directory.miss_mach_latency_hist |      167158     26.90%     26.90% |      118706     19.10%     46.00% |      110856     17.84%     63.83% |      118958     19.14%     82.98% |       84009     13.52%     96.49% |       20348      3.27%     99.77% |        1415      0.23%     99.99% |          34      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       621485                      
+system.ruby.Directory.miss_mach_latency_hist::samples       622541                      
+system.ruby.Directory.miss_mach_latency_hist::mean  1189.437427                      
+system.ruby.Directory.miss_mach_latency_hist::gmean   897.560922                      
+system.ruby.Directory.miss_mach_latency_hist::stdev   753.521175                      
+system.ruby.Directory.miss_mach_latency_hist |      167657     26.93%     26.93% |      119336     19.17%     46.10% |      114643     18.42%     64.52% |      119663     19.22%     83.74% |       81942     13.16%     96.90% |       18097      2.91%     99.81% |        1188      0.19%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       622541                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            3                      
@@ -1154,451 +1141,447 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion |
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            3                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples          141                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples          123                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean            2                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         141    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total          141                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     2.000000                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         123    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total          123                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples          810                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1148.616049                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean   750.657657                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   779.125924                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |         224     27.65%     27.65% |         172     21.23%     48.89% |         153     18.89%     67.78% |         128     15.80%     83.58% |         106     13.09%     96.67% |          24      2.96%     99.63% |           3      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total          810                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples          763                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1134.049803                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean   747.970071                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   769.263081                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |         224     29.36%     29.36% |         143     18.74%     48.10% |         151     19.79%     67.89% |         131     17.17%     85.06% |          89     11.66%     96.72% |          23      3.01%     99.74% |           2      0.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total          763                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples         1766                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean  1144.541336                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean   803.018182                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   753.048599                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         509     28.82%     28.82% |         313     17.72%     46.55% |         343     19.42%     65.97% |         352     19.93%     85.90% |         203     11.49%     97.40% |          43      2.43%     99.83% |           3      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total         1766                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples         1750                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean  1148.216000                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean   774.336775                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   773.632611                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         512     29.26%     29.26% |         314     17.94%     47.20% |         306     17.49%     64.69% |         351     20.06%     84.74% |         219     12.51%     97.26% |          44      2.51%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total         1750                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       399836                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1198.486512                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   901.317161                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   763.780785                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |      107742     26.95%     26.95% |       76501     19.13%     46.08% |       71226     17.81%     63.89% |       76458     19.12%     83.02% |       53889     13.48%     96.49% |       13087      3.27%     99.77% |         911      0.23%     99.99% |          22      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       399836                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       399913                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1188.423977                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   896.341171                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   753.818281                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |      108009     27.01%     27.01% |       76571     19.15%     46.16% |       73658     18.42%     64.57% |       76661     19.17%     83.74% |       52633     13.16%     96.90% |       11588      2.90%     99.80% |         782      0.20%    100.00% |          11      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total       399913                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           46                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           58                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean            2                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     2.000000                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          46    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           46                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          58    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           58                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples          464                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1119.299569                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean   729.023445                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   767.409492                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |         136     29.31%     29.31% |          88     18.97%     48.28% |          98     21.12%     69.40% |          78     16.81%     86.21% |          42      9.05%     95.26% |          21      4.53%     99.78% |           1      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total          464                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples          445                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1147.208989                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean   769.145243                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   758.950513                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist |         129     28.99%     28.99% |          75     16.85%     45.84% |          95     21.35%     67.19% |          82     18.43%     85.62% |          53     11.91%     97.53% |           9      2.02%     99.55% |           2      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total          445                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples          988                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1146.752024                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   773.176325                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   781.220856                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         300     30.36%     30.36% |         167     16.90%     47.27% |         179     18.12%     65.38% |         179     18.12%     83.50% |         135     13.66%     97.17% |          25      2.53%     99.70% |           3      0.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total          988                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples          990                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1179.422222                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   812.498260                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   785.413197                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         272     27.47%     27.47% |         184     18.59%     46.06% |         189     19.09%     65.15% |         172     17.37%     82.53% |         131     13.23%     95.76% |          40      4.04%     99.80% |           2      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total          990                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       221649                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1201.480747                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   904.233709                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   763.843702                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |       59416     26.81%     26.81% |       42205     19.04%     45.85% |       39630     17.88%     63.73% |       42500     19.17%     82.90% |       30120     13.59%     96.49% |        7261      3.28%     99.77% |         504      0.23%     99.99% |          12      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total       221649                      
-system.ruby.Directory_Controller.GETX          237776      0.00%      0.00%
-system.ruby.Directory_Controller.GETS          429309      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown        44122      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown        43680      0.00%      0.00%
-system.ruby.Directory_Controller.Data_Owner          324      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens       243004      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner          548      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens       377814      0.00%      0.00%
-system.ruby.Directory_Controller.Tokens           130      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens          793      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       621328      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       242939      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX        220131      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS        396984      0.00%      0.00%
-system.ruby.Directory_Controller.O.Lockdown         3690      0.00%      0.00%
-system.ruby.Directory_Controller.O.Data_All_Tokens           60      0.00%      0.00%
-system.ruby.Directory_Controller.O.Tokens            4      0.00%      0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens          785      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX         2197      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETS         3978      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown        17299      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_Owner          324      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens       242616      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner          548      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens       377404      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Tokens          123      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETX           123      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETS           247      0.00%      0.00%
-system.ruby.Directory_Controller.L.Lockdown          395      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown        43680      0.00%      0.00%
-system.ruby.Directory_Controller.L.Data_All_Tokens          294      0.00%      0.00%
-system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens          410      0.00%      0.00%
-system.ruby.Directory_Controller.L.Tokens            2      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETX           70      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETS          121      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Lockdown          124      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Data_All_Tokens           34      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Tokens            1      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Ack_All_Tokens            2      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack       242815      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.GETX           34      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.GETS           64      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Lockdown           12      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens            6      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Data         4224      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Ack          124      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.GETX          495      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.GETS          954      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Lockdown           35      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data        22567      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.GETX        14726      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.GETS        26961      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown        22567      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data       594537      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load      |       50092     12.44%     12.44% |       50720     12.60%     25.04% |       50362     12.51%     37.55% |       50243     12.48%     50.03% |       50550     12.56%     62.59% |       50015     12.42%     75.01% |       50346     12.51%     87.52% |       50237     12.48%    100.00%
-system.ruby.L1Cache_Controller.Load::total       402565                      
-system.ruby.L1Cache_Controller.Store     |       28010     12.55%     12.55% |       28064     12.58%     25.13% |       28024     12.56%     37.69% |       27802     12.46%     50.14% |       27671     12.40%     62.54% |       28081     12.58%     75.13% |       27742     12.43%     87.56% |       27760     12.44%    100.00%
-system.ruby.L1Cache_Controller.Store::total       223154                      
-system.ruby.L1Cache_Controller.L1_Replacement |     1468380     12.49%     12.49% |     1481332     12.60%     25.08% |     1472761     12.52%     37.61% |     1468524     12.49%     50.09% |     1470130     12.50%     62.59% |     1467500     12.48%     75.07% |     1468017     12.48%     87.55% |     1463638     12.45%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total     11760282                      
-system.ruby.L1Cache_Controller.Data_Shared |         197     12.64%     12.64% |         195     12.52%     25.16% |         194     12.45%     37.61% |         178     11.42%     49.04% |         190     12.20%     61.23% |         196     12.58%     73.81% |         203     13.03%     86.84% |         205     13.16%    100.00%
-system.ruby.L1Cache_Controller.Data_Shared::total         1558                      
-system.ruby.L1Cache_Controller.Data_Owner |          28      9.69%      9.69% |          43     14.88%     24.57% |          30     10.38%     34.95% |          39     13.49%     48.44% |          33     11.42%     59.86% |          38     13.15%     73.01% |          33     11.42%     84.43% |          45     15.57%    100.00%
-system.ruby.L1Cache_Controller.Data_Owner::total          289                      
-system.ruby.L1Cache_Controller.Data_All_Tokens |       81911     12.48%     12.48% |       82621     12.59%     25.08% |       82201     12.53%     37.61% |       81831     12.47%     50.08% |       82005     12.50%     62.58% |       81869     12.48%     75.05% |       81876     12.48%     87.53% |       81790     12.47%    100.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens::total       656104                      
-system.ruby.L1Cache_Controller.Ack       |           0      0.00%      0.00% |           2     16.67%     16.67% |           0      0.00%     16.67% |           3     25.00%     41.67% |           1      8.33%     50.00% |           0      0.00%     50.00% |           2     16.67%     66.67% |           4     33.33%    100.00%
-system.ruby.L1Cache_Controller.Ack::total           12                      
-system.ruby.L1Cache_Controller.Ack_All_Tokens |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       222628                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1191.257915                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   899.756167                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   752.985446                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |       59648     26.79%     26.79% |       42765     19.21%     46.00% |       40985     18.41%     64.41% |       43002     19.32%     83.73% |       29309     13.17%     96.89% |        6509      2.92%     99.82% |         406      0.18%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total       222628                      
+system.ruby.Directory_Controller.GETX          239460      0.00%      0.00%
+system.ruby.Directory_Controller.GETS          428967      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown        38034      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown        37727      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner          321      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens       240316      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner          543      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens       381575      0.00%      0.00%
+system.ruby.Directory_Controller.Tokens           112      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens          797      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       622354      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       240209      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX        220941      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS        397128      0.00%      0.00%
+system.ruby.Directory_Controller.O.Lockdown         3790      0.00%      0.00%
+system.ruby.Directory_Controller.O.Data_All_Tokens           54      0.00%      0.00%
+system.ruby.Directory_Controller.O.Tokens           10      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens          794      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX         2346      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETS         3933      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown        16200      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner          320      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens       239889      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner          543      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens       381172      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Tokens          100      0.00%      0.00%
+system.ruby.Directory_Controller.L.GETX           121      0.00%      0.00%
+system.ruby.Directory_Controller.L.GETS           186      0.00%      0.00%
+system.ruby.Directory_Controller.L.Lockdown          271      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown        37725      0.00%      0.00%
+system.ruby.Directory_Controller.L.Data_Owner            1      0.00%      0.00%
+system.ruby.Directory_Controller.L.Data_All_Tokens          344      0.00%      0.00%
+system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens          403      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETX           57      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETS          112      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Lockdown          106      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Data_All_Tokens           29      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Ack_All_Tokens            1      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Data            2      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack       240103      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.GETX          159      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.GETS          140      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Lockdown           11      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Unlockdown            2      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Memory_Data         4297      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Memory_Ack          106      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.GETX          500      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.GETS          898      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Lockdown           24      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data        17632      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.GETX        15336      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.GETS        26570      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown        17632      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Ack_All_Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data       600423      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load      |       50682     12.59%     12.59% |       50375     12.51%     25.10% |       50329     12.50%     37.61% |       50270     12.49%     50.09% |       50502     12.55%     62.64% |       50212     12.47%     75.11% |       50142     12.46%     87.57% |       50051     12.43%    100.00%
+system.ruby.L1Cache_Controller.Load::total       402563                      
+system.ruby.L1Cache_Controller.Store     |       27842     12.42%     12.42% |       28274     12.62%     25.04% |       27922     12.46%     37.50% |       28383     12.66%     50.16% |       27759     12.39%     62.55% |       27925     12.46%     75.01% |       28049     12.51%     87.52% |       27971     12.48%    100.00%
+system.ruby.L1Cache_Controller.Store::total       224125                      
+system.ruby.L1Cache_Controller.L1_Replacement |     1479559     12.54%     12.54% |     1480747     12.55%     25.09% |     1474669     12.50%     37.59% |     1479770     12.54%     50.13% |     1471682     12.47%     62.61% |     1470820     12.47%     75.07% |     1470605     12.46%     87.54% |     1470089     12.46%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total     11797941                      
+system.ruby.L1Cache_Controller.Data_Shared |         200     13.10%     13.10% |         183     11.98%     25.08% |         165     10.81%     35.89% |         194     12.70%     48.59% |         206     13.49%     62.08% |         197     12.90%     74.98% |         182     11.92%     86.90% |         200     13.10%    100.00%
+system.ruby.L1Cache_Controller.Data_Shared::total         1527                      
+system.ruby.L1Cache_Controller.Data_Owner |          30     10.20%     10.20% |          29      9.86%     20.07% |          31     10.54%     30.61% |          36     12.24%     42.86% |          45     15.31%     58.16% |          39     13.27%     71.43% |          42     14.29%     85.71% |          42     14.29%    100.00%
+system.ruby.L1Cache_Controller.Data_Owner::total          294                      
+system.ruby.L1Cache_Controller.Data_All_Tokens |       81637     12.54%     12.54% |       81865     12.57%     25.11% |       81340     12.49%     37.60% |       81615     12.53%     50.13% |       81335     12.49%     62.62% |       81198     12.47%     75.09% |       81224     12.47%     87.56% |       81006     12.44%    100.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens::total       651220                      
+system.ruby.L1Cache_Controller.Ack       |           2     18.18%     18.18% |           2     18.18%     36.36% |           3     27.27%     63.64% |           0      0.00%     63.64% |           0      0.00%     63.64% |           1      9.09%     72.73% |           2     18.18%     90.91% |           1      9.09%    100.00%
+system.ruby.L1Cache_Controller.Ack::total           11                      
+system.ruby.L1Cache_Controller.Ack_All_Tokens |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.Ack_All_Tokens::total            3                      
-system.ruby.L1Cache_Controller.Transient_Local_GETX |      195106     12.49%     12.49% |      195050     12.49%     24.98% |      195093     12.49%     37.47% |      195313     12.51%     49.98% |      195440     12.51%     62.49% |      195030     12.49%     74.98% |      195367     12.51%     87.49% |      195357     12.51%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETX::total      1561756                      
-system.ruby.L1Cache_Controller.Transient_Local_GETS |      352347     12.51%     12.51% |      351718     12.49%     24.99% |      352073     12.50%     37.49% |      352195     12.50%     50.00% |      351891     12.49%     62.49% |      352426     12.51%     75.00% |      352090     12.50%     87.50% |      352196     12.50%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS::total      2816936                      
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total            4                      
-system.ruby.L1Cache_Controller.Persistent_GETX |       13616     12.50%     12.50% |       13644     12.52%     25.02% |       13615     12.50%     37.52% |       13572     12.46%     49.97% |       13607     12.49%     62.46% |       13620     12.50%     74.96% |       13688     12.56%     87.53% |       13592     12.47%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETX::total       108954                      
-system.ruby.L1Cache_Controller.Persistent_GETS |       24975     12.49%     12.49% |       24920     12.47%     24.96% |       24971     12.49%     37.45% |       24992     12.50%     49.96% |       25025     12.52%     62.48% |       25035     12.52%     75.00% |       25004     12.51%     87.51% |       24964     12.49%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS::total       199886                      
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total            3                      
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock |       49211     12.50%     12.50% |       49238     12.51%     25.01% |       49216     12.50%     37.52% |       49238     12.51%     50.03% |       49170     12.49%     62.52% |       49145     12.49%     75.01% |       49110     12.48%     87.49% |       49245     12.51%    100.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total       393573                      
-system.ruby.L1Cache_Controller.Request_Timeout |       33208     12.52%     12.52% |       33841     12.76%     25.27% |       33107     12.48%     37.75% |       32943     12.42%     50.17% |       33071     12.47%     62.64% |       33150     12.50%     75.14% |       33269     12.54%     87.68% |       32690     12.32%    100.00%
-system.ruby.L1Cache_Controller.Request_Timeout::total       265279                      
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX |           5      5.95%      5.95% |          11     13.10%     19.05% |           8      9.52%     28.57% |           9     10.71%     39.29% |          15     17.86%     57.14% |          10     11.90%     69.05% |          10     11.90%     80.95% |          16     19.05%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total           84                      
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS |           9      7.26%      7.26% |           6      4.84%     12.10% |          13     10.48%     22.58% |          12      9.68%     32.26% |          24     19.35%     51.61% |          23     18.55%     70.16% |          18     14.52%     84.68% |          19     15.32%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total          124                      
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers |       77853     12.48%     12.48% |       78535     12.59%     25.08% |       78143     12.53%     37.60% |       77810     12.48%     50.08% |       77949     12.50%     62.58% |       77828     12.48%     75.06% |       77835     12.48%     87.54% |       77726     12.46%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total       623679                      
-system.ruby.L1Cache_Controller.NP.Load   |       50055     12.44%     12.44% |       50685     12.60%     25.04% |       50318     12.51%     37.55% |       50200     12.48%     50.03% |       50501     12.55%     62.59% |       49984     12.43%     75.01% |       50303     12.51%     87.52% |       50198     12.48%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total       402244                      
-system.ruby.L1Cache_Controller.NP.Store  |       27993     12.55%     12.55% |       28040     12.57%     25.13% |       28001     12.56%     37.68% |       27785     12.46%     50.14% |       27658     12.40%     62.54% |       28065     12.58%     75.13% |       27732     12.44%     87.56% |       27741     12.44%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       223015                      
-system.ruby.L1Cache_Controller.NP.Data_Shared |          14     11.86%     11.86% |          17     14.41%     26.27% |          16     13.56%     39.83% |          13     11.02%     50.85% |           8      6.78%     57.63% |          14     11.86%     69.49% |          17     14.41%     83.90% |          19     16.10%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_Shared::total          118                      
-system.ruby.L1Cache_Controller.NP.Data_Owner |           6      6.38%      6.38% |          15     15.96%     22.34% |          12     12.77%     35.11% |          12     12.77%     47.87% |           8      8.51%     56.38% |          12     12.77%     69.15% |          11     11.70%     80.85% |          18     19.15%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_Owner::total           94                      
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens |        4014     12.52%     12.52% |        4049     12.63%     25.15% |        4005     12.49%     37.64% |        3980     12.41%     50.05% |        3998     12.47%     62.52% |        3995     12.46%     74.98% |        4003     12.48%     87.46% |        4021     12.54%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total        32065                      
-system.ruby.L1Cache_Controller.NP.Ack    |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           1     20.00%     60.00% |           2     40.00%    100.00%
-system.ruby.L1Cache_Controller.NP.Ack::total            5                      
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX |      194672     12.49%     12.49% |      194611     12.49%     24.98% |      194621     12.49%     37.47% |      194855     12.51%     49.98% |      195006     12.52%     62.49% |      194570     12.49%     74.98% |      194932     12.51%     87.49% |      194889     12.51%    100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total      1558156                      
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS |      351505     12.51%     12.51% |      350885     12.49%     24.99% |      351223     12.50%     37.49% |      351366     12.50%     49.99% |      351081     12.49%     62.49% |      351596     12.51%     75.00% |      351307     12.50%     87.50% |      351400     12.50%    100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total      2810363                      
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock |       43131     12.51%     12.51% |       43109     12.51%     25.02% |       43069     12.50%     37.52% |       43054     12.49%     50.01% |       43044     12.49%     62.50% |       43094     12.50%     75.00% |       43053     12.49%     87.49% |       43119     12.51%    100.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total       344673                      
-system.ruby.L1Cache_Controller.I.Load    |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total            1                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |          84     12.37%     12.37% |          83     12.22%     24.59% |          95     13.99%     38.59% |          78     11.49%     50.07% |          80     11.78%     61.86% |          95     13.99%     75.85% |          77     11.34%     87.19% |          87     12.81%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total          679                      
-system.ruby.L1Cache_Controller.I.Data_All_Tokens |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Data_All_Tokens::total            3                      
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total            1                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |         202     12.72%     12.72% |         192     12.09%     24.81% |         201     12.66%     37.47% |         180     11.34%     48.80% |         203     12.78%     61.59% |         202     12.72%     74.31% |         204     12.85%     87.15% |         204     12.85%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total         1588                      
-system.ruby.L1Cache_Controller.S.Data_Shared |           1      6.25%      6.25% |           1      6.25%     12.50% |           2     12.50%     25.00% |           4     25.00%     50.00% |           1      6.25%     56.25% |           0      0.00%     56.25% |           4     25.00%     81.25% |           3     18.75%    100.00%
-system.ruby.L1Cache_Controller.S.Data_Shared::total           16                      
-system.ruby.L1Cache_Controller.S.Data_Owner |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETX |      196232     12.51%     12.51% |      195799     12.48%     24.99% |      196154     12.51%     37.50% |      195687     12.48%     49.98% |      196316     12.52%     62.49% |      196150     12.51%     75.00% |      196028     12.50%     87.50% |      196103     12.50%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETX::total      1568469                      
+system.ruby.L1Cache_Controller.Transient_Local_GETS |      351777     12.49%     12.49% |      352077     12.50%     24.99% |      352116     12.50%     37.48% |      352186     12.50%     49.99% |      351951     12.49%     62.48% |      352239     12.50%     74.98% |      352314     12.51%     87.49% |      352412     12.51%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS::total      2817072                      
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.Persistent_GETX |       11862     12.44%     12.44% |       11847     12.42%     24.86% |       11952     12.53%     37.39% |       11999     12.58%     49.97% |       11950     12.53%     62.49% |       11869     12.44%     74.94% |       11944     12.52%     87.46% |       11962     12.54%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETX::total        95385                      
+system.ruby.L1Cache_Controller.Persistent_GETS |       21376     12.51%     12.51% |       21244     12.43%     24.95% |       21303     12.47%     37.41% |       21384     12.52%     49.93% |       21354     12.50%     62.43% |       21395     12.52%     74.95% |       21385     12.52%     87.47% |       21409     12.53%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS::total       170850                      
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock |       42523     12.51%     12.51% |       42669     12.56%     25.07% |       42506     12.51%     37.57% |       42378     12.47%     50.04% |       42457     12.49%     62.54% |       42497     12.50%     75.04% |       42432     12.49%     87.53% |       42390     12.47%    100.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total       339852                      
+system.ruby.L1Cache_Controller.Request_Timeout |       32684     12.55%     12.55% |       33861     13.00%     25.55% |       32124     12.33%     37.89% |       31734     12.19%     50.07% |       32267     12.39%     62.46% |       33153     12.73%     75.19% |       32442     12.46%     87.65% |       32169     12.35%    100.00%
+system.ruby.L1Cache_Controller.Request_Timeout::total       260434                      
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX |           8     11.27%     11.27% |           9     12.68%     23.94% |           6      8.45%     32.39% |          10     14.08%     46.48% |           9     12.68%     59.15% |          13     18.31%     77.46% |           8     11.27%     88.73% |           8     11.27%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total           71                      
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS |          17     15.45%     15.45% |           9      8.18%     23.64% |          12     10.91%     34.55% |          12     10.91%     45.45% |          12     10.91%     56.36% |          16     14.55%     70.91% |          13     11.82%     82.73% |          19     17.27%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total          110                      
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers |       78263     12.53%     12.53% |       78422     12.55%     25.08% |       78036     12.49%     37.57% |       78402     12.55%     50.12% |       77999     12.49%     62.61% |       77876     12.47%     75.08% |       77945     12.48%     87.55% |       77747     12.45%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total       624690                      
+system.ruby.L1Cache_Controller.NP.Load   |       50641     12.59%     12.59% |       50346     12.51%     25.10% |       50307     12.51%     37.61% |       50235     12.49%     50.10% |       50465     12.54%     62.64% |       50181     12.47%     75.11% |       50103     12.45%     87.57% |       50012     12.43%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total       402290                      
+system.ruby.L1Cache_Controller.NP.Store  |       27827     12.42%     12.42% |       28259     12.62%     25.04% |       27909     12.46%     37.50% |       28369     12.67%     50.16% |       27742     12.39%     62.55% |       27906     12.46%     75.01% |       28031     12.51%     87.52% |       27951     12.48%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       223994                      
+system.ruby.L1Cache_Controller.NP.Data_Shared |          12     12.37%     12.37% |          13     13.40%     25.77% |           9      9.28%     35.05% |          11     11.34%     46.39% |          17     17.53%     63.92% |          13     13.40%     77.32% |          13     13.40%     90.72% |           9      9.28%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_Shared::total           97                      
+system.ruby.L1Cache_Controller.NP.Data_Owner |           7      7.53%      7.53% |           9      9.68%     17.20% |           9      9.68%     26.88% |          12     12.90%     39.78% |          17     18.28%     58.06% |          10     10.75%     68.82% |          15     16.13%     84.95% |          14     15.05%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_Owner::total           93                      
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens |        3330     12.69%     12.69% |        3406     12.98%     25.66% |        3272     12.47%     38.13% |        3177     12.10%     50.24% |        3300     12.57%     62.81% |        3285     12.52%     75.33% |        3247     12.37%     87.70% |        3229     12.30%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total        26246                      
+system.ruby.L1Cache_Controller.NP.Ack    |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
+system.ruby.L1Cache_Controller.NP.Ack::total            4                      
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX |      195766     12.51%     12.51% |      195334     12.48%     24.99% |      195705     12.51%     37.50% |      195249     12.48%     49.98% |      195873     12.52%     62.49% |      195671     12.50%     75.00% |      195587     12.50%     87.50% |      195671     12.50%    100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total      1564856                      
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS |      350998     12.49%     12.49% |      351273     12.50%     24.99% |      351329     12.50%     37.48% |      351358     12.50%     49.99% |      351184     12.49%     62.48% |      351458     12.50%     74.98% |      351554     12.51%     87.49% |      351604     12.51%    100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total      2810758                      
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock |       37177     12.51%     12.51% |       37151     12.50%     25.00% |       37150     12.50%     37.50% |       37175     12.50%     50.00% |       37190     12.51%     62.51% |       37145     12.49%     75.01% |       37164     12.50%     87.51% |       37143     12.49%    100.00%
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total       297295                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |          77     11.83%     11.83% |          84     12.90%     24.73% |          86     13.21%     37.94% |          78     11.98%     49.92% |          83     12.75%     62.67% |          85     13.06%     75.73% |          91     13.98%     89.71% |          67     10.29%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total          651                      
+system.ruby.L1Cache_Controller.I.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total            3                      
+system.ruby.L1Cache_Controller.I.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.Persistent_GETS::total            3                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |         210     13.21%     13.21% |         190     11.95%     25.16% |         180     11.32%     36.48% |         210     13.21%     49.69% |         206     12.96%     62.64% |         196     12.33%     74.97% |         187     11.76%     86.73% |         211     13.27%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total         1590                      
+system.ruby.L1Cache_Controller.S.Data_Shared |           5     25.00%     25.00% |           2     10.00%     35.00% |           0      0.00%     35.00% |           2     10.00%     45.00% |           2     10.00%     55.00% |           3     15.00%     70.00% |           1      5.00%     75.00% |           5     25.00%    100.00%
+system.ruby.L1Cache_Controller.S.Data_Shared::total           20                      
+system.ruby.L1Cache_Controller.S.Data_Owner |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
 system.ruby.L1Cache_Controller.S.Data_Owner::total            1                      
-system.ruby.L1Cache_Controller.S.Data_All_Tokens |           1      9.09%      9.09% |           0      0.00%      9.09% |           1      9.09%     18.18% |           2     18.18%     36.36% |           2     18.18%     54.55% |           3     27.27%     81.82% |           1      9.09%     90.91% |           1      9.09%    100.00%
-system.ruby.L1Cache_Controller.S.Data_All_Tokens::total           11                      
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total            2                      
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total            4                      
-system.ruby.L1Cache_Controller.S.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETX::total            3                      
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total            3                      
-system.ruby.L1Cache_Controller.O.L1_Replacement |          56     11.86%     11.86% |          64     13.56%     25.42% |          50     10.59%     36.02% |          70     14.83%     50.85% |          61     12.92%     63.77% |          57     12.08%     75.85% |          51     10.81%     86.65% |          63     13.35%    100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total          472                      
-system.ruby.L1Cache_Controller.O.Data_All_Tokens |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Data_All_Tokens::total            3                      
-system.ruby.L1Cache_Controller.O.Ack     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.S.Data_All_Tokens |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           1     20.00%     80.00% |           1     20.00%    100.00%
+system.ruby.L1Cache_Controller.S.Data_All_Tokens::total            5                      
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total            3                      
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.S.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETX::total            2                      
+system.ruby.L1Cache_Controller.S.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETS::total            1                      
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.O.L1_Replacement |          58     12.18%     12.18% |          57     11.97%     24.16% |          45      9.45%     33.61% |          63     13.24%     46.85% |          62     13.03%     59.87% |          56     11.76%     71.64% |          63     13.24%     84.87% |          72     15.13%    100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total          476                      
+system.ruby.L1Cache_Controller.O.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Data_All_Tokens::total            4                      
+system.ruby.L1Cache_Controller.O.Ack     |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.O.Ack::total            1                      
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total            2                      
-system.ruby.L1Cache_Controller.O.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETX::total            2                      
-system.ruby.L1Cache_Controller.O.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total            2                      
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total            1                      
+system.ruby.L1Cache_Controller.O.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.O.Persistent_GETS::total            1                      
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock |           8     16.33%     16.33% |           8     16.33%     32.65% |           3      6.12%     38.78% |           7     14.29%     53.06% |           7     14.29%     67.35% |           5     10.20%     77.55% |           7     14.29%     91.84% |           4      8.16%    100.00%
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total           49                      
-system.ruby.L1Cache_Controller.M.Load    |           5     16.67%     16.67% |           3     10.00%     26.67% |           0      0.00%     26.67% |           6     20.00%     46.67% |           3     10.00%     56.67% |           5     16.67%     73.33% |           4     13.33%     86.67% |           4     13.33%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total           30                      
-system.ruby.L1Cache_Controller.M.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     28.57%     28.57% |           3     42.86%     71.43% |           1     14.29%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           1     14.29%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total            7                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |       49776     12.44%     12.44% |       50403     12.60%     25.04% |       50051     12.51%     37.55% |       49936     12.48%     50.04% |       50218     12.55%     62.59% |       49702     12.42%     75.01% |       50042     12.51%     87.52% |       49911     12.48%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       400039                      
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX |          22     14.10%     14.10% |          21     13.46%     27.56% |          23     14.74%     42.31% |          18     11.54%     53.85% |          15      9.62%     63.46% |          15      9.62%     73.08% |          21     13.46%     86.54% |          21     13.46%    100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total          156                      
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS |          35     12.24%     12.24% |          37     12.94%     25.17% |          32     11.19%     36.36% |          44     15.38%     51.75% |          40     13.99%     65.73% |          32     11.19%     76.92% |          29     10.14%     87.06% |          37     12.94%    100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total          286                      
-system.ruby.L1Cache_Controller.M.Persistent_GETX |           7     10.61%     10.61% |          10     15.15%     25.76% |           9     13.64%     39.39% |           8     12.12%     51.52% |          12     18.18%     69.70% |           7     10.61%     80.30% |           6      9.09%     89.39% |           7     10.61%    100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETX::total           66                      
-system.ruby.L1Cache_Controller.M.Persistent_GETS |          15     16.48%     16.48% |          10     10.99%     27.47% |          17     18.68%     46.15% |          14     15.38%     61.54% |           7      7.69%     69.23% |          11     12.09%     81.32% |           9      9.89%     91.21% |           8      8.79%    100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETS::total           91                      
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock |         294     12.03%     12.03% |         300     12.27%     24.30% |         315     12.89%     37.19% |         322     13.18%     50.37% |         304     12.44%     62.81% |         298     12.19%     75.00% |         316     12.93%     87.93% |         295     12.07%    100.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total         2444                      
-system.ruby.L1Cache_Controller.MM.Load   |           4     23.53%     23.53% |           2     11.76%     35.29% |           3     17.65%     52.94% |           1      5.88%     58.82% |           2     11.76%     70.59% |           1      5.88%     76.47% |           2     11.76%     88.24% |           2     11.76%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           17                      
-system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.MM.Store::total            4                      
-system.ruby.L1Cache_Controller.MM.L1_Replacement |       27953     12.55%     12.55% |       28013     12.58%     25.13% |       27961     12.55%     37.68% |       27754     12.46%     50.14% |       27630     12.41%     62.55% |       28013     12.58%     75.13% |       27692     12.43%     87.56% |       27705     12.44%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total       222721                      
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX |          14     17.07%     17.07% |           8      9.76%     26.83% |          13     15.85%     42.68% |           7      8.54%     51.22% |           8      9.76%     60.98% |          15     18.29%     79.27% |           8      9.76%     89.02% |           9     10.98%    100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total           82                      
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS |          23     15.33%     15.33% |          21     14.00%     29.33% |          25     16.67%     46.00% |          19     12.67%     58.67% |          10      6.67%     65.33% |          19     12.67%     78.00% |          16     10.67%     88.67% |          17     11.33%    100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total          150                      
-system.ruby.L1Cache_Controller.MM.Persistent_GETX |           5     15.15%     15.15% |           1      3.03%     18.18% |           6     18.18%     36.36% |           4     12.12%     48.48% |           2      6.06%     54.55% |           8     24.24%     78.79% |           6     18.18%     96.97% |           1      3.03%    100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETX::total           33                      
-system.ruby.L1Cache_Controller.MM.Persistent_GETS |           6      8.57%      8.57% |          11     15.71%     24.29% |           8     11.43%     35.71% |           9     12.86%     48.57% |           9     12.86%     61.43% |          10     14.29%     75.71% |           6      8.57%     84.29% |          11     15.71%    100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETS::total           70                      
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock |         152     11.86%     11.86% |         150     11.70%     23.56% |         155     12.09%     35.65% |         177     13.81%     49.45% |         183     14.27%     63.73% |         147     11.47%     75.20% |         173     13.49%     88.69% |         145     11.31%    100.00%
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total         1282                      
-system.ruby.L1Cache_Controller.M_W.Load  |           8     11.59%     11.59% |          10     14.49%     26.09% |          10     14.49%     40.58% |           5      7.25%     47.83% |          14     20.29%     68.12% |           7     10.14%     78.26% |           8     11.59%     89.86% |           7     10.14%    100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total           69                      
-system.ruby.L1Cache_Controller.M_W.Store |           6     28.57%     28.57% |           2      9.52%     38.10% |           4     19.05%     57.14% |           1      4.76%     61.90% |           1      4.76%     66.67% |           2      9.52%     76.19% |           0      0.00%     76.19% |           5     23.81%    100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total           21                      
-system.ruby.L1Cache_Controller.M_W.L1_Replacement |      361207     12.32%     12.32% |      368703     12.58%     24.90% |      366785     12.51%     37.41% |      366334     12.50%     49.91% |      368143     12.56%     62.47% |      365562     12.47%     74.94% |      366558     12.50%     87.44% |      368107     12.56%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      2931399                      
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX |          57     12.08%     12.08% |          59     12.50%     24.58% |          64     13.56%     38.14% |          52     11.02%     49.15% |          55     11.65%     60.81% |          72     15.25%     76.06% |          57     12.08%     88.14% |          56     11.86%    100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total          472                      
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS |         105     12.95%     12.95% |         101     12.45%     25.40% |         104     12.82%     38.22% |         106     13.07%     51.29% |          91     11.22%     62.52% |         110     13.56%     76.08% |          95     11.71%     87.79% |          99     12.21%    100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total          811                      
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX |           1      2.13%      2.13% |           6     12.77%     14.89% |           5     10.64%     25.53% |           6     12.77%     38.30% |          12     25.53%     63.83% |           6     12.77%     76.60% |           4      8.51%     85.11% |           7     14.89%    100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total           47                      
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS |           8      9.20%      9.20% |           4      4.60%     13.79% |          10     11.49%     25.29% |           8      9.20%     34.48% |          16     18.39%     52.87% |          13     14.94%     67.82% |          14     16.09%     83.91% |          14     16.09%    100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total           87                      
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock |         450     12.82%     12.82% |         461     13.13%     25.95% |         453     12.90%     38.85% |         452     12.87%     51.72% |         381     10.85%     62.57% |         401     11.42%     74.00% |         458     13.04%     87.04% |         455     12.96%    100.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total         3511                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX |           1      2.08%      2.08% |           6     12.50%     14.58% |           5     10.42%     25.00% |           6     12.50%     37.50% |          12     25.00%     62.50% |           6     12.50%     75.00% |           4      8.33%     83.33% |           8     16.67%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total           48                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS |           8      8.60%      8.60% |           5      5.38%     13.98% |          10     10.75%     24.73% |          10     10.75%     35.48% |          17     18.28%     53.76% |          13     13.98%     67.74% |          15     16.13%     83.87% |          15     16.13%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total           93                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers |       49852     12.44%     12.44% |       50481     12.60%     25.04% |       50132     12.51%     37.56% |       50020     12.49%     50.04% |       50291     12.55%     62.60% |       49763     12.42%     75.02% |       50106     12.51%     87.52% |       49984     12.48%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total       400629                      
-system.ruby.L1Cache_Controller.MM_W.Load |           2      8.00%      8.00% |           3     12.00%     20.00% |           2      8.00%     28.00% |           4     16.00%     44.00% |           3     12.00%     56.00% |           7     28.00%     84.00% |           3     12.00%     96.00% |           1      4.00%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total           25                      
-system.ruby.L1Cache_Controller.MM_W.Store |           2     14.29%     14.29% |           3     21.43%     35.71% |           2     14.29%     50.00% |           3     21.43%     71.43% |           1      7.14%     78.57% |           0      0.00%     78.57% |           1      7.14%     85.71% |           2     14.29%    100.00%
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock |           9     16.67%     16.67% |           2      3.70%     20.37% |           3      5.56%     25.93% |           9     16.67%     42.59% |           7     12.96%     55.56% |           8     14.81%     70.37% |           8     14.81%     85.19% |           8     14.81%    100.00%
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total           54                      
+system.ruby.L1Cache_Controller.M.Load    |           5     17.86%     17.86% |           4     14.29%     32.14% |           1      3.57%     35.71% |           2      7.14%     42.86% |           5     17.86%     60.71% |           1      3.57%     64.29% |           4     14.29%     78.57% |           6     21.43%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total           28                      
+system.ruby.L1Cache_Controller.M.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     37.50%     37.50% |           1     12.50%     50.00% |           0      0.00%     50.00% |           1     12.50%     62.50% |           1     12.50%     75.00% |           2     25.00%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total            8                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |       50355     12.59%     12.59% |       50070     12.52%     25.10% |       50054     12.51%     37.62% |       49943     12.48%     50.10% |       50172     12.54%     62.64% |       49895     12.47%     75.12% |       49825     12.46%     87.57% |       49715     12.43%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       400029                      
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX |          15      9.32%      9.32% |          25     15.53%     24.84% |          19     11.80%     36.65% |          21     13.04%     49.69% |          24     14.91%     64.60% |          23     14.29%     78.88% |          24     14.91%     93.79% |          10      6.21%    100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total          161                      
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS |          36     12.63%     12.63% |          38     13.33%     25.96% |          24      8.42%     34.39% |          39     13.68%     48.07% |          36     12.63%     60.70% |          30     10.53%     71.23% |          38     13.33%     84.56% |          44     15.44%    100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total          285                      
+system.ruby.L1Cache_Controller.M.Persistent_GETX |          11     16.42%     16.42% |           9     13.43%     29.85% |          10     14.93%     44.78% |           4      5.97%     50.75% |           8     11.94%     62.69% |           7     10.45%     73.13% |          11     16.42%     89.55% |           7     10.45%    100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETX::total           67                      
+system.ruby.L1Cache_Controller.M.Persistent_GETS |          17     13.82%     13.82% |          16     13.01%     26.83% |          18     14.63%     41.46% |          24     19.51%     60.98% |          15     12.20%     73.17% |           9      7.32%     80.49% |          10      8.13%     88.62% |          14     11.38%    100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETS::total          123                      
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock |         274     12.00%     12.00% |         302     13.22%     25.22% |         296     12.96%     38.18% |         287     12.57%     50.74% |         274     12.00%     62.74% |         276     12.08%     74.82% |         270     11.82%     86.65% |         305     13.35%    100.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total         2284                      
+system.ruby.L1Cache_Controller.MM.Load   |           1      6.67%      6.67% |           2     13.33%     20.00% |           1      6.67%     26.67% |           3     20.00%     46.67% |           2     13.33%     60.00% |           4     26.67%     86.67% |           0      0.00%     86.67% |           2     13.33%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           15                      
+system.ruby.L1Cache_Controller.MM.Store  |           1     10.00%     10.00% |           2     20.00%     30.00% |           1     10.00%     40.00% |           0      0.00%     40.00% |           2     20.00%     60.00% |           2     20.00%     80.00% |           0      0.00%     80.00% |           2     20.00%    100.00%
+system.ruby.L1Cache_Controller.MM.Store::total           10                      
+system.ruby.L1Cache_Controller.MM.L1_Replacement |       27793     12.42%     12.42% |       28225     12.62%     25.04% |       27866     12.46%     37.49% |       28335     12.66%     50.16% |       27712     12.39%     62.54% |       27881     12.46%     75.01% |       27995     12.51%     87.52% |       27922     12.48%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total       223729                      
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX |          11     12.94%     12.94% |          15     17.65%     30.59% |          10     11.76%     42.35% |          10     11.76%     54.12% |           9     10.59%     64.71% |          15     17.65%     82.35% |           8      9.41%     91.76% |           7      8.24%    100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total           85                      
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS |          18     13.14%     13.14% |          16     11.68%     24.82% |          19     13.87%     38.69% |          12      8.76%     47.45% |          16     11.68%     59.12% |          11      8.03%     67.15% |          25     18.25%     85.40% |          20     14.60%    100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total          137                      
+system.ruby.L1Cache_Controller.MM.Persistent_GETX |           3      9.68%      9.68% |           3      9.68%     19.35% |           4     12.90%     32.26% |           7     22.58%     54.84% |           3      9.68%     64.52% |           5     16.13%     80.65% |           3      9.68%     90.32% |           3      9.68%    100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETX::total           31                      
+system.ruby.L1Cache_Controller.MM.Persistent_GETS |           4      8.16%      8.16% |           5     10.20%     18.37% |          11     22.45%     40.82% |           7     14.29%     55.10% |           6     12.24%     67.35% |           2      4.08%     71.43% |           8     16.33%     87.76% |           6     12.24%    100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETS::total           49                      
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock |         147     11.73%     11.73% |         165     13.17%     24.90% |         166     13.25%     38.15% |         141     11.25%     49.40% |         139     11.09%     60.49% |         187     14.92%     75.42% |         164     13.09%     88.51% |         144     11.49%    100.00%
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total         1253                      
+system.ruby.L1Cache_Controller.M_W.Load  |           6     12.77%     12.77% |           6     12.77%     25.53% |           4      8.51%     34.04% |           9     19.15%     53.19% |           3      6.38%     59.57% |           4      8.51%     68.09% |           8     17.02%     85.11% |           7     14.89%    100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total           47                      
+system.ruby.L1Cache_Controller.M_W.Store |           3     11.54%     11.54% |           3     11.54%     23.08% |           3     11.54%     34.62% |           1      3.85%     38.46% |           4     15.38%     53.85% |           4     15.38%     69.23% |           6     23.08%     92.31% |           2      7.69%    100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total           26                      
+system.ruby.L1Cache_Controller.M_W.L1_Replacement |      366785     12.57%     12.57% |      364136     12.48%     25.04% |      364171     12.48%     37.52% |      365652     12.53%     50.05% |      367583     12.59%     62.64% |      363631     12.46%     75.10% |      363794     12.46%     87.57% |      362856     12.43%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      2918608                      
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX |          64     13.06%     13.06% |          57     11.63%     24.69% |          61     12.45%     37.14% |          57     11.63%     48.78% |          64     13.06%     61.84% |          58     11.84%     73.67% |          63     12.86%     86.53% |          66     13.47%    100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total          490                      
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS |         124     15.10%     15.10% |         103     12.55%     27.65% |          88     10.72%     38.37% |         113     13.76%     52.13% |          92     11.21%     63.34% |         100     12.18%     75.52% |         104     12.67%     88.19% |          97     11.81%    100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total          821                      
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX |           7     14.58%     14.58% |           4      8.33%     22.92% |           4      8.33%     31.25% |           5     10.42%     41.67% |           7     14.58%     56.25% |          10     20.83%     77.08% |           5     10.42%     87.50% |           6     12.50%    100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total           48                      
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS |          11     15.94%     15.94% |           8     11.59%     27.54% |           7     10.14%     37.68% |           7     10.14%     47.83% |           5      7.25%     55.07% |           8     11.59%     66.67% |          10     14.49%     81.16% |          13     18.84%    100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total           69                      
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock |         444     13.26%     13.26% |         440     13.14%     26.40% |         447     13.35%     39.76% |         403     12.04%     51.79% |         444     13.26%     65.05% |         402     12.01%     77.06% |         363     10.84%     87.90% |         405     12.10%    100.00%
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total         3348                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX |           7     14.00%     14.00% |           4      8.00%     22.00% |           4      8.00%     30.00% |           5     10.00%     40.00% |           7     14.00%     54.00% |          12     24.00%     78.00% |           5     10.00%     88.00% |           6     12.00%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total           50                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS |          11     15.71%     15.71% |           8     11.43%     27.14% |           7     10.00%     37.14% |           7     10.00%     47.14% |           5      7.14%     54.29% |           9     12.86%     67.14% |          10     14.29%     81.43% |          13     18.57%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total           70                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers |       50434     12.59%     12.59% |       50157     12.52%     25.11% |       50128     12.51%     37.62% |       50032     12.49%     50.10% |       50253     12.54%     62.65% |       49963     12.47%     75.12% |       49907     12.46%     87.57% |       49791     12.43%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total       400665                      
+system.ruby.L1Cache_Controller.MM_W.Load |           8     24.24%     24.24% |           1      3.03%     27.27% |           1      3.03%     30.30% |           3      9.09%     39.39% |           4     12.12%     51.52% |           3      9.09%     60.61% |           4     12.12%     72.73% |           9     27.27%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total           33                      
+system.ruby.L1Cache_Controller.MM_W.Store |           3     21.43%     21.43% |           1      7.14%     28.57% |           2     14.29%     42.86% |           1      7.14%     50.00% |           2     14.29%     64.29% |           1      7.14%     71.43% |           3     21.43%     92.86% |           1      7.14%    100.00%
 system.ruby.L1Cache_Controller.MM_W.Store::total           14                      
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      205695     12.56%     12.56% |      204042     12.46%     25.01% |      205541     12.55%     37.56% |      204063     12.46%     50.01% |      203908     12.45%     62.46% |      207650     12.68%     75.14% |      205078     12.52%     87.66% |      202224     12.34%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      1638201                      
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX |          28     10.98%     10.98% |          23      9.02%     20.00% |          40     15.69%     35.69% |          41     16.08%     51.76% |          33     12.94%     64.71% |          35     13.73%     78.43% |          23      9.02%     87.45% |          32     12.55%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total          255                      
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS |          61     13.17%     13.17% |          44      9.50%     22.68% |          64     13.82%     36.50% |          70     15.12%     51.62% |          76     16.41%     68.03% |          48     10.37%     78.40% |          51     11.02%     89.42% |          49     10.58%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total          463                      
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX |           4     11.76%     11.76% |           5     14.71%     26.47% |           3      8.82%     35.29% |           3      8.82%     44.12% |           3      8.82%     52.94% |           4     11.76%     64.71% |           5     14.71%     79.41% |           7     20.59%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total           34                      
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS |           1      3.57%      3.57% |           1      3.57%      7.14% |           3     10.71%     17.86% |           1      3.57%     21.43% |           6     21.43%     42.86% |          10     35.71%     78.57% |           2      7.14%     85.71% |           4     14.29%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total           28                      
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock |         239     12.35%     12.35% |         242     12.51%     24.86% |         240     12.40%     37.26% |         257     13.28%     50.54% |         244     12.61%     63.15% |         254     13.13%     76.28% |         213     11.01%     87.29% |         246     12.71%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total         1935                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX |           4     11.11%     11.11% |           5     13.89%     25.00% |           3      8.33%     33.33% |           3      8.33%     41.67% |           3      8.33%     50.00% |           4     11.11%     61.11% |           6     16.67%     77.78% |           8     22.22%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total           36                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS |           1      3.23%      3.23% |           1      3.23%      6.45% |           3      9.68%     16.13% |           2      6.45%     22.58% |           7     22.58%     45.16% |          10     32.26%     77.42% |           3      9.68%     87.10% |           4     12.90%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total           31                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers |       28001     12.55%     12.55% |       28054     12.58%     25.13% |       28011     12.56%     37.69% |       27790     12.46%     50.15% |       27658     12.40%     62.55% |       28065     12.58%     75.13% |       27729     12.43%     87.56% |       27742     12.44%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total       223050                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |      295093     12.61%     12.61% |      294925     12.61%     25.22% |      294016     12.57%     37.79% |      291033     12.44%     50.23% |      290166     12.40%     62.64% |      294109     12.57%     75.21% |      290971     12.44%     87.65% |      288911     12.35%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total      2339224                      
-system.ruby.L1Cache_Controller.IM.Data_Owner |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      206388     12.57%     12.57% |      205534     12.52%     25.09% |      205266     12.50%     37.60% |      207686     12.65%     50.25% |      201809     12.29%     62.54% |      204178     12.44%     74.98% |      204640     12.47%     87.44% |      206137     12.56%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      1641638                      
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX |          39     15.06%     15.06% |          31     11.97%     27.03% |          29     11.20%     38.22% |          28     10.81%     49.03% |          36     13.90%     62.93% |          31     11.97%     74.90% |          35     13.51%     88.42% |          30     11.58%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total          259                      
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS |          58     12.18%     12.18% |          74     15.55%     27.73% |          62     13.03%     40.76% |          36      7.56%     48.32% |          61     12.82%     61.13% |          66     13.87%     75.00% |          64     13.45%     88.45% |          55     11.55%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total          476                      
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX |           1      5.00%      5.00% |           5     25.00%     30.00% |           2     10.00%     40.00% |           4     20.00%     60.00% |           2     10.00%     70.00% |           1      5.00%     75.00% |           3     15.00%     90.00% |           2     10.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total           20                      
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS |           6     15.38%     15.38% |           1      2.56%     17.95% |           5     12.82%     30.77% |           5     12.82%     43.59% |           7     17.95%     61.54% |           7     17.95%     79.49% |           3      7.69%     87.18% |           5     12.82%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total           39                      
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock |         228     12.34%     12.34% |         250     13.53%     25.87% |         228     12.34%     38.20% |         228     12.34%     50.54% |         244     13.20%     63.74% |         231     12.50%     76.24% |         214     11.58%     87.82% |         225     12.18%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total         1848                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX |           1      4.76%      4.76% |           5     23.81%     28.57% |           2      9.52%     38.10% |           5     23.81%     61.90% |           2      9.52%     71.43% |           1      4.76%     76.19% |           3     14.29%     90.48% |           2      9.52%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total           21                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS |           6     15.00%     15.00% |           1      2.50%     17.50% |           5     12.50%     30.00% |           5     12.50%     42.50% |           7     17.50%     60.00% |           7     17.50%     77.50% |           3      7.50%     85.00% |           6     15.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total           40                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers |       27829     12.42%     12.42% |       28265     12.62%     25.04% |       27908     12.46%     37.50% |       28370     12.66%     50.16% |       27746     12.39%     62.55% |       27913     12.46%     75.01% |       28038     12.52%     87.52% |       27956     12.48%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total       224025                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |      296218     12.51%     12.51% |      301018     12.71%     25.23% |      295962     12.50%     37.73% |      297411     12.56%     50.29% |      293177     12.38%     62.67% |      292697     12.36%     75.04% |      294725     12.45%     87.49% |      296256     12.51%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total      2367464                      
+system.ruby.L1Cache_Controller.IM.Data_Owner |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.IM.Data_Owner::total            3                      
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens |       28000     12.55%     12.55% |       28057     12.58%     25.13% |       28014     12.56%     37.68% |       27793     12.46%     50.14% |       27665     12.40%     62.54% |       28078     12.59%     75.13% |       27738     12.43%     87.56% |       27748     12.44%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total       223093                      
-system.ruby.L1Cache_Controller.IM.Ack    |           0      0.00%      0.00% |           1     16.67%     16.67% |           0      0.00%     16.67% |           2     33.33%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total            6                      
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX |          90     11.97%     11.97% |         100     13.30%     25.27% |          94     12.50%     37.77% |          98     13.03%     50.80% |          73      9.71%     60.51% |          97     12.90%     73.40% |         103     13.70%     87.10% |          97     12.90%    100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total          752                      
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS |         161     12.28%     12.28% |         188     14.34%     26.62% |         172     13.12%     39.74% |         163     12.43%     52.17% |         159     12.13%     64.30% |         175     13.35%     77.65% |         133     10.14%     87.80% |         160     12.20%    100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total         1311                      
-system.ruby.L1Cache_Controller.IM.Persistent_GETX |           7      9.86%      9.86% |          13     18.31%     28.17% |           8     11.27%     39.44% |          11     15.49%     54.93% |          11     15.49%     70.42% |           8     11.27%     81.69% |           6      8.45%     90.14% |           7      9.86%    100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETX::total           71                      
-system.ruby.L1Cache_Controller.IM.Persistent_GETS |          12     10.34%     10.34% |           7      6.03%     16.38% |          16     13.79%     30.17% |          11      9.48%     39.66% |          15     12.93%     52.59% |          20     17.24%     69.83% |          18     15.52%     85.34% |          17     14.66%    100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETS::total          116                      
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock |        1699     12.54%     12.54% |        1672     12.34%     24.89% |        1699     12.54%     37.43% |        1727     12.75%     50.18% |        1702     12.57%     62.75% |        1679     12.40%     75.15% |        1654     12.21%     87.36% |        1712     12.64%    100.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total        13544                      
-system.ruby.L1Cache_Controller.IM.Request_Timeout |       11980     12.55%     12.55% |       12224     12.80%     25.35% |       11886     12.45%     37.80% |       11479     12.02%     49.82% |       11994     12.56%     62.39% |       12457     13.05%     75.43% |       12326     12.91%     88.35% |       11127     11.65%    100.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout::total        95473                      
-system.ruby.L1Cache_Controller.OM.L1_Replacement |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          40     57.14%     57.14% |           0      0.00%     57.14% |           0      0.00%     57.14% |          30     42.86%    100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total           70                      
-system.ruby.L1Cache_Controller.OM.Ack_All_Tokens |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens |       27833     12.42%     12.42% |       28267     12.62%     25.04% |       27913     12.46%     37.50% |       28379     12.67%     50.16% |       27750     12.39%     62.55% |       27915     12.46%     75.01% |       28038     12.51%     87.52% |       27961     12.48%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total       224056                      
+system.ruby.L1Cache_Controller.IM.Ack    |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total            4                      
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX |          90     12.28%     12.28% |          99     13.51%     25.78% |         102     13.92%     39.70% |          91     12.41%     52.11% |          75     10.23%     62.35% |         113     15.42%     77.76% |          78     10.64%     88.40% |          85     11.60%    100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total          733                      
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS |         148     11.45%     11.45% |         145     11.21%     22.66% |         163     12.61%     35.27% |         181     14.00%     49.27% |         167     12.92%     62.18% |         179     13.84%     76.02% |         159     12.30%     88.32% |         151     11.68%    100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total         1293                      
+system.ruby.L1Cache_Controller.IM.Persistent_GETX |           7     13.21%     13.21% |           8     15.09%     28.30% |           4      7.55%     35.85% |           6     11.32%     47.17% |          11     20.75%     67.92% |           4      7.55%     75.47% |           4      7.55%     83.02% |           9     16.98%    100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETX::total           53                      
+system.ruby.L1Cache_Controller.IM.Persistent_GETS |          13     10.92%     10.92% |          15     12.61%     23.53% |          13     10.92%     34.45% |          13     10.92%     45.38% |          16     13.45%     58.82% |          10      8.40%     67.23% |          20     16.81%     84.03% |          19     15.97%    100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETS::total          119                      
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock |        1529     13.05%     13.05% |        1520     12.97%     26.02% |        1441     12.30%     38.32% |        1393     11.89%     50.20% |        1425     12.16%     62.37% |        1519     12.96%     75.33% |        1459     12.45%     87.78% |        1432     12.22%    100.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total        11718                      
+system.ruby.L1Cache_Controller.IM.Request_Timeout |       11235     12.07%     12.07% |       12352     13.27%     25.33% |       11420     12.27%     37.60% |       11309     12.15%     49.74% |       11543     12.40%     62.14% |       11451     12.30%     74.44% |       11863     12.74%     87.18% |       11935     12.82%    100.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout::total        93108                      
+system.ruby.L1Cache_Controller.OM.L1_Replacement |           0      0.00%      0.00% |          27    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement::total           27                      
+system.ruby.L1Cache_Controller.OM.Ack_All_Tokens |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total            3                      
-system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total            2                      
-system.ruby.L1Cache_Controller.OM.Request_Timeout |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Request_Timeout::total            2                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |      527596     12.50%     12.50% |      534359     12.66%     25.17% |      527205     12.49%     37.66% |      528297     12.52%     50.18% |      528825     12.53%     62.71% |      521299     12.35%     75.07% |      526429     12.48%     87.54% |      525605     12.46%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total      4219615                      
-system.ruby.L1Cache_Controller.IS.Data_Shared |         181     12.75%     12.75% |         177     12.46%     25.21% |         176     12.39%     37.61% |         159     11.20%     48.80% |         181     12.75%     61.55% |         182     12.82%     74.37% |         182     12.82%     87.18% |         182     12.82%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared::total         1420                      
-system.ruby.L1Cache_Controller.IS.Data_Owner |          22     11.52%     11.52% |          27     14.14%     25.65% |          18      9.42%     35.08% |          26     13.61%     48.69% |          24     12.57%     61.26% |          26     13.61%     74.87% |          22     11.52%     86.39% |          26     13.61%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Owner::total          191                      
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens |       49867     12.44%     12.44% |       50496     12.60%     25.04% |       50150     12.51%     37.55% |       50036     12.48%     50.04% |       50320     12.56%     62.59% |       49785     12.42%     75.02% |       50124     12.51%     87.52% |       50011     12.48%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total       400789                      
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX |         152     11.69%     11.69% |         159     12.23%     23.92% |         175     13.46%     37.38% |         167     12.85%     50.23% |         173     13.31%     63.54% |         154     11.85%     75.38% |         145     11.15%     86.54% |         175     13.46%    100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total         1300                      
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS |         325     12.87%     12.87% |         314     12.44%     25.31% |         332     13.15%     38.46% |         302     11.96%     50.42% |         305     12.08%     62.50% |         312     12.36%     74.85% |         322     12.75%     87.60% |         313     12.40%    100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total         2525                      
-system.ruby.L1Cache_Controller.IS.Persistent_GETX |          14     12.17%     12.17% |          10      8.70%     20.87% |          18     15.65%     36.52% |          14     12.17%     48.70% |          17     14.78%     63.48% |          12     10.43%     73.91% |          19     16.52%     90.43% |          11      9.57%    100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETX::total          115                      
-system.ruby.L1Cache_Controller.IS.Persistent_GETS |          28     11.72%     11.72% |          23      9.62%     21.34% |          32     13.39%     34.73% |          25     10.46%     45.19% |          35     14.64%     59.83% |          32     13.39%     73.22% |          39     16.32%     89.54% |          25     10.46%    100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETS::total          239                      
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock |        3103     12.48%     12.48% |        3161     12.72%     25.20% |        3104     12.49%     37.69% |        3090     12.43%     50.12% |        3120     12.55%     62.67% |        3099     12.47%     75.14% |        3066     12.34%     87.48% |        3113     12.52%    100.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total        24856                      
-system.ruby.L1Cache_Controller.IS.Request_Timeout |       21020     12.47%     12.47% |       21488     12.74%     25.21% |       21067     12.49%     37.70% |       21326     12.65%     50.35% |       20944     12.42%     62.77% |       20610     12.22%     74.99% |       20711     12.28%     87.27% |       21463     12.73%    100.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout::total       168629                      
-system.ruby.L1Cache_Controller.I_L.Load  |          18     10.06%     10.06% |          16      8.94%     18.99% |          29     16.20%     35.20% |          27     15.08%     50.28% |          27     15.08%     65.36% |          11      6.15%     71.51% |          26     14.53%     86.03% |          25     13.97%    100.00%
-system.ruby.L1Cache_Controller.I_L.Load::total          179                      
-system.ruby.L1Cache_Controller.I_L.Store |           9      9.68%      9.68% |          18     19.35%     29.03% |          14     15.05%     44.09% |          10     10.75%     54.84% |          10     10.75%     65.59% |          13     13.98%     79.57% |           9      9.68%     89.25% |          10     10.75%    100.00%
-system.ruby.L1Cache_Controller.I_L.Store::total           93                      
-system.ruby.L1Cache_Controller.I_L.L1_Replacement |         125      9.36%      9.36% |          83      6.21%     15.57% |         178     13.32%     28.89% |         173     12.95%     41.84% |         239     17.89%     59.73% |         184     13.77%     73.50% |         192     14.37%     87.87% |         162     12.13%    100.00%
-system.ruby.L1Cache_Controller.I_L.L1_Replacement::total         1336                      
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens |          27     21.26%     21.26% |          18     14.17%     35.43% |          29     22.83%     58.27% |          16     12.60%     70.87% |          17     13.39%     84.25% |           7      5.51%     89.76% |           7      5.51%     95.28% |           6      4.72%    100.00%
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total          127                      
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX |          69     11.94%     11.94% |          69     11.94%     23.88% |          63     10.90%     34.78% |          75     12.98%     47.75% |          76     13.15%     60.90% |          71     12.28%     73.18% |          78     13.49%     86.68% |          77     13.32%    100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total          578                      
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS |         132     12.88%     12.88% |         128     12.49%     25.37% |         121     11.80%     37.17% |         125     12.20%     49.37% |         127     12.39%     61.76% |         134     13.07%     74.83% |         137     13.37%     88.20% |         121     11.80%    100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total         1025                      
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX |       13578     12.51%     12.51% |       13598     12.53%     25.04% |       13560     12.49%     37.53% |       13520     12.46%     49.98% |       13540     12.47%     62.46% |       13571     12.50%     74.96% |       13635     12.56%     87.52% |       13544     12.48%    100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total       108546                      
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS |       24905     12.51%     12.51% |       24862     12.48%     24.99% |       24875     12.49%     37.48% |       24914     12.51%     49.99% |       24915     12.51%     62.50% |       24926     12.52%     75.02% |       24887     12.50%     87.52% |       24855     12.48%    100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total       199139                      
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock |          25      8.53%      8.53% |          34     11.60%     20.14% |          35     11.95%     32.08% |          35     11.95%     44.03% |          46     15.70%     59.73% |          46     15.70%     75.43% |          32     10.92%     86.35% |          40     13.65%    100.00%
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total          293                      
-system.ruby.L1Cache_Controller.S_L.L1_Replacement |          46     14.37%     14.37% |          31      9.69%     24.06% |          38     11.88%     35.94% |           8      2.50%     38.44% |          52     16.25%     54.69% |          22      6.88%     61.56% |          48     15.00%     76.56% |          75     23.44%    100.00%
-system.ruby.L1Cache_Controller.S_L.L1_Replacement::total          320                      
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS |           0      0.00%      0.00% |           1      3.23%      3.23% |           3      9.68%     12.90% |           4     12.90%     25.81% |           7     22.58%     48.39% |           3      9.68%     58.06% |           7     22.58%     80.65% |           6     19.35%    100.00%
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total           31                      
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock |          23     12.23%     12.23% |          15      7.98%     20.21% |          27     14.36%     34.57% |          24     12.77%     47.34% |          25     13.30%     60.64% |          26     13.83%     74.47% |          24     12.77%     87.23% |          24     12.77%    100.00%
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total          188                      
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement |         143      9.18%      9.18% |         175     11.23%     20.41% |         168     10.78%     31.19% |         236     15.15%     46.34% |         181     11.62%     57.96% |         285     18.29%     76.25% |         169     10.85%     87.10% |         201     12.90%    100.00%
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total         1558                      
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     20.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total            5                      
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total            2                      
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX |           0      0.00%      0.00% |           1     10.00%     10.00% |           1     10.00%     20.00% |           2     20.00%     40.00% |           3     30.00%     70.00% |           1     10.00%     80.00% |           0      0.00%     80.00% |           2     20.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total           10                      
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     16.13%     16.13% |           1      3.23%     19.35% |           4     12.90%     32.26% |           2      6.45%     38.71% |           8     25.81%     64.52% |          11     35.48%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total           31                      
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock |          28     10.18%     10.18% |          38     13.82%     24.00% |          38     13.82%     37.82% |          31     11.27%     49.09% |          35     12.73%     61.82% |          41     14.91%     76.73% |          31     11.27%     88.00% |          33     12.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total          275                      
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout |          22      5.98%      5.98% |          62     16.85%     22.83% |          33      8.97%     31.79% |          61     16.58%     48.37% |          42     11.41%     59.78% |          13      3.53%     63.32% |          89     24.18%     87.50% |          46     12.50%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total          368                      
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement |         404     13.20%     13.20% |         259      8.46%     21.67% |         472     15.42%     37.09% |         362     11.83%     48.92% |         384     12.55%     61.47% |         320     10.46%     71.93% |         506     16.54%     88.46% |         353     11.54%    100.00%
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total         3060                      
-system.ruby.L1Cache_Controller.IS_L.Data_Shared |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           2     50.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_Shared::total            4                      
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens |           0      0.00%      0.00% |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           1     12.50%     62.50% |           0      0.00%     62.50% |           1     12.50%     75.00% |           2     25.00%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total            8                      
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     14.81%     14.81% |           3     11.11%     25.93% |           6     22.22%     48.15% |           2      7.41%     55.56% |           6     22.22%     77.78% |           6     22.22%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total           27                      
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS |           0      0.00%      0.00% |           1      1.89%      1.89% |           2      3.77%      5.66% |           5      9.43%     15.09% |          10     18.87%     33.96% |           8     15.09%     49.06% |          14     26.42%     75.47% |          13     24.53%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total           53                      
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock |          59     11.32%     11.32% |          48      9.21%     20.54% |          78     14.97%     35.51% |          62     11.90%     47.41% |          78     14.97%     62.38% |          55     10.56%     72.94% |          83     15.93%     88.87% |          58     11.13%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total          521                      
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout |         186     23.05%     23.05% |          67      8.30%     31.35% |         121     14.99%     46.34% |          77      9.54%     55.89% |          90     11.15%     67.04% |          70      8.67%     75.71% |         143     17.72%     93.43% |          53      6.57%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total          807                      
-system.ruby.L2Cache_Controller.L1_GETS         402399      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS_Last_Token           20      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         223106      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_INV             683      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement       598575      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data          975      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens       623413      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Owned          430      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX        15565      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS        28553      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock        43680      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       401075      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       222380      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_INV          492      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data          901      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens       597337      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Owned          345      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock        36371      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS           61      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L1_GETX           35      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L1_INV             3      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L2_Replacement         7485      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Shared_Data            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens          457      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Owned            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETX            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETS           15      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token           20      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement          848      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Shared_Data            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Writeback_All_Tokens           42      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Owned            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETS            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement |      531190     12.53%     12.53% |      530879     12.52%     25.06% |      530459     12.51%     37.57% |      529762     12.50%     50.07% |      530166     12.51%     62.58% |      531419     12.54%     75.12% |      528660     12.47%     87.59% |      526084     12.41%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total      4238619                      
+system.ruby.L1Cache_Controller.IS.Data_Shared |         183     13.01%     13.01% |         167     11.87%     24.88% |         156     11.09%     35.96% |         180     12.79%     48.76% |         187     13.29%     62.05% |         181     12.86%     74.91% |         167     11.87%     86.78% |         186     13.22%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared::total         1407                      
+system.ruby.L1Cache_Controller.IS.Data_Owner |          22     11.17%     11.17% |          19      9.64%     20.81% |          22     11.17%     31.98% |          24     12.18%     44.16% |          28     14.21%     58.38% |          28     14.21%     72.59% |          27     13.71%     86.29% |          27     13.71%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Owner::total          197                      
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens |       50456     12.59%     12.59% |       50172     12.52%     25.11% |       50143     12.51%     37.62% |       50046     12.49%     50.10% |       50272     12.54%     62.64% |       49986     12.47%     75.12% |       49929     12.46%     87.57% |       49812     12.43%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total       400816                      
+system.ruby.L1Cache_Controller.IS.Ack    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IS.Ack::total            2                      
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX |         185     13.17%     13.17% |         180     12.81%     25.98% |         163     11.60%     37.58% |         170     12.10%     49.68% |         176     12.53%     62.21% |         180     12.81%     75.02% |         173     12.31%     87.33% |         178     12.67%    100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total         1405                      
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS |         290     12.06%     12.06% |         311     12.94%     25.00% |         311     12.94%     37.94% |         331     13.77%     51.71% |         291     12.10%     63.81% |         280     11.65%     75.46% |         262     10.90%     86.36% |         328     13.64%    100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total         2404                      
+system.ruby.L1Cache_Controller.IS.Persistent_GETX |          17     18.48%     18.48% |          10     10.87%     29.35% |          12     13.04%     42.39% |           8      8.70%     51.09% |          10     10.87%     61.96% |          16     17.39%     79.35% |           7      7.61%     86.96% |          12     13.04%    100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETX::total           92                      
+system.ruby.L1Cache_Controller.IS.Persistent_GETS |          14      8.09%      8.09% |          17      9.83%     17.92% |          21     12.14%     30.06% |          22     12.72%     42.77% |          16      9.25%     52.02% |          32     18.50%     70.52% |          25     14.45%     84.97% |          26     15.03%    100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETS::total          173                      
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock |        2575     12.30%     12.30% |        2712     12.95%     25.25% |        2643     12.62%     37.87% |        2601     12.42%     50.29% |        2597     12.40%     62.69% |        2587     12.35%     75.05% |        2648     12.65%     87.69% |        2577     12.31%    100.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total        20940                      
+system.ruby.L1Cache_Controller.IS.Request_Timeout |       21384     12.87%     12.87% |       21323     12.83%     25.70% |       20616     12.41%     38.11% |       20325     12.23%     50.34% |       20632     12.42%     62.75% |       21552     12.97%     75.72% |       20368     12.26%     87.98% |       19971     12.02%    100.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout::total       166171                      
+system.ruby.L1Cache_Controller.I_L.Load  |          21     14.00%     14.00% |          16     10.67%     24.67% |          15     10.00%     34.67% |          18     12.00%     46.67% |          23     15.33%     62.00% |          19     12.67%     74.67% |          23     15.33%     90.00% |          15     10.00%    100.00%
+system.ruby.L1Cache_Controller.I_L.Load::total          150                      
+system.ruby.L1Cache_Controller.I_L.Store |           8     10.96%     10.96% |           9     12.33%     23.29% |           4      5.48%     28.77% |          11     15.07%     43.84% |           9     12.33%     56.16% |          11     15.07%     71.23% |           8     10.96%     82.19% |          13     17.81%    100.00%
+system.ruby.L1Cache_Controller.I_L.Store::total           73                      
+system.ruby.L1Cache_Controller.I_L.L1_Replacement |          86      6.80%      6.80% |         120      9.49%     16.30% |         129     10.21%     26.50% |         242     19.15%     45.65% |         166     13.13%     58.78% |         201     15.90%     74.68% |         183     14.48%     89.16% |         137     10.84%    100.00%
+system.ruby.L1Cache_Controller.I_L.L1_Replacement::total         1264                      
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens |          18     20.93%     20.93% |          19     22.09%     43.02% |          12     13.95%     56.98% |          12     13.95%     70.93% |          10     11.63%     82.56% |           5      5.81%     88.37% |           8      9.30%     97.67% |           2      2.33%    100.00%
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total           86                      
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX |          61     12.90%     12.90% |          57     12.05%     24.95% |          63     13.32%     38.27% |          60     12.68%     50.95% |          58     12.26%     63.21% |          58     12.26%     75.48% |          60     12.68%     88.16% |          56     11.84%    100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total          473                      
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS |         105     11.74%     11.74% |         117     13.09%     24.83% |         119     13.31%     38.14% |         115     12.86%     51.01% |         103     11.52%     62.53% |         115     12.86%     75.39% |         108     12.08%     87.47% |         112     12.53%    100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total          894                      
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX |       11816     12.43%     12.43% |       11806     12.42%     24.85% |       11913     12.53%     37.39% |       11963     12.59%     49.97% |       11904     12.52%     62.50% |       11820     12.44%     74.93% |       11909     12.53%     87.46% |       11915     12.54%    100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total        95046                      
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS |       21311     12.52%     12.52% |       21181     12.44%     24.97% |       21223     12.47%     37.44% |       21295     12.51%     49.95% |       21275     12.50%     62.45% |       21312     12.52%     74.97% |       21292     12.51%     87.48% |       21308     12.52%    100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total       170197                      
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock |          32     12.03%     12.03% |          28     10.53%     22.56% |          38     14.29%     36.84% |          34     12.78%     49.62% |          33     12.41%     62.03% |          36     13.53%     75.56% |          35     13.16%     88.72% |          30     11.28%    100.00%
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total          266                      
+system.ruby.L1Cache_Controller.S_L.L1_Replacement |          49     12.89%     12.89% |          40     10.53%     23.42% |          38     10.00%     33.42% |          25      6.58%     40.00% |          47     12.37%     52.37% |           7      1.84%     54.21% |          60     15.79%     70.00% |         114     30.00%    100.00%
+system.ruby.L1Cache_Controller.S_L.L1_Replacement::total          380                      
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      7.69%      7.69% |           3     23.08%     30.77% |           1      7.69%     38.46% |           2     15.38%     53.85% |           3     23.08%     76.92% |           3     23.08%    100.00%
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total           13                      
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock |          28     14.29%     14.29% |          25     12.76%     27.04% |          25     12.76%     39.80% |          31     15.82%     55.61% |          20     10.20%     65.82% |          18      9.18%     75.00% |          21     10.71%     85.71% |          28     14.29%    100.00%
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total          196                      
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement |         100      8.63%      8.63% |         166     14.32%     22.95% |          84      7.25%     30.20% |          99      8.54%     38.74% |         192     16.57%     55.31% |         157     13.55%     68.85% |         183     15.79%     84.64% |         178     15.36%    100.00%
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total         1159                      
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           1     25.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total            4                      
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     42.86%     42.86% |           1     14.29%     57.14% |           0      0.00%     57.14% |           3     42.86%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total            7                      
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS |           0      0.00%      0.00% |           1      4.76%      4.76% |           0      0.00%      4.76% |           1      4.76%      9.52% |           6     28.57%     38.10% |           2      9.52%     47.62% |           7     33.33%     80.95% |           4     19.05%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total           21                      
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock |          28     11.62%     11.62% |          32     13.28%     24.90% |          21      8.71%     33.61% |          29     12.03%     45.64% |          35     14.52%     60.17% |          24      9.96%     70.12% |          32     13.28%     83.40% |          40     16.60%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total          241                      
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout |          16      3.53%      3.53% |          99     21.85%     25.39% |          40      8.83%     34.22% |          55     12.14%     46.36% |          54     11.92%     58.28% |          15      3.31%     61.59% |          83     18.32%     79.91% |          91     20.09%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total          453                      
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement |         250     10.84%     10.84% |         201      8.71%     19.55% |         329     14.26%     33.81% |         264     11.44%     45.25% |         307     13.31%     58.56% |         417     18.08%     76.64% |         199      8.63%     85.26% |         340     14.74%    100.00%
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total         2307                      
+system.ruby.L1Cache_Controller.IS_L.Data_Shared |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Data_Shared::total            3                      
+system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total            3                      
+system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total            2                      
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX |           0      0.00%      0.00% |           2     10.53%     10.53% |           2     10.53%     21.05% |           2     10.53%     31.58% |           2     10.53%     42.11% |           4     21.05%     63.16% |           2     10.53%     73.68% |           5     26.32%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total           19                      
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      7.14%      7.14% |           7     16.67%     23.81% |           7     16.67%     40.48% |          10     23.81%     64.29% |           5     11.90%     76.19% |          10     23.81%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total           42                      
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock |          52     12.71%     12.71% |          42     10.27%     22.98% |          48     11.74%     34.72% |          47     11.49%     46.21% |          49     11.98%     58.19% |          64     15.65%     73.84% |          54     13.20%     87.04% |          53     12.96%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total          409                      
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout |          49      6.98%      6.98% |          87     12.39%     19.37% |          48      6.84%     26.21% |          45      6.41%     32.62% |          38      5.41%     38.03% |         135     19.23%     57.26% |         128     18.23%     75.50% |         172     24.50%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total          702                      
+system.ruby.L2Cache_Controller.L1_GETS         402424      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS_Last_Token           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         224067      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_INV             651      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement       603716      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Shared_Data          977      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens       624428      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Owned          419      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX        13627      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS        24405      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock        37727      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       401143      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       223340      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_INV          458      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data          915      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens       602465      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Owned          344      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock        32152      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L1_GETX           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L1_INV             1      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L2_Replacement         5743      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens          453      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_Owned            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETX           12      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETS           17      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement          857      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Shared_Data            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_All_Tokens           57      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Owned            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Persistent_GETS            3      0.00%      0.00%
 system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L1_GETS           20      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement          895      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L1_GETS           24      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L1_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L2_Replacement          866      0.00%      0.00%
 system.ruby.L2Cache_Controller.O.Writeback_Shared_Data            3      0.00%      0.00%
 system.ruby.L2Cache_Controller.O.Writeback_All_Tokens          613      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETS           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS         1170      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX          655      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement       588544      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETX         2903      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETS         5169      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETS           73      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETX           33      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_INV          188      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L2_Replacement          800      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data           62      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens        24964      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Owned           75      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX        12653      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS        23355      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock         7296      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.L2_Replacement            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.Writeback_Shared_Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETX            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETS           18      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS         1151      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX          659      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement       595469      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETX         2203      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETS         4098      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETS           62      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETX           41      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_INV          191      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L2_Replacement          781      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data           55      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens        20840      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_Owned           69      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX        11409      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS        20269      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock         5552      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_L.L1_INV            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock           23      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index f78dc39b7..299a78275 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.004710                       # Number of seconds simulated
-sim_ticks                                     4710288                       # Number of ticks simulated
-final_tick                                    4710288                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.004733                       # Number of seconds simulated
+sim_ticks                                     4733400                       # Number of ticks simulated
+final_tick                                    4733400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  49486                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 481348                       # Number of bytes of host memory used
-host_seconds                                    95.18                       # Real time elapsed on the host
+host_tick_rate                                  45459                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 533892                       # Number of bytes of host memory used
+host_seconds                                   104.13                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     38770176                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           38770176                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14150080                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total        14150080                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       605784                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              605784                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       221095                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             221095                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   8230956578                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            8230956578                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   3004079581                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           3004079581                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0  11235036159                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total          11235036159                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      605795                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     221095                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    605795                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   221095                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               37774848                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                  995776                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                13961856                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                38770880                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys             14150080                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                  15559                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                  2886                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39017600                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           39017600                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0     14216768                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total        14216768                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       609650                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              609650                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       222137                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             222137                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   8243038830                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            8243038830                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   3003500232                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           3003500232                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0  11246539063                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total          11246539063                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      609676                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     222137                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    609676                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   222137                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               38007168                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                 1010496                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                14020224                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                39019264                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys             14216768                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                  15789                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                  3025                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             74027                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             73691                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             74048                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             73659                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             73761                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             73677                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             73634                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             73735                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             74231                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             74363                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             73892                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             74507                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             74187                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             73965                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             74227                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             74490                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::10                0                       # Per bank write bursts
@@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0             27260                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1             27309                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2             27417                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3             27165                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4             27317                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5             27153                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6             27104                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7             27429                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             27470                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1             27400                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2             27273                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3             27416                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4             27333                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5             27456                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6             27361                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7             27357                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
@@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13                0                       # Pe
 system.mem_ctrls.perBankWrBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry                       409                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                       4710276                       # Total gap between requests
+system.mem_ctrls.numWrRetry                       314                       # Number of times write queue was full causing retry
+system.mem_ctrls.totGap                       4733386                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                605795                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                609676                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               221095                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     191                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     460                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                     934                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                    1567                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                    2278                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                    3218                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                    4416                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                    5814                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8                    7450                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9                    9494                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10                  12542                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11                  17459                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12                  24829                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13                  35282                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14                  47987                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15                  59847                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16                  67739                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17                  68317                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18                  61075                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19                  48105                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20                  34077                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21                  22801                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22                  15601                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23                  11679                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24                   9169                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25                   6988                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26                   4984                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27                   3131                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28                   1722                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29                    781                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30                    262                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31                     37                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               222137                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     153                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     427                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                     792                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                    1352                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                    2079                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                    3064                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                    4054                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                    5356                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::8                    6864                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::9                    8709                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::10                  11287                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::11                  15494                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::12                  22545                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::13                  32679                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::14                  46246                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::15                  60217                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::16                  70227                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::17                  72202                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::18                  64822                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::19                  51161                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::20                  35852                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::21                  23634                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::22                  16041                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::23                  11999                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::24                   9304                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::25                   7005                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::26                   4851                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::27                   2978                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::28                   1553                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::29                    670                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::30                    234                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::31                     36                       # What read queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
@@ -137,1366 +137,1371 @@ system.mem_ctrls.wrQLenPdf::17                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::18                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     11                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                      8                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     11                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     20                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     29                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     44                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     68                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     74                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                    134                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    217                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                    283                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                    350                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                    534                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                    693                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                   1556                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                   3238                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                   5631                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                   8129                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                  10368                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                  12019                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                  13539                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                  14215                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                  14950                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48                  15548                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49                  16303                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50                  16948                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51                  16348                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52                  15770                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53                  15893                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54                  16867                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55                  10738                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56                   3547                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57                   1132                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58                    718                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59                    521                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60                    376                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61                    342                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62                    281                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63                    722                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples       217263                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    238.124375                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   188.064482                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   172.867949                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        37866     17.43%     17.43% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        92203     42.44%     59.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383        44887     20.66%     80.53% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511        21105      9.71%     90.24% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639        10935      5.03%     95.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         5805      2.67%     97.95% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         2648      1.22%     99.17% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023         1064      0.49%     99.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151          750      0.35%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total       217263                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples        13625                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      43.319780                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     31.150642                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     26.199447                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7            1380     10.13%     10.13% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15           1829     13.42%     23.55% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23           675      4.95%     28.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31           992      7.28%     35.79% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39          1096      8.04%     43.83% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47          1136      8.34%     52.17% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55          1294      9.50%     61.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63          1412     10.36%     72.03% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71          1517     11.13%     83.16% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79          1303      9.56%     92.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87           700      5.14%     97.86% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95           229      1.68%     99.54% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103           55      0.40%     99.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::104-111            6      0.04%     99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::248-255            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total         13625                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples        13624                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.012405                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.010105                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.322047                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16            13591     99.76%     99.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                6      0.04%     99.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                7      0.05%     99.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                3      0.02%     99.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20                1      0.01%     99.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21                4      0.03%     99.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22                1      0.01%     99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23                3      0.02%     99.94% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24                1      0.01%     99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25                3      0.02%     99.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26                1      0.01%     99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30                2      0.01%     99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32                1      0.01%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total         13624                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                     73947917                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                85162325                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                    2951160                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                       125.29                       # Average queueing delay per DRAM burst
+system.mem_ctrls.wrQLenPdf::21                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     26                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     34                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     36                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     78                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                    108                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                    123                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    228                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                    333                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                    413                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                    587                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                   1402                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                   3145                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                   5659                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                   8204                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                  10599                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::44                  12359                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                  13826                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                  14746                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                  15249                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::48                  15665                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::49                  16347                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::50                  17294                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::51                  16657                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::52                  15930                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::53                  15968                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::54                  16886                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::55                  10292                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::56                   3285                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::57                   1017                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::58                    646                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::59                    453                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::60                    337                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::61                    286                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::62                    263                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::63                    592                       # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples       220003                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    236.476194                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   186.977193                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   171.485363                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        38448     17.48%     17.48% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        94335     42.88%     60.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383        45147     20.52%     80.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511        20844      9.47%     90.35% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639        11176      5.08%     95.43% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         5677      2.58%     98.01% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         2632      1.20%     99.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023         1100      0.50%     99.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151          644      0.29%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total       220003                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples        13685                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      43.395031                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     31.687462                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     25.881507                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-7            1275      9.32%      9.32% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-15           1849     13.51%     22.83% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23           705      5.15%     27.98% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-31          1036      7.57%     35.55% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-39          1094      7.99%     43.54% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-47          1201      8.78%     52.32% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-55          1379     10.08%     62.40% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-63          1411     10.31%     72.71% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-71          1476     10.79%     83.49% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-79          1271      9.29%     92.78% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87           698      5.10%     97.88% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-95           219      1.60%     99.48% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::96-103           51      0.37%     99.85% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::104-111           18      0.13%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-119            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total         13685                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples        13685                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.007746                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.006574                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.222457                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16            13658     99.80%     99.80% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                7      0.05%     99.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                5      0.04%     99.89% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                5      0.04%     99.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20                1      0.01%     99.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21                1      0.01%     99.94% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22                3      0.02%     99.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23                1      0.01%     99.97% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24                1      0.01%     99.98% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26                2      0.01%     99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28                1      0.01%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total         13685                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                     74960248                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                86243626                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                    2969310                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                       126.22                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                  144.29                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      8019.65                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      2964.12                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   8231.11                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   3004.08                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                  145.22                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      8029.57                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      2961.98                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   8243.39                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   3003.50                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        85.81                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    62.65                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   23.16                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                      19.64                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      50.37                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   379240                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  211876                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 64.25                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                97.10                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                          5.70                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    73.12                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy               1639862280                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                911034600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy              7354464000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy             2258160768                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy            307170240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy           3205313604                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             10145400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy            15686150892                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           3335.321599                       # Core power per rank (mW)
+system.mem_ctrls.busUtil                        85.87                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    62.73                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   23.14                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                      19.75                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      50.40                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   379960                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  212957                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 63.98                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                97.19                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                          5.69                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    72.93                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy               1660614480                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                922563600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy              7399816320                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy             2267792640                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy            308695920                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy           3221230284                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             10195800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy            15790909044                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower           3341.005647                       # Core power per rank (mW)
 system.mem_ctrls_0.memoryStateTime::IDLE           11                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF        157040                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF        157820                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT       4546003                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT       4568577                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy            307170240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            101631456                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy           2732643600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy             3141445296                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.967675                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE      4545964                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF        157040                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy            308695920                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy            102136248                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy           2746215600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy             3157047768                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            667.967693                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE      4568542                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF        157820                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           98805                       # number of read accesses completed
-system.cpu0.num_writes                          55123                       # number of write accesses completed
-system.cpu1.num_reads                           98745                       # number of read accesses completed
-system.cpu1.num_writes                          55054                       # number of write accesses completed
-system.cpu2.num_reads                           99065                       # number of read accesses completed
-system.cpu2.num_writes                          56148                       # number of write accesses completed
-system.cpu3.num_reads                           99193                       # number of read accesses completed
-system.cpu3.num_writes                          54886                       # number of write accesses completed
-system.cpu4.num_reads                           98751                       # number of read accesses completed
-system.cpu4.num_writes                          55749                       # number of write accesses completed
-system.cpu5.num_reads                           98704                       # number of read accesses completed
-system.cpu5.num_writes                          55417                       # number of write accesses completed
-system.cpu6.num_reads                           99258                       # number of read accesses completed
-system.cpu6.num_writes                          55160                       # number of write accesses completed
-system.cpu7.num_reads                          100000                       # number of read accesses completed
-system.cpu7.num_writes                          55957                       # number of write accesses completed
+system.cpu0.num_reads                           99240                       # number of read accesses completed
+system.cpu0.num_writes                          55703                       # number of write accesses completed
+system.cpu1.num_reads                           99630                       # number of read accesses completed
+system.cpu1.num_writes                          55894                       # number of write accesses completed
+system.cpu2.num_reads                          100000                       # number of read accesses completed
+system.cpu2.num_writes                          55558                       # number of write accesses completed
+system.cpu3.num_reads                           99663                       # number of read accesses completed
+system.cpu3.num_writes                          55627                       # number of write accesses completed
+system.cpu4.num_reads                           99301                       # number of read accesses completed
+system.cpu4.num_writes                          55122                       # number of write accesses completed
+system.cpu5.num_reads                           99744                       # number of read accesses completed
+system.cpu5.num_writes                          55403                       # number of write accesses completed
+system.cpu6.num_reads                           99405                       # number of read accesses completed
+system.cpu6.num_writes                          55787                       # number of write accesses completed
+system.cpu7.num_reads                           99787                       # number of read accesses completed
+system.cpu7.num_writes                          56016                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       626839                      
-system.ruby.outstanding_req_hist::mean      15.998453                      
-system.ruby.outstanding_req_hist::gmean     15.997188                      
-system.ruby.outstanding_req_hist::stdev      0.125853                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          26      0.00%      0.02% |      626709     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        626839                      
+system.ruby.outstanding_req_hist::samples       630953                      
+system.ruby.outstanding_req_hist::mean      15.998455                      
+system.ruby.outstanding_req_hist::gmean     15.997199                      
+system.ruby.outstanding_req_hist::stdev      0.125474                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          31      0.00%      0.02% |      630818     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        630953                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples              626711                      
-system.ruby.latency_hist::mean             961.893678                      
-system.ruby.latency_hist::gmean            687.559253                      
-system.ruby.latency_hist::stdev            669.975884                      
-system.ruby.latency_hist                 |      233282     37.22%     37.22% |      116315     18.56%     55.78% |      118100     18.84%     74.63% |      122318     19.52%     94.14% |       34176      5.45%     99.60% |        2441      0.39%     99.99% |          77      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                626711                      
+system.ruby.latency_hist::samples              630825                      
+system.ruby.latency_hist::mean             960.308815                      
+system.ruby.latency_hist::gmean            687.329820                      
+system.ruby.latency_hist::stdev            668.477616                      
+system.ruby.latency_hist                 |      236510     37.49%     37.49% |      115846     18.36%     55.86% |      117532     18.63%     74.49% |      125080     19.83%     94.32% |       33628      5.33%     99.65% |        2176      0.34%     99.99% |          53      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                630825                      
 system.ruby.hit_latency_hist::bucket_size          256                      
 system.ruby.hit_latency_hist::max_bucket         2559                      
-system.ruby.hit_latency_hist::samples             687                      
-system.ruby.hit_latency_hist::mean          97.013100                      
-system.ruby.hit_latency_hist::gmean         31.183687                      
-system.ruby.hit_latency_hist::stdev        145.506218                      
-system.ruby.hit_latency_hist             |         624     90.83%     90.83% |          49      7.13%     97.96% |          10      1.46%     99.42% |           1      0.15%     99.56% |           2      0.29%     99.85% |           0      0.00%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               687                      
+system.ruby.hit_latency_hist::samples             703                      
+system.ruby.hit_latency_hist::mean         107.428165                      
+system.ruby.hit_latency_hist::gmean         37.578183                      
+system.ruby.hit_latency_hist::stdev        143.869758                      
+system.ruby.hit_latency_hist             |         636     90.47%     90.47% |          48      6.83%     97.30% |          15      2.13%     99.43% |           2      0.28%     99.72% |           0      0.00%     99.72% |           2      0.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               703                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples         626024                      
-system.ruby.miss_latency_hist::mean        962.842800                      
-system.ruby.miss_latency_hist::gmean       689.897168                      
-system.ruby.miss_latency_hist::stdev       669.712845                      
-system.ruby.miss_latency_hist            |      232609     37.16%     37.16% |      116304     18.58%     55.73% |      118098     18.86%     74.60% |      122317     19.54%     94.14% |       34176      5.46%     99.60% |        2441      0.39%     99.99% |          77      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           626024                      
-system.ruby.L1Cache.incomplete_times             1059                      
-system.ruby.Directory.incomplete_times         174559                      
+system.ruby.miss_latency_hist::samples         630122                      
+system.ruby.miss_latency_hist::mean        961.260337                      
+system.ruby.miss_latency_hist::gmean       689.562128                      
+system.ruby.miss_latency_hist::stdev       668.225537                      
+system.ruby.miss_latency_hist            |      235826     37.43%     37.43% |      115829     18.38%     55.81% |      117530     18.65%     74.46% |      125080     19.85%     94.31% |       33628      5.34%     99.65% |        2176      0.35%     99.99% |          53      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           630122                      
+system.ruby.L1Cache.incomplete_times             1012                      
+system.ruby.Directory.incomplete_times         171726                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           16                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        78341                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78357                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78655                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78671                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           72                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses        78269                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses        78341                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           26                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        78152                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78178                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           56                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses        78599                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses        78655                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits           28                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        78868                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78896                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L2cache.demand_hits           62                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L2cache.demand_misses        78090                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L2cache.demand_accesses        78152                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        78522                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78543                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L2cache.demand_misses        78806                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L2cache.demand_accesses        78868                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits           19                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        78934                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78953                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L2cache.demand_hits           57                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L2cache.demand_misses        78465                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L2cache.demand_accesses        78522                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits           14                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        77966                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        77980                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L2cache.demand_hits           67                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L2cache.demand_misses        78867                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L2cache.demand_accesses        78934                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_hits           18                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        78870                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78888                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L2cache.demand_hits           73                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L2cache.demand_misses        77893                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L2cache.demand_accesses        77966                       # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Dcache.demand_hits           17                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        78468                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78485                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L2cache.demand_hits           74                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L2cache.demand_misses        78796                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L2cache.demand_accesses        78870                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Dcache.demand_hits           15                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        79005                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        79020                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
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 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl4.L2cache.demand_hits           61                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L2cache.demand_misses        78407                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L2cache.demand_accesses        78468                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           25                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        78409                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78434                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L2cache.demand_hits           67                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L2cache.demand_misses        78938                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L2cache.demand_accesses        79005                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits           20                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78750                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78770                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L2cache.demand_hits           64                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L2cache.demand_misses        78345                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L2cache.demand_accesses        78409                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           20                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        78115                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78135                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L2cache.demand_misses        78686                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L2cache.demand_accesses        78750                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits           12                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78669                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78681                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L2cache.demand_hits           78                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L2cache.demand_misses        78037                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L2cache.demand_accesses        78115                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           15                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        78607                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78622                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L2cache.demand_hits           84                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L2cache.demand_misses        78585                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L2cache.demand_accesses        78669                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           17                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        78957                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78974                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L2cache.demand_hits           66                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L2cache.demand_misses        78541                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L2cache.demand_accesses        78607                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L2cache.demand_hits           84                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L2cache.demand_misses        78873                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L2cache.demand_accesses        78957                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized    15.720849                      
-system.ruby.network.routers0.msg_count.Request_Control::2        78269                      
-system.ruby.network.routers0.msg_count.Request_Control::3          139                      
-system.ruby.network.routers0.msg_count.Response_Data::4        80871                      
-system.ruby.network.routers0.msg_count.Response_Control::4      1088778                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5        27580                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2        73745                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3        73741                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5        45977                      
-system.ruby.network.routers0.msg_count.Broadcast_Control::3       546833                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5        78448                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       626152                      
-system.ruby.network.routers0.msg_bytes.Request_Control::3         1112                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4      5822712                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4      8710224                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5      1985760                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2       589960                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3       589928                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5       367816                      
-system.ruby.network.routers0.msg_bytes.Broadcast_Control::3      4374664                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5       627584                      
-system.ruby.network.routers1.percent_links_utilized    15.700680                      
-system.ruby.network.routers1.msg_count.Request_Control::2        78090                      
-system.ruby.network.routers1.msg_count.Request_Control::3          131                      
-system.ruby.network.routers1.msg_count.Response_Data::4        80580                      
-system.ruby.network.routers1.msg_count.Response_Control::4      1088026                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5        27553                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2        73740                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3        73737                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5        45984                      
-system.ruby.network.routers1.msg_count.Broadcast_Control::3       546998                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5        78286                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       624720                      
-system.ruby.network.routers1.msg_bytes.Request_Control::3         1048                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4      5801760                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4      8704208                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5      1983816                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2       589920                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3       589896                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5       367872                      
-system.ruby.network.routers1.msg_bytes.Broadcast_Control::3      4375984                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5       626288                      
-system.ruby.network.routers2.percent_links_utilized    15.754615                      
-system.ruby.network.routers2.msg_count.Request_Control::2        78465                      
-system.ruby.network.routers2.msg_count.Request_Control::3          122                      
-system.ruby.network.routers2.msg_count.Response_Data::4        80996                      
-system.ruby.network.routers2.msg_count.Response_Control::4      1090199                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5        27924                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2        74047                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3        74045                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5        45930                      
-system.ruby.network.routers2.msg_count.Broadcast_Control::3       546610                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5        78653                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2       627720                      
-system.ruby.network.routers2.msg_bytes.Request_Control::3          976                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4      5831712                      
-system.ruby.network.routers2.msg_bytes.Response_Control::4      8721592                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5      2010528                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2       592376                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3       592360                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5       367440                      
-system.ruby.network.routers2.msg_bytes.Broadcast_Control::3      4372880                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5       629224                      
-system.ruby.network.routers3.percent_links_utilized    15.668559                      
-system.ruby.network.routers3.msg_count.Request_Control::2        77893                      
-system.ruby.network.routers3.msg_count.Request_Control::3          152                      
-system.ruby.network.routers3.msg_count.Response_Data::4        80452                      
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-system.ruby.network.routers3.msg_count.Writeback_Data::5        27209                      
-system.ruby.network.routers3.msg_count.Writeback_Control::2        73510                      
-system.ruby.network.routers3.msg_count.Writeback_Control::3        73508                      
-system.ruby.network.routers3.msg_count.Writeback_Control::5        46106                      
-system.ruby.network.routers3.msg_count.Broadcast_Control::3       547207                      
-system.ruby.network.routers3.msg_count.Unblock_Control::5        78083                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2       623144                      
-system.ruby.network.routers3.msg_bytes.Request_Control::3         1216                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4      5792544                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4      8693832                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::5      1959048                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::2       588080                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3       588064                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::5       368848                      
-system.ruby.network.routers3.msg_bytes.Broadcast_Control::3      4377656                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::5       624664                      
-system.ruby.network.routers4.percent_links_utilized    15.743220                      
-system.ruby.network.routers4.msg_count.Request_Control::2        78407                      
-system.ruby.network.routers4.msg_count.Request_Control::3          142                      
-system.ruby.network.routers4.msg_count.Response_Data::4        80934                      
-system.ruby.network.routers4.msg_count.Response_Control::4      1089785                      
-system.ruby.network.routers4.msg_count.Writeback_Data::5        27788                      
-system.ruby.network.routers4.msg_count.Writeback_Control::2        74021                      
-system.ruby.network.routers4.msg_count.Writeback_Control::3        74018                      
-system.ruby.network.routers4.msg_count.Writeback_Control::5        46049                      
-system.ruby.network.routers4.msg_count.Broadcast_Control::3       546700                      
-system.ruby.network.routers4.msg_count.Unblock_Control::5        78584                      
-system.ruby.network.routers4.msg_bytes.Request_Control::2       627256                      
-system.ruby.network.routers4.msg_bytes.Request_Control::3         1136                      
-system.ruby.network.routers4.msg_bytes.Response_Data::4      5827248                      
-system.ruby.network.routers4.msg_bytes.Response_Control::4      8718280                      
-system.ruby.network.routers4.msg_bytes.Writeback_Data::5      2000736                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::2       592168                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3       592144                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::5       368392                      
-system.ruby.network.routers4.msg_bytes.Broadcast_Control::3      4373600                      
-system.ruby.network.routers4.msg_bytes.Unblock_Control::5       628672                      
-system.ruby.network.routers5.percent_links_utilized    15.734245                      
-system.ruby.network.routers5.msg_count.Request_Control::2        78345                      
-system.ruby.network.routers5.msg_count.Request_Control::3          100                      
-system.ruby.network.routers5.msg_count.Response_Data::4        80818                      
-system.ruby.network.routers5.msg_count.Response_Control::4      1089383                      
-system.ruby.network.routers5.msg_count.Writeback_Data::5        27834                      
-system.ruby.network.routers5.msg_count.Writeback_Control::2        73849                      
-system.ruby.network.routers5.msg_count.Writeback_Control::3        73844                      
-system.ruby.network.routers5.msg_count.Writeback_Control::5        45837                      
-system.ruby.network.routers5.msg_count.Broadcast_Control::3       546773                      
-system.ruby.network.routers5.msg_count.Unblock_Control::5        78514                      
-system.ruby.network.routers5.msg_bytes.Request_Control::2       626760                      
-system.ruby.network.routers5.msg_bytes.Request_Control::3          800                      
-system.ruby.network.routers5.msg_bytes.Response_Data::4      5818896                      
-system.ruby.network.routers5.msg_bytes.Response_Control::4      8715064                      
-system.ruby.network.routers5.msg_bytes.Writeback_Data::5      2004048                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::2       590792                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3       590752                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::5       366696                      
-system.ruby.network.routers5.msg_bytes.Broadcast_Control::3      4374184                      
-system.ruby.network.routers5.msg_bytes.Unblock_Control::5       628112                      
-system.ruby.network.routers6.percent_links_utilized    15.693334                      
-system.ruby.network.routers6.msg_count.Request_Control::2        78037                      
-system.ruby.network.routers6.msg_count.Request_Control::3          131                      
-system.ruby.network.routers6.msg_count.Response_Data::4        80574                      
-system.ruby.network.routers6.msg_count.Response_Control::4      1087587                      
-system.ruby.network.routers6.msg_count.Writeback_Data::5        27513                      
-system.ruby.network.routers6.msg_count.Writeback_Control::2        73565                      
-system.ruby.network.routers6.msg_count.Writeback_Control::3        73562                      
-system.ruby.network.routers6.msg_count.Writeback_Control::5        45870                      
-system.ruby.network.routers6.msg_count.Broadcast_Control::3       547058                      
-system.ruby.network.routers6.msg_count.Unblock_Control::5        78212                      
-system.ruby.network.routers6.msg_bytes.Request_Control::2       624296                      
-system.ruby.network.routers6.msg_bytes.Request_Control::3         1048                      
-system.ruby.network.routers6.msg_bytes.Response_Data::4      5801328                      
-system.ruby.network.routers6.msg_bytes.Response_Control::4      8700696                      
-system.ruby.network.routers6.msg_bytes.Writeback_Data::5      1980936                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::2       588520                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3       588496                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::5       366960                      
-system.ruby.network.routers6.msg_bytes.Broadcast_Control::3      4376464                      
-system.ruby.network.routers6.msg_bytes.Unblock_Control::5       625696                      
-system.ruby.network.routers7.percent_links_utilized    15.751256                      
-system.ruby.network.routers7.msg_count.Request_Control::2        78539                      
-system.ruby.network.routers7.msg_count.Request_Control::3          141                      
-system.ruby.network.routers7.msg_count.Response_Data::4        81044                      
-system.ruby.network.routers7.msg_count.Response_Control::4      1090607                      
-system.ruby.network.routers7.msg_count.Writeback_Data::5        27694                      
-system.ruby.network.routers7.msg_count.Writeback_Control::2        74130                      
-system.ruby.network.routers7.msg_count.Writeback_Control::3        74128                      
-system.ruby.network.routers7.msg_count.Writeback_Control::5        46215                      
-system.ruby.network.routers7.msg_count.Broadcast_Control::3       546562                      
-system.ruby.network.routers7.msg_count.Unblock_Control::5        78755                      
-system.ruby.network.routers7.msg_bytes.Request_Control::2       628312                      
-system.ruby.network.routers7.msg_bytes.Request_Control::3         1128                      
-system.ruby.network.routers7.msg_bytes.Response_Data::4      5835168                      
-system.ruby.network.routers7.msg_bytes.Response_Control::4      8724856                      
-system.ruby.network.routers7.msg_bytes.Writeback_Data::5      1993968                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::2       593040                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3       593024                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::5       369720                      
-system.ruby.network.routers7.msg_bytes.Broadcast_Control::3      4372496                      
-system.ruby.network.routers7.msg_bytes.Unblock_Control::5       630040                      
-system.ruby.network.routers8.percent_links_utilized    57.696143                      
-system.ruby.network.routers8.msg_count.Request_Control::2       626043                      
-system.ruby.network.routers8.msg_count.Request_Control::3         1058                      
-system.ruby.network.routers8.msg_count.Response_Data::4       605779                      
-system.ruby.network.routers8.msg_count.Writeback_Data::5       221095                      
-system.ruby.network.routers8.msg_count.Writeback_Control::2       590607                      
-system.ruby.network.routers8.msg_count.Writeback_Control::3       590583                      
-system.ruby.network.routers8.msg_count.Writeback_Control::5       367967                      
-system.ruby.network.routers8.msg_count.Broadcast_Control::3       624964                      
-system.ruby.network.routers8.msg_count.Unblock_Control::5       627535                      
-system.ruby.network.routers8.msg_bytes.Request_Control::2      5008344                      
-system.ruby.network.routers8.msg_bytes.Request_Control::3         8464                      
-system.ruby.network.routers8.msg_bytes.Response_Data::4     43616088                      
-system.ruby.network.routers8.msg_bytes.Writeback_Data::5     15918840                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::2      4724856                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3      4724664                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::5      2943736                      
-system.ruby.network.routers8.msg_bytes.Broadcast_Control::3      4999712                      
-system.ruby.network.routers8.msg_bytes.Unblock_Control::5      5020280                      
-system.ruby.network.routers9.percent_links_utilized    22.596120                      
-system.ruby.network.routers9.msg_count.Request_Control::2       626043                      
-system.ruby.network.routers9.msg_count.Request_Control::3         1058                      
-system.ruby.network.routers9.msg_count.Response_Data::4       626025                      
-system.ruby.network.routers9.msg_count.Response_Control::4      4355547                      
-system.ruby.network.routers9.msg_count.Writeback_Data::5       221095                      
-system.ruby.network.routers9.msg_count.Writeback_Control::2       590607                      
-system.ruby.network.routers9.msg_count.Writeback_Control::3       590583                      
-system.ruby.network.routers9.msg_count.Writeback_Control::5       367968                      
-system.ruby.network.routers9.msg_count.Broadcast_Control::3      4374748                      
-system.ruby.network.routers9.msg_count.Unblock_Control::5       627535                      
-system.ruby.network.routers9.msg_bytes.Request_Control::2      5008344                      
-system.ruby.network.routers9.msg_bytes.Request_Control::3         8464                      
-system.ruby.network.routers9.msg_bytes.Response_Data::4     45073800                      
-system.ruby.network.routers9.msg_bytes.Response_Control::4     34844376                      
-system.ruby.network.routers9.msg_bytes.Writeback_Data::5     15918840                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::2      4724856                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4724664                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::5      2943744                      
-system.ruby.network.routers9.msg_bytes.Broadcast_Control::3     34997984                      
-system.ruby.network.routers9.msg_bytes.Unblock_Control::5      5020280                      
-system.ruby.network.msg_count.Request_Control      1881305                      
-system.ruby.network.msg_count.Response_Data      1878073                      
-system.ruby.network.msg_count.Response_Control     13066641                      
-system.ruby.network.msg_count.Writeback_Data       663285                      
-system.ruby.network.msg_count.Writeback_Control      4647473                      
-system.ruby.network.msg_count.Broadcast_Control      9374453                      
-system.ruby.network.msg_count.Unblock_Control      1882605                      
-system.ruby.network.msg_byte.Request_Control     15050440                      
-system.ruby.network.msg_byte.Response_Data    135221256                      
-system.ruby.network.msg_byte.Response_Control    104533128                      
-system.ruby.network.msg_byte.Writeback_Data     47756520                      
-system.ruby.network.msg_byte.Writeback_Control     37179784                      
-system.ruby.network.msg_byte.Broadcast_Control     74995624                      
-system.ruby.network.msg_byte.Unblock_Control     15060840                      
-system.ruby.network.routers0.throttle0.link_utilization    19.845060                      
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::3          139                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4        78266                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::4       544412                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        73741                      
-system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3       546833                      
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3         1112                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5635152                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4      4355296                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       589928                      
-system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3      4374664                      
-system.ruby.network.routers0.throttle1.link_utilization    11.596637                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2        78269                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4         2605                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::4       544366                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5        27580                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2        73745                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5        45977                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5        78448                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2       626152                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4       187560                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4      4354928                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5      1985760                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2       589960                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5       367816                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5       627584                      
-system.ruby.network.routers1.throttle0.link_utilization    19.818746                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::3          131                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4        78087                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::4       543391                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3        73737                      
-system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3       546998                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3         1048                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4      5622264                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4      4347128                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3       589896                      
-system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3      4375984                      
-system.ruby.network.routers1.throttle1.link_utilization    11.582614                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2        78090                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         2493                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::4       544635                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5        27553                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2        73740                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5        45984                      
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5        78286                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2       624720                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       179496                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4      4357080                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5      1983816                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2       589920                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5       367872                      
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5       626288                      
-system.ruby.network.routers2.throttle0.link_utilization    19.881343                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::3          122                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4        78462                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::4       546002                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3        74045                      
-system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3       546610                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3          976                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4      5649264                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4      4368016                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3       592360                      
-system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3      4372880                      
-system.ruby.network.routers2.throttle1.link_utilization    11.627888                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2        78465                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         2534                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::4       544197                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5        27924                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2        74047                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5        45930                      
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5        78653                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       627720                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4       182448                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4      4353576                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5      2010528                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2       592376                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5       367440                      
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5       629224                      
-system.ruby.network.routers3.throttle0.link_utilization    19.784459                      
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::3          152                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4        77890                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::4       541933                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3        73508                      
-system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3       547207                      
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3         1216                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4      5608080                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4      4335464                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3       588064                      
-system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3      4377656                      
-system.ruby.network.routers3.throttle1.link_utilization    11.552659                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::2        77893                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::4         2562                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::4       544796                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5        27209                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2        73510                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5        46106                      
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5        78083                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2       623144                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4       184464                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4      4358368                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5      1959048                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2       588080                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5       368848                      
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5       624664                      
-system.ruby.network.routers4.throttle0.link_utilization    19.871067                      
-system.ruby.network.routers4.throttle0.msg_count.Request_Control::3          142                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::4        78404                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Control::4       545473                      
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3        74018                      
-system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3       546700                      
-system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3         1136                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4      5645088                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4      4363784                      
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3       592144                      
-system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3      4373600                      
-system.ruby.network.routers4.throttle1.link_utilization    11.615373                      
-system.ruby.network.routers4.throttle1.msg_count.Request_Control::2        78407                      
-system.ruby.network.routers4.throttle1.msg_count.Response_Data::4         2530                      
-system.ruby.network.routers4.throttle1.msg_count.Response_Control::4       544312                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5        27788                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2        74021                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5        46049                      
-system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5        78584                      
-system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2       627256                      
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4       182160                      
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4      4354496                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5      2000736                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2       592168                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5       368392                      
-system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5       628672                      
-system.ruby.network.routers5.throttle0.link_utilization    19.858552                      
-system.ruby.network.routers5.throttle0.msg_count.Request_Control::3          100                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::4        78343                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Control::4       544986                      
-system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3        73844                      
-system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3       546773                      
-system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3          800                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4      5640696                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4      4359888                      
-system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3       590752                      
-system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3      4374184                      
-system.ruby.network.routers5.throttle1.link_utilization    11.609938                      
-system.ruby.network.routers5.throttle1.msg_count.Request_Control::2        78345                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::4         2475                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Control::4       544397                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5        27834                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2        73849                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5        45837                      
-system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5        78514                      
-system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2       626760                      
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-system.ruby.LD.latency_hist              |      150128     37.27%     37.27% |       74474     18.49%     55.76% |       75905     18.84%     74.61% |       78649     19.53%     94.13% |       22036      5.47%     99.60% |        1551      0.39%     99.99% |          46      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             402790                      
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-system.ruby.LD.hit_latency_hist::max_bucket         1279                      
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-system.ruby.LD.hit_latency_hist::gmean      30.555946                      
-system.ruby.LD.hit_latency_hist::stdev     138.573266                      
-system.ruby.LD.hit_latency_hist          |         340     74.07%     74.07% |          75     16.34%     90.41% |          27      5.88%     96.30% |           8      1.74%     98.04% |           4      0.87%     98.91% |           2      0.44%     99.35% |           1      0.22%     99.56% |           0      0.00%     99.56% |           1      0.22%     99.78% |           1      0.22%    100.00%
-system.ruby.LD.hit_latency_hist::total            459                      
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+system.ruby.LD.latency_hist::stdev         668.516283                      
+system.ruby.LD.latency_hist              |      152104     37.48%     37.48% |       74658     18.40%     55.87% |       75456     18.59%     74.46% |       80607     19.86%     94.33% |       21579      5.32%     99.64% |        1421      0.35%     99.99% |          32      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total             405857                      
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+system.ruby.LD.hit_latency_hist          |         403     89.96%     89.96% |          31      6.92%     96.88% |          11      2.46%     99.33% |           2      0.45%     99.78% |           0      0.00%     99.78% |           1      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.LD.miss_latency_hist::bucket_size          512                      
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-system.ruby.LD.miss_latency_hist::gmean    689.397106                      
-system.ruby.LD.miss_latency_hist::stdev    669.896353                      
-system.ruby.LD.miss_latency_hist         |      149678     37.20%     37.20% |       74467     18.51%     55.71% |       75903     18.87%     74.58% |       78649     19.55%     94.13% |       22036      5.48%     99.60% |        1551      0.39%     99.99% |          46      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        402331                      
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+system.ruby.LD.miss_latency_hist         |      151670     37.41%     37.41% |       74645     18.41%     55.82% |       75455     18.61%     74.44% |       80607     19.88%     94.32% |       21579      5.32%     99.64% |        1421      0.35%     99.99% |          32      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        405409                      
 system.ruby.ST.latency_hist::bucket_size          512                      
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-system.ruby.ST.latency_hist::gmean         688.650583                      
-system.ruby.ST.latency_hist::stdev         669.628569                      
-system.ruby.ST.latency_hist              |       83154     37.14%     37.14% |       41841     18.69%     55.82% |       42195     18.84%     74.66% |       43669     19.50%     94.17% |       12140      5.42%     99.59% |         890      0.40%     99.99% |          31      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             223921                      
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+system.ruby.ST.latency_hist              |       84406     37.52%     37.52% |       41188     18.31%     55.83% |       42076     18.70%     74.53% |       44473     19.77%     94.30% |       12049      5.36%     99.66% |         755      0.34%     99.99% |          21      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.ST.hit_latency_hist::gmean      32.486812                      
-system.ruby.ST.hit_latency_hist::stdev     158.831790                      
-system.ruby.ST.hit_latency_hist          |         209     91.67%     91.67% |          14      6.14%     97.81% |           4      1.75%     99.56% |           0      0.00%     99.56% |           0      0.00%     99.56% |           0      0.00%     99.56% |           1      0.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            228                      
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+system.ruby.ST.hit_latency_hist::gmean      32.839822                      
+system.ruby.ST.hit_latency_hist::stdev     139.085518                      
+system.ruby.ST.hit_latency_hist          |         233     91.37%     91.37% |          17      6.67%     98.04% |           4      1.57%     99.61% |           0      0.00%     99.61% |           0      0.00%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.ST.miss_latency_hist::bucket_size          512                      
 system.ruby.ST.miss_latency_hist::max_bucket         5119                      
-system.ruby.ST.miss_latency_hist::samples       223693                      
-system.ruby.ST.miss_latency_hist::mean     963.014587                      
-system.ruby.ST.miss_latency_hist::gmean    690.797485                      
-system.ruby.ST.miss_latency_hist::stdev    669.384126                      
-system.ruby.ST.miss_latency_hist         |       82931     37.07%     37.07% |       41837     18.70%     55.78% |       42195     18.86%     74.64% |       43668     19.52%     94.16% |       12140      5.43%     99.59% |         890      0.40%     99.99% |          31      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        223693                      
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+system.ruby.ST.miss_latency_hist::gmean    690.038778                      
+system.ruby.ST.miss_latency_hist::stdev    668.139804                      
+system.ruby.ST.miss_latency_hist         |       84156     37.45%     37.45% |       41184     18.33%     55.78% |       42075     18.72%     74.50% |       44473     19.79%     94.29% |       12049      5.36%     99.65% |         755      0.34%     99.99% |          21      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        224713                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
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-system.ruby.L1Cache.hit_mach_latency_hist::samples          154                      
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 system.ruby.L1Cache.hit_mach_latency_hist::mean            2                      
-system.ruby.L1Cache.hit_mach_latency_hist::gmean            2                      
-system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         154    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total          154                      
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+system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         145    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.L1Cache.miss_mach_latency_hist::samples        23051                      
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-system.ruby.L1Cache.miss_mach_latency_hist::stdev   668.277259                      
-system.ruby.L1Cache.miss_mach_latency_hist |        9264     40.19%     40.19% |        4006     17.38%     57.57% |        4352     18.88%     76.45% |        4291     18.62%     95.06% |        1074      4.66%     99.72% |          61      0.26%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total        23051                      
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+system.ruby.L1Cache.miss_mach_latency_hist |        9174     39.65%     39.65% |        4098     17.71%     57.36% |        4329     18.71%     76.07% |        4414     19.08%     95.15% |        1060      4.58%     99.73% |          61      0.26%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples        21992                      
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-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev   664.096141                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request |        9933     45.17%     45.17% |        3702     16.83%     62.00% |        4645     21.12%     83.12% |        3181     14.46%     97.59% |         505      2.30%     99.88% |          25      0.11%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total        21992                      
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+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request |        9921     44.84%     44.84% |        3726     16.84%     61.68% |        4701     21.25%     82.93% |        3270     14.78%     97.71% |         497      2.25%     99.95% |          10      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total        22125                      
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 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket         1279                      
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-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev    75.655363                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward |       19198     87.30%     87.30% |        2163      9.84%     97.13% |         495      2.25%     99.38% |          92      0.42%     99.80% |          38      0.17%     99.97% |           5      0.02%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total        21992                      
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+system.ruby.L1Cache.miss_latency_hist.initial_to_forward |       19195     86.76%     86.76% |        2271     10.26%     97.02% |         528      2.39%     99.41% |          69      0.31%     99.72% |          53      0.24%     99.96% |           9      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size           32                      
 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket          319                      
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-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev    49.391287                      
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response |        3796     17.26%     17.26% |        4651     21.15%     38.41% |        5306     24.13%     62.54% |        3457     15.72%     78.26% |        2571     11.69%     89.95% |        1647      7.49%     97.44% |         520      2.36%     99.80% |          43      0.20%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total        21992                      
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+system.ruby.L1Cache.miss_latency_hist.forward_to_first_response |        3841     17.36%     17.36% |        4772     21.57%     38.93% |        5269     23.81%     62.74% |        3490     15.77%     78.52% |        2590     11.71%     90.22% |        1631      7.37%     97.60% |         486      2.20%     99.79% |          45      0.20%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion |       19838     90.21%     90.21% |         977      4.44%     94.65% |         719      3.27%     97.92% |         362      1.65%     99.56% |          86      0.39%     99.95% |           9      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.L1Cache.miss_latency_hist.first_response_to_completion |       20108     90.88%     90.88% |         907      4.10%     94.98% |         690      3.12%     98.10% |         325      1.47%     99.57% |          83      0.38%     99.95% |          11      0.05%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.L2Cache.hit_mach_latency_hist |         470     88.18%     88.18% |          49      9.19%     97.37% |          10      1.88%     99.25% |           1      0.19%     99.44% |           2      0.38%     99.81% |           0      0.00%     99.81% |           1      0.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total          533                      
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+system.ruby.L2Cache.hit_mach_latency_hist |         491     87.99%     87.99% |          48      8.60%     96.59% |          15      2.69%     99.28% |           2      0.36%     99.64% |           0      0.00%     99.64% |           2      0.36%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.Directory.miss_mach_latency_hist::max_bucket         5119                      
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-system.ruby.Directory.miss_mach_latency_hist::stdev   669.706434                      
-system.ruby.Directory.miss_mach_latency_hist |      223345     37.04%     37.04% |      112298     18.62%     55.66% |      113746     18.86%     74.53% |      118026     19.57%     94.10% |       33102      5.49%     99.59% |        2380      0.39%     99.99% |          74      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       602973                      
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+system.ruby.Directory.miss_mach_latency_hist |      226652     37.34%     37.34% |      111731     18.41%     55.75% |      113201     18.65%     74.40% |      120666     19.88%     94.28% |       32568      5.37%     99.64% |        2115      0.35%     99.99% |          52      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       606985                      
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 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket         5119                      
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-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev   658.219998                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request |      190127     44.38%     44.38% |       73544     17.17%     61.55% |       91535     21.37%     82.91% |       63246     14.76%     97.67% |        9543      2.23%     99.90% |         411      0.10%    100.00% |           8      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total       428414                      
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+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev   657.460406                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request |      194525     44.69%     44.69% |       73174     16.81%     61.50% |       93400     21.46%     82.96% |       64531     14.83%     97.79% |        9251      2.13%     99.91% |         371      0.09%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total       435259                      
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-system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev    21.002732                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward |      397834     92.86%     92.86% |       30211      7.05%     99.91% |         312      0.07%     99.99% |          45      0.01%    100.00% |           9      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.initial_to_forward::total       428414                      
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+system.ruby.Directory.miss_latency_hist.initial_to_forward |      407343     93.59%     93.59% |       27542      6.33%     99.91% |         308      0.07%     99.98% |          47      0.01%    100.00% |          11      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.initial_to_forward::total       435259                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size           32                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket          319                      
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-system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev    33.547976                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response |      108299     25.28%     25.28% |      144980     33.84%     59.12% |      106832     24.94%     84.06% |       47268     11.03%     95.09% |       17336      4.05%     99.14% |        3507      0.82%     99.96% |         190      0.04%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::total       428414                      
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+system.ruby.Directory.miss_latency_hist.forward_to_first_response |      107270     24.65%     24.65% |      146874     33.74%     58.39% |      109544     25.17%     83.56% |       49169     11.30%     94.85% |       18405      4.23%     99.08% |        3851      0.88%     99.97% |         146      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size          128                      
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket         1279                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples       428414                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean   140.948863                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev   103.640016                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion |      228976     53.45%     53.45% |      147468     34.42%     87.87% |       37831      8.83%     96.70% |        9715      2.27%     98.97% |        4262      0.99%     99.96% |         161      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::total       428414                      
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+system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean   140.609226                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev   102.245912                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion |      231026     53.08%     53.08% |      153949     35.37%     88.45% |       36417      8.37%     96.81% |        9414      2.16%     98.98% |        4317      0.99%     99.97% |         136      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::total       435259                      
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 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples          105                      
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 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean            2                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         105    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total          105                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          88    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples        12935                      
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-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   669.891938                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |        5225     40.39%     40.39% |        2209     17.08%     57.47% |        2482     19.19%     76.66% |        2372     18.34%     95.00% |         613      4.74%     99.74% |          33      0.26%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total        12935                      
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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   146.740195                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         235     66.38%     66.38% |          75     21.19%     87.57% |          27      7.63%     95.20% |           8      2.26%     97.46% |           4      1.13%     98.59% |           2      0.56%     99.15% |           1      0.28%     99.44% |           0      0.00%     99.44% |           1      0.28%     99.72% |           1      0.28%    100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total          354                      
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+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   666.420559                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |        5201     39.60%     39.60% |        2327     17.72%     57.32% |        2488     18.94%     76.26% |        2478     18.87%     95.13% |         599      4.56%     99.69% |          40      0.30%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         315     87.50%     87.50% |          31      8.61%     96.11% |          11      3.06%     99.17% |           2      0.56%     99.72% |           0      0.00%     99.72% |           1      0.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
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-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   669.836857                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |      144453     37.10%     37.10% |       72258     18.56%     55.65% |       73421     18.86%     74.51% |       76277     19.59%     94.10% |       21423      5.50%     99.60% |        1518      0.39%     99.99% |          45      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       389396                      
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+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   668.294745                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |      146469     37.34%     37.34% |       72318     18.44%     55.77% |       72967     18.60%     74.37% |       78129     19.92%     94.29% |       20980      5.35%     99.64% |        1381      0.35%     99.99% |          31      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           49                      
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 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean            2                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          49    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           49                      
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 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   666.219932                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |        4039     39.93%     39.93% |        1797     17.76%     57.69% |        1870     18.49%     76.18% |        1919     18.97%     95.15% |         461      4.56%     99.70% |          28      0.28%     99.98% |           2      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total        10116                      
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-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         160     89.39%     89.39% |          14      7.82%     97.21% |           4      2.23%     99.44% |           0      0.00%     99.44% |           0      0.00%     99.44% |           0      0.00%     99.44% |           1      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
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-system.ruby.ST.Directory.miss_type_mach_latency_hist |       78892     36.94%     36.94% |       40040     18.75%     55.69% |       40325     18.88%     74.57% |       41749     19.55%     94.11% |       11679      5.47%     99.58% |         862      0.40%     99.99% |          29      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.Directory_Controller.NO_B_S.PUT           41      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockS           38      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockM          972      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.GETX            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.GETS            3      0.00%      0.00%
 system.ruby.Directory_Controller.NO_B_S_W.PUT          138      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.UnblockS         1059      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks         1058      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.UnblockS         1012      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks         1010      0.00%      0.00%
 system.ruby.Directory_Controller.O_B.GETX            9      0.00%      0.00%
-system.ruby.Directory_Controller.O_B.GETS           25      0.00%      0.00%
-system.ruby.Directory_Controller.O_B.UnblockS        16632      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.GETX         1927      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.GETS         3352      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data       589145      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.GETX           51      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.GETS          103      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.Memory_Data        16634      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETX         1371      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETS         2380      0.00%      0.00%
-system.ruby.Directory_Controller.WB.PUT            65      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Unblock         1518      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Clean         7905      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Dirty         1418      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean       360062      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty       219677      0.00%      0.00%
-system.ruby.Directory_Controller.WB_O_W.Memory_Ack         1418      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETX           34      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS           71      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack       219676      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load      |       50441     12.51%     12.51% |       50284     12.47%     24.99% |       50341     12.49%     37.48% |       50472     12.52%     50.00% |       50384     12.50%     62.50% |       50303     12.48%     74.98% |       50287     12.48%     87.45% |       50586     12.55%    100.00%
-system.ruby.L1Cache_Controller.Load::total       403098                      
-system.ruby.L1Cache_Controller.Store     |       27978     12.49%     12.49% |       27946     12.47%     24.96% |       28262     12.61%     37.57% |       27557     12.30%     49.87% |       28153     12.56%     62.43% |       28184     12.58%     75.01% |       27910     12.46%     87.47% |       28086     12.53%    100.00%
-system.ruby.L1Cache_Controller.Store::total       224076                      
-system.ruby.L1Cache_Controller.L2_Replacement |       78258     12.50%     12.50% |       78079     12.47%     24.98% |       78452     12.53%     37.51% |       77881     12.44%     49.95% |       78395     12.52%     62.48% |       78336     12.51%     74.99% |       78026     12.47%     87.45% |       78526     12.55%    100.00%
-system.ruby.L1Cache_Controller.L2_Replacement::total       625953                      
-system.ruby.L1Cache_Controller.L1_to_L2  |      976938     12.50%     12.50% |      978501     12.52%     25.01% |      977534     12.50%     37.52% |      974694     12.47%     49.98% |      977852     12.51%     62.49% |      976494     12.49%     74.98% |      976920     12.50%     87.48% |      978975     12.52%    100.00%
-system.ruby.L1Cache_Controller.L1_to_L2::total      7817908                      
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D |          73     13.37%     13.37% |          64     11.72%     25.09% |          59     10.81%     35.90% |          74     13.55%     49.45% |          63     11.54%     60.99% |          64     11.72%     72.71% |          79     14.47%     87.18% |          70     12.82%    100.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total          546                      
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 |          73     13.37%     13.37% |          64     11.72%     25.09% |          59     10.81%     35.90% |          74     13.55%     49.45% |          63     11.54%     60.99% |          64     11.72%     72.71% |          79     14.47%     87.18% |          70     12.82%    100.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1::total          546                      
-system.ruby.L1Cache_Controller.Other_GETX |      195769     12.50%     12.50% |      195808     12.50%     25.01% |      195461     12.48%     37.49% |      196183     12.53%     50.02% |      195586     12.49%     62.51% |      195564     12.49%     75.00% |      195830     12.51%     87.50% |      195657     12.50%    100.00%
-system.ruby.L1Cache_Controller.Other_GETX::total      1565858                      
-system.ruby.L1Cache_Controller.Other_GETS |      351064     12.50%     12.50% |      351190     12.50%     25.00% |      351149     12.50%     37.50% |      351024     12.50%     50.00% |      351114     12.50%     62.50% |      351209     12.50%     75.00% |      351228     12.50%     87.51% |      350905     12.49%    100.00%
-system.ruby.L1Cache_Controller.Other_GETS::total      2808883                      
-system.ruby.L1Cache_Controller.Merged_GETS |         139     13.14%     13.14% |         131     12.38%     25.52% |         122     11.53%     37.05% |         152     14.37%     51.42% |         142     13.42%     64.84% |         100      9.45%     74.29% |         131     12.38%     86.67% |         141     13.33%    100.00%
-system.ruby.L1Cache_Controller.Merged_GETS::total         1058                      
-system.ruby.L1Cache_Controller.Ack       |      544353     12.50%     12.50% |      543353     12.48%     24.98% |      545955     12.54%     37.51% |      541876     12.44%     49.95% |      545429     12.52%     62.48% |      544934     12.51%     74.99% |      542876     12.47%     87.46% |      546350     12.54%    100.00%
-system.ruby.L1Cache_Controller.Ack::total      4355126                      
-system.ruby.L1Cache_Controller.Shared_Ack |          59     14.01%     14.01% |          38      9.03%     23.04% |          47     11.16%     34.20% |          57     13.54%     47.74% |          44     10.45%     58.19% |          52     12.35%     70.55% |          63     14.96%     85.51% |          61     14.49%    100.00%
-system.ruby.L1Cache_Controller.Shared_Ack::total          421                      
-system.ruby.L1Cache_Controller.Data      |        3443     12.55%     12.55% |        3428     12.50%     25.05% |        3401     12.40%     37.44% |        3393     12.37%     49.81% |        3427     12.49%     62.30% |        3495     12.74%     75.04% |        3416     12.45%     87.49% |        3431     12.51%    100.00%
-system.ruby.L1Cache_Controller.Data::total        27434                      
-system.ruby.L1Cache_Controller.Shared_Data |        1248     13.12%     13.12% |        1157     12.16%     25.28% |        1179     12.39%     37.67% |        1166     12.26%     49.93% |        1183     12.43%     62.36% |        1208     12.70%     75.06% |        1185     12.46%     87.51% |        1188     12.49%    100.00%
-system.ruby.L1Cache_Controller.Shared_Data::total         9514                      
-system.ruby.L1Cache_Controller.Exclusive_Data |       73575     12.49%     12.49% |       73502     12.48%     24.97% |       73882     12.54%     37.51% |       73331     12.45%     49.96% |       73794     12.53%     62.48% |       73640     12.50%     74.99% |       73433     12.47%     87.45% |       73919     12.55%    100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total       589076                      
-system.ruby.L1Cache_Controller.Writeback_Ack |       73741     12.49%     12.49% |       73736     12.49%     24.97% |       74045     12.54%     37.51% |       73508     12.45%     49.96% |       74018     12.53%     62.49% |       73844     12.50%     74.99% |       73562     12.46%     87.45% |       74128     12.55%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total       590582                      
-system.ruby.L1Cache_Controller.Writeback_Nack |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total            1                      
-system.ruby.L1Cache_Controller.All_acks  |        1299     13.13%     13.13% |        1192     12.05%     25.18% |        1222     12.35%     37.54% |        1212     12.25%     49.79% |        1221     12.34%     62.14% |        1259     12.73%     74.87% |        1245     12.59%     87.45% |        1241     12.55%    100.00%
-system.ruby.L1Cache_Controller.All_acks::total         9891                      
-system.ruby.L1Cache_Controller.All_acks_no_sharers |       76966     12.49%     12.49% |       76895     12.48%     24.97% |       77240     12.54%     37.51% |       76678     12.45%     49.95% |       77182     12.53%     62.48% |       77082     12.51%     74.99% |       76789     12.46%     87.45% |       77296     12.55%    100.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers::total       616128                      
-system.ruby.L1Cache_Controller.I.Load    |       50343     12.51%     12.51% |       50202     12.48%     24.99% |       50229     12.48%     37.47% |       50381     12.52%     50.00% |       50297     12.50%     62.50% |       50214     12.48%     74.98% |       50172     12.47%     87.45% |       50503     12.55%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       402341                      
-system.ruby.L1Cache_Controller.I.Store   |       27925     12.48%     12.48% |       27886     12.47%     24.95% |       28233     12.62%     37.57% |       27511     12.30%     49.87% |       28108     12.57%     62.44% |       28131     12.58%     75.01% |       27864     12.46%     87.47% |       28034     12.53%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       223692                      
-system.ruby.L1Cache_Controller.I.L2_Replacement |        1231     13.06%     13.06% |        1181     12.53%     25.59% |        1181     12.53%     38.11% |        1159     12.29%     50.41% |        1164     12.35%     62.76% |        1144     12.14%     74.89% |        1231     13.06%     87.95% |        1136     12.05%    100.00%
-system.ruby.L1Cache_Controller.I.L2_Replacement::total         9427                      
-system.ruby.L1Cache_Controller.I.L1_to_L2 |          85     12.25%     12.25% |          91     13.11%     25.36% |          73     10.52%     35.88% |          83     11.96%     47.84% |          90     12.97%     60.81% |          97     13.98%     74.78% |          89     12.82%     87.61% |          86     12.39%    100.00%
-system.ruby.L1Cache_Controller.I.L1_to_L2::total          694                      
-system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           0      0.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           1     12.50%    100.00%
-system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total            8                      
-system.ruby.L1Cache_Controller.I.Other_GETX |      194598     12.50%     12.50% |      194683     12.50%     25.00% |      194349     12.48%     37.49% |      195081     12.53%     50.02% |      194486     12.49%     62.51% |      194479     12.49%     75.00% |      194715     12.51%     87.51% |      194530     12.49%    100.00%
-system.ruby.L1Cache_Controller.I.Other_GETX::total      1556921                      
-system.ruby.L1Cache_Controller.I.Other_GETS |      349168     12.50%     12.50% |      349401     12.51%     25.00% |      349271     12.50%     37.50% |      349157     12.50%     50.00% |      349254     12.50%     62.50% |      349362     12.50%     75.00% |      349363     12.50%     87.51% |      349100     12.49%    100.00%
-system.ruby.L1Cache_Controller.I.Other_GETS::total      2794076                      
-system.ruby.L1Cache_Controller.S.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total            2                      
-system.ruby.L1Cache_Controller.S.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory_Controller.O_B.GETS           27      0.00%      0.00%
+system.ruby.Directory_Controller.O_B.UnblockS        16608      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.GETX         1928      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.GETS         3580      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data       593042      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.GETX           49      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.GETS          101      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.Memory_Data        16608      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETX         1361      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETS         2377      0.00%      0.00%
+system.ruby.Directory_Controller.WB.PUT            69      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Unblock         1497      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Clean         8046      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Dirty         1391      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean       362783      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty       220746      0.00%      0.00%
+system.ruby.Directory_Controller.WB_O_W.GETX            1      0.00%      0.00%
+system.ruby.Directory_Controller.WB_O_W.Memory_Ack         1391      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.GETX           39      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.GETS           78      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack       220746      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load      |       50425     12.41%     12.41% |       50709     12.48%     24.90% |       50956     12.55%     37.45% |       50792     12.51%     49.95% |       51090     12.58%     62.53% |       50892     12.53%     75.06% |       50587     12.45%     87.51% |       50715     12.49%    100.00%
+system.ruby.L1Cache_Controller.Load::total       406166                      
+system.ruby.L1Cache_Controller.Store     |       28286     12.56%     12.56% |       28252     12.55%     25.11% |       28051     12.46%     37.57% |       28152     12.50%     50.08% |       27992     12.43%     62.51% |       27935     12.41%     74.92% |       28146     12.50%     87.42% |       28326     12.58%    100.00%
+system.ruby.L1Cache_Controller.Store::total       225140                      
+system.ruby.L1Cache_Controller.L2_Replacement |       78587     12.47%     12.47% |       78793     12.51%     24.98% |       78855     12.52%     37.49% |       78785     12.50%     50.00% |       78925     12.53%     62.53% |       78672     12.49%     75.01% |       78574     12.47%     87.48% |       78861     12.52%    100.00%
+system.ruby.L1Cache_Controller.L2_Replacement::total       630052                      
+system.ruby.L1Cache_Controller.L1_to_L2  |      979843     12.49%     12.49% |      985286     12.56%     25.04% |      982191     12.52%     37.56% |      981607     12.51%     50.06% |      980625     12.50%     62.56% |      979114     12.48%     75.04% |      981906     12.51%     87.55% |      977135     12.45%    100.00%
+system.ruby.L1Cache_Controller.L1_to_L2::total      7847707                      
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D |          58     10.07%     10.07% |          65     11.28%     21.35% |          70     12.15%     33.51% |          75     13.02%     46.53% |          70     12.15%     58.68% |          68     11.81%     70.49% |          84     14.58%     85.07% |          86     14.93%    100.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total          576                      
+system.ruby.L1Cache_Controller.Complete_L2_to_L1 |          58     10.07%     10.07% |          65     11.28%     21.35% |          70     12.15%     33.51% |          75     13.02%     46.53% |          70     12.15%     58.68% |          68     11.81%     70.49% |          84     14.58%     85.07% |          86     14.93%    100.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1::total          576                      
+system.ruby.L1Cache_Controller.Other_GETX |      196471     12.49%     12.49% |      196526     12.49%     24.98% |      196715     12.51%     37.49% |      196608     12.50%     49.99% |      196780     12.51%     62.50% |      196834     12.51%     75.01% |      196619     12.50%     87.51% |      196466     12.49%    100.00%
+system.ruby.L1Cache_Controller.Other_GETX::total      1573019                      
+system.ruby.L1Cache_Controller.Other_GETS |      354173     12.51%     12.51% |      353911     12.50%     25.01% |      353677     12.49%     37.51% |      353845     12.50%     50.01% |      353517     12.49%     62.49% |      353736     12.50%     74.99% |      354047     12.51%     87.50% |      353925     12.50%    100.00%
+system.ruby.L1Cache_Controller.Other_GETS::total      2830831                      
+system.ruby.L1Cache_Controller.Merged_GETS |         129     12.77%     12.77% |         125     12.38%     25.15% |         131     12.97%     38.12% |         122     12.08%     50.20% |         132     13.07%     63.27% |         133     13.17%     76.44% |         121     11.98%     88.42% |         117     11.58%    100.00%
+system.ruby.L1Cache_Controller.Merged_GETS::total         1010                      
+system.ruby.L1Cache_Controller.Ack       |      546875     12.47%     12.47% |      548356     12.51%     24.98% |      548622     12.51%     37.50% |      548157     12.50%     50.00% |      549146     12.53%     62.53% |      547407     12.49%     75.01% |      546694     12.47%     87.49% |      548631     12.51%    100.00%
+system.ruby.L1Cache_Controller.Ack::total      4383888                      
+system.ruby.L1Cache_Controller.Shared_Ack |          47     11.66%     11.66% |          60     14.89%     26.55% |          55     13.65%     40.20% |          43     10.67%     50.87% |          52     12.90%     63.77% |          44     10.92%     74.69% |          47     11.66%     86.35% |          55     13.65%    100.00%
+system.ruby.L1Cache_Controller.Shared_Ack::total          403                      
+system.ruby.L1Cache_Controller.Data      |        3359     12.22%     12.22% |        3473     12.63%     24.85% |        3497     12.72%     37.57% |        3463     12.60%     50.16% |        3413     12.41%     62.58% |        3427     12.46%     75.04% |        3416     12.42%     87.47% |        3446     12.53%    100.00%
+system.ruby.L1Cache_Controller.Data::total        27494                      
+system.ruby.L1Cache_Controller.Shared_Data |        1154     12.00%     12.00% |        1176     12.23%     24.23% |        1180     12.27%     36.51% |        1237     12.87%     49.37% |        1274     13.25%     62.62% |        1156     12.02%     74.64% |        1231     12.80%     87.45% |        1207     12.55%    100.00%
+system.ruby.L1Cache_Controller.Shared_Data::total         9615                      
+system.ruby.L1Cache_Controller.Exclusive_Data |       74082     12.49%     12.49% |       74152     12.50%     25.00% |       74187     12.51%     37.51% |       74094     12.49%     50.00% |       74246     12.52%     62.52% |       74100     12.50%     75.02% |       73934     12.47%     87.48% |       74216     12.52%    100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total       593011                      
+system.ruby.L1Cache_Controller.Writeback_Ack |       74170     12.48%     12.48% |       74404     12.52%     24.99% |       74292     12.50%     37.49% |       74341     12.51%     50.00% |       74357     12.51%     62.50% |       74258     12.49%     74.99% |       74151     12.47%     87.47% |       74500     12.53%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total       594473                      
+system.ruby.L1Cache_Controller.All_acks  |        1194     11.98%     11.98% |        1225     12.29%     24.27% |        1234     12.38%     36.65% |        1275     12.79%     49.44% |        1320     13.24%     62.68% |        1193     11.97%     74.65% |        1269     12.73%     87.38% |        1258     12.62%    100.00%
+system.ruby.L1Cache_Controller.All_acks::total         9968                      
+system.ruby.L1Cache_Controller.All_acks_no_sharers |       77401     12.48%     12.48% |       77577     12.51%     24.99% |       77629     12.52%     37.51% |       77517     12.50%     50.01% |       77614     12.52%     62.52% |       77490     12.50%     75.02% |       77312     12.47%     87.49% |       77611     12.51%    100.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers::total       620151                      
+system.ruby.L1Cache_Controller.I.Load    |       50351     12.42%     12.42% |       50613     12.48%     24.90% |       50864     12.55%     37.45% |       50687     12.50%     49.95% |       51000     12.58%     62.53% |       50800     12.53%     75.06% |       50486     12.45%     87.51% |       50617     12.49%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       405418                      
+system.ruby.L1Cache_Controller.I.Store   |       28246     12.57%     12.57% |       28190     12.54%     25.11% |       28000     12.46%     37.58% |       28107     12.51%     50.08% |       27935     12.43%     62.51% |       27882     12.41%     74.92% |       28099     12.50%     87.43% |       28254     12.57%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       224713                      
+system.ruby.L1Cache_Controller.I.L2_Replacement |        1236     12.89%     12.89% |        1152     12.01%     24.90% |        1250     13.03%     37.93% |        1180     12.30%     50.23% |        1243     12.96%     63.19% |        1211     12.63%     75.81% |        1148     11.97%     87.78% |        1172     12.22%    100.00%
+system.ruby.L1Cache_Controller.I.L2_Replacement::total         9592                      
+system.ruby.L1Cache_Controller.I.L1_to_L2 |          99     12.47%     12.47% |          92     11.59%     24.06% |          95     11.96%     36.02% |          85     10.71%     46.73% |          93     11.71%     58.44% |         121     15.24%     73.68% |          87     10.96%     84.63% |         122     15.37%    100.00%
+system.ruby.L1Cache_Controller.I.L1_to_L2::total          794                      
+system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D |           1     11.11%     11.11% |           1     11.11%     22.22% |           1     11.11%     33.33% |           0      0.00%     33.33% |           2     22.22%     55.56% |           2     22.22%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00%
+system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total            9                      
+system.ruby.L1Cache_Controller.I.Other_GETX |      195341     12.49%     12.49% |      195451     12.50%     24.99% |      195544     12.50%     37.49% |      195508     12.50%     49.99% |      195605     12.51%     62.49% |      195730     12.51%     75.01% |      195526     12.50%     87.51% |      195339     12.49%    100.00%
+system.ruby.L1Cache_Controller.I.Other_GETX::total      1564044                      
+system.ruby.L1Cache_Controller.I.Other_GETS |      352206     12.51%     12.51% |      352024     12.50%     25.01% |      351754     12.49%     37.50% |      351944     12.50%     50.00% |      351596     12.49%     62.49% |      351866     12.50%     74.99% |      352184     12.51%     87.50% |      352077     12.50%    100.00%
+system.ruby.L1Cache_Controller.I.Other_GETS::total      2815651                      
+system.ruby.L1Cache_Controller.S.Load    |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total            3                      
+system.ruby.L1Cache_Controller.S.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.S.Store::total            1                      
-system.ruby.L1Cache_Controller.S.L2_Replacement |        3281     12.66%     12.66% |        3158     12.19%     24.84% |        3224     12.44%     37.28% |        3212     12.39%     49.68% |        3210     12.39%     62.06% |        3343     12.90%     74.96% |        3230     12.46%     87.43% |        3259     12.57%    100.00%
-system.ruby.L1Cache_Controller.S.L2_Replacement::total        25917                      
-system.ruby.L1Cache_Controller.S.L1_to_L2 |        3309     12.66%     12.66% |        3182     12.17%     24.83% |        3249     12.43%     37.26% |        3236     12.38%     49.64% |        3243     12.41%     62.05% |        3372     12.90%     74.95% |        3258     12.46%     87.41% |        3290     12.59%    100.00%
-system.ruby.L1Cache_Controller.S.L1_to_L2::total        26139                      
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D |           1      5.56%      5.56% |           2     11.11%     16.67% |           1      5.56%     22.22% |           5     27.78%     50.00% |           0      0.00%     50.00% |           1      5.56%     55.56% |           3     16.67%     72.22% |           5     27.78%    100.00%
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total           18                      
-system.ruby.L1Cache_Controller.S.Other_GETX |          27     12.16%     12.16% |          23     10.36%     22.52% |          25     11.26%     33.78% |          23     10.36%     44.14% |          37     16.67%     60.81% |          31     13.96%     74.77% |          28     12.61%     87.39% |          28     12.61%    100.00%
-system.ruby.L1Cache_Controller.S.Other_GETX::total          222                      
-system.ruby.L1Cache_Controller.S.Other_GETS |          50     11.88%     11.88% |          58     13.78%     25.65% |          48     11.40%     37.05% |          57     13.54%     50.59% |          53     12.59%     63.18% |          48     11.40%     74.58% |          56     13.30%     87.89% |          51     12.11%    100.00%
-system.ruby.L1Cache_Controller.S.Other_GETS::total          421                      
-system.ruby.L1Cache_Controller.O.L2_Replacement |         853     12.74%     12.74% |         805     12.02%     24.76% |         861     12.86%     37.62% |         860     12.84%     50.46% |         837     12.50%     62.96% |         826     12.34%     75.30% |         802     11.98%     87.28% |         852     12.72%    100.00%
-system.ruby.L1Cache_Controller.O.L2_Replacement::total         6696                      
-system.ruby.L1Cache_Controller.O.L1_to_L2 |          72     12.50%     12.50% |          69     11.98%     24.48% |          72     12.50%     36.98% |          78     13.54%     50.52% |          78     13.54%     64.06% |          62     10.76%     74.83% |          75     13.02%     87.85% |          70     12.15%    100.00%
-system.ruby.L1Cache_Controller.O.L1_to_L2::total          576                      
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D |           1     20.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total            5                      
-system.ruby.L1Cache_Controller.O.Other_GETX |           6     12.77%     12.77% |           5     10.64%     23.40% |           9     19.15%     42.55% |           8     17.02%     59.57% |           7     14.89%     74.47% |           3      6.38%     80.85% |           7     14.89%     95.74% |           2      4.26%    100.00%
-system.ruby.L1Cache_Controller.O.Other_GETX::total           47                      
-system.ruby.L1Cache_Controller.O.Other_GETS |           8     16.33%     16.33% |           5     10.20%     26.53% |           4      8.16%     34.69% |           7     14.29%     48.98% |           4      8.16%     57.14% |           9     18.37%     75.51% |           5     10.20%     85.71% |           7     14.29%    100.00%
-system.ruby.L1Cache_Controller.O.Other_GETS::total           49                      
-system.ruby.L1Cache_Controller.O.Merged_GETS |           3     13.04%     13.04% |           4     17.39%     30.43% |           4     17.39%     47.83% |           3     13.04%     60.87% |           4     17.39%     78.26% |           2      8.70%     86.96% |           1      4.35%     91.30% |           2      8.70%    100.00%
-system.ruby.L1Cache_Controller.O.Merged_GETS::total           23                      
-system.ruby.L1Cache_Controller.M.Load    |           3      8.33%      8.33% |           5     13.89%     22.22% |           7     19.44%     41.67% |           3      8.33%     50.00% |           6     16.67%     66.67% |           6     16.67%     83.33% |           1      2.78%     86.11% |           5     13.89%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total           36                      
-system.ruby.L1Cache_Controller.M.Store   |           2     11.76%     11.76% |           4     23.53%     35.29% |           3     17.65%     52.94% |           0      0.00%     52.94% |           0      0.00%     52.94% |           5     29.41%     82.35% |           3     17.65%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total           17                      
-system.ruby.L1Cache_Controller.M.L2_Replacement |       45717     12.49%     12.49% |       45764     12.50%     25.00% |       45686     12.48%     37.48% |       45851     12.53%     50.01% |       45789     12.51%     62.52% |       45558     12.45%     74.97% |       45647     12.47%     87.44% |       45961     12.56%    100.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement::total       365973                      
-system.ruby.L1Cache_Controller.M.L1_to_L2 |       46965     12.51%     12.51% |       46934     12.50%     25.00% |       46906     12.49%     37.49% |       47064     12.53%     50.02% |       46964     12.50%     62.53% |       46761     12.45%     74.98% |       46832     12.47%     87.45% |       47142     12.55%    100.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2::total       375568                      
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D |          43     13.87%     13.87% |          35     11.29%     25.16% |          31     10.00%     35.16% |          44     14.19%     49.35% |          35     11.29%     60.65% |          43     13.87%     74.52% |          42     13.55%     88.06% |          37     11.94%    100.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total          310                      
-system.ruby.L1Cache_Controller.M.Other_GETX |         481     13.18%     13.18% |         466     12.77%     25.95% |         455     12.47%     38.42% |         444     12.17%     50.59% |         438     12.00%     62.59% |         461     12.63%     75.23% |         479     13.13%     88.35% |         425     11.65%    100.00%
-system.ruby.L1Cache_Controller.M.Other_GETX::total         3649                      
-system.ruby.L1Cache_Controller.M.Other_GETS |         748     12.76%     12.76% |         702     11.97%     24.73% |         764     13.03%     37.76% |         746     12.72%     50.48% |         725     12.36%     62.84% |         741     12.64%     75.48% |         698     11.90%     87.38% |         740     12.62%    100.00%
-system.ruby.L1Cache_Controller.M.Other_GETS::total         5864                      
-system.ruby.L1Cache_Controller.M.Merged_GETS |          64     12.14%     12.14% |          63     11.95%     24.10% |          62     11.76%     35.86% |          79     14.99%     50.85% |          78     14.80%     65.65% |          50      9.49%     75.14% |          63     11.95%     87.10% |          68     12.90%    100.00%
-system.ruby.L1Cache_Controller.M.Merged_GETS::total          527                      
-system.ruby.L1Cache_Controller.MM.Load   |           3     12.00%     12.00% |           1      4.00%     16.00% |           2      8.00%     24.00% |           5     20.00%     44.00% |           4     16.00%     60.00% |           3     12.00%     72.00% |           4     16.00%     88.00% |           3     12.00%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           25                      
-system.ruby.L1Cache_Controller.MM.Store  |           1      9.09%      9.09% |           2     18.18%     27.27% |           1      9.09%     36.36% |           1      9.09%     45.45% |           1      9.09%     54.55% |           0      0.00%     54.55% |           1      9.09%     63.64% |           4     36.36%    100.00%
-system.ruby.L1Cache_Controller.MM.Store::total           11                      
-system.ruby.L1Cache_Controller.MM.L2_Replacement |       27176     12.47%     12.47% |       27171     12.47%     24.94% |       27500     12.62%     37.55% |       26799     12.30%     49.85% |       27395     12.57%     62.42% |       27465     12.60%     75.02% |       27116     12.44%     87.47% |       27318     12.53%    100.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement::total       217940                      
-system.ruby.L1Cache_Controller.MM.L1_to_L2 |       27906     12.48%     12.48% |       27872     12.47%     24.95% |       28217     12.62%     37.57% |       27501     12.30%     49.87% |       28089     12.56%     62.43% |       28113     12.57%     75.01% |       27857     12.46%     87.47% |       28015     12.53%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2::total       223570                      
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D |          27     13.17%     13.17% |          25     12.20%     25.37% |          24     11.71%     37.07% |          25     12.20%     49.27% |          26     12.68%     61.95% |          19      9.27%     71.22% |          33     16.10%     87.32% |          26     12.68%    100.00%
+system.ruby.L1Cache_Controller.S.L2_Replacement |        3179     12.24%     12.24% |        3234     12.45%     24.69% |        3311     12.75%     37.44% |        3261     12.56%     50.00% |        3325     12.80%     62.80% |        3200     12.32%     75.13% |        3275     12.61%     87.74% |        3185     12.26%    100.00%
+system.ruby.L1Cache_Controller.S.L2_Replacement::total        25970                      
+system.ruby.L1Cache_Controller.S.L1_to_L2 |        3204     12.23%     12.23% |        3269     12.47%     24.70% |        3343     12.76%     37.46% |        3292     12.56%     50.02% |        3354     12.80%     62.82% |        3229     12.32%     75.14% |        3299     12.59%     87.72% |        3217     12.28%    100.00%
+system.ruby.L1Cache_Controller.S.L1_to_L2::total        26207                      
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D |           4     20.00%     20.00% |           1      5.00%     25.00% |           2     10.00%     35.00% |           3     15.00%     50.00% |           2     10.00%     60.00% |           2     10.00%     70.00% |           3     15.00%     85.00% |           3     15.00%    100.00%
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total           20                      
+system.ruby.L1Cache_Controller.S.Other_GETX |          25     10.29%     10.29% |          35     14.40%     24.69% |          33     13.58%     38.27% |          30     12.35%     50.62% |          29     11.93%     62.55% |          33     13.58%     76.13% |          24      9.88%     86.01% |          34     13.99%    100.00%
+system.ruby.L1Cache_Controller.S.Other_GETX::total          243                      
+system.ruby.L1Cache_Controller.S.Other_GETS |          44     10.92%     10.92% |          50     12.41%     23.33% |          48     11.91%     35.24% |          49     12.16%     47.39% |          52     12.90%     60.30% |          52     12.90%     73.20% |          61     15.14%     88.34% |          47     11.66%    100.00%
+system.ruby.L1Cache_Controller.S.Other_GETS::total          403                      
+system.ruby.L1Cache_Controller.O.L2_Replacement |         898     13.24%     13.24% |         855     12.61%     25.84% |         861     12.69%     38.54% |         871     12.84%     51.38% |         823     12.13%     63.51% |         817     12.04%     75.56% |         846     12.47%     88.03% |         812     11.97%    100.00%
+system.ruby.L1Cache_Controller.O.L2_Replacement::total         6783                      
+system.ruby.L1Cache_Controller.O.L1_to_L2 |          75     13.16%     13.16% |          74     12.98%     26.14% |          66     11.58%     37.72% |          72     12.63%     50.35% |          66     11.58%     61.93% |          73     12.81%     74.74% |          82     14.39%     89.12% |          62     10.88%    100.00%
+system.ruby.L1Cache_Controller.O.L1_to_L2::total          570                      
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total            3                      
+system.ruby.L1Cache_Controller.O.Other_GETX |           5     13.16%     13.16% |           3      7.89%     21.05% |           7     18.42%     39.47% |           5     13.16%     52.63% |           2      5.26%     57.89% |           4     10.53%     68.42% |           5     13.16%     81.58% |           7     18.42%    100.00%
+system.ruby.L1Cache_Controller.O.Other_GETX::total           38                      
+system.ruby.L1Cache_Controller.O.Other_GETS |           2      3.64%      3.64% |           5      9.09%     12.73% |           9     16.36%     29.09% |           5      9.09%     38.18% |          10     18.18%     56.36% |           6     10.91%     67.27% |          10     18.18%     85.45% |           8     14.55%    100.00%
+system.ruby.L1Cache_Controller.O.Other_GETS::total           55                      
+system.ruby.L1Cache_Controller.O.Merged_GETS |           0      0.00%      0.00% |           2     14.29%     14.29% |           1      7.14%     21.43% |           1      7.14%     28.57% |           2     14.29%     42.86% |           3     21.43%     64.29% |           2     14.29%     78.57% |           3     21.43%    100.00%
+system.ruby.L1Cache_Controller.O.Merged_GETS::total           14                      
+system.ruby.L1Cache_Controller.M.Load    |           5     13.51%     13.51% |           9     24.32%     37.84% |           7     18.92%     56.76% |           5     13.51%     70.27% |           2      5.41%     75.68% |           1      2.70%     78.38% |           4     10.81%     89.19% |           4     10.81%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total           37                      
+system.ruby.L1Cache_Controller.M.Store   |           0      0.00%      0.00% |           7     35.00%     35.00% |           0      0.00%     35.00% |           3     15.00%     50.00% |           2     10.00%     60.00% |           2     10.00%     70.00% |           2     10.00%     80.00% |           4     20.00%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total           20                      
+system.ruby.L1Cache_Controller.M.L2_Replacement |       45800     12.42%     12.42% |       46049     12.49%     24.90% |       46199     12.53%     37.43% |       46062     12.49%     49.92% |       46337     12.56%     62.48% |       46329     12.56%     75.05% |       45903     12.45%     87.49% |       46127     12.51%    100.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement::total       368806                      
+system.ruby.L1Cache_Controller.M.L1_to_L2 |       47052     12.43%     12.43% |       47253     12.48%     24.91% |       47440     12.53%     37.45% |       47312     12.50%     49.95% |       47567     12.57%     62.51% |       47475     12.54%     75.06% |       47100     12.44%     87.50% |       47318     12.50%    100.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2::total       378517                      
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D |          32      9.44%      9.44% |          37     10.91%     20.35% |          37     10.91%     31.27% |          48     14.16%     45.43% |          43     12.68%     58.11% |          39     11.50%     69.62% |          53     15.63%     85.25% |          50     14.75%    100.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total          339                      
+system.ruby.L1Cache_Controller.M.Other_GETX |         465     12.67%     12.67% |         445     12.13%     24.80% |         472     12.86%     37.67% |         457     12.46%     50.12% |         497     13.55%     63.67% |         429     11.69%     75.36% |         449     12.24%     87.60% |         455     12.40%    100.00%
+system.ruby.L1Cache_Controller.M.Other_GETX::total         3669                      
+system.ruby.L1Cache_Controller.M.Other_GETS |         787     13.14%     13.14% |         748     12.49%     25.62% |         758     12.65%     38.27% |         778     12.99%     51.26% |         725     12.10%     63.36% |         725     12.10%     75.46% |         745     12.44%     87.90% |         725     12.10%    100.00%
+system.ruby.L1Cache_Controller.M.Other_GETS::total         5991                      
+system.ruby.L1Cache_Controller.M.Merged_GETS |          74     13.91%     13.91% |          72     13.53%     27.44% |          69     12.97%     40.41% |          68     12.78%     53.20% |          61     11.47%     64.66% |          61     11.47%     76.13% |          66     12.41%     88.53% |          61     11.47%    100.00%
+system.ruby.L1Cache_Controller.M.Merged_GETS::total          532                      
+system.ruby.L1Cache_Controller.MM.Load   |           0      0.00%      0.00% |           1      7.69%      7.69% |           2     15.38%     23.08% |           3     23.08%     46.15% |           1      7.69%     53.85% |           1      7.69%     61.54% |           2     15.38%     76.92% |           3     23.08%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           13                      
+system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           3     25.00%     25.00% |           1      8.33%     33.33% |           1      8.33%     41.67% |           2     16.67%     58.33% |           3     25.00%     83.33% |           1      8.33%     91.67% |           1      8.33%    100.00%
+system.ruby.L1Cache_Controller.MM.Store::total           12                      
+system.ruby.L1Cache_Controller.MM.L2_Replacement |       27474     12.55%     12.55% |       27503     12.56%     25.12% |       27234     12.44%     37.56% |       27411     12.52%     50.08% |       27197     12.42%     62.50% |       27115     12.39%     74.89% |       27402     12.52%     87.41% |       27565     12.59%    100.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement::total       218901                      
+system.ruby.L1Cache_Controller.MM.L1_to_L2 |       28221     12.57%     12.57% |       28176     12.55%     25.11% |       27986     12.46%     37.57% |       28104     12.51%     50.09% |       27921     12.43%     62.52% |       27848     12.40%     74.92% |       28097     12.51%     87.43% |       28234     12.57%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2::total       224587                      
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D |          21     10.24%     10.24% |          25     12.20%     22.44% |          30     14.63%     37.07% |          24     11.71%     48.78% |          22     10.73%     59.51% |          25     12.20%     71.71% |          28     13.66%     85.37% |          30     14.63%    100.00%
 system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total          205                      
-system.ruby.L1Cache_Controller.MM.Other_GETX |         267     12.74%     12.74% |         270     12.88%     25.62% |         259     12.36%     37.98% |         265     12.64%     50.62% |         246     11.74%     62.36% |         255     12.17%     74.52% |         260     12.40%     86.93% |         274     13.07%    100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETX::total         2096                      
-system.ruby.L1Cache_Controller.MM.Other_GETS |         451     13.18%     13.18% |         418     12.22%     25.40% |         435     12.72%     38.12% |         419     12.25%     50.37% |         438     12.80%     63.17% |         394     11.52%     74.69% |         458     13.39%     88.07% |         408     11.93%    100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETS::total         3421                      
-system.ruby.L1Cache_Controller.MM.Merged_GETS |          47     13.31%     13.31% |          45     12.75%     26.06% |          44     12.46%     38.53% |          43     12.18%     50.71% |          42     11.90%     62.61% |          38     10.76%     73.37% |          48     13.60%     86.97% |          46     13.03%    100.00%
-system.ruby.L1Cache_Controller.MM.Merged_GETS::total          353                      
-system.ruby.L1Cache_Controller.IR.Load   |           1     16.67%     16.67% |           1     16.67%     33.33% |           2     33.33%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           0      0.00%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETX |         277     12.99%     12.99% |         248     11.63%     24.62% |         289     13.56%     38.18% |         251     11.77%     49.95% |         272     12.76%     62.71% |         302     14.17%     76.88% |         242     11.35%     88.23% |         251     11.77%    100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETX::total         2132                      
+system.ruby.L1Cache_Controller.MM.Other_GETS |         465     13.21%     13.21% |         422     11.99%     25.21% |         450     12.79%     37.99% |         437     12.42%     50.41% |         445     12.65%     63.06% |         445     12.65%     75.70% |         428     12.16%     87.87% |         427     12.13%    100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETS::total         3519                      
+system.ruby.L1Cache_Controller.MM.Merged_GETS |          42     14.00%     14.00% |          39     13.00%     27.00% |          41     13.67%     40.67% |          30     10.00%     50.67% |          40     13.33%     64.00% |          35     11.67%     75.67% |          40     13.33%     89.00% |          33     11.00%    100.00%
+system.ruby.L1Cache_Controller.MM.Merged_GETS::total          300                      
+system.ruby.L1Cache_Controller.IR.Load   |           1     16.67%     16.67% |           0      0.00%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           2     33.33%     83.33% |           0      0.00%     83.33% |           1     16.67%    100.00%
 system.ruby.L1Cache_Controller.IR.Load::total            6                      
-system.ruby.L1Cache_Controller.IR.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.IR.Store::total            2                      
-system.ruby.L1Cache_Controller.IR.L1_to_L2 |           7     35.00%     35.00% |           0      0.00%     35.00% |           1      5.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |          12     60.00%    100.00%
-system.ruby.L1Cache_Controller.IR.L1_to_L2::total           20                      
-system.ruby.L1Cache_Controller.SR.Load   |           1      7.69%      7.69% |           1      7.69%     15.38% |           1      7.69%     23.08% |           4     30.77%     53.85% |           0      0.00%     53.85% |           1      7.69%     61.54% |           3     23.08%     84.62% |           2     15.38%    100.00%
+system.ruby.L1Cache_Controller.IR.Store  |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.IR.Store::total            3                      
+system.ruby.L1Cache_Controller.IR.L1_to_L2 |           1      8.33%      8.33% |          10     83.33%     91.67% |           0      0.00%     91.67% |           0      0.00%     91.67% |           0      0.00%     91.67% |           0      0.00%     91.67% |           0      0.00%     91.67% |           1      8.33%    100.00%
+system.ruby.L1Cache_Controller.IR.L1_to_L2::total           12                      
+system.ruby.L1Cache_Controller.SR.Load   |           3     23.08%     23.08% |           0      0.00%     23.08% |           0      0.00%     23.08% |           2     15.38%     38.46% |           2     15.38%     53.85% |           0      0.00%     53.85% |           3     23.08%     76.92% |           3     23.08%    100.00%
 system.ruby.L1Cache_Controller.SR.Load::total           13                      
-system.ruby.L1Cache_Controller.SR.Store  |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           3     60.00%    100.00%
-system.ruby.L1Cache_Controller.SR.Store::total            5                      
-system.ruby.L1Cache_Controller.SR.L1_to_L2 |          11     21.57%     21.57% |          14     27.45%     49.02% |           0      0.00%     49.02% |          12     23.53%     72.55% |           0      0.00%     72.55% |           0      0.00%     72.55% |           9     17.65%     90.20% |           5      9.80%    100.00%
-system.ruby.L1Cache_Controller.SR.L1_to_L2::total           51                      
-system.ruby.L1Cache_Controller.OR.Load   |           1     20.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.OR.Load::total            5                      
-system.ruby.L1Cache_Controller.OR.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           6     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           6     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OR.L1_to_L2::total           12                      
-system.ruby.L1Cache_Controller.MR.Load   |          27     13.64%     13.64% |          21     10.61%     24.24% |          27     13.64%     37.88% |          27     13.64%     51.52% |          20     10.10%     61.62% |          23     11.62%     73.23% |          28     14.14%     87.37% |          25     12.63%    100.00%
-system.ruby.L1Cache_Controller.MR.Load::total          198                      
-system.ruby.L1Cache_Controller.MR.Store  |          16     14.29%     14.29% |          14     12.50%     26.79% |           4      3.57%     30.36% |          17     15.18%     45.54% |          15     13.39%     58.93% |          20     17.86%     76.79% |          14     12.50%     89.29% |          12     10.71%    100.00%
-system.ruby.L1Cache_Controller.MR.Store::total          112                      
-system.ruby.L1Cache_Controller.MR.L1_to_L2 |          88     17.78%     17.78% |          39      7.88%     25.66% |          51     10.30%     35.96% |          88     17.78%     53.74% |          74     14.95%     68.69% |          39      7.88%     76.57% |          69     13.94%     90.51% |          47      9.49%    100.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2::total          495                      
-system.ruby.L1Cache_Controller.MMR.Load  |          19     13.77%     13.77% |          13      9.42%     23.19% |          18     13.04%     36.23% |          20     14.49%     50.72% |          17     12.32%     63.04% |          13      9.42%     72.46% |          23     16.67%     89.13% |          15     10.87%    100.00%
-system.ruby.L1Cache_Controller.MMR.Load::total          138                      
-system.ruby.L1Cache_Controller.MMR.Store |           8     11.94%     11.94% |          12     17.91%     29.85% |           6      8.96%     38.81% |           5      7.46%     46.27% |           9     13.43%     59.70% |           6      8.96%     68.66% |          10     14.93%     83.58% |          11     16.42%    100.00%
-system.ruby.L1Cache_Controller.MMR.Store::total           67                      
-system.ruby.L1Cache_Controller.MMR.L1_to_L2 |          77     18.55%     18.55% |          56     13.49%     32.05% |          70     16.87%     48.92% |          35      8.43%     57.35% |          58     13.98%     71.33% |          20      4.82%     76.14% |          76     18.31%     94.46% |          23      5.54%    100.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2::total          415                      
-system.ruby.L1Cache_Controller.IM.L1_to_L2 |      278544     12.60%     12.60% |      277743     12.56%     25.16% |      280869     12.70%     37.86% |      272194     12.31%     50.17% |      276047     12.48%     62.65% |      276727     12.51%     75.16% |      274477     12.41%     87.57% |      274776     12.43%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2::total      2211377                      
-system.ruby.L1Cache_Controller.IM.Other_GETX |          85     16.16%     16.16% |          58     11.03%     27.19% |          69     13.12%     40.30% |          47      8.94%     49.24% |          75     14.26%     63.50% |          70     13.31%     76.81% |          62     11.79%     88.59% |          60     11.41%    100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETX::total          526                      
-system.ruby.L1Cache_Controller.IM.Other_GETS |         106     11.79%     11.79% |         118     13.13%     24.92% |         113     12.57%     37.49% |         111     12.35%     49.83% |         103     11.46%     61.29% |         111     12.35%     73.64% |         119     13.24%     86.87% |         118     13.13%    100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETS::total          899                      
-system.ruby.L1Cache_Controller.IM.Ack    |      136713     12.57%     12.57% |      135265     12.43%     25.00% |      137767     12.66%     37.67% |      133467     12.27%     49.94% |      136048     12.51%     62.44% |      136618     12.56%     75.00% |      135810     12.49%     87.49% |      136093     12.51%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total      1087781                      
-system.ruby.L1Cache_Controller.IM.Data   |        1382     12.80%     12.80% |        1402     12.99%     25.79% |        1328     12.30%     38.10% |        1322     12.25%     50.34% |        1363     12.63%     62.97% |        1329     12.31%     75.28% |        1343     12.44%     87.72% |        1325     12.28%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total        10794                      
-system.ruby.L1Cache_Controller.IM.Exclusive_Data |       26543     12.47%     12.47% |       26483     12.44%     24.91% |       26903     12.64%     37.54% |       26188     12.30%     49.85% |       26745     12.56%     62.41% |       26801     12.59%     75.00% |       26521     12.46%     87.45% |       26709     12.55%    100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       212893                      
-system.ruby.L1Cache_Controller.SM.L1_to_L2 |           0      0.00%      0.00% |           6     18.18%     18.18% |           4     12.12%     30.30% |           7     21.21%     51.52% |           0      0.00%     51.52% |           0      0.00%     51.52% |           0      0.00%     51.52% |          16     48.48%    100.00%
-system.ruby.L1Cache_Controller.SM.L1_to_L2::total           33                      
-system.ruby.L1Cache_Controller.SM.Ack    |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |          14     66.67%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total           21                      
-system.ruby.L1Cache_Controller.SM.Data   |           0      0.00%      0.00% |           1     16.67%     16.67% |           1     16.67%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           3     50.00%    100.00%
-system.ruby.L1Cache_Controller.SM.Data::total            6                      
-system.ruby.L1Cache_Controller.ISM.L1_to_L2 |        1378     12.28%     12.28% |        1476     13.15%     25.43% |        1358     12.10%     37.52% |        1291     11.50%     49.02% |        1461     13.02%     62.04% |        1735     15.46%     77.50% |        1152     10.26%     87.76% |        1374     12.24%    100.00%
-system.ruby.L1Cache_Controller.ISM.L1_to_L2::total        11225                      
-system.ruby.L1Cache_Controller.ISM.Ack   |        2968     12.36%     12.36% |        3074     12.80%     25.15% |        2971     12.37%     37.52% |        3107     12.93%     50.46% |        3108     12.94%     63.39% |        3097     12.89%     76.29% |        2854     11.88%     88.17% |        2842     11.83%    100.00%
-system.ruby.L1Cache_Controller.ISM.Ack::total        24021                      
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers |        1382     12.80%     12.80% |        1403     12.99%     25.79% |        1329     12.31%     38.09% |        1323     12.25%     50.34% |        1363     12.62%     62.96% |        1329     12.31%     75.27% |        1343     12.44%     87.70% |        1328     12.30%    100.00%
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total        10800                      
-system.ruby.L1Cache_Controller.M_W.Load  |           2      9.52%      9.52% |           6     28.57%     38.10% |           4     19.05%     57.14% |           1      4.76%     61.90% |           2      9.52%     71.43% |           3     14.29%     85.71% |           3     14.29%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total           21                      
-system.ruby.L1Cache_Controller.M_W.Store |           2     14.29%     14.29% |           4     28.57%     42.86% |           1      7.14%     50.00% |           2     14.29%     64.29% |           1      7.14%     71.43% |           1      7.14%     78.57% |           3     21.43%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total           14                      
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 |       74738     12.51%     12.51% |       76785     12.85%     25.37% |       73525     12.31%     37.68% |       73939     12.38%     50.05% |       74584     12.49%     62.54% |       74401     12.46%     75.00% |       74616     12.49%     87.49% |       74732     12.51%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2::total       597320                      
-system.ruby.L1Cache_Controller.M_W.Ack   |       98263     12.50%     12.50% |       98562     12.53%     25.03% |       97942     12.46%     37.49% |       98017     12.46%     49.95% |       97892     12.45%     62.40% |       97827     12.44%     74.84% |       98974     12.59%     87.43% |       98873     12.57%    100.00%
-system.ruby.L1Cache_Controller.M_W.Ack::total       786350                      
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers |       47030     12.50%     12.50% |       47015     12.50%     25.00% |       46978     12.49%     37.49% |       47141     12.53%     50.02% |       47047     12.51%     62.53% |       46836     12.45%     74.98% |       46909     12.47%     87.45% |       47210     12.55%    100.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total       376166                      
-system.ruby.L1Cache_Controller.MM_W.Load |           2     11.11%     11.11% |           4     22.22%     33.33% |           2     11.11%     44.44% |           1      5.56%     50.00% |           3     16.67%     66.67% |           4     22.22%     88.89% |           2     11.11%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total           18                      
-system.ruby.L1Cache_Controller.MM_W.Store |           1     14.29%     14.29% |           0      0.00%     14.29% |           0      0.00%     14.29% |           1     14.29%     28.57% |           0      0.00%     28.57% |           2     28.57%     57.14% |           2     28.57%     85.71% |           1     14.29%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total            7                      
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 |       41839     12.37%     12.37% |       42308     12.51%     24.87% |       42669     12.61%     37.49% |       42131     12.45%     49.94% |       42574     12.59%     62.53% |       41857     12.37%     74.90% |       42636     12.60%     87.50% |       42269     12.50%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total       338283                      
-system.ruby.L1Cache_Controller.MM_W.Ack  |       54858     12.28%     12.28% |       55978     12.53%     24.81% |       55938     12.52%     37.33% |       55130     12.34%     49.66% |       56721     12.69%     62.36% |       56318     12.60%     74.96% |       55482     12.42%     87.38% |       56384     12.62%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Ack::total       446809                      
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers |       26545     12.47%     12.47% |       26487     12.44%     24.91% |       26904     12.64%     37.55% |       26190     12.30%     49.85% |       26746     12.56%     62.41% |       26802     12.59%     75.00% |       26524     12.46%     87.46% |       26709     12.54%    100.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total       212907                      
-system.ruby.L1Cache_Controller.IS.L1_to_L2 |      496961     12.46%     12.46% |      496660     12.45%     24.91% |      494888     12.41%     37.32% |      501380     12.57%     49.89% |      498894     12.51%     62.39% |      497896     12.48%     74.88% |      500417     12.55%     87.42% |      501712     12.58%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2::total      3988808                      
-system.ruby.L1Cache_Controller.IS.Other_GETX |         120     13.70%     13.70% |         102     11.64%     25.34% |         104     11.87%     37.21% |         122     13.93%     51.14% |         116     13.24%     64.38% |          92     10.50%     74.89% |         101     11.53%     86.42% |         119     13.58%    100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETX::total          876                      
-system.ruby.L1Cache_Controller.IS.Other_GETS |         212     13.16%     13.16% |         192     11.92%     25.08% |         219     13.59%     38.67% |         199     12.35%     51.02% |         188     11.67%     62.69% |         205     12.73%     75.42% |         205     12.73%     88.14% |         191     11.86%    100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETS::total         1611                      
-system.ruby.L1Cache_Controller.IS.Ack    |      244322     12.52%     12.52% |      243435     12.47%     24.99% |      243945     12.50%     37.48% |      245096     12.56%     50.04% |      244536     12.53%     62.56% |      243639     12.48%     75.04% |      242664     12.43%     87.48% |      244497     12.52%    100.00%
-system.ruby.L1Cache_Controller.IS.Ack::total      1952134                      
-system.ruby.L1Cache_Controller.IS.Shared_Ack |          37     12.63%     12.63% |          28      9.56%     22.18% |          26      8.87%     31.06% |          37     12.63%     43.69% |          35     11.95%     55.63% |          36     12.29%     67.92% |          48     16.38%     84.30% |          46     15.70%    100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Ack::total          293                      
-system.ruby.L1Cache_Controller.IS.Data   |        2061     12.39%     12.39% |        2025     12.17%     24.56% |        2072     12.46%     37.02% |        2070     12.44%     49.46% |        2064     12.41%     61.87% |        2166     13.02%     74.89% |        2073     12.46%     87.36% |        2103     12.64%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total        16634                      
-system.ruby.L1Cache_Controller.IS.Shared_Data |        1248     13.12%     13.12% |        1157     12.16%     25.28% |        1179     12.39%     37.67% |        1166     12.26%     49.93% |        1183     12.43%     62.36% |        1208     12.70%     75.06% |        1185     12.46%     87.51% |        1188     12.49%    100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Data::total         9514                      
-system.ruby.L1Cache_Controller.IS.Exclusive_Data |       47032     12.50%     12.50% |       47019     12.50%     25.00% |       46979     12.49%     37.49% |       47143     12.53%     50.02% |       47049     12.51%     62.53% |       46839     12.45%     74.98% |       46912     12.47%     87.45% |       47210     12.55%    100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       376183                      
-system.ruby.L1Cache_Controller.SS.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00%
-system.ruby.L1Cache_Controller.SS.Load::total            3                      
-system.ruby.L1Cache_Controller.SS.L1_to_L2 |        4693     11.36%     11.36% |        5086     12.31%     23.68% |        5364     12.99%     36.66% |        5399     13.07%     49.74% |        5426     13.14%     62.87% |        5212     12.62%     75.49% |        4958     12.00%     87.50% |        5163     12.50%    100.00%
-system.ruby.L1Cache_Controller.SS.L1_to_L2::total        41301                      
-system.ruby.L1Cache_Controller.SS.Ack    |        7229     12.46%     12.46% |        7039     12.13%     24.60% |        7385     12.73%     37.33% |        7059     12.17%     49.49% |        7124     12.28%     61.78% |        7435     12.82%     74.59% |        7092     12.23%     86.82% |        7647     13.18%    100.00%
-system.ruby.L1Cache_Controller.SS.Ack::total        58010                      
-system.ruby.L1Cache_Controller.SS.Shared_Ack |          22     17.19%     17.19% |          10      7.81%     25.00% |          21     16.41%     41.41% |          20     15.62%     57.03% |           9      7.03%     64.06% |          16     12.50%     76.56% |          15     11.72%     88.28% |          15     11.72%    100.00%
-system.ruby.L1Cache_Controller.SS.Shared_Ack::total          128                      
-system.ruby.L1Cache_Controller.SS.All_acks |        1299     13.13%     13.13% |        1192     12.05%     25.18% |        1222     12.35%     37.54% |        1212     12.25%     49.79% |        1221     12.34%     62.14% |        1259     12.73%     74.87% |        1245     12.59%     87.45% |        1241     12.55%    100.00%
-system.ruby.L1Cache_Controller.SS.All_acks::total         9891                      
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers |        2009     12.36%     12.36% |        1990     12.24%     24.60% |        2029     12.48%     37.08% |        2024     12.45%     49.54% |        2026     12.46%     62.00% |        2115     13.01%     75.01% |        2013     12.38%     87.39% |        2049     12.61%    100.00%
+system.ruby.L1Cache_Controller.SR.Store  |           1     14.29%     14.29% |           1     14.29%     28.57% |           2     28.57%     57.14% |           1     14.29%     71.43% |           0      0.00%     71.43% |           2     28.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SR.Store::total            7                      
+system.ruby.L1Cache_Controller.SR.L1_to_L2 |           6     20.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           9     30.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           5     16.67%     66.67% |          10     33.33%    100.00%
+system.ruby.L1Cache_Controller.SR.L1_to_L2::total           30                      
+system.ruby.L1Cache_Controller.OR.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.OR.Load::total            1                      
+system.ruby.L1Cache_Controller.OR.Store  |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OR.Store::total            2                      
+system.ruby.L1Cache_Controller.OR.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00%
+system.ruby.L1Cache_Controller.OR.L1_to_L2::total            5                      
+system.ruby.L1Cache_Controller.MR.Load   |          20      9.26%      9.26% |          23     10.65%     19.91% |          23     10.65%     30.56% |          33     15.28%     45.83% |          28     12.96%     58.80% |          26     12.04%     70.83% |          36     16.67%     87.50% |          27     12.50%    100.00%
+system.ruby.L1Cache_Controller.MR.Load::total          216                      
+system.ruby.L1Cache_Controller.MR.Store  |          12      9.76%      9.76% |          14     11.38%     21.14% |          14     11.38%     32.52% |          15     12.20%     44.72% |          15     12.20%     56.91% |          13     10.57%     67.48% |          17     13.82%     81.30% |          23     18.70%    100.00%
+system.ruby.L1Cache_Controller.MR.Store::total          123                      
+system.ruby.L1Cache_Controller.MR.L1_to_L2 |          61     10.65%     10.65% |          80     13.96%     24.61% |          51      8.90%     33.51% |          40      6.98%     40.49% |          77     13.44%     53.93% |          68     11.87%     65.79% |          53      9.25%     75.04% |         143     24.96%    100.00%
+system.ruby.L1Cache_Controller.MR.L1_to_L2::total          573                      
+system.ruby.L1Cache_Controller.MMR.Load  |          14     10.77%     10.77% |          14     10.77%     21.54% |          19     14.62%     36.15% |          17     13.08%     49.23% |          10      7.69%     56.92% |          17     13.08%     70.00% |          21     16.15%     86.15% |          18     13.85%    100.00%
+system.ruby.L1Cache_Controller.MMR.Load::total          130                      
+system.ruby.L1Cache_Controller.MMR.Store |           7      9.33%      9.33% |          11     14.67%     24.00% |          11     14.67%     38.67% |           7      9.33%     48.00% |          12     16.00%     64.00% |           8     10.67%     74.67% |           7      9.33%     84.00% |          12     16.00%    100.00%
+system.ruby.L1Cache_Controller.MMR.Store::total           75                      
+system.ruby.L1Cache_Controller.MMR.L1_to_L2 |          50     11.39%     11.39% |          56     12.76%     24.15% |          72     16.40%     40.55% |          41      9.34%     49.89% |          73     16.63%     66.51% |          45     10.25%     76.77% |          49     11.16%     87.93% |          53     12.07%    100.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2::total          439                      
+system.ruby.L1Cache_Controller.IM.L1_to_L2 |      283520     12.65%     12.65% |      280559     12.52%     25.18% |      278577     12.43%     37.61% |      282969     12.63%     50.24% |      277805     12.40%     62.64% |      276768     12.35%     74.99% |      280123     12.50%     87.49% |      280175     12.51%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2::total      2240496                      
+system.ruby.L1Cache_Controller.IM.Other_GETX |          69     13.75%     13.75% |          47      9.36%     23.11% |          73     14.54%     37.65% |          58     11.55%     49.20% |          71     14.14%     63.35% |          55     10.96%     74.30% |          74     14.74%     89.04% |          55     10.96%    100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETX::total          502                      
+system.ruby.L1Cache_Controller.IM.Other_GETS |         129     13.59%     13.59% |         118     12.43%     26.03% |         120     12.64%     38.67% |         118     12.43%     51.11% |         128     13.49%     64.59% |         136     14.33%     78.93% |          87      9.17%     88.09% |         113     11.91%    100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETS::total          949                      
+system.ruby.L1Cache_Controller.IM.Ack    |      138770     12.59%     12.59% |      138200     12.54%     25.12% |      136999     12.43%     37.55% |      138460     12.56%     50.11% |      136866     12.42%     62.53% |      136573     12.39%     74.92% |      137631     12.48%     87.40% |      138894     12.60%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total      1102393                      
+system.ruby.L1Cache_Controller.IM.Data   |        1307     12.02%     12.02% |        1378     12.67%     24.68% |        1329     12.22%     36.90% |        1405     12.92%     49.82% |        1332     12.24%     62.06% |        1346     12.37%     74.43% |        1347     12.38%     86.82% |        1434     13.18%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total        10878                      
+system.ruby.L1Cache_Controller.IM.Exclusive_Data |       26937     12.60%     12.60% |       26811     12.54%     25.14% |       26670     12.47%     37.61% |       26702     12.49%     50.10% |       26603     12.44%     62.54% |       26535     12.41%     74.95% |       26750     12.51%     87.46% |       26817     12.54%    100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       213825                      
+system.ruby.L1Cache_Controller.SM.L1_to_L2 |           6      9.38%      9.38% |          25     39.06%     48.44% |           5      7.81%     56.25% |           2      3.12%     59.38% |           0      0.00%     59.38% |          26     40.62%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.L1_to_L2::total           64                      
+system.ruby.L1Cache_Controller.SM.Ack    |           1      2.33%      2.33% |           7     16.28%     18.60% |          14     32.56%     51.16% |           7     16.28%     67.44% |           0      0.00%     67.44% |          14     32.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total           43                      
+system.ruby.L1Cache_Controller.SM.Data   |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           2     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Data::total            8                      
+system.ruby.L1Cache_Controller.OM.Ack    |           0      0.00%      0.00% |           7     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           7     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total           14                      
+system.ruby.L1Cache_Controller.OM.All_acks_no_sharers |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total            2                      
+system.ruby.L1Cache_Controller.ISM.L1_to_L2 |        1168     10.71%     10.71% |        1389     12.74%     23.46% |        1158     10.62%     34.08% |        1445     13.26%     47.34% |        1501     13.77%     61.10% |        1257     11.53%     72.64% |        1603     14.71%     87.34% |        1380     12.66%    100.00%
+system.ruby.L1Cache_Controller.ISM.L1_to_L2::total        10901                      
+system.ruby.L1Cache_Controller.ISM.Ack   |        2566     11.15%     11.15% |        3004     13.06%     24.21% |        2589     11.25%     35.46% |        2967     12.89%     48.35% |        2929     12.73%     61.08% |        2855     12.41%     73.49% |        3081     13.39%     86.88% |        3019     13.12%    100.00%
+system.ruby.L1Cache_Controller.ISM.Ack::total        23010                      
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers |        1308     12.02%     12.02% |        1379     12.67%     24.68% |        1331     12.23%     36.91% |        1407     12.92%     49.83% |        1332     12.24%     62.07% |        1348     12.38%     74.45% |        1347     12.37%     86.83% |        1434     13.17%    100.00%
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total        10886                      
+system.ruby.L1Cache_Controller.M_W.Load  |           6     21.43%     21.43% |           3     10.71%     32.14% |           4     14.29%     46.43% |           2      7.14%     53.57% |           3     10.71%     64.29% |           7     25.00%     89.29% |           1      3.57%     92.86% |           2      7.14%    100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total           28                      
+system.ruby.L1Cache_Controller.M_W.Store |           2     11.76%     11.76% |           2     11.76%     23.53% |           3     17.65%     41.18% |           3     17.65%     58.82% |           3     17.65%     76.47% |           1      5.88%     82.35% |           1      5.88%     88.24% |           2     11.76%    100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total           17                      
+system.ruby.L1Cache_Controller.M_W.L1_to_L2 |       70208     12.27%     12.27% |       71483     12.50%     24.77% |       72279     12.64%     37.41% |       71279     12.46%     49.87% |       72276     12.64%     62.50% |       71468     12.49%     75.00% |       71747     12.54%     87.54% |       71273     12.46%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_to_L2::total       572013                      
+system.ruby.L1Cache_Controller.M_W.Ack   |       95563     12.35%     12.35% |       97187     12.56%     24.92% |       96343     12.45%     37.37% |       97412     12.59%     49.96% |       97834     12.65%     62.61% |       96623     12.49%     75.10% |       96494     12.47%     87.57% |       96142     12.43%    100.00%
+system.ruby.L1Cache_Controller.M_W.Ack::total       773598                      
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers |       47143     12.43%     12.43% |       47339     12.49%     24.92% |       47513     12.53%     37.45% |       47388     12.50%     49.95% |       47640     12.56%     62.51% |       47564     12.54%     75.06% |       47183     12.44%     87.50% |       47397     12.50%    100.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total       379167                      
+system.ruby.L1Cache_Controller.MM_W.Load |           1     14.29%     14.29% |           2     28.57%     42.86% |           0      0.00%     42.86% |           1     14.29%     57.14% |           0      0.00%     57.14% |           2     28.57%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total            7                      
+system.ruby.L1Cache_Controller.MM_W.Store |           2     25.00%     25.00% |           0      0.00%     25.00% |           2     25.00%     50.00% |           0      0.00%     50.00% |           1     12.50%     62.50% |           2     25.00%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total            8                      
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2 |       41379     12.65%     12.65% |       41221     12.60%     25.25% |       41051     12.55%     37.80% |       40535     12.39%     50.19% |       40742     12.46%     62.65% |       40472     12.37%     75.02% |       41502     12.69%     87.71% |       40195     12.29%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total       327097                      
+system.ruby.L1Cache_Controller.MM_W.Ack  |       55447     12.59%     12.59% |       55256     12.55%     25.14% |       55503     12.61%     37.75% |       54454     12.37%     50.12% |       54820     12.45%     62.57% |       54819     12.45%     75.02% |       55083     12.51%     87.53% |       54923     12.47%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Ack::total       440305                      
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers |       26939     12.60%     12.60% |       26813     12.54%     25.14% |       26673     12.47%     37.61% |       26704     12.49%     50.10% |       26606     12.44%     62.54% |       26536     12.41%     74.95% |       26751     12.51%     87.46% |       26819     12.54%    100.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total       213841                      
+system.ruby.L1Cache_Controller.IS.L1_to_L2 |      499192     12.41%     12.41% |      505934     12.58%     24.99% |      504666     12.55%     37.54% |      500825     12.45%     49.99% |      503592     12.52%     62.51% |      505147     12.56%     75.07% |      502816     12.50%     87.58% |      499646     12.42%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_to_L2::total      4021818                      
+system.ruby.L1Cache_Controller.IS.Other_GETX |          95     10.66%     10.66% |         120     13.47%     24.13% |         122     13.69%     37.82% |         108     12.12%     49.94% |         113     12.68%     62.63% |         103     11.56%     74.19% |         115     12.91%     87.09% |         115     12.91%    100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETX::total          891                      
+system.ruby.L1Cache_Controller.IS.Other_GETS |         217     12.73%     12.73% |         214     12.55%     25.28% |         221     12.96%     38.24% |         233     13.67%     51.91% |         238     13.96%     65.87% |         192     11.26%     77.13% |         183     10.73%     87.86% |         207     12.14%    100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETS::total         1705                      
+system.ruby.L1Cache_Controller.IS.Ack    |      247332     12.45%     12.45% |      247416     12.45%     24.90% |      250036     12.58%     37.48% |      247568     12.46%     49.94% |      249322     12.55%     62.49% |      249531     12.56%     75.05% |      247241     12.44%     87.50% |      248455     12.50%    100.00%
+system.ruby.L1Cache_Controller.IS.Ack::total      1986901                      
+system.ruby.L1Cache_Controller.IS.Shared_Ack |          33     11.07%     11.07% |          39     13.09%     24.16% |          44     14.77%     38.93% |          33     11.07%     50.00% |          37     12.42%     62.42% |          37     12.42%     74.83% |          31     10.40%     85.23% |          44     14.77%    100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Ack::total          298                      
+system.ruby.L1Cache_Controller.IS.Data   |        2051     12.35%     12.35% |        2094     12.61%     24.96% |        2166     13.04%     38.00% |        2056     12.38%     50.38% |        2081     12.53%     62.91% |        2079     12.52%     75.43% |        2069     12.46%     87.89% |        2012     12.11%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total        16608                      
+system.ruby.L1Cache_Controller.IS.Shared_Data |        1154     12.00%     12.00% |        1176     12.23%     24.23% |        1180     12.27%     36.51% |        1237     12.87%     49.37% |        1274     13.25%     62.62% |        1156     12.02%     74.64% |        1231     12.80%     87.45% |        1207     12.55%    100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Data::total         9615                      
+system.ruby.L1Cache_Controller.IS.Exclusive_Data |       47145     12.43%     12.43% |       47341     12.48%     24.92% |       47517     12.53%     37.45% |       47392     12.50%     49.95% |       47643     12.56%     62.51% |       47565     12.54%     75.06% |       47184     12.44%     87.50% |       47399     12.50%    100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       379186                      
+system.ruby.L1Cache_Controller.SS.L1_to_L2 |        5412     13.03%     13.03% |        5439     13.09%     26.12% |        5189     12.49%     38.62% |        5322     12.81%     51.43% |        5271     12.69%     64.12% |        4898     11.79%     75.91% |        5046     12.15%     88.06% |        4958     11.94%    100.00%
+system.ruby.L1Cache_Controller.SS.L1_to_L2::total        41535                      
+system.ruby.L1Cache_Controller.SS.Ack    |        7196     12.49%     12.49% |        7279     12.63%     25.12% |        7138     12.39%     37.51% |        7289     12.65%     50.16% |        7368     12.79%     62.94% |        6992     12.13%     75.08% |        7164     12.43%     87.51% |        7198     12.49%    100.00%
+system.ruby.L1Cache_Controller.SS.Ack::total        57624                      
+system.ruby.L1Cache_Controller.SS.Shared_Ack |          14     13.33%     13.33% |          21     20.00%     33.33% |          11     10.48%     43.81% |          10      9.52%     53.33% |          15     14.29%     67.62% |           7      6.67%     74.29% |          16     15.24%     89.52% |          11     10.48%    100.00%
+system.ruby.L1Cache_Controller.SS.Shared_Ack::total          105                      
+system.ruby.L1Cache_Controller.SS.All_acks |        1194     11.98%     11.98% |        1225     12.29%     24.27% |        1234     12.38%     36.65% |        1275     12.79%     49.44% |        1320     13.24%     62.68% |        1193     11.97%     74.65% |        1269     12.73%     87.38% |        1258     12.62%    100.00%
+system.ruby.L1Cache_Controller.SS.All_acks::total         9968                      
+system.ruby.L1Cache_Controller.SS.All_acks_no_sharers |        2011     12.37%     12.37% |        2045     12.58%     24.95% |        2112     12.99%     37.95% |        2018     12.41%     50.36% |        2035     12.52%     62.88% |        2042     12.56%     75.44% |        2031     12.49%     87.94% |        1961     12.06%    100.00%
 system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total        16255                      
-system.ruby.L1Cache_Controller.OI.Other_GETX |           8     33.33%     33.33% |           5     20.83%     54.17% |           2      8.33%     62.50% |           2      8.33%     70.83% |           0      0.00%     70.83% |           2      8.33%     79.17% |           2      8.33%     87.50% |           3     12.50%    100.00%
+system.ruby.L1Cache_Controller.OI.Load   |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Load::total            1                      
+system.ruby.L1Cache_Controller.OI.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Store::total            1                      
+system.ruby.L1Cache_Controller.OI.Other_GETX |           4     16.67%     16.67% |           1      4.17%     20.83% |           3     12.50%     33.33% |           2      8.33%     41.67% |           3     12.50%     54.17% |           1      4.17%     58.33% |           2      8.33%     66.67% |           8     33.33%    100.00%
 system.ruby.L1Cache_Controller.OI.Other_GETX::total           24                      
-system.ruby.L1Cache_Controller.OI.Other_GETS |           2      9.52%      9.52% |           4     19.05%     28.57% |           2      9.52%     38.10% |           3     14.29%     52.38% |           2      9.52%     61.90% |           2      9.52%     71.43% |           1      4.76%     76.19% |           5     23.81%    100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETS::total           21                      
-system.ruby.L1Cache_Controller.OI.Merged_GETS |           4     17.39%     17.39% |           1      4.35%     21.74% |           2      8.70%     30.43% |           4     17.39%     47.83% |           8     34.78%     82.61% |           2      8.70%     91.30% |           0      0.00%     91.30% |           2      8.70%    100.00%
-system.ruby.L1Cache_Controller.OI.Merged_GETS::total           23                      
-system.ruby.L1Cache_Controller.OI.Writeback_Ack |        1185     12.71%     12.71% |        1110     11.90%     24.61% |        1162     12.46%     37.08% |        1206     12.93%     50.01% |        1193     12.79%     62.81% |        1169     12.54%     75.34% |        1142     12.25%     87.59% |        1157     12.41%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack::total         9324                      
-system.ruby.L1Cache_Controller.MI.Load   |          12     10.34%     10.34% |           9      7.76%     18.10% |          21     18.10%     36.21% |          10      8.62%     44.83% |          14     12.07%     56.90% |          18     15.52%     72.41% |          19     16.38%     88.79% |          13     11.21%    100.00%
-system.ruby.L1Cache_Controller.MI.Load::total          116                      
-system.ruby.L1Cache_Controller.MI.Store  |          11     17.19%     17.19% |          11     17.19%     34.38% |           8     12.50%     46.88% |           8     12.50%     59.38% |           5      7.81%     67.19% |           9     14.06%     81.25% |           5      7.81%     89.06% |           7     10.94%    100.00%
-system.ruby.L1Cache_Controller.MI.Store::total           64                      
-system.ruby.L1Cache_Controller.MI.Other_GETX |         176     11.77%     11.77% |         195     13.04%     24.82% |         189     12.64%     37.46% |         191     12.78%     50.23% |         181     12.11%     62.34% |         171     11.44%     73.78% |         176     11.77%     85.55% |         216     14.45%    100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETX::total         1495                      
-system.ruby.L1Cache_Controller.MI.Other_GETS |         319     12.65%     12.65% |         292     11.58%     24.24% |         293     11.62%     35.86% |         325     12.89%     48.75% |         347     13.76%     62.51% |         337     13.37%     75.88% |         323     12.81%     88.69% |         285     11.31%    100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETS::total         2521                      
-system.ruby.L1Cache_Controller.MI.Merged_GETS |          21     15.91%     15.91% |          18     13.64%     29.55% |          10      7.58%     37.12% |          23     17.42%     54.55% |          10      7.58%     62.12% |           8      6.06%     68.18% |          19     14.39%     82.58% |          23     17.42%    100.00%
-system.ruby.L1Cache_Controller.MI.Merged_GETS::total          132                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack |       72372     12.48%     12.48% |       72427     12.49%     24.98% |       72692     12.54%     37.52% |       72109     12.44%     49.95% |       72644     12.53%     62.48% |       72502     12.51%     74.99% |       72242     12.46%     87.45% |       72752     12.55%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       579740                      
-system.ruby.L1Cache_Controller.II.Load   |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.II.Load::total            2                      
-system.ruby.L1Cache_Controller.II.Other_GETX |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETS |           5     26.32%     26.32% |           2     10.53%     36.84% |           2     10.53%     47.37% |           5     26.32%     73.68% |           1      5.26%     78.95% |           0      0.00%     78.95% |           1      5.26%     84.21% |           3     15.79%    100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETS::total           19                      
+system.ruby.L1Cache_Controller.OI.Merged_GETS |           2      8.33%      8.33% |           1      4.17%     12.50% |           2      8.33%     20.83% |           4     16.67%     37.50% |           5     20.83%     58.33% |           2      8.33%     66.67% |           5     20.83%     87.50% |           3     12.50%    100.00%
+system.ruby.L1Cache_Controller.OI.Merged_GETS::total           24                      
+system.ruby.L1Cache_Controller.OI.Writeback_Ack |        1223     12.96%     12.96% |        1193     12.64%     25.60% |        1191     12.62%     38.22% |        1164     12.33%     50.56% |        1166     12.36%     62.91% |        1162     12.31%     75.23% |        1200     12.72%     87.94% |        1138     12.06%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack::total         9437                      
+system.ruby.L1Cache_Controller.MI.Load   |           5      4.63%      4.63% |          17     15.74%     20.37% |          12     11.11%     31.48% |          18     16.67%     48.15% |          16     14.81%     62.96% |          15     13.89%     76.85% |           8      7.41%     84.26% |          17     15.74%    100.00%
+system.ruby.L1Cache_Controller.MI.Load::total          108                      
+system.ruby.L1Cache_Controller.MI.Store  |           6     10.17%     10.17% |           8     13.56%     23.73% |           5      8.47%     32.20% |           4      6.78%     38.98% |           6     10.17%     49.15% |          10     16.95%     66.10% |          10     16.95%     83.05% |          10     16.95%    100.00%
+system.ruby.L1Cache_Controller.MI.Store::total           59                      
+system.ruby.L1Cache_Controller.MI.Other_GETX |         190     12.89%     12.89% |         176     11.94%     24.83% |         172     11.67%     36.50% |         189     12.82%     49.32% |         186     12.62%     61.94% |         177     12.01%     73.95% |         182     12.35%     86.30% |         202     13.70%    100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETX::total         1474                      
+system.ruby.L1Cache_Controller.MI.Other_GETS |         318     12.53%     12.53% |         328     12.92%     25.45% |         315     12.41%     37.86% |         276     10.87%     48.74% |         322     12.69%     61.43% |         314     12.37%     73.80% |         348     13.71%     87.51% |         317     12.49%    100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETS::total         2538                      
+system.ruby.L1Cache_Controller.MI.Merged_GETS |          11      7.86%      7.86% |          11      7.86%     15.71% |          18     12.86%     28.57% |          19     13.57%     42.14% |          24     17.14%     59.29% |          32     22.86%     82.14% |           8      5.71%     87.86% |          17     12.14%    100.00%
+system.ruby.L1Cache_Controller.MI.Merged_GETS::total          140                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack |       72753     12.47%     12.47% |       73034     12.52%     24.98% |       72926     12.50%     37.48% |       72986     12.51%     49.99% |       73002     12.51%     62.50% |       72918     12.50%     74.99% |       72767     12.47%     87.46% |       73153     12.54%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       583539                      
+system.ruby.L1Cache_Controller.II.Other_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.II.Other_GETX::total            2                      
-system.ruby.L1Cache_Controller.II.Writeback_Ack |         184     12.12%     12.12% |         199     13.11%     25.23% |         191     12.58%     37.81% |         193     12.71%     50.53% |         181     11.92%     62.45% |         173     11.40%     73.85% |         178     11.73%     85.57% |         219     14.43%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total         1518                      
-system.ruby.L1Cache_Controller.II.Writeback_Nack |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total            1                      
-system.ruby.L1Cache_Controller.IT.Load   |           1     25.00%     25.00% |           0      0.00%     25.00% |           2     50.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IT.Load::total            4                      
-system.ruby.L1Cache_Controller.IT.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.IT.Store::total            2                      
-system.ruby.L1Cache_Controller.IT.L1_to_L2 |           7     35.00%     35.00% |           0      0.00%     35.00% |           1      5.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |          12     60.00%    100.00%
-system.ruby.L1Cache_Controller.IT.L1_to_L2::total           20                      
-system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           0      0.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           1     12.50%    100.00%
-system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total            8                      
-system.ruby.L1Cache_Controller.ST.Load   |           1     16.67%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           3     50.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.II.Other_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.II.Other_GETS::total            1                      
+system.ruby.L1Cache_Controller.II.Writeback_Ack |         194     12.96%     12.96% |         177     11.82%     24.78% |         175     11.69%     36.47% |         191     12.76%     49.23% |         189     12.63%     61.86% |         178     11.89%     73.75% |         184     12.29%     86.04% |         209     13.96%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack::total         1497                      
+system.ruby.L1Cache_Controller.IT.Load   |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IT.Load::total            3                      
+system.ruby.L1Cache_Controller.IT.Store  |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IT.Store::total            1                      
+system.ruby.L1Cache_Controller.IT.L1_to_L2 |           1      3.57%      3.57% |          10     35.71%     39.29% |           0      0.00%     39.29% |           0      0.00%     39.29% |           6     21.43%     60.71% |           3     10.71%     71.43% |           0      0.00%     71.43% |           8     28.57%    100.00%
+system.ruby.L1Cache_Controller.IT.L1_to_L2::total           28                      
+system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 |           1     11.11%     11.11% |           1     11.11%     22.22% |           1     11.11%     33.33% |           0      0.00%     33.33% |           2     22.22%     55.56% |           2     22.22%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00%
+system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total            9                      
+system.ruby.L1Cache_Controller.ST.Load   |           1     16.67%     16.67% |           0      0.00%     16.67% |           0      0.00%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           2     33.33%     66.67% |           2     33.33%    100.00%
 system.ruby.L1Cache_Controller.ST.Load::total            6                      
-system.ruby.L1Cache_Controller.ST.Store  |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           3     75.00%    100.00%
-system.ruby.L1Cache_Controller.ST.Store::total            4                      
-system.ruby.L1Cache_Controller.ST.L1_to_L2 |          11     10.89%     10.89% |          14     13.86%     24.75% |           8      7.92%     32.67% |          12     11.88%     44.55% |           0      0.00%     44.55% |           0      0.00%     44.55% |           9      8.91%     53.47% |          47     46.53%    100.00%
-system.ruby.L1Cache_Controller.ST.L1_to_L2::total          101                      
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 |           1      5.56%      5.56% |           2     11.11%     16.67% |           1      5.56%     22.22% |           5     27.78%     50.00% |           0      0.00%     50.00% |           1      5.56%     55.56% |           3     16.67%     72.22% |           5     27.78%    100.00%
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total           18                      
-system.ruby.L1Cache_Controller.OT.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
-system.ruby.L1Cache_Controller.OT.Load::total            3                      
-system.ruby.L1Cache_Controller.OT.L1_to_L2 |           3     20.00%     20.00% |           0      0.00%     20.00% |           6     40.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           6     40.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OT.L1_to_L2::total           15                      
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 |           1     20.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total            5                      
-system.ruby.L1Cache_Controller.MT.Load   |          15     16.85%     16.85% |          10     11.24%     28.09% |          12     13.48%     41.57% |          11     12.36%     53.93% |          11     12.36%     66.29% |           9     10.11%     76.40% |          13     14.61%     91.01% |           8      8.99%    100.00%
-system.ruby.L1Cache_Controller.MT.Load::total           89                      
-system.ruby.L1Cache_Controller.MT.Store  |           7     15.91%     15.91% |           5     11.36%     27.27% |           1      2.27%     29.55% |           8     18.18%     47.73% |           9     20.45%     68.18% |           4      9.09%     77.27% |           5     11.36%     88.64% |           5     11.36%    100.00%
-system.ruby.L1Cache_Controller.MT.Store::total           44                      
-system.ruby.L1Cache_Controller.MT.L1_to_L2 |         153     13.17%     13.17% |          95      8.18%     21.34% |         101      8.69%     30.03% |         171     14.72%     44.75% |         156     13.43%     58.18% |         158     13.60%     71.77% |         214     18.42%     90.19% |         114      9.81%    100.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2::total         1162                      
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 |          43     13.87%     13.87% |          35     11.29%     25.16% |          31     10.00%     35.16% |          44     14.19%     49.35% |          35     11.29%     60.65% |          43     13.87%     74.52% |          42     13.55%     88.06% |          37     11.94%    100.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total          310                      
-system.ruby.L1Cache_Controller.MMT.Load  |          10     13.89%     13.89% |           8     11.11%     25.00% |          10     13.89%     38.89% |           8     11.11%     50.00% |           9     12.50%     62.50% |           6      8.33%     70.83% |          13     18.06%     88.89% |           8     11.11%    100.00%
-system.ruby.L1Cache_Controller.MMT.Load::total           72                      
-system.ruby.L1Cache_Controller.MMT.Store |           5     14.71%     14.71% |           6     17.65%     32.35% |           4     11.76%     44.12% |           3      8.82%     52.94% |           3      8.82%     61.76% |           6     17.65%     79.41% |           3      8.82%     88.24% |           4     11.76%    100.00%
-system.ruby.L1Cache_Controller.MMT.Store::total           34                      
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 |          91     12.59%     12.59% |          71      9.82%     22.41% |          96     13.28%     35.68% |          73     10.10%     45.78% |         114     15.77%     61.55% |          32      4.43%     65.98% |         176     24.34%     90.32% |          70      9.68%    100.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2::total          723                      
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 |          27     13.17%     13.17% |          25     12.20%     25.37% |          24     11.71%     37.07% |          25     12.20%     49.27% |          26     12.68%     61.95% |          19      9.27%     71.22% |          33     16.10%     87.32% |          26     12.68%    100.00%
+system.ruby.L1Cache_Controller.ST.Store  |           1     16.67%     16.67% |           0      0.00%     16.67% |           3     50.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.ST.Store::total            6                      
+system.ruby.L1Cache_Controller.ST.L1_to_L2 |          10     14.29%     14.29% |           7     10.00%     24.29% |           0      0.00%     24.29% |           9     12.86%     37.14% |           1      1.43%     38.57% |           9     12.86%     51.43% |           3      4.29%     55.71% |          31     44.29%    100.00%
+system.ruby.L1Cache_Controller.ST.L1_to_L2::total           70                      
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 |           4     20.00%     20.00% |           1      5.00%     25.00% |           2     10.00%     35.00% |           3     15.00%     50.00% |           2     10.00%     60.00% |           2     10.00%     70.00% |           3     15.00%     85.00% |           3     15.00%    100.00%
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total           20                      
+system.ruby.L1Cache_Controller.OT.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.OT.Load::total            1                      
+system.ruby.L1Cache_Controller.OT.Store  |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OT.Store::total            1                      
+system.ruby.L1Cache_Controller.OT.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00%
+system.ruby.L1Cache_Controller.OT.L1_to_L2::total            5                      
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total            3                      
+system.ruby.L1Cache_Controller.MT.Load   |           9      7.89%      7.89% |          19     16.67%     24.56% |          15     13.16%     37.72% |          15     13.16%     50.88% |          17     14.91%     65.79% |          12     10.53%     76.32% |          13     11.40%     87.72% |          14     12.28%    100.00%
+system.ruby.L1Cache_Controller.MT.Load::total          114                      
+system.ruby.L1Cache_Controller.MT.Store  |           6     12.00%     12.00% |           6     12.00%     24.00% |           4      8.00%     32.00% |           4      8.00%     40.00% |           6     12.00%     52.00% |           5     10.00%     62.00% |           5     10.00%     72.00% |          14     28.00%    100.00%
+system.ruby.L1Cache_Controller.MT.Store::total           50                      
+system.ruby.L1Cache_Controller.MT.L1_to_L2 |         121     10.82%     10.82% |         141     12.61%     23.43% |          82      7.33%     30.77% |         189     16.91%     47.67% |         135     12.08%     59.75% |         120     10.73%     70.48% |         127     11.36%     81.84% |         203     18.16%    100.00%
+system.ruby.L1Cache_Controller.MT.L1_to_L2::total         1118                      
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 |          32      9.44%      9.44% |          37     10.91%     20.35% |          37     10.91%     31.27% |          48     14.16%     45.43% |          43     12.68%     58.11% |          39     11.50%     69.62% |          53     15.63%     85.25% |          50     14.75%    100.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total          339                      
+system.ruby.L1Cache_Controller.MMT.Load  |           8     13.11%     13.11% |           6      9.84%     22.95% |           9     14.75%     37.70% |           8     13.11%     50.82% |           8     13.11%     63.93% |           7     11.48%     75.41% |          10     16.39%     91.80% |           5      8.20%    100.00%
+system.ruby.L1Cache_Controller.MMT.Load::total           61                      
+system.ruby.L1Cache_Controller.MMT.Store |           3      7.32%      7.32% |           6     14.63%     21.95% |           5     12.20%     34.15% |           6     14.63%     48.78% |           8     19.51%     68.29% |           5     12.20%     80.49% |           4      9.76%     90.24% |           4      9.76%    100.00%
+system.ruby.L1Cache_Controller.MMT.Store::total           41                      
+system.ruby.L1Cache_Controller.MMT.L1_to_L2 |          57      6.88%      6.88% |          68      8.21%     15.10% |         131     15.82%     30.92% |          77      9.30%     40.22% |         145     17.51%     57.73% |          87     10.51%     68.24% |         167     20.17%     88.41% |          96     11.59%    100.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2::total          828                      
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 |          21     10.24%     10.24% |          25     12.20%     22.44% |          30     14.63%     37.07% |          24     11.71%     48.78% |          22     10.73%     59.51% |          25     12.20%     71.71% |          28     13.66%     85.37% |          30     14.63%    100.00%
 system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total          205                      
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index a573d3fa4..118b5390e 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.007555                       # Number of seconds simulated
-sim_ticks                                     7555268                       # Number of ticks simulated
-final_tick                                    7555268                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.007664                       # Number of seconds simulated
+sim_ticks                                     7663697                       # Number of ticks simulated
+final_tick                                    7663697                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 300368                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 516584                       # Number of bytes of host memory used
-host_seconds                                    25.15                       # Real time elapsed on the host
+host_tick_rate                                 221013                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 570240                       # Number of bytes of host memory used
+host_seconds                                    34.68                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39518912                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           39518912                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0     39517888                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total        39517888                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       617483                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              617483                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       617467                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             617467                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   5230643307                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            5230643307                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   5230507773                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           5230507773                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0  10461151080                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total          10461151080                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      617498                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     617467                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    617498                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   617467                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               38662976                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                  856576                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                39021568                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                39519872                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys             39517888                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                  13384                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                  7703                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39606720                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           39606720                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0     39605504                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total        39605504                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       618855                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              618855                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       618836                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             618836                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   5168095764                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            5168095764                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   5167937094                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           5167937094                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0  10336032857                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total          10336032857                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      618867                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     618836                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    618867                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   618836                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               38729152                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                  877568                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                39100032                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                39607488                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys             39605504                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                  13712                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                  7842                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             75345                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             75630                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             75779                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             75335                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             74961                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             75413                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             76010                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             75636                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             76101                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             75669                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             75586                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             75582                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             75688                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             75150                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             75932                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             75435                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::10                0                       # Per bank write bursts
@@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0             76025                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1             76356                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2             76461                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3             76035                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4             75665                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5             76133                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6             76696                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7             76341                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             76815                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1             76432                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2             76283                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3             76308                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4             76418                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5             75865                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6             76657                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7             76160                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
@@ -68,53 +68,53 @@ system.mem_ctrls.perBankWrBursts::13                0                       # Pe
 system.mem_ctrls.perBankWrBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry                      1313                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                       7555254                       # Total gap between requests
+system.mem_ctrls.numWrRetry                      1565                       # Number of times write queue was full causing retry
+system.mem_ctrls.totGap                       7663682                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                617498                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                618867                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               617467                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                      27                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     395                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                    1547                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                    4803                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                   10732                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                   19329                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                   29926                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                   39736                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8                   47332                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9                   51238                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10                  49822                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11                  45328                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12                  39038                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13                  34104                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14                  29932                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15                  27412                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16                  25532                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17                  24223                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18                  23465                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19                  22388                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20                  20868                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21                  18295                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22                  14861                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23                  10803                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24                   6963                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25                   3724                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26                   1587                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27                    536                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28                    146                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29                     19                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30                      3                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               618836                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                      17                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     261                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                    1039                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                    3286                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                    7979                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                   15656                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                   25778                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                   37228                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::8                   46409                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::9                   53585                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::10                  54448                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::11                  51035                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::12                  44560                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::13                  37792                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::14                  31846                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::15                  28053                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::16                  25672                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::17                  23930                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::18                  22890                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::19                  21644                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::20                  19735                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::21                  17142                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::22                  13645                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::23                   9856                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::24                   6202                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::25                   3287                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::26                   1464                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::27                    529                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::28                    152                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::29                     30                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::30                      5                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
@@ -147,511 +147,511 @@ system.mem_ctrls.wrQLenPdf::27                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::28                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     72                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                    237                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    615                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                   1345                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                   2774                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                   4991                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                   7821                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                  10763                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                  14754                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                  18194                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                  20672                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                  23139                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                  24969                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                  25977                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                  27541                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                  28269                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48                  29583                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49                  30968                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50                  32545                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51                  33941                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52                  33783                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53                  34127                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54                  36711                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55                  56250                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56                  47740                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57                  20435                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58                  15303                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59                  10488                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60                   7108                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61                   4178                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62                   1989                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63                   2445                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples       244165                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    318.158098                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   243.329803                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   225.133894                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        33053     13.54%     13.54% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        74498     30.51%     44.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383        47835     19.59%     63.64% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511        35613     14.59%     78.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639        24095      9.87%     88.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767        14293      5.85%     93.95% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         7627      3.12%     97.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023         3851      1.58%     98.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151         3300      1.35%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total       244165                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples        38107                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      15.852311                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean      8.829731                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     11.389209                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-3           12433     32.63%     32.63% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::4-7            1821      4.78%     37.41% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-11            458      1.20%     38.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-15           176      0.46%     39.07% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19          3225      8.46%     47.53% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23          7120     18.68%     66.22% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27          6436     16.89%     83.11% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31          5233     13.73%     96.84% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35          1168      3.07%     99.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39            36      0.09%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.wrQLenPdf::31                     15                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     38                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                    123                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                    305                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    824                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                   1781                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                   3229                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                   4948                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                   8209                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                  11908                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                  15017                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                  18231                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                  20205                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::44                  21771                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                  23468                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                  24901                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                  25709                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::48                  26816                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::49                  28040                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::50                  29869                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::51                  32691                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::52                  34751                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::53                  37242                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::54                  41772                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::55                  66357                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::56                  58736                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::57                  24195                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::58                  18322                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::59                  13247                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::60                   8126                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::61                   4786                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::62                   2460                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::63                   2871                       # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples       245598                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    316.887532                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   240.845849                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   227.054939                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        34539     14.06%     14.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        75522     30.75%     44.81% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383        47012     19.14%     63.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511        34656     14.11%     78.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639        24109      9.82%     87.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767        14722      5.99%     93.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         7733      3.15%     97.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023         3901      1.59%     98.61% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151         3404      1.39%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total       245598                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples        38184                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      15.848078                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean      8.302353                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     11.863449                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-3           13558     35.51%     35.51% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::4-7            1227      3.21%     38.72% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-11            321      0.84%     39.56% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-15           186      0.49%     40.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-19          3091      8.10%     48.14% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-23          6038     15.81%     63.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-27          5831     15.27%     79.23% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::28-31          6271     16.42%     95.65% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-35          1620      4.24%     99.89% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-39            40      0.10%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::80-83             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total         38107                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples        38107                       # Writes before turning the bus around for reads
+system.mem_ctrls.rdPerTurnAround::total         38184                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples        38183                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::mean             16                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16            38107    100.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total         38107                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                    111252820                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat               122730891                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                    3020545                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                       184.16                       # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::16            38183    100.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total         38183                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                    114251031                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat               125748748                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                    3025715                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                       188.80                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                  203.16                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      5117.35                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      5164.82                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   5230.77                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   5230.51                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                  207.80                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      5053.59                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      5101.98                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   5168.20                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   5167.94                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        80.33                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    39.98                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   40.35                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                      18.19                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      53.14                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   369680                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  599969                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 61.19                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                98.39                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                          6.12                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    79.88                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy               1845214560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy               1025119200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy              7536484800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy             6319337472                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy            493303200                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy           5147480988                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             16294800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy            22383235020                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           2963.601171                       # Core power per rank (mW)
+system.mem_ctrls.busUtil                        79.34                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    39.48                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   39.86                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                      18.24                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      53.79                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   369216                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  601261                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 61.01                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                98.41                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                          6.19                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    79.80                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy               1856244600                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy               1031247000                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy              7550137920                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy             6332442624                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy            500423040                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy           5221769544                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             16530000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy            22508794728                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower           2937.826817                       # Core power per rank (mW)
 system.mem_ctrls_0.memoryStateTime::IDLE           12                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF        252200                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF        255840                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT       7300517                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT       7405878                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy            493303200                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            163216080                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy           4388427600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy             5044946880                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.969017                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE      7300480                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF        252200                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy            500423040                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy            165571776                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy           4451763600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy             5117758416                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            667.969048                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE      7405844                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF        255840                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           98710                       # number of read accesses completed
-system.cpu0.num_writes                          55193                       # number of write accesses completed
-system.cpu1.num_reads                           99197                       # number of read accesses completed
-system.cpu1.num_writes                          54876                       # number of write accesses completed
-system.cpu2.num_reads                           99807                       # number of read accesses completed
-system.cpu2.num_writes                          55097                       # number of write accesses completed
-system.cpu3.num_reads                           99629                       # number of read accesses completed
-system.cpu3.num_writes                          55678                       # number of write accesses completed
-system.cpu4.num_reads                           99475                       # number of read accesses completed
-system.cpu4.num_writes                          55578                       # number of write accesses completed
-system.cpu5.num_reads                          100000                       # number of read accesses completed
-system.cpu5.num_writes                          55526                       # number of write accesses completed
-system.cpu6.num_reads                           99558                       # number of read accesses completed
-system.cpu6.num_writes                          55241                       # number of write accesses completed
-system.cpu7.num_reads                           99313                       # number of read accesses completed
-system.cpu7.num_writes                          55346                       # number of write accesses completed
+system.cpu0.num_reads                           99096                       # number of read accesses completed
+system.cpu0.num_writes                          55531                       # number of write accesses completed
+system.cpu1.num_reads                           99775                       # number of read accesses completed
+system.cpu1.num_writes                          55445                       # number of write accesses completed
+system.cpu2.num_reads                           99195                       # number of read accesses completed
+system.cpu2.num_writes                          55707                       # number of write accesses completed
+system.cpu3.num_reads                           99465                       # number of read accesses completed
+system.cpu3.num_writes                          55386                       # number of write accesses completed
+system.cpu4.num_reads                          100000                       # number of read accesses completed
+system.cpu4.num_writes                          55371                       # number of write accesses completed
+system.cpu5.num_reads                           99596                       # number of read accesses completed
+system.cpu5.num_writes                          55348                       # number of write accesses completed
+system.cpu6.num_reads                           99601                       # number of read accesses completed
+system.cpu6.num_writes                          55337                       # number of write accesses completed
+system.cpu7.num_reads                           99679                       # number of read accesses completed
+system.cpu7.num_writes                          55088                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                 32                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                 319                       # delay histogram for all message
-system.ruby.delayHist::samples                1255488                       # delay histogram for all message
-system.ruby.delayHist::mean                  2.169527                       # delay histogram for all message
-system.ruby.delayHist::stdev                 7.600459                       # delay histogram for all message
-system.ruby.delayHist                    |     1238674     98.66%     98.66% |       10648      0.85%     99.51% |        5547      0.44%     99.95% |         516      0.04%     99.99% |          82      0.01%    100.00% |          21      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                  1255488                       # delay histogram for all message
+system.ruby.delayHist::samples                1258206                       # delay histogram for all message
+system.ruby.delayHist::mean                  2.294932                       # delay histogram for all message
+system.ruby.delayHist::stdev                 7.756260                       # delay histogram for all message
+system.ruby.delayHist                    |     1240255     98.57%     98.57% |       11748      0.93%     99.51% |        5468      0.43%     99.94% |         595      0.05%     99.99% |         125      0.01%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                  1258206                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       625936                      
+system.ruby.outstanding_req_hist::samples       627344                      
 system.ruby.outstanding_req_hist::mean      15.998449                      
-system.ruby.outstanding_req_hist::gmean     15.997183                      
-system.ruby.outstanding_req_hist::stdev      0.125950                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          27      0.00%      0.02% |      625805     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        625936                      
+system.ruby.outstanding_req_hist::gmean     15.997186                      
+system.ruby.outstanding_req_hist::stdev      0.125821                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          29      0.00%      0.02% |      627211     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        627344                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples              625808                      
-system.ruby.latency_hist::mean            1545.142387                      
-system.ruby.latency_hist::gmean           1522.552701                      
-system.ruby.latency_hist::stdev            264.347793                      
-system.ruby.latency_hist                 |          80      0.01%      0.01% |        8131      1.30%      1.31% |      315699     50.45%     51.76% |      277984     44.42%     96.18% |       23716      3.79%     99.97% |         198      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                625808                      
+system.ruby.latency_hist::samples              627216                      
+system.ruby.latency_hist::mean            1563.828817                      
+system.ruby.latency_hist::gmean           1541.754061                      
+system.ruby.latency_hist::stdev            262.502843                      
+system.ruby.latency_hist                 |          74      0.01%      0.01% |        6345      1.01%      1.02% |      297362     47.41%     48.43% |      296923     47.34%     95.77% |       26326      4.20%     99.97% |         186      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                627216                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples         625808                      
-system.ruby.miss_latency_hist::mean       1545.142387                      
-system.ruby.miss_latency_hist::gmean      1522.552701                      
-system.ruby.miss_latency_hist::stdev       264.347793                      
-system.ruby.miss_latency_hist            |          80      0.01%      0.01% |        8131      1.30%      1.31% |      315699     50.45%     51.76% |      277984     44.42%     96.18% |       23716      3.79%     99.97% |         198      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           625808                      
-system.ruby.L1Cache.incomplete_times             8330                      
-system.ruby.Directory.incomplete_times         617475                      
+system.ruby.miss_latency_hist::samples         627216                      
+system.ruby.miss_latency_hist::mean       1563.828817                      
+system.ruby.miss_latency_hist::gmean      1541.754061                      
+system.ruby.miss_latency_hist::stdev       262.502843                      
+system.ruby.miss_latency_hist            |          74      0.01%      0.01% |        6345      1.01%      1.02% |      297362     47.41%     48.43% |      296923     47.34%     95.77% |       26326      4.20%     99.97% |         186      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           627216                      
+system.ruby.L1Cache.incomplete_times             8365                      
+system.ruby.Directory.incomplete_times         618848                      
 system.ruby.l1_cntrl0.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses        78125                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses        78125                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.cacheMemory.demand_misses        78375                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses        78375                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl1.cacheMemory.demand_misses        78092                       # Number of cache demand misses
-system.ruby.l1_cntrl1.cacheMemory.demand_accesses        78092                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.cacheMemory.demand_misses        78728                       # Number of cache demand misses
+system.ruby.l1_cntrl1.cacheMemory.demand_accesses        78728                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl2.cacheMemory.demand_misses        78168                       # Number of cache demand misses
-system.ruby.l1_cntrl2.cacheMemory.demand_accesses        78168                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.cacheMemory.demand_misses        78427                       # Number of cache demand misses
+system.ruby.l1_cntrl2.cacheMemory.demand_accesses        78427                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl3.cacheMemory.demand_misses        78501                       # Number of cache demand misses
-system.ruby.l1_cntrl3.cacheMemory.demand_accesses        78501                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.cacheMemory.demand_misses        78400                       # Number of cache demand misses
+system.ruby.l1_cntrl3.cacheMemory.demand_accesses        78400                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl4.cacheMemory.demand_misses        78224                       # Number of cache demand misses
-system.ruby.l1_cntrl4.cacheMemory.demand_accesses        78224                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.cacheMemory.demand_misses        78248                       # Number of cache demand misses
+system.ruby.l1_cntrl4.cacheMemory.demand_accesses        78248                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl5.cacheMemory.demand_misses        78367                       # Number of cache demand misses
-system.ruby.l1_cntrl5.cacheMemory.demand_accesses        78367                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.cacheMemory.demand_misses        78372                       # Number of cache demand misses
+system.ruby.l1_cntrl5.cacheMemory.demand_accesses        78372                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl6.cacheMemory.demand_misses        78095                       # Number of cache demand misses
-system.ruby.l1_cntrl6.cacheMemory.demand_accesses        78095                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.cacheMemory.demand_misses        78413                       # Number of cache demand misses
+system.ruby.l1_cntrl6.cacheMemory.demand_accesses        78413                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl7.cacheMemory.demand_misses        78258                       # Number of cache demand misses
-system.ruby.l1_cntrl7.cacheMemory.demand_accesses        78258                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.cacheMemory.demand_misses        78273                       # Number of cache demand misses
+system.ruby.l1_cntrl7.cacheMemory.demand_accesses        78273                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.185365                      
-system.ruby.network.routers0.msg_count.Control::2        78125                      
-system.ruby.network.routers0.msg_count.Data::2        77570                      
-system.ruby.network.routers0.msg_count.Response_Data::4        79137                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3        78585                      
-system.ruby.network.routers0.msg_bytes.Control::2       625000                      
-system.ruby.network.routers0.msg_bytes.Data::2      5585040                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4      5697864                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3       628680                      
-system.ruby.network.routers1.percent_links_utilized     5.183506                      
-system.ruby.network.routers1.msg_count.Control::2        78092                      
-system.ruby.network.routers1.msg_count.Data::2        77517                      
-system.ruby.network.routers1.msg_count.Response_Data::4        79134                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3        78560                      
-system.ruby.network.routers1.msg_bytes.Control::2       624736                      
-system.ruby.network.routers1.msg_bytes.Data::2      5581224                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4      5697648                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3       628480                      
-system.ruby.network.routers2.percent_links_utilized     5.188578                      
-system.ruby.network.routers2.msg_count.Control::2        78168                      
-system.ruby.network.routers2.msg_count.Data::2        77620                      
-system.ruby.network.routers2.msg_count.Response_Data::4        79184                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3        78640                      
-system.ruby.network.routers2.msg_bytes.Control::2       625344                      
-system.ruby.network.routers2.msg_bytes.Data::2      5588640                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4      5701248                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3       629120                      
-system.ruby.network.routers3.percent_links_utilized     5.211370                      
-system.ruby.network.routers3.msg_count.Control::2        78501                      
-system.ruby.network.routers3.msg_count.Data::2        77919                      
-system.ruby.network.routers3.msg_count.Response_Data::4        79574                      
-system.ruby.network.routers3.msg_count.Writeback_Control::3        78994                      
-system.ruby.network.routers3.msg_bytes.Control::2       628008                      
-system.ruby.network.routers3.msg_bytes.Data::2      5610168                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4      5729328                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3       631952                      
-system.ruby.network.routers4.percent_links_utilized     5.192410                      
-system.ruby.network.routers4.msg_count.Control::2        78224                      
-system.ruby.network.routers4.msg_count.Data::2        77649                      
-system.ruby.network.routers4.msg_count.Response_Data::4        79271                      
-system.ruby.network.routers4.msg_count.Writeback_Control::3        78698                      
-system.ruby.network.routers4.msg_bytes.Control::2       625792                      
-system.ruby.network.routers4.msg_bytes.Data::2      5590728                      
-system.ruby.network.routers4.msg_bytes.Response_Data::4      5707512                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3       629584                      
-system.ruby.network.routers5.percent_links_utilized     5.202986                      
-system.ruby.network.routers5.msg_count.Control::2        78366                      
-system.ruby.network.routers5.msg_count.Data::2        77813                      
-system.ruby.network.routers5.msg_count.Response_Data::4        79427                      
-system.ruby.network.routers5.msg_count.Writeback_Control::3        78875                      
-system.ruby.network.routers5.msg_bytes.Control::2       626928                      
-system.ruby.network.routers5.msg_bytes.Data::2      5602536                      
-system.ruby.network.routers5.msg_bytes.Response_Data::4      5718744                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3       631000                      
-system.ruby.network.routers6.percent_links_utilized     5.183810                      
-system.ruby.network.routers6.msg_count.Control::2        78095                      
-system.ruby.network.routers6.msg_count.Data::2        77543                      
-system.ruby.network.routers6.msg_count.Response_Data::4        79117                      
-system.ruby.network.routers6.msg_count.Writeback_Control::3        78568                      
-system.ruby.network.routers6.msg_bytes.Control::2       624760                      
-system.ruby.network.routers6.msg_bytes.Data::2      5583096                      
-system.ruby.network.routers6.msg_bytes.Response_Data::4      5696424                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3       628544                      
-system.ruby.network.routers7.percent_links_utilized     5.195587                      
-system.ruby.network.routers7.msg_count.Control::2        78258                      
-system.ruby.network.routers7.msg_count.Data::2        77722                      
-system.ruby.network.routers7.msg_count.Response_Data::4        79294                      
-system.ruby.network.routers7.msg_count.Writeback_Control::3        78760                      
-system.ruby.network.routers7.msg_bytes.Control::2       626064                      
-system.ruby.network.routers7.msg_bytes.Data::2      5595984                      
-system.ruby.network.routers7.msg_bytes.Response_Data::4      5709168                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3       630080                      
-system.ruby.network.routers8.percent_links_utilized    41.047495                      
-system.ruby.network.routers8.msg_count.Control::2       625829                      
-system.ruby.network.routers8.msg_count.Data::2       621353                      
-system.ruby.network.routers8.msg_count.Response_Data::4       617479                      
-system.ruby.network.routers8.msg_count.Writeback_Control::3       629681                      
-system.ruby.network.routers8.msg_bytes.Control::2      5006632                      
-system.ruby.network.routers8.msg_bytes.Data::2     44737416                      
-system.ruby.network.routers8.msg_bytes.Response_Data::4     44458488                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3      5037448                      
-system.ruby.network.routers9.percent_links_utilized     9.176790                      
-system.ruby.network.routers9.msg_count.Control::2       625829                      
-system.ruby.network.routers9.msg_count.Data::2       621353                      
-system.ruby.network.routers9.msg_count.Response_Data::4       625808                      
-system.ruby.network.routers9.msg_count.Writeback_Control::3       629681                      
-system.ruby.network.routers9.msg_bytes.Control::2      5006632                      
-system.ruby.network.routers9.msg_bytes.Data::2     44737416                      
-system.ruby.network.routers9.msg_bytes.Response_Data::4     45058176                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3      5037448                      
-system.ruby.network.msg_count.Control         1877487                      
-system.ruby.network.msg_count.Data            1864059                      
-system.ruby.network.msg_count.Response_Data      1877425                      
-system.ruby.network.msg_count.Writeback_Control      1889042                      
-system.ruby.network.msg_byte.Control         15019896                      
-system.ruby.network.msg_byte.Data           134212248                      
-system.ruby.network.msg_byte.Response_Data    135174600                      
-system.ruby.network.msg_byte.Writeback_Control     15112336                      
-system.ruby.network.routers0.throttle0.link_utilization     5.173099                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4        78122                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        78585                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5624784                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       628680                      
-system.ruby.network.routers0.throttle1.link_utilization     5.197632                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2        78125                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2        77570                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4         1015                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2       625000                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2      5585040                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4        73080                      
-system.ruby.network.routers1.throttle0.link_utilization     5.171087                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4        78091                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3        78560                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4      5622552                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3       628480                      
-system.ruby.network.routers1.throttle1.link_utilization     5.195924                      
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+system.ruby.network.routers4.throttle1.link_utilization     5.134643                      
+system.ruby.network.routers4.throttle1.msg_count.Control::2        78248                      
+system.ruby.network.routers4.throttle1.msg_count.Data::2        77658                      
+system.ruby.network.routers4.throttle1.msg_count.Response_Data::4         1093                      
+system.ruby.network.routers4.throttle1.msg_bytes.Control::2       625984                      
+system.ruby.network.routers4.throttle1.msg_bytes.Data::2      5591376                      
+system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4        78696                      
+system.ruby.network.routers5.throttle0.link_utilization     5.116121                      
+system.ruby.network.routers5.throttle0.msg_count.Response_Data::4        78370                      
+system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3        78838                      
+system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4      5642640                      
+system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3       630704                      
+system.ruby.network.routers5.throttle1.link_utilization     5.140561                      
+system.ruby.network.routers5.throttle1.msg_count.Control::2        78372                      
+system.ruby.network.routers5.throttle1.msg_count.Data::2        77763                      
+system.ruby.network.routers5.throttle1.msg_count.Response_Data::4         1075                      
+system.ruby.network.routers5.throttle1.msg_bytes.Control::2       626976                      
+system.ruby.network.routers5.throttle1.msg_bytes.Data::2      5598936                      
+system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4        77400                      
+system.ruby.network.routers6.throttle0.link_utilization     5.118600                      
+system.ruby.network.routers6.throttle0.msg_count.Response_Data::4        78409                      
+system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3        78867                      
+system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4      5645448                      
+system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3       630936                      
+system.ruby.network.routers6.throttle1.link_utilization     5.142531                      
+system.ruby.network.routers6.throttle1.msg_count.Control::2        78413                      
+system.ruby.network.routers6.throttle1.msg_count.Data::2        77861                      
+system.ruby.network.routers6.throttle1.msg_count.Response_Data::4         1006                      
+system.ruby.network.routers6.throttle1.msg_bytes.Control::2       627304                      
+system.ruby.network.routers6.throttle1.msg_bytes.Data::2      5605992                      
+system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4        72432                      
+system.ruby.network.routers7.throttle0.link_utilization     5.109845                      
+system.ruby.network.routers7.throttle0.msg_count.Response_Data::4        78272                      
+system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3        78758                      
+system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4      5635584                      
+system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3       630064                      
+system.ruby.network.routers7.throttle1.link_utilization     5.135217                      
+system.ruby.network.routers7.throttle1.msg_count.Control::2        78273                      
+system.ruby.network.routers7.throttle1.msg_count.Data::2        77733                      
+system.ruby.network.routers7.throttle1.msg_count.Response_Data::4         1025                      
+system.ruby.network.routers7.throttle1.msg_bytes.Control::2       626184                      
+system.ruby.network.routers7.throttle1.msg_bytes.Data::2      5596776                      
+system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4        73800                      
+system.ruby.network.routers8.throttle0.link_utilization    40.652025                      
+system.ruby.network.routers8.throttle0.msg_count.Control::2       627233                      
+system.ruby.network.routers8.throttle0.msg_count.Data::2       622630                      
+system.ruby.network.routers8.throttle0.msg_bytes.Control::2      5017864                      
+system.ruby.network.routers8.throttle0.msg_bytes.Data::2     44829360                      
+system.ruby.network.routers8.throttle1.link_utilization    40.454718                      
+system.ruby.network.routers8.throttle1.msg_count.Response_Data::4       618852                      
+system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3       630991                      
+system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4     44557344                      
+system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3      5047928                      
+system.ruby.network.routers9.throttle0.link_utilization     5.116473                      
+system.ruby.network.routers9.throttle0.msg_count.Response_Data::4        78373                      
+system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3        78865                      
+system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4      5642856                      
+system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3       630920                      
+system.ruby.network.routers9.throttle1.link_utilization     5.139184                      
+system.ruby.network.routers9.throttle1.msg_count.Response_Data::4        78724                      
+system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3        79187                      
+system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4      5668128                      
+system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3       633496                      
+system.ruby.network.routers9.throttle2.link_utilization     5.119533                      
+system.ruby.network.routers9.throttle2.msg_count.Response_Data::4        78423                      
+system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3        78884                      
+system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4      5646456                      
+system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3       631072                      
+system.ruby.network.routers9.throttle3.link_utilization     5.117843                      
+system.ruby.network.routers9.throttle3.msg_count.Response_Data::4        78399                      
+system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3        78841                      
+system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4      5644728                      
+system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3       630728                      
+system.ruby.network.routers9.throttle4.link_utilization     5.108272                      
+system.ruby.network.routers9.throttle4.msg_count.Response_Data::4        78246                      
+system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3        78751                      
+system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4      5633712                      
+system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3       630008                      
+system.ruby.network.routers9.throttle5.link_utilization     5.116121                      
+system.ruby.network.routers9.throttle5.msg_count.Response_Data::4        78370                      
+system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3        78838                      
+system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4      5642640                      
+system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3       630704                      
+system.ruby.network.routers9.throttle6.link_utilization     5.118600                      
+system.ruby.network.routers9.throttle6.msg_count.Response_Data::4        78409                      
+system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3        78867                      
+system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4      5645448                      
+system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3       630936                      
+system.ruby.network.routers9.throttle7.link_utilization     5.109845                      
+system.ruby.network.routers9.throttle7.msg_count.Response_Data::4        78272                      
+system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3        78758                      
+system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4      5635584                      
+system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3       630064                      
+system.ruby.network.routers9.throttle8.link_utilization    40.652051                      
+system.ruby.network.routers9.throttle8.msg_count.Control::2       627233                      
+system.ruby.network.routers9.throttle8.msg_count.Data::2       622630                      
+system.ruby.network.routers9.throttle8.msg_bytes.Control::2      5017864                      
+system.ruby.network.routers9.throttle8.msg_bytes.Data::2     44829360                      
 system.ruby.delayVCHist.vnet_1::bucket_size            4                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           39                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples        625808                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.264720                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        1.304410                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |      600768     96.00%     96.00% |       18387      2.94%     98.94% |        5734      0.92%     99.85% |         745      0.12%     99.97% |         149      0.02%    100.00% |          19      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total          625808                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples        627216                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.278025                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        1.343597                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |      601064     95.83%     95.83% |       19006      3.03%     98.86% |        6107      0.97%     99.83% |         844      0.13%     99.97% |         158      0.03%     99.99% |          32      0.01%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total          627216                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size           32                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket          319                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples        629680                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         4.062621                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev       10.310093                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |      612866     97.33%     97.33% |       10648      1.69%     99.02% |        5547      0.88%     99.90% |         516      0.08%     99.98% |          82      0.01%    100.00% |          21      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total          629680                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples        630990                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         4.299775                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev       10.492949                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |      613039     97.16%     97.16% |       11748      1.86%     99.02% |        5468      0.87%     99.88% |         595      0.09%     99.98% |         125      0.02%    100.00% |          15      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total          630990                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples           403166                      
-system.ruby.LD.latency_hist::mean         1544.913271                      
-system.ruby.LD.latency_hist::gmean        1522.275613                      
-system.ruby.LD.latency_hist::stdev         264.561950                      
-system.ruby.LD.latency_hist              |          54      0.01%      0.01% |        5301      1.31%      1.33% |      203466     50.47%     51.80% |      178892     44.37%     96.17% |       15319      3.80%     99.97% |         134      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             403166                      
+system.ruby.LD.latency_hist::samples           403846                      
+system.ruby.LD.latency_hist::mean         1564.356052                      
+system.ruby.LD.latency_hist::gmean        1542.244005                      
+system.ruby.LD.latency_hist::stdev         262.678202                      
+system.ruby.LD.latency_hist              |          49      0.01%      0.01% |        4121      1.02%      1.03% |      191073     47.31%     48.35% |      191459     47.41%     95.75% |       17013      4.21%     99.97% |         131      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total             403846                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
-system.ruby.LD.miss_latency_hist::samples       403166                      
-system.ruby.LD.miss_latency_hist::mean    1544.913271                      
-system.ruby.LD.miss_latency_hist::gmean   1522.275613                      
-system.ruby.LD.miss_latency_hist::stdev    264.561950                      
-system.ruby.LD.miss_latency_hist         |          54      0.01%      0.01% |        5301      1.31%      1.33% |      203466     50.47%     51.80% |      178892     44.37%     96.17% |       15319      3.80%     99.97% |         134      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        403166                      
+system.ruby.LD.miss_latency_hist::samples       403846                      
+system.ruby.LD.miss_latency_hist::mean    1564.356052                      
+system.ruby.LD.miss_latency_hist::gmean   1542.244005                      
+system.ruby.LD.miss_latency_hist::stdev    262.678202                      
+system.ruby.LD.miss_latency_hist         |          49      0.01%      0.01% |        4121      1.02%      1.03% |      191073     47.31%     48.35% |      191459     47.41%     95.75% |       17013      4.21%     99.97% |         131      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        403846                      
 system.ruby.ST.latency_hist::bucket_size          512                      
 system.ruby.ST.latency_hist::max_bucket          5119                      
-system.ruby.ST.latency_hist::samples           222642                      
-system.ruby.ST.latency_hist::mean         1545.557276                      
-system.ruby.ST.latency_hist::gmean        1523.054587                      
-system.ruby.ST.latency_hist::stdev         263.959637                      
-system.ruby.ST.latency_hist              |          26      0.01%      0.01% |        2830      1.27%      1.28% |      112233     50.41%     51.69% |       99092     44.51%     96.20% |        8397      3.77%     99.97% |          64      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             222642                      
+system.ruby.ST.latency_hist::samples           223370                      
+system.ruby.ST.latency_hist::mean         1562.875592                      
+system.ruby.ST.latency_hist::gmean        1540.868654                      
+system.ruby.ST.latency_hist::stdev         262.183398                      
+system.ruby.ST.latency_hist              |          25      0.01%      0.01% |        2224      1.00%      1.01% |      106289     47.58%     48.59% |      105464     47.21%     95.81% |        9313      4.17%     99.98% |          55      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total             223370                      
 system.ruby.ST.miss_latency_hist::bucket_size          512                      
 system.ruby.ST.miss_latency_hist::max_bucket         5119                      
-system.ruby.ST.miss_latency_hist::samples       222642                      
-system.ruby.ST.miss_latency_hist::mean    1545.557276                      
-system.ruby.ST.miss_latency_hist::gmean   1523.054587                      
-system.ruby.ST.miss_latency_hist::stdev    263.959637                      
-system.ruby.ST.miss_latency_hist         |          26      0.01%      0.01% |        2830      1.27%      1.28% |      112233     50.41%     51.69% |       99092     44.51%     96.20% |        8397      3.77%     99.97% |          64      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        222642                      
+system.ruby.ST.miss_latency_hist::samples       223370                      
+system.ruby.ST.miss_latency_hist::mean    1562.875592                      
+system.ruby.ST.miss_latency_hist::gmean   1540.868654                      
+system.ruby.ST.miss_latency_hist::stdev    262.183398                      
+system.ruby.ST.miss_latency_hist         |          25      0.01%      0.01% |        2224      1.00%      1.01% |      106289     47.58%     48.59% |      105464     47.21%     95.81% |        9313      4.17%     99.98% |          55      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        223370                      
 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size          256                      
 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket         2559                      
-system.ruby.L1Cache.miss_mach_latency_hist::samples         8330                      
-system.ruby.L1Cache.miss_mach_latency_hist::mean  1434.603121                      
-system.ruby.L1Cache.miss_mach_latency_hist::gmean  1410.421846                      
-system.ruby.L1Cache.miss_mach_latency_hist::stdev   264.603090                      
-system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |           1      0.01%      0.01% |           5      0.06%      0.07% |         356      4.27%      4.35% |        2133     25.61%     29.95% |        3056     36.69%     66.64% |        1973     23.69%     90.32% |         656      7.88%     98.20% |         135      1.62%     99.82% |          15      0.18%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total         8330                      
+system.ruby.L1Cache.miss_mach_latency_hist::samples         8365                      
+system.ruby.L1Cache.miss_mach_latency_hist::mean  1451.964973                      
+system.ruby.L1Cache.miss_mach_latency_hist::gmean  1428.123132                      
+system.ruby.L1Cache.miss_mach_latency_hist::stdev   264.328285                      
+system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           7      0.08%      0.08% |         311      3.72%      3.80% |        1935     23.13%     26.93% |        3130     37.42%     64.35% |        2091     25.00%     89.35% |         726      8.68%     98.03% |         146      1.75%     99.77% |          19      0.23%    100.00%
+system.ruby.L1Cache.miss_mach_latency_hist::total         8365                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.Directory.miss_mach_latency_hist::samples       617478                      
-system.ruby.Directory.miss_mach_latency_hist::mean  1546.633602                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  1524.124795                      
-system.ruby.Directory.miss_mach_latency_hist::stdev   264.028380                      
-system.ruby.Directory.miss_mach_latency_hist |          79      0.01%      0.01% |        7770      1.26%      1.27% |      310510     50.29%     51.56% |      275355     44.59%     96.15% |       23566      3.82%     99.97% |         198      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       617478                      
+system.ruby.Directory.miss_mach_latency_hist::samples       618851                      
+system.ruby.Directory.miss_mach_latency_hist::mean  1565.340878                      
+system.ruby.Directory.miss_mach_latency_hist::gmean  1543.350381                      
+system.ruby.Directory.miss_mach_latency_hist::stdev   262.151529                      
+system.ruby.Directory.miss_mach_latency_hist |          74      0.01%      0.01% |        6027      0.97%      0.99% |      292297     47.23%     48.22% |      294106     47.52%     95.74% |       26161      4.23%     99.97% |         186      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       618851                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            3                      
@@ -677,82 +677,82 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion |
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            3                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size          256                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket         2559                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples         5325                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1437.811643                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean  1413.385470                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   266.536201                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           1      0.02%      0.02% |           2      0.04%      0.06% |         221      4.15%      4.21% |        1362     25.58%     29.78% |        1962     36.85%     66.63% |        1238     23.25%     89.88% |         433      8.13%     98.01% |          97      1.82%     99.83% |           9      0.17%    100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         5325                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples         5351                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1448.396001                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean  1424.162973                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   266.250656                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           4      0.07%      0.07% |         221      4.13%      4.20% |        1256     23.47%     27.68% |        2002     37.41%     65.09% |        1297     24.24%     89.33% |         460      8.60%     97.93% |          99      1.85%     99.78% |          12      0.22%    100.00%
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         5351                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       397841                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1546.346799                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  1523.788586                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   264.241520                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |          53      0.01%      0.01% |        5078      1.28%      1.29% |      200142     50.31%     51.60% |      177221     44.55%     96.14% |       15213      3.82%     99.97% |         134      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       397841                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       398495                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1565.913166                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  1543.894470                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   262.281631                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |          49      0.01%      0.01% |        3896      0.98%      0.99% |      187815     47.13%     48.12% |      189702     47.60%     95.73% |       16902      4.24%     99.97% |         131      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total       398495                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          256                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket         2559                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples         3005                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1428.917471                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean  1405.185421                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   261.089644                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      0.10%      0.10% |         135      4.49%      4.59% |         771     25.66%     30.25% |        1094     36.41%     66.66% |         735     24.46%     91.11% |         223      7.42%     98.54% |          38      1.26%     99.80% |           6      0.20%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         3005                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples         3014                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1458.301261                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean  1435.181075                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   260.804046                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      0.10%      0.10% |          90      2.99%      3.09% |         679     22.53%     25.61% |        1128     37.43%     63.04% |         794     26.34%     89.38% |         266      8.83%     98.21% |          47      1.56%     99.77% |           7      0.23%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         3014                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       219637                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1547.153103                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  1524.733978                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   263.641675                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          26      0.01%      0.01% |        2692      1.23%      1.24% |      110368     50.25%     51.49% |       98134     44.68%     96.17% |        8353      3.80%     99.97% |          64      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total       219637                      
-system.ruby.Directory_Controller.GETX          689360      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX          617467      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX_NotOwner         3886      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       617479      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       617466      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX        617498      0.00%      0.00%
-system.ruby.Directory_Controller.M.GETX          8330      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX        617467      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX_NotOwner         3886      0.00%      0.00%
-system.ruby.Directory_Controller.IM.GETX        63241      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       617479      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETX          291      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack       617466      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load      |       50298     12.48%     12.48% |       50313     12.48%     24.95% |       50604     12.55%     37.51% |       50559     12.54%     50.05% |       50335     12.48%     62.53% |       50365     12.49%     75.02% |       50340     12.49%     87.51% |       50369     12.49%    100.00%
-system.ruby.L1Cache_Controller.Load::total       403183                      
-system.ruby.L1Cache_Controller.Store     |       27827     12.50%     12.50% |       27779     12.48%     24.97% |       27564     12.38%     37.36% |       27942     12.55%     49.91% |       27889     12.53%     62.43% |       28002     12.58%     75.01% |       27755     12.47%     87.47% |       27889     12.53%    100.00%
-system.ruby.L1Cache_Controller.Store::total       222647                      
-system.ruby.L1Cache_Controller.Data      |       78122     12.48%     12.48% |       78091     12.48%     24.96% |       78164     12.49%     37.45% |       78497     12.54%     50.00% |       78221     12.50%     62.49% |       78365     12.52%     75.02% |       78092     12.48%     87.50% |       78256     12.50%    100.00%
-system.ruby.L1Cache_Controller.Data::total       625808                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |        1015     12.18%     12.18% |        1043     12.52%     24.71% |        1020     12.24%     36.95% |        1077     12.93%     49.88% |        1050     12.61%     62.48% |        1062     12.75%     75.23% |        1025     12.30%     87.54% |        1038     12.46%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         8330                      
-system.ruby.L1Cache_Controller.Replacement |       78121     12.48%     12.48% |       78088     12.48%     24.96% |       78164     12.49%     37.45% |       78497     12.54%     50.00% |       78220     12.50%     62.49% |       78363     12.52%     75.02% |       78091     12.48%     87.50% |       78254     12.50%    100.00%
-system.ruby.L1Cache_Controller.Replacement::total       625798                      
-system.ruby.L1Cache_Controller.Writeback_Ack |       77106     12.49%     12.49% |       77045     12.48%     24.97% |       77144     12.49%     37.46% |       77418     12.54%     50.00% |       77169     12.50%     62.49% |       77300     12.52%     75.01% |       77066     12.48%     87.49% |       77216     12.51%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total       617464                      
-system.ruby.L1Cache_Controller.Writeback_Nack |         464     11.94%     11.94% |         472     12.15%     24.09% |         476     12.25%     36.34% |         499     12.84%     49.18% |         479     12.33%     61.50% |         513     13.20%     74.70% |         477     12.27%     86.98% |         506     13.02%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total         3886                      
-system.ruby.L1Cache_Controller.I.Load    |       50298     12.48%     12.48% |       50313     12.48%     24.95% |       50604     12.55%     37.51% |       50559     12.54%     50.05% |       50335     12.48%     62.53% |       50365     12.49%     75.02% |       50340     12.49%     87.51% |       50369     12.49%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       403183                      
-system.ruby.L1Cache_Controller.I.Store   |       27827     12.50%     12.50% |       27779     12.48%     24.97% |       27564     12.38%     37.36% |       27942     12.55%     49.91% |       27889     12.53%     62.43% |       28002     12.58%     75.01% |       27755     12.47%     87.47% |       27889     12.53%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       222647                      
-system.ruby.L1Cache_Controller.I.Replacement |         551     12.40%     12.40% |         571     12.85%     25.25% |         544     12.24%     37.49% |         578     13.01%     50.50% |         571     12.85%     63.34% |         549     12.35%     75.70% |         548     12.33%     88.03% |         532     11.97%    100.00%
-system.ruby.L1Cache_Controller.I.Replacement::total         4444                      
-system.ruby.L1Cache_Controller.II.Writeback_Nack |         464     11.94%     11.94% |         472     12.15%     24.09% |         476     12.25%     36.34% |         499     12.84%     49.18% |         479     12.33%     61.50% |         513     13.20%     74.70% |         477     12.27%     86.98% |         506     13.02%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total         3886                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |         551     12.40%     12.40% |         571     12.85%     25.25% |         544     12.24%     37.49% |         578     13.01%     50.50% |         571     12.85%     63.34% |         549     12.35%     75.70% |         548     12.33%     88.03% |         532     11.97%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total         4444                      
-system.ruby.L1Cache_Controller.M.Replacement |       77570     12.48%     12.48% |       77517     12.48%     24.96% |       77620     12.49%     37.45% |       77919     12.54%     49.99% |       77649     12.50%     62.49% |       77814     12.52%     75.01% |       77543     12.48%     87.49% |       77722     12.51%    100.00%
-system.ruby.L1Cache_Controller.M.Replacement::total       621354                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETX |         464     11.94%     11.94% |         472     12.15%     24.09% |         476     12.25%     36.34% |         499     12.84%     49.18% |         479     12.33%     61.50% |         513     13.20%     74.70% |         477     12.27%     86.98% |         506     13.02%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         3886                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack |       77106     12.49%     12.49% |       77045     12.48%     24.97% |       77144     12.49%     37.46% |       77418     12.54%     50.00% |       77169     12.50%     62.49% |       77300     12.52%     75.01% |       77066     12.48%     87.49% |       77216     12.51%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       617464                      
-system.ruby.L1Cache_Controller.IS.Data   |       50296     12.48%     12.48% |       50312     12.48%     24.95% |       50601     12.55%     37.51% |       50556     12.54%     50.05% |       50332     12.48%     62.53% |       50363     12.49%     75.02% |       50339     12.49%     87.51% |       50367     12.49%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total       403166                      
-system.ruby.L1Cache_Controller.IM.Data   |       27826     12.50%     12.50% |       27779     12.48%     24.98% |       27563     12.38%     37.36% |       27941     12.55%     49.90% |       27889     12.53%     62.43% |       28002     12.58%     75.01% |       27753     12.47%     87.47% |       27889     12.53%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total       222642                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       220356                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1564.305946                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  1542.366929                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   261.913507                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          25      0.01%      0.01% |        2131      0.97%      0.98% |      104482     47.42%     48.39% |      104404     47.38%     95.77% |        9259      4.20%     99.98% |          55      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total       220356                      
+system.ruby.Directory_Controller.GETX          692466      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX          618836      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX_NotOwner         3793      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       618852      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       618834      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX        618868      0.00%      0.00%
+system.ruby.Directory_Controller.M.GETX          8365      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX        618836      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX_NotOwner         3793      0.00%      0.00%
+system.ruby.Directory_Controller.IM.GETX        64870      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       618852      0.00%      0.00%
+system.ruby.Directory_Controller.MI.GETX          363      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack       618834      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load      |       50369     12.47%     12.47% |       50818     12.58%     25.06% |       50345     12.47%     37.52% |       50466     12.50%     50.02% |       50330     12.46%     62.48% |       50594     12.53%     75.01% |       50513     12.51%     87.51% |       50423     12.49%    100.00%
+system.ruby.L1Cache_Controller.Load::total       403858                      
+system.ruby.L1Cache_Controller.Store     |       28006     12.54%     12.54% |       27910     12.49%     25.03% |       28082     12.57%     37.60% |       27934     12.51%     50.11% |       27918     12.50%     62.61% |       27778     12.44%     75.04% |       27900     12.49%     87.53% |       27850     12.47%    100.00%
+system.ruby.L1Cache_Controller.Store::total       223378                      
+system.ruby.L1Cache_Controller.Data      |       78373     12.50%     12.50% |       78724     12.55%     25.05% |       78423     12.50%     37.55% |       78399     12.50%     50.05% |       78246     12.48%     62.52% |       78370     12.49%     75.02% |       78409     12.50%     87.52% |       78272     12.48%    100.00%
+system.ruby.L1Cache_Controller.Data::total       627216                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |        1063     12.71%     12.71% |        1045     12.49%     25.20% |        1039     12.42%     37.62% |        1019     12.18%     49.80% |        1093     13.07%     62.87% |        1075     12.85%     75.72% |        1006     12.03%     87.75% |        1025     12.25%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         8365                      
+system.ruby.L1Cache_Controller.Replacement |       78371     12.50%     12.50% |       78724     12.55%     25.05% |       78423     12.50%     37.55% |       78396     12.50%     50.05% |       78244     12.48%     62.52% |       78368     12.49%     75.02% |       78409     12.50%     87.52% |       78269     12.48%    100.00%
+system.ruby.L1Cache_Controller.Replacement::total       627204                      
+system.ruby.L1Cache_Controller.Writeback_Ack |       77308     12.49%     12.49% |       77675     12.55%     25.04% |       77381     12.50%     37.55% |       77377     12.50%     50.05% |       77151     12.47%     62.52% |       77293     12.49%     75.01% |       77403     12.51%     87.52% |       77244     12.48%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total       618832                      
+system.ruby.L1Cache_Controller.Writeback_Nack |         494     13.02%     13.02% |         467     12.31%     25.34% |         463     12.21%     37.54% |         445     11.73%     49.27% |         507     13.37%     62.64% |         470     12.39%     75.03% |         458     12.07%     87.11% |         489     12.89%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total         3793                      
+system.ruby.L1Cache_Controller.I.Load    |       50369     12.47%     12.47% |       50818     12.58%     25.06% |       50345     12.47%     37.52% |       50466     12.50%     50.02% |       50330     12.46%     62.48% |       50594     12.53%     75.01% |       50513     12.51%     87.51% |       50423     12.49%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       403858                      
+system.ruby.L1Cache_Controller.I.Store   |       28006     12.54%     12.54% |       27910     12.49%     25.03% |       28082     12.57%     37.60% |       27934     12.51%     50.11% |       27918     12.50%     62.61% |       27778     12.44%     75.04% |       27900     12.49%     87.53% |       27850     12.47%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       223378                      
+system.ruby.L1Cache_Controller.I.Replacement |         569     12.45%     12.45% |         578     12.64%     25.09% |         576     12.60%     37.69% |         574     12.55%     50.24% |         586     12.82%     63.06% |         605     13.23%     76.29% |         548     11.99%     88.28% |         536     11.72%    100.00%
+system.ruby.L1Cache_Controller.I.Replacement::total         4572                      
+system.ruby.L1Cache_Controller.II.Writeback_Nack |         494     13.02%     13.02% |         467     12.31%     25.34% |         463     12.21%     37.54% |         445     11.73%     49.27% |         507     13.37%     62.64% |         470     12.39%     75.03% |         458     12.07%     87.11% |         489     12.89%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total         3793                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |         569     12.45%     12.45% |         578     12.64%     25.09% |         576     12.60%     37.69% |         574     12.55%     50.24% |         586     12.82%     63.06% |         605     13.23%     76.29% |         548     11.99%     88.28% |         536     11.72%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total         4572                      
+system.ruby.L1Cache_Controller.M.Replacement |       77802     12.50%     12.50% |       78146     12.55%     25.05% |       77847     12.50%     37.55% |       77822     12.50%     50.05% |       77658     12.47%     62.52% |       77763     12.49%     75.01% |       77861     12.51%     87.52% |       77733     12.48%    100.00%
+system.ruby.L1Cache_Controller.M.Replacement::total       622632                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETX |         494     13.02%     13.02% |         467     12.31%     25.34% |         463     12.21%     37.54% |         445     11.73%     49.27% |         507     13.37%     62.64% |         470     12.39%     75.03% |         458     12.07%     87.11% |         489     12.89%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         3793                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack |       77308     12.49%     12.49% |       77675     12.55%     25.04% |       77381     12.50%     37.55% |       77377     12.50%     50.05% |       77151     12.47%     62.52% |       77293     12.49%     75.01% |       77403     12.51%     87.52% |       77244     12.48%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       618832                      
+system.ruby.L1Cache_Controller.IS.Data   |       50369     12.47%     12.47% |       50815     12.58%     25.06% |       50341     12.47%     37.52% |       50465     12.50%     50.02% |       50329     12.46%     62.48% |       50593     12.53%     75.01% |       50512     12.51%     87.51% |       50422     12.49%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total       403846                      
+system.ruby.L1Cache_Controller.IM.Data   |       28004     12.54%     12.54% |       27909     12.49%     25.03% |       28082     12.57%     37.60% |       27934     12.51%     50.11% |       27917     12.50%     62.61% |       27777     12.44%     75.04% |       27897     12.49%     87.53% |       27850     12.47%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total       223370                      
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index c01cc2902..96f88f923 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1809 +1,1817 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000790                       # Number of seconds simulated
-sim_ticks                                   789792500                       # Number of ticks simulated
-final_tick                                  789792500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000889                       # Number of seconds simulated
+sim_ticks                                   888991000                       # Number of ticks simulated
+final_tick                                  888991000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              129975147                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221936                       # Number of bytes of host memory used
-host_seconds                                     6.08                       # Real time elapsed on the host
+host_tick_rate                              170326912                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278304                       # Number of bytes of host memory used
+host_seconds                                     5.22                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 78179                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 78681                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 79146                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 76465                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 76157                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 75918                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 79229                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 81414                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               625189                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       393152                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5414                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5436                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5494                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5519                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5358                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5458                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5447                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5462                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            436740                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11021                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  11082                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10980                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10945                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11015                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10874                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  10980                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87862                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6143                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5414                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5436                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5494                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5519                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5358                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5458                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5447                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5462                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                49731                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                 98986759                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                 99622369                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                100211131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                 96816569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                 96426593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                 96123982                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                100316222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                103082772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               791586398                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         497791509                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                 6854965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                 6882820                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                 6956257                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                 6987911                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                 6784060                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                 6910676                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                 6896748                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                 6915741                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              552980688                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         497791509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               105841724                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               106505190                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               107167389                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               103804480                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               103210653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               103034658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               107212970                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               109998512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1344567086                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 77301                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 77008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 78427                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 77571                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 81605                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 77234                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 80454                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 78765                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               628365                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       396032                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5354                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5486                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5463                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5457                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5464                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5585                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5519                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5444                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            439804                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10773                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10795                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  11043                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  11171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10895                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10977                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87447                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6188                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5354                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5486                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5463                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5457                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5585                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5519                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5444                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49960                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                 86953636                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                 86624049                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                 88220241                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                 87257351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                 91795080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                 86878270                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                 90500354                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                 88600447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               706829428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         445484825                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                 6022558                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                 6171041                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                 6145169                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                 6138420                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                 6146294                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                 6282403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                 6208162                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                 6123797                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              494722669                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         445484825                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0                92976194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1                92795090                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2                94365410                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3                93395771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4                97941374                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5                93160673                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6                96708516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7                94724244                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1201552097                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                           99211                       # number of read accesses completed
-system.cpu0.num_writes                          54990                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22470                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             393.865816                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13332                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22858                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.583253                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99131                       # number of read accesses completed
+system.cpu0.num_writes                          55164                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22535                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             395.025918                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13450                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22939                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.586338                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      393.865816                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.769269                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.769269                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          352                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              337265                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             337265                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8594                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8594                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1143                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1143                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9737                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9737                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9737                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9737                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36367                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36367                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           24030                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          24030                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60397                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60397                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60397                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60397                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0   1097985534                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total   1097985534                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0   1003527320                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total   1003527320                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   2101512854                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   2101512854                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   2101512854                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   2101512854                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          44961                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         44961                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25173                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25173                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70134                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70134                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70134                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70134                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.808857                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.808857                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954594                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.954594                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.861166                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.861166                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.861166                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.861166                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs      1144726                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      395.025918                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.771535                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.771535                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          341                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.789062                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              338659                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             338659                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8591                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8591                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1192                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1192                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9783                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9783                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9783                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9783                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36665                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36665                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23983                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23983                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60648                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60648                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60648                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60648                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0   1205183022                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total   1205183022                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0   1064148669                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total   1064148669                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   2269331691                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   2269331691                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   2269331691                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   2269331691                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45256                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45256                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25175                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25175                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70431                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70431                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70431                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70431                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.810169                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.810169                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952651                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.952651                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.861098                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.861098                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.861098                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.861098                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs      1129963                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               61078                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               56549                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    18.742035                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    19.982016                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9946                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9946                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36367                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36367                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        24030                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        24030                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60397                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60397                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60397                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60397                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9956                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9956                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5416                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5416                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15372                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15372                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   1042449014                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total   1042449014                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    966947420                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    966947420                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   2009396434                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   2009396434                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   2009396434                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   2009396434                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    778948863                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    778948863                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   2127994240                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   2127994240                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2906943103                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2906943103                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.808857                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.808857                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954594                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954594                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.861166                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.861166                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.861166                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.861166                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918                       # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks           9979                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9979                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36665                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36665                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23983                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23983                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60648                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60648                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60648                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60648                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9718                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9718                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5355                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5355                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15073                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15073                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   1168518022                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total   1168518022                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0   1040166669                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total   1040166669                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   2208684691                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   2208684691                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   2208684691                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   2208684691                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    789521900                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    789521900                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1493953369                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1493953369                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2283475269                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2283475269                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.810169                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.810169                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952651                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952651                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.861098                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.861098                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.861098                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.861098                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                          100000                       # number of read accesses completed
-system.cpu1.num_writes                          55318                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22177                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             393.980771                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13598                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22566                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.602588                       # Average number of references to valid blocks.
+system.cpu1.num_reads                           99860                       # number of read accesses completed
+system.cpu1.num_writes                          55211                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22541                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             395.711444                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13500                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22934                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.588646                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      393.980771                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.769494                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.769494                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          357                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              338430                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             338430                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8884                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8884                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1068                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1068                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9952                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9952                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9952                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9952                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36538                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36538                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23930                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23930                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60468                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60468                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60468                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60468                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1   1108002821                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total   1108002821                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    993849096                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    993849096                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   2101851917                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   2101851917                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   2101851917                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   2101851917                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45422                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45422                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         24998                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        24998                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70420                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70420                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70420                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70420                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.804412                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.804412                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.957277                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.957277                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.858677                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.858677                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.858677                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.858677                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs      1147241                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      395.711444                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.772874                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.772874                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          338                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              338432                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             338432                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8752                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8752                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1139                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1139                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9891                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9891                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9891                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9891                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36537                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36537                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23971                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23971                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60508                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60508                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60508                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60508                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1   1195916774                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total   1195916774                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1   1059745891                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total   1059745891                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   2255662665                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   2255662665                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   2255662665                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   2255662665                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45289                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45289                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         25110                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        25110                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70399                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70399                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70399                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70399                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.806752                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.806752                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954640                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954640                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.859501                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.859501                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.859501                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.859501                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs      1120827                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               61428                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               56192                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    18.676190                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    19.946380                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9780                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9780                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36538                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36538                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23930                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23930                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60468                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60468                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60468                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60468                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1        10010                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total        10010                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5438                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5438                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15448                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15448                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   1052180887                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total   1052180887                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    957433148                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    957433148                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   2009614035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   2009614035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   2009614035                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   2009614035                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    780874824                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    780874824                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   2141613646                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   2141613646                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2922488470                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2922488470                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.804412                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.804412                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.957277                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.957277                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858677                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.858677                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858677                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.858677                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394                       # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks           9897                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9897                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36537                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36537                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23971                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23971                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60508                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60508                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60508                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60508                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9744                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9744                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5487                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5487                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15231                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15231                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   1159382774                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total   1159382774                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1   1035775891                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total   1035775891                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   2195158665                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   2195158665                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   2195158665                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   2195158665                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    792485431                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    792485431                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1532713252                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1532713252                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2325198683                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2325198683                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.806752                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.806752                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954640                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954640                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.859501                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.859501                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.859501                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.859501                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99906                       # number of read accesses completed
-system.cpu2.num_writes                          55186                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22429                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             394.168243                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13360                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22814                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.585605                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99820                       # number of read accesses completed
+system.cpu2.num_writes                          54950                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22307                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             395.344704                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13648                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22708                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.601022                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      394.168243                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.769860                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.769860                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          385                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          348                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.751953                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              338029                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             338029                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8660                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8660                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1124                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1124                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9784                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9784                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9784                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9784                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36507                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36507                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           24000                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          24000                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60507                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60507                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60507                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60507                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2   1106428919                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total   1106428919                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2   1000960978                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total   1000960978                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   2107389897                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   2107389897                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   2107389897                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   2107389897                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45167                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45167                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25124                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25124                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70291                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70291                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70291                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70291                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.808267                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.808267                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955262                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.955262                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.860807                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.860807                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.860807                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.860807                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs      1143492                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      395.344704                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.772158                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.772158                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          349                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              339436                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             339436                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8860                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8860                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1133                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1133                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9993                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9993                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9993                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9993                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36664                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36664                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23971                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23971                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60635                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60635                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60635                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60635                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2   1194013761                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total   1194013761                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2   1064419870                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total   1064419870                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   2258433631                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   2258433631                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   2258433631                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   2258433631                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45524                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45524                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25104                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25104                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70628                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70628                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70628                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70628                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805377                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.805377                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954868                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.954868                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.858512                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.858512                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.858512                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.858512                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs      1131174                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               61259                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               56579                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    18.666514                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    19.992824                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9834                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9834                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36507                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36507                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24000                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        24000                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60507                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60507                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60507                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60507                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9899                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9899                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5496                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5496                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15395                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15395                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   1050702877                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total   1050702877                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    964435030                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    964435030                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   2015137907                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   2015137907                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   2015137907                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   2015137907                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    774345338                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    774345338                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   2129438676                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   2129438676                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2903784014                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2903784014                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.808267                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.808267                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955262                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955262                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860807                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.860807                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860807                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.860807                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326                       # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks           9745                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9745                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36664                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36664                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23971                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23971                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60635                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60635                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60635                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60635                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9885                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9885                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5464                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5464                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15349                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15349                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   1157350761                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total   1157350761                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2   1040448870                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total   1040448870                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   2197799631                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   2197799631                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   2197799631                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   2197799631                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    800475880                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    800475880                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1507844825                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1507844825                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2308320705                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2308320705                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805377                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805377                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954868                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954868                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858512                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.858512                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858512                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.858512                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99687                       # number of read accesses completed
-system.cpu3.num_writes                          54914                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22514                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             394.486423                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13398                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22905                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.584938                       # Average number of references to valid blocks.
+system.cpu3.num_reads                           99181                       # number of read accesses completed
+system.cpu3.num_writes                          54913                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22385                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             394.599023                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13320                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22779                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.584749                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      394.486423                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.770481                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.770481                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          351                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              337490                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             337490                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8775                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8775                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1091                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1091                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9866                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9866                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9866                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9866                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36393                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36393                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23929                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23929                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60322                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60322                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60322                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60322                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3   1101223942                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total   1101223942                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    999641040                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    999641040                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   2100864982                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   2100864982                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   2100864982                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   2100864982                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45168                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45168                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         25020                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        25020                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70188                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70188                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70188                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70188                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.805725                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.805725                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.956395                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.956395                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.859435                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.859435                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.859435                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.859435                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs      1140042                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      394.599023                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.770701                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.770701                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          338                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           56                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              337671                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             337671                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8526                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8526                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1172                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1172                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9698                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9698                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9698                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9698                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36662                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36662                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23851                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23851                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60513                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60513                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60513                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60513                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3   1194465114                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total   1194465114                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3   1056306776                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total   1056306776                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   2250771890                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   2250771890                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   2250771890                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   2250771890                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45188                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45188                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25023                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25023                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70211                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70211                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70211                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70211                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.811322                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.811322                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953163                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.953163                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.861873                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.861873                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.861873                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.861873                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs      1130263                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               60968                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               56535                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    18.699022                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    19.992270                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9981                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9981                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36393                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36393                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23929                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23929                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60322                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60322                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60322                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60322                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9906                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9906                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5522                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5522                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15428                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15428                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   1045674368                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total   1045674368                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    963227618                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    963227618                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   2008901986                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   2008901986                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   2008901986                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   2008901986                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    776644993                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    776644993                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   2134037166                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   2134037166                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2910682159                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2910682159                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.805725                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.805725                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.956395                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.956395                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.859435                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.859435                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.859435                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.859435                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613                       # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks           9719                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9719                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36662                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36662                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23851                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23851                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60513                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60513                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60513                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60513                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9988                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9988                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5458                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5458                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15446                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15446                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   1157803114                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total   1157803114                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3   1032457776                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total   1032457776                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   2190260890                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   2190260890                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   2190260890                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   2190260890                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    807637161                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    807637161                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1532365329                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1532365329                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2340002490                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2340002490                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.811322                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.811322                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953163                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953163                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.861873                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.861873                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.861873                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.861873                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99646                       # number of read accesses completed
-system.cpu4.num_writes                          55076                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22475                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             394.666578                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13432                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22873                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.587243                       # Average number of references to valid blocks.
+system.cpu4.num_reads                           99531                       # number of read accesses completed
+system.cpu4.num_writes                          55217                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22414                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             393.784167                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13493                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22803                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.591720                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      394.666578                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.770833                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.770833                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          352                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              338590                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             338590                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8683                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8683                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1163                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1163                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9846                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9846                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9846                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9846                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36657                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36657                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23918                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23918                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60575                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60575                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60575                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60575                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4   1108449638                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total   1108449638                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    999797609                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    999797609                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   2108247247                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   2108247247                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   2108247247                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   2108247247                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45340                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45340                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         25081                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        25081                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70421                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70421                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70421                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70421                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.808491                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.808491                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953630                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.953630                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.860184                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.860184                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.860184                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.860184                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs      1151337                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      393.784167                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.769110                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.769110                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          342                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           47                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              337660                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             337660                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8661                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8661                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1197                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1197                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                9858                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               9858                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               9858                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              9858                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36381                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36381                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           24008                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          24008                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60389                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60389                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60389                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60389                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4   1185615268                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total   1185615268                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4   1062060825                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total   1062060825                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   2247676093                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   2247676093                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   2247676093                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   2247676093                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45042                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45042                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25205                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25205                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70247                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70247                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70247                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70247                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.807713                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.807713                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952509                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.952509                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.859667                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.859667                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.859667                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.859667                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs      1133314                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               61602                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               56676                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    18.689929                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    19.996365                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9802                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9802                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36657                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36657                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23918                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23918                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60575                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60575                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60575                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60575                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9982                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9982                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5360                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5360                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15342                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15342                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   1052462662                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total   1052462662                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    963409159                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    963409159                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   2015871821                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   2015871821                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   2015871821                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   2015871821                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    780487806                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    780487806                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   2113182760                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   2113182760                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2893670566                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2893670566                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.808491                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.808491                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953630                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953630                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860184                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.860184                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860184                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.860184                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369                       # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks           9784                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9784                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36381                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36381                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24008                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        24008                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60389                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60389                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60389                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60389                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4        10053                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total        10053                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5464                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5464                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15517                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15517                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   1149238268                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total   1149238268                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4   1038052825                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total   1038052825                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   2187291093                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   2187291093                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   2187291093                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   2187291093                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    813079130                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    813079130                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1517158795                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1517158795                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2330237925                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2330237925                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.807713                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.807713                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952509                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952509                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.859667                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.859667                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.859667                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.859667                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99659                       # number of read accesses completed
-system.cpu5.num_writes                          54989                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22353                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             392.762821                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13360                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22726                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.587873                       # Average number of references to valid blocks.
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          55296                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22532                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             395.145821                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13497                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22906                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.589234                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      392.762821                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.767115                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.767115                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          373                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          325                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           48                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.728516                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              337942                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             337942                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8666                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8666                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1136                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1136                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9802                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9802                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9802                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9802                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36641                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36641                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23834                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23834                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60475                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60475                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60475                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60475                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5   1106472248                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total   1106472248                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    994607245                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    994607245                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   2101079493                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   2101079493                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   2101079493                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   2101079493                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          45307                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         45307                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         24970                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        24970                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70277                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70277                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70277                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70277                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808727                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.808727                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954505                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.954505                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.860523                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.860523                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.860523                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.860523                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs      1144155                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      395.145821                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.771769                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.771769                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          374                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          335                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.730469                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              337979                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             337979                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8739                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8739                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1202                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1202                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9941                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9941                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9941                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9941                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36450                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36450                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23918                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23918                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60368                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60368                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60368                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60368                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5   1193062548                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total   1193062548                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5   1058341769                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total   1058341769                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   2251404317                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   2251404317                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   2251404317                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   2251404317                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45189                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45189                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25120                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25120                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70309                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70309                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70309                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70309                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806612                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.806612                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952150                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.952150                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.858610                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.858610                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.858610                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.858610                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs      1121436                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               61191                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               56172                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    18.698093                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    19.964324                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9829                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9829                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36641                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36641                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23834                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23834                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60475                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60475                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60475                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60475                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9934                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9934                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5460                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5460                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15394                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15394                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   1050521774                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total   1050521774                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    958365245                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    958365245                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   2008887019                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   2008887019                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   2008887019                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   2008887019                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    778256892                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    778256892                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   2141596587                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   2141596587                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2919853479                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2919853479                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808727                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808727                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954505                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954505                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860523                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.860523                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860523                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.860523                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523                       # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks           9981                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9981                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36450                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36450                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23918                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23918                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60368                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60368                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60368                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60368                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9842                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9842                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5587                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5587                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15429                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15429                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   1156614548                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total   1156614548                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5   1034424769                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total   1034424769                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   2191039317                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   2191039317                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   2191039317                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   2191039317                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    798681353                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    798681353                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1559836698                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1559836698                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2358518051                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2358518051                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806612                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806612                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952150                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952150                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858610                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.858610                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858610                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.858610                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99691                       # number of read accesses completed
-system.cpu6.num_writes                          55108                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22433                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             394.732703                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13465                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22813                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.590234                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99879                       # number of read accesses completed
+system.cpu6.num_writes                          55426                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22371                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             395.326557                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13543                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22792                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.594200                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      394.732703                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.770962                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.770962                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          380                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          337                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.742188                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              339043                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             339043                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8806                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8806                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1144                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1144                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9950                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9950                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9950                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9950                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36628                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36628                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23944                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23944                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60572                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60572                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60572                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60572                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6   1115774950                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total   1115774950                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    994580574                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    994580574                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   2110355524                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   2110355524                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   2110355524                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   2110355524                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45434                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45434                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         25088                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        25088                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70522                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70522                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70522                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70522                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806180                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.806180                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954401                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.954401                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.858909                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.858909                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.858909                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.858909                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs      1141787                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      395.326557                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.772122                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.772122                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.822266                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              339285                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             339285                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8751                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8751                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1170                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1170                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9921                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9921                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9921                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9921                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36633                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36633                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           24021                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          24021                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60654                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60654                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60654                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60654                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6   1194061806                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total   1194061806                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6   1068136243                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total   1068136243                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   2262198049                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   2262198049                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   2262198049                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   2262198049                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45384                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45384                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25191                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25191                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70575                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70575                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70575                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70575                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807179                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.807179                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953555                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.953555                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859426                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859426                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859426                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859426                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs      1121671                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               61213                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               56232                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    18.652688                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    19.947201                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9839                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9839                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36628                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36628                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23944                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23944                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60572                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60572                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60572                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60572                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9790                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9790                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5449                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5449                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15239                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15239                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   1059827480                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total   1059827480                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    958175570                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    958175570                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   2018003050                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   2018003050                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   2018003050                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   2018003050                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    767222409                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    767222409                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   2138123651                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   2138123651                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2905346060                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2905346060                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806180                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806180                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954401                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954401                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858909                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.858909                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858909                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.858909                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224                       # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks           9808                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9808                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36633                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36633                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24021                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        24021                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60654                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60654                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60654                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60654                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9734                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9734                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5519                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5519                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15253                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15253                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   1157429806                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total   1157429806                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6   1044117243                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total   1044117243                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   2201547049                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   2201547049                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   2201547049                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   2201547049                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    789209928                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    789209928                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1545234814                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1545234814                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2334444742                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2334444742                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807179                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807179                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953555                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953555                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859426                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859426                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859426                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859426                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99881                       # number of read accesses completed
-system.cpu7.num_writes                          55258                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22490                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             394.773487                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13394                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22887                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.585223                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99237                       # number of read accesses completed
+system.cpu7.num_writes                          54706                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22568                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             396.130968                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13545                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22967                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.589759                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      394.773487                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.771042                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.771042                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          361                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.775391                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              338728                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             338728                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8705                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8705                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1114                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1114                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9819                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9819                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9819                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9819                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36637                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36637                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23983                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23983                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60620                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60620                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60620                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60620                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7   1106293724                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total   1106293724                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7   1002572296                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total   1002572296                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   2108866020                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   2108866020                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   2108866020                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   2108866020                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45342                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45342                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25097                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25097                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70439                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70439                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70439                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70439                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.808015                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.808015                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955612                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.955612                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.860603                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.860603                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.860603                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.860603                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs      1141532                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      396.130968                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.773693                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.773693                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          336                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              337631                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             337631                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8763                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8763                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1110                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1110                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9873                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9873                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9873                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9873                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36422                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36422                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23951                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23951                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60373                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60373                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60373                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60373                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7   1187262746                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total   1187262746                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7   1066556279                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total   1066556279                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   2253819025                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   2253819025                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   2253819025                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   2253819025                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45185                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45185                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25061                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25061                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70246                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70246                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70246                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70246                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.806064                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.806064                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955708                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.955708                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.859451                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.859451                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.859451                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.859451                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs      1126172                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               61288                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               56351                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    18.625702                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    19.984951                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9784                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9784                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36637                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36637                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23983                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23983                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60620                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60620                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60620                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60620                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9862                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9862                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5465                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5465                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15327                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15327                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   1050368666                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total   1050368666                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    966121280                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    966121280                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   2016489946                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   2016489946                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   2016489946                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   2016489946                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    770060879                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    770060879                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   2135523645                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   2135523645                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2905584524                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2905584524                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.808015                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.808015                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955612                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955612                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860603                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.860603                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860603                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.860603                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738                       # average overall mshr uncacheable latency
+system.cpu7.l1c.writebacks::writebacks           9950                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9950                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36422                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36422                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23951                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23951                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60373                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60373                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60373                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60373                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9901                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9901                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5444                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5444                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15345                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15345                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   1150841746                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total   1150841746                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7   1042608279                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total   1042608279                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   2193450025                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   2193450025                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   2193450025                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   2193450025                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    802753372                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    802753372                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1502766880                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1502766880                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2305520252                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2305520252                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.806064                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.806064                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955708                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955708                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859451                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.859451                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859451                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.859451                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    12865                       # number of replacements
-system.l2c.tags.tagsinuse                  778.482244                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     150454                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    13664                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    11.010978                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13238                       # number of replacements
+system.l2c.tags.tagsinuse                  783.486176                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     163749                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14027                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.673843                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     726.215945                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             5.941011                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             6.607450                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             6.516565                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             6.767835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.065793                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             6.555833                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             6.650782                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.161030                       # Average occupied blocks per requestor
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-system.l2c.tags.age_task_id_blocks_1024::0          529                       # Occupied blocks per task id
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-system.l2c.tags.tag_accesses                  1961721                       # Number of tag accesses
-system.l2c.tags.data_accesses                 1961721                       # Number of data accesses
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-system.l2c.ReadReq_hits::total                  85447                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           75954                       # number of Writeback hits
-system.l2c.Writeback_hits::total                75954                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  258                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  259                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  265                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  289                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  279                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  276                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2192                       # number of UpgradeReq hits
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-system.l2c.demand_hits::cpu2                    12371                       # number of demand (read+write) hits
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-system.l2c.ReadReq_misses::cpu3                   653                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu6                   680                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   698                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 5369                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               2017                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2027                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2036                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2040                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2009                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1982                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1969                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               2002                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16082                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4591                       # number of ReadExReq misses
+system.l2c.tags.occ_blocks::writebacks     731.907933                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.423018                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             6.356158                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             6.459637                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             6.505664                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.498026                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.297131                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             6.613319                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.425290                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.714754                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006272                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.006207                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::total           0.765123                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          789                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          503                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.770508                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  2093442                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2093442                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks           77141                       # number of Writeback hits
+system.l2c.Writeback_hits::total                77141                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0                  278                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  288                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  234                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  250                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  237                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  267                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  288                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  265                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2107                       # number of UpgradeReq hits
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+system.l2c.ReadExReq_hits::total                14236                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0             10764                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu3             10852                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu5             10815                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu6             10778                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu7             10709                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total            86309                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::total                  100545                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                 100545                       # number of overall hits
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 system.l2c.ReadExReq_misses::cpu1                4534                       # number of ReadExReq misses
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-system.l2c.overall_misses::cpu5                  5325                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5163                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5398                       # number of overall misses
-system.l2c.overall_misses::total                42104                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        38166948                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        42177940                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        42464442                       # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_rate::cpu0        0.880276                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.877186                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.899441                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.893526                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.898977                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.884864                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.877759                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.886022                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.887254                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.726489                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.713342                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.726877                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.722422                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.723266                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.714984                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.727835                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.730572                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.723218                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0     0.059584                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1     0.058895                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2     0.060645                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3     0.059211                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu4     0.063947                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu5     0.059320                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu6     0.061640                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu7     0.060037                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.060408                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0            0.298272                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.291916                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2            0.298855                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.298473                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.294470                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.300525                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.291909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.303873                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.297448                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.296240                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.295239                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu3            0.295660                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.301397                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.297218                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.301521                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.301729                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.298321                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.298272                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.291916                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2           0.298855                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.298473                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.294470                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.300525                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.291909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.303873                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.297448                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 60390.740506                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 61394.381368                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 61453.606368                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 61192.859112                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 60431.632777                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 61890.053812                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 61108.128143                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 54706.996788                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 55460.636416                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 55510.229841                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 55549.921676                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 55489.007443                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 55550.636951                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 55507.683756                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 55535.136549                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 55580.935532                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 55523.253539                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 55460.636416                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 55510.229841                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 55549.921676                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 55489.007443                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 55550.636951                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 55507.683756                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 55535.136549                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 55580.935532                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 55523.253539                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              8422                       # number of cycles access was blocked
+system.l2c.overall_miss_rate::cpu3           0.295660                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.301397                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.297218                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.301521                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.301729                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.298321                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 29972.358121                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 30263.732620                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 30704.012422                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 29711.153003                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 29288.762447                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 29602.095029                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 29495.889265                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 29497.087379                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 29816.566733                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 54515.956634                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 54589.978606                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 54599.434773                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 54578.288282                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 54533.253863                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 54454.277291                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 54767.848214                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 54681.721168                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 54590.372681                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0 60282.178886                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1 60444.527326                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2 60422.884451                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3 60581.166911                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu4 60926.122951                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61696.370968                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu6 59855.144068                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu7 59990.412281                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 60524.869526                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 55255.577393                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 55350.586836                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 55358.638460                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 55351.866792                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 55401.128524                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 55375.237181                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 55433.370288                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 55357.282977                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 55360.731373                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 55255.577393                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 55350.586836                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 55358.638460                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 55351.866792                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 55401.128524                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 55375.237181                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 55433.370288                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 55357.282977                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 55360.731373                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              8992                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     1138                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     1204                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      7.400703                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      7.468439                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6144                       # number of writebacks
-system.l2c.writebacks::total                     6144                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2                  3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu4                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                  3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                  5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                40                       # number of ReadReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu2               2                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              4                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
+system.l2c.writebacks::writebacks                6188                       # number of writebacks
+system.l2c.writebacks::total                     6188                       # number of writebacks
+system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                8                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                2                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu3                1                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                1                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              23                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                   7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                   6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                   8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                   8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                   5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                   8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 63                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                  7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                  6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                  8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                  8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                  5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                  8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                63                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              628                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              680                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              688                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              646                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              652                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              666                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              676                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              693                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            5329                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          2017                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2027                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2034                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2040                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          2008                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1982                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1968                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          2002                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        16078                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4588                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4530                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4579                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4586                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4599                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4651                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4482                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4697                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         36712                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5216                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5210                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5267                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5232                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5251                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5317                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              5158                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5390                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            42041                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5216                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5210                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5267                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5232                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5251                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5317                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             5158                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5390                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           42041                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0         9956                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1        10009                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2         9898                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3         9906                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu4         9982                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu5         9934                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu6         9790                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu7         9862                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        79337                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0         5414                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1         5436                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2         5494                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3         5519                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu4         5358                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu6         5448                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu7         5462                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        43589                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0        15370                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1        15445                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2        15392                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3        15425                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu4        15340                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu5        15392                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu6        15238                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu7        15324                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       122926                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     30458949                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     33700940                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     34051940                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     31884439                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     31746444                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     33289946                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu6     33296940                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu7     33931439                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    262361037                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     84760496                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     85183996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     85374489                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     85565499                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     84458998                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     83295996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     82516991                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     84106992                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    675263457                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    195759954                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1    192669961                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2    194828295                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    195239452                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    196619949                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    197755466                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    190831957                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    200614450                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1564319484                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    226218903                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1    226370901                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2    228880235                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3    227123891                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    228366393                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    231045412                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    224128897                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    234545889                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1826680521                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    226218903                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    226370901                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    228880235                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    227123891                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    228366393                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    231045412                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    224128897                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    234545889                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1826680521                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    420391962                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    422439462                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    417792957                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    418505281                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    421118468                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    419294453                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    413123964                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    416090788                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3348757335                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    237106474                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    237782975                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    241705476                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    241076980                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    235943478                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    241042480                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    238750464                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    240064477                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1913472804                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    657498436                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    660222437                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    659498433                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    659582261                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    657061946                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    660336933                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    651874428                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    656155265                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5262230139                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.055477                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.059623                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.060499                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.057530                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.056918                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.058876                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.059168                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.061338                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.058679                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.886593                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.877489                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.886275                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.885033                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.873803                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.875055                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.875445                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.878841                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.879829                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.726985                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.721452                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.730070                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.724830                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717361                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.725925                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.715746                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.726415                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.723603                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.295843                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.294617                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.298515                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.298018                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.293910                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.300073                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.291627                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.303423                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.297002                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.295843                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.294617                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.298515                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.298018                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.293910                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.300073                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.291627                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.303423                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.297002                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 43449.977903                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 43449.977903                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_mshr_hits::cpu4                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5                1                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              26                       # number of ReadExReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu4           12                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu5            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu6            6                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu7            6                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           46                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                   6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                   3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                   5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                  16                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 72                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                  6                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                  3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                  5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                 16                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                72                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         1198                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         1198                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          2044                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          2057                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          2093                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          2098                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          2109                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          2051                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          2068                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          2059                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        16579                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4627                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4532                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4674                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4616                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4656                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4680                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4700                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4687                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         37172                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0          678                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1          673                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2          700                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3          679                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu4          720                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu5          673                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu6          702                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu7          678                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total         5503                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5305                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5205                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5374                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5295                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5376                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5353                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5402                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5365                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            42675                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5305                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5205                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5374                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5295                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5376                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5353                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5402                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5365                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           42675                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0         9717                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1         9744                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2         9883                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3         9988                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu4        10053                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu5         9842                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu6         9734                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu7         9901                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        78862                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0         5354                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1         5486                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2         5463                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3         5457                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu4         5464                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu5         5585                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu6         5519                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu7         5444                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        43772                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0        15071                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1        15230                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2        15346                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3        15445                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu4        15517                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu5        15427                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu6        15253                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu7        15345                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       122634                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     89873000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     90484998                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     92033997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     92268499                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     92811998                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     90292999                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     90927999                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     90564000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    729257490                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    206241460                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    202149464                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    208464458                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    205784957                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    207399964                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    208084972                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    210466959                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    209572454                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1658164688                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     34242946                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     34066945                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     35309442                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     34442937                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     37046924                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     35143925                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     35167942                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     34075942                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    279497003                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    240484406                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    236216409                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    243773900                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    240227894                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    244446888                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    243228897                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    245634901                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    243648396                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1937661691                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    240484406                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    236216409                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    243773900                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    240227894                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    244446888                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    243228897                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    245634901                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    243648396                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1937661691                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    429696979                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    430709962                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    436642475                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    441286981                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    444007972                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    434245978                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    430003472                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    437630301                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3484224120                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    244327984                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    248490489                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    246535993                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    247729989                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    247792491                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    253848482                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    250349488                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    246216989                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1985291905                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    674024963                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    679200451                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    683178468                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    689016970                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    691800463                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    688094460                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    680352960                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    683847290                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5469516025                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.880276                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.877186                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.899441                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.893526                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.898977                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.884433                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.877759                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.885591                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.887147                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.725235                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.713027                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.726566                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.722266                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.722645                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.714831                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.727216                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.729949                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.722713                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.059235                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.058547                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.060559                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.058864                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.062899                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.058537                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.061118                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.059510                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.059908                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.297599                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.291580                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.298688                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.295381                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.300503                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.296664                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.300964                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.301168                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.297818                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.297599                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.291580                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.298688                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.295381                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.300503                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.296664                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.300964                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.301168                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.297818                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 43969.178082                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 43988.817696                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 43972.287148                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 43979.265491                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44007.585586                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44023.890297                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 43969.051741                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 43984.458475                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 45405.077704                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 45405.077704                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests        252480                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       249408                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        253876                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       250804                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq               84654                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84652                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43588                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43585                       # Transaction distribution
-system.membus.trans_dist::Writeback              6143                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60492                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           49595                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             50638                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3207                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       426554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 426554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1061863                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1061863                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            58325                       # Total snoops (count)
-system.membus.snoop_fanout::samples            252480                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               78861                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84355                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43772                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43770                       # Transaction distribution
+system.membus.trans_dist::Writeback              6188                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1234                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            61487                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           50676                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49401                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3090                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5496                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       428330                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 428330                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1068167                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1068167                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            57121                       # Total snoops (count)
+system.membus.snoop_fanout::samples            253876                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  252480    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253876    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              252480                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           472884580                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              59.9                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          313892142                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             39.7                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       684630                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       383351                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       298207                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             371695                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            371689                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43589                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43585                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback            75954                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29169                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29167                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           162397                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          162391                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120614                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120783                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120664                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120646                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120853                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120726                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120516                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120736                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                965538                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1756616                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1750933                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1748576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1754368                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1762730                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1756512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1757509                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1755676                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14042920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          324098                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           684630                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.384232                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.250303                       # Request fanout histogram
+system.membus.snoop_fanout::total              253876                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           481009549                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              54.1                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          317350499                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             35.7                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       783985                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       389410                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       391503                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          13238                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         4575                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         8663                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              78862                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            371257                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43772                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43769                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback            83329                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           20018                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29498                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29497                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           162169                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          162167                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       292402                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       122283                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122529                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122863                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122791                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       122959                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122669                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122503                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                981417                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1781215                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1778494                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1776817                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1770963                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1771805                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1794946                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1778453                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1777585                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14230278                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          335326                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           797223                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.523507                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.320965                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 176832     25.83%     25.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 250927     36.65%     62.48% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 141295     20.64%     83.12% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  69195     10.11%     93.23% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  30377      4.44%     97.66% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                  11672      1.70%     99.37% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                   3607      0.53%     99.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                    725      0.11%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 184121     23.10%     23.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 277567     34.82%     57.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 172653     21.66%     79.57% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  93165     11.69%     91.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  44731      5.61%     96.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                  17914      2.25%     99.11% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                   5826      0.73%     99.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   1211      0.15%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                     35      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             684630                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          782327755                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             99.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         100591456                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            12.7                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         100721944                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            12.8                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         100768962                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            12.8                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         100555978                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            12.7                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         100847968                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            12.8                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         100723976                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            12.8                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         100740497                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            12.8                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         100846524                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            12.8                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::max_value              8                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total             797223                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          882991225                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             99.3                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         100686388                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         100571959                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         100903359                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            11.4                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         100786975                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         100705827                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         100586898                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         100884775                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            11.3                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         100465612                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            11.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index ff9b64e46..d439f20bd 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1766 +1,1775 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000473                       # Number of seconds simulated
-sim_ticks                                   473398500                       # Number of ticks simulated
-final_tick                                  473398500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000517                       # Number of seconds simulated
+sim_ticks                                   516502000                       # Number of ticks simulated
+final_tick                                  516502000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                               74773462                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221944                       # Number of bytes of host memory used
-host_seconds                                     6.33                       # Real time elapsed on the host
+host_tick_rate                               87177041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277532                       # Number of bytes of host memory used
+host_seconds                                     5.92                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 85610                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 86349                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 81279                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 82686                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 83314                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 81031                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 83113                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 86498                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               669880                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       430080                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5517                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5460                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5549                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5366                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5369                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5497                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5427                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            473601                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11018                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  11064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10845                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10992                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  10927                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  11038                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10915                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  10898                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87697                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5517                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5460                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5549                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5366                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5369                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5497                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5427                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5336                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                50241                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                180841300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                182402352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                171692559                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                174664685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                175991263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                171168688                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                175566674                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                182717098                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1415044619                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         908494640                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                11654029                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                11533623                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                11721626                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                11335059                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                11341396                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                11611782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                11463915                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                11271688                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1000427758                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         908494640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               192495329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               193935976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               183414185                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               185999744                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               187332659                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               182780469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               187030588                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               193988785                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2415472377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 77818                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 80958                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 77616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 81564                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 77320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 77018                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 77760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 78103                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               628157                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       397760                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5585                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5520                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5375                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5451                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5416                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5446                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5475                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5563                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            441591                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10975                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10902                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  11130                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10918                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10679                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10819                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87365                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6215                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5585                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5520                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5375                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5451                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5416                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5446                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5475                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5563                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                50046                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                150663502                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                156742859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                150272409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                157916136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                149699324                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                149114621                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                150551208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                151215291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1216175349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         770103504                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                10813124                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                10687277                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                10406542                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                10553686                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                10485923                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                10544006                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                10600153                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                10770529                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              854964744                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         770103504                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               161476625                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               167430136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               160678952                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               168469822                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               160185246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               159658627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               161151360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               161985820                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2071140092                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                           99308                       # number of read accesses completed
-system.cpu0.num_writes                          55247                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22271                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             390.476059                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13537                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22673                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.597054                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99458                       # number of read accesses completed
+system.cpu0.num_writes                          55230                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22190                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             391.694293                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13468                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22585                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.596325                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      390.476059                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.762649                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.762649                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          391                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              337706                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             337706                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8778                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8778                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1202                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1202                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9980                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9980                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9980                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9980                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36312                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36312                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23969                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23969                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60281                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60281                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60281                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60281                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    585914746                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    585914746                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    661973304                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    661973304                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1247888050                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1247888050                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1247888050                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1247888050                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45090                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45090                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25171                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25171                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70261                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70261                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70261                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70261                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.805323                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.805323                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952247                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.952247                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.857958                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.857958                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.857958                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.857958                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 20701.183623                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       772989                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      391.694293                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.765028                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.765028                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              337088                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             337088                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1212                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1212                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9897                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9897                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9897                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36327                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36327                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23903                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23903                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60230                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60230                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60230                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60230                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    590238894                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    590238894                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    671544552                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    671544552                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1261783446                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1261783446                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1261783446                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1261783446                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45012                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45012                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25115                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25115                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70127                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70127                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70127                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70127                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807051                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.807051                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.951742                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.951742                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.858870                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.858870                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.858870                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.858870                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       738586                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               66053                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               60679                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    11.702557                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.172020                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9819                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9819                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36312                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36312                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23969                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23969                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60281                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60281                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60281                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60281                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9835                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9835                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5519                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5519                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15354                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15354                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    529167946                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    529167946                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    625061532                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    625061532                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1154229478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1154229478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1154229478                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1154229478                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    639072193                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    639072193                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    970312557                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    970312557                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1609384750                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1609384750                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.805323                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.805323                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952247                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952247                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.857958                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.857958                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.857958                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.857958                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14572.811908                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14572.811908                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19147.483917                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19147.483917                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19147.483917                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760                       # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks           9780                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9780                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36327                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36327                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23903                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23903                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60230                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60230                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60230                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60230                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9914                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9914                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5586                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5586                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15500                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15500                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    553912894                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    553912894                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    647643552                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    647643552                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1201556446                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1201556446                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1201556446                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1201556446                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    648458134                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    648458134                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    875575663                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    875575663                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1524033797                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1524033797                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807051                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807051                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.951742                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.951742                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858870                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.858870                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858870                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.858870                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           98972                       # number of read accesses completed
-system.cpu1.num_writes                          54740                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               21894                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             389.013692                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13227                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22299                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.593166                       # Average number of references to valid blocks.
+system.cpu1.num_reads                           99343                       # number of read accesses completed
+system.cpu1.num_writes                          54840                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22376                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             393.102021                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13319                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22762                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.585142                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      389.013692                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.759792                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.759792                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          405                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          401                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.791016                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              335323                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             335323                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8521                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8521                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1152                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1152                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9673                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9673                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9673                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9673                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36191                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36191                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23860                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23860                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60051                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60051                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60051                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60051                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    587357926                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    587357926                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    665550173                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    665550173                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1252908099                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1252908099                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1252908099                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1252908099                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          44712                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         44712                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         25012                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        25012                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           69724                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          69724                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          69724                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         69724                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809425                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.809425                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953942                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.953942                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.861267                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.861267                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.861267                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.861267                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27893.972045                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 27893.972045                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 20864.067193                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       781068                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      393.102021                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.767777                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.767777                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              337670                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             337670                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8618                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8618                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1175                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1175                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9793                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9793                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9793                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9793                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36716                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36716                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23707                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23707                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60423                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60423                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60423                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60423                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    601446212                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    601446212                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    664813201                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    664813201                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1266259413                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1266259413                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1266259413                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1266259413                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45334                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45334                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24882                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24882                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70216                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70216                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70216                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70216                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809900                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.809900                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.952777                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.952777                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.860530                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.860530                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.860530                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.860530                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       733404                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               66159                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               60457                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    11.805922                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.131002                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9676                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9676                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36191                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36191                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23860                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23860                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60051                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60051                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60051                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60051                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9870                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9870                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5462                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5462                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15332                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15332                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    530766130                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    530766130                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    628779775                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    628779775                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1159545905                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1159545905                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1159545905                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1159545905                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    639204350                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    639204350                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    954877634                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    954877634                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1594081984                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1594081984                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809425                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809425                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953942                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953942                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.861267                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.861267                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.861267                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.861267                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14665.693957                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14665.693957                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 26352.882439                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19309.352134                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19309.352134                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19309.352134                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19309.352134                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470                       # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks           9757                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9757                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36716                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36716                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23707                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23707                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60423                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60423                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60423                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60423                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9790                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9790                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5520                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5520                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15310                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15310                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    564731212                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    564731212                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    641108201                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    641108201                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1205839413                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1205839413                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1205839413                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1205839413                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    639869720                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    639869720                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    879270140                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    879270140                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1519139860                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1519139860                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809900                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809900                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.952777                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.952777                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860530                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.860530                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860530                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.860530                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99459                       # number of read accesses completed
-system.cpu2.num_writes                          55455                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22538                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             392.681778                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13552                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22938                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.590810                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99555                       # number of read accesses completed
+system.cpu2.num_writes                          54722                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22333                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             393.011664                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13583                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22742                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.597265                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      392.681778                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.766957                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.766957                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          393                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              337495                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             337495                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8694                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8694                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1182                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1182                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9876                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9876                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9876                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9876                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36455                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36455                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23891                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23891                       # number of WriteReq misses
+system.cpu2.l1c.tags.occ_blocks::cpu2      393.011664                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.767601                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.767601                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              337922                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             337922                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8790                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8790                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1177                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1177                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9967                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9967                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9967                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9967                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36445                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36445                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23901                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23901                       # number of WriteReq misses
 system.cpu2.l1c.demand_misses::cpu2             60346                       # number of demand (read+write) misses
 system.cpu2.l1c.demand_misses::total            60346                       # number of demand (read+write) misses
 system.cpu2.l1c.overall_misses::cpu2            60346                       # number of overall misses
 system.cpu2.l1c.overall_misses::total           60346                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    592802045                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    592802045                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    663383699                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    663383699                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1256185744                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1256185744                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1256185744                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1256185744                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45149                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45149                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25073                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25073                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70222                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70222                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70222                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70222                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807438                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.807438                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.952858                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.952858                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.859360                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.859360                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.859360                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.859360                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 27767.096354                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 20816.387896                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       773062                       # number of cycles access was blocked
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    601110816                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    601110816                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    668105531                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    668105531                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1269216347                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1269216347                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1269216347                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1269216347                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45235                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45235                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25078                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25078                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70313                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70313                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70313                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70313                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805681                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.805681                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953066                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.953066                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.858248                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.858248                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.858248                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.858248                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       742378                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               66064                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               60996                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    11.701713                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.170929                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9793                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9793                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36455                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36455                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23891                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23891                       # number of WriteReq MSHR misses
+system.cpu2.l1c.writebacks::writebacks           9726                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9726                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36445                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36445                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23901                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23901                       # number of WriteReq MSHR misses
 system.cpu2.l1c.demand_mshr_misses::cpu2        60346                       # number of demand (read+write) MSHR misses
 system.cpu2.l1c.demand_mshr_misses::total        60346                       # number of demand (read+write) MSHR misses
 system.cpu2.l1c.overall_mshr_misses::cpu2        60346                       # number of overall MSHR misses
 system.cpu2.l1c.overall_mshr_misses::total        60346                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9727                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9727                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5550                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5550                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15277                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15277                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    535820289                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    535820289                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    626605165                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    626605165                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1162425454                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1162425454                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1162425454                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1162425454                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    629981617                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    629981617                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    971621622                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    971621622                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1601603239                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1601603239                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807438                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807438                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.952858                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.952858                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859360                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.859360                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859360                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.859360                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14698.128899                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14698.128899                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26227.665857                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19262.676134                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19262.676134                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19262.676134                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19262.676134                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 64766.281176                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64766.281176                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 175066.958919                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175066.958919                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 104837.549192                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192                       # average overall mshr uncacheable latency
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9904                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9904                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5377                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5377                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15281                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15281                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    564666816                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    564666816                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    644204531                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    644204531                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1208871347                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1208871347                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1208871347                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1208871347                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    647672238                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    647672238                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    840893759                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    840893759                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1488565997                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1488565997                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805681                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805681                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953066                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953066                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858248                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.858248                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858248                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.858248                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99575                       # number of read accesses completed
-system.cpu3.num_writes                          55091                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22304                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             392.069306                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13533                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22710                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.595905                       # Average number of references to valid blocks.
+system.cpu3.num_reads                           99759                       # number of read accesses completed
+system.cpu3.num_writes                          54933                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22211                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             391.604025                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13361                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22604                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.591090                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      392.069306                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.765760                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.765760                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          399                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              336765                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             336765                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8633                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8633                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1152                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1152                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9785                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9785                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9785                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9785                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36428                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36428                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23860                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23860                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60288                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60288                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60288                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60288                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    584499068                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    584499068                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    664565432                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    664565432                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1249064500                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1249064500                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1249064500                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1249064500                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45061                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45061                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         25012                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        25012                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70073                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70073                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70073                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70073                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.808415                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.808415                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953942                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.953942                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.860360                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.860360                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.860360                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.860360                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16045.324146                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27852.700419                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 27852.700419                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 20718.293856                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 20718.293856                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 20718.293856                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       775679                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      391.604025                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.764852                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.764852                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              336889                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             336889                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8685                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1067                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1067                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9752                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9752                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9752                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9752                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36549                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36549                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23764                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23764                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60313                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60313                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60313                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60313                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    596458593                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    596458593                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    667670467                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    667670467                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1264129060                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1264129060                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1264129060                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1264129060                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45234                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45234                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         24831                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        24831                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70065                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70065                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70065                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70065                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807998                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.807998                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.957030                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.957030                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.860815                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.860815                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.860815                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.860815                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       744732                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               66211                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               61238                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    11.715259                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.161272                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9857                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9857                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36428                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36428                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23860                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23860                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60288                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60288                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60288                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60288                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9854                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9854                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5367                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5367                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15221                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15221                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    527611348                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    527611348                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    627817964                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    627817964                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1155429312                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1155429312                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1155429312                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1155429312                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    639378023                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    639378023                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    962583192                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    962583192                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1601961215                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1601961215                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.808415                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.808415                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953942                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953942                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860360                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.860360                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860360                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.860360                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14483.675964                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14483.675964                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 26312.571836                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 26312.571836                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19165.162420                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19165.162420                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19165.162420                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19165.162420                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 64885.125127                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64885.125127                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 179352.187814                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179352.187814                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 105246.778464                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464                       # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks           9780                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9780                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36549                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36549                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23764                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23764                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60313                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60313                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60313                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60313                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3        10012                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total        10012                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5455                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5455                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15467                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15467                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    559909593                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    559909593                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    643907467                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    643907467                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1203817060                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1203817060                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1203817060                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1203817060                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    654349566                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    654349566                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    848349724                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    848349724                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1502699290                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1502699290                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807998                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807998                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.957030                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.957030                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860815                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.860815                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860815                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.860815                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99348                       # number of read accesses completed
-system.cpu4.num_writes                          54723                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22403                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             391.522543                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13385                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22785                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.587448                       # Average number of references to valid blocks.
+system.cpu4.num_reads                          100000                       # number of read accesses completed
+system.cpu4.num_writes                          55127                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22421                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             392.948683                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13931                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22818                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.610527                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      391.522543                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.764692                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.764692                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          382                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.746094                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              337332                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             337332                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8635                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8635                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1108                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1108                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9743                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9743                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9743                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9743                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36706                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36706                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23706                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23706                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60412                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60412                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60412                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60412                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    597809741                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    597809741                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    658168265                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    658168265                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1255978006                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1255978006                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1255978006                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1255978006                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45341                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45341                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24814                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24814                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70155                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70155                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70155                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70155                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.809554                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.809554                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.955348                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.955348                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.861122                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.861122                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.861122                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.861122                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16286.431128                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 16286.431128                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27763.784063                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 27763.784063                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 20790.207343                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 20790.207343                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       777995                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      392.948683                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.767478                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.767478                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.775391                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              339409                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             339409                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               9015                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              9015                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1217                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1217                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4               10232                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total              10232                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4              10232                       # number of overall hits
+system.cpu4.l1c.overall_hits::total             10232                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36534                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36534                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23911                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23911                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60445                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60445                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60445                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60445                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    594216920                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    594216920                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    670376038                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    670376038                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1264592958                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1264592958                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1264592958                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1264592958                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45549                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45549                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25128                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25128                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70677                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70677                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70677                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70677                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.802081                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.802081                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.951568                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.951568                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.855229                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.855229                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.855229                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.855229                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       737141                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               66371                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               60832                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    11.721912                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.117652                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9776                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9776                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36706                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36706                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23706                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23706                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60412                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60412                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60412                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60412                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9778                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9778                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5370                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5370                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15148                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15148                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    540346315                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    540346315                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    621672271                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    621672271                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1162018586                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1162018586                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1162018586                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1162018586                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    636494546                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    636494546                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    958781259                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    958781259                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1595275805                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1595275805                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.809554                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.809554                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.955348                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.955348                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.861122                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.861122                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.861122                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.861122                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14720.926143                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14720.926143                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19234.896809                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19234.896809                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661                       # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks           9985                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9985                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36534                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36534                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23911                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23911                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60445                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60445                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60445                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60445                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9865                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9865                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5418                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5418                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15283                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15283                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    557683920                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    557683920                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    646466038                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    646466038                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1204149958                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1204149958                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1204149958                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1204149958                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    645821695                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    645821695                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    857369844                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    857369844                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1503191539                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1503191539                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.802081                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.802081                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.951568                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.951568                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.855229                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.855229                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.855229                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.855229                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99076                       # number of read accesses completed
-system.cpu5.num_writes                          54802                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22210                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             392.101349                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13412                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22600                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.593451                       # Average number of references to valid blocks.
+system.cpu5.num_reads                           99788                       # number of read accesses completed
+system.cpu5.num_writes                          55138                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22475                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             392.735284                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13651                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22873                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.596817                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      392.101349                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.765823                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.765823                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              335763                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             335763                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8687                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8687                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1188                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1188                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9875                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9875                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9875                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9875                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36386                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36386                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23589                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23589                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             59975                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            59975                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            59975                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           59975                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    587220514                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    587220514                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    653847941                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    653847941                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1241068455                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1241068455                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1241068455                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1241068455                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          45073                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         45073                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         24777                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        24777                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           69850                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          69850                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          69850                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         69850                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.807268                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.807268                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952052                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.952052                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.858626                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.858626                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.858626                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.858626                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 20693.096373                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       773798                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      392.735284                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.767061                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.767061                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              340255                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             340255                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8878                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8878                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1131                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1131                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5               10009                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total              10009                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5              10009                       # number of overall hits
+system.cpu5.l1c.overall_hits::total             10009                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36858                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36858                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23929                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23929                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60787                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60787                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60787                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60787                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    604018831                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    604018831                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    667551562                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    667551562                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1271570393                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1271570393                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1271570393                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1271570393                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45736                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45736                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25060                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25060                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70796                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70796                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70796                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70796                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.805886                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.805886                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954868                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.954868                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.858622                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.858622                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.858622                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.858622                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       731203                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               65921                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               60676                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    11.738262                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.050943                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9805                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9805                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36386                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36386                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23589                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23589                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        59975                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        59975                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        59975                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        59975                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9927                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9927                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5497                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5497                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15424                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15424                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    530387712                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    530387712                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    617501507                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    617501507                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1147889219                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1147889219                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1147889219                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1147889219                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    644126924                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    644126924                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    971277615                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    971277615                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1615404539                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1615404539                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.807268                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.807268                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952052                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952052                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858626                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.858626                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858626                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.858626                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14576.697411                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14576.697411                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26177.519479                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19139.461759                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19139.461759                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19139.461759                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64886.362849                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176692.307622                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 104733.178099                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099                       # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks           9872                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9872                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36858                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36858                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23929                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23929                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60787                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60787                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60787                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60787                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9627                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9627                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5446                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5446                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15073                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15073                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    567160831                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    567160831                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    643622562                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    643622562                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1210783393                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1210783393                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1210783393                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1210783393                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    632098852                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    632098852                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    869172204                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    869172204                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1501271056                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1501271056                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.805886                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.805886                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954868                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954868                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858622                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.858622                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858622                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.858622                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                          100000                       # number of read accesses completed
-system.cpu6.num_writes                          55196                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22166                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             390.500017                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13797                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22571                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.611271                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99577                       # number of read accesses completed
+system.cpu6.num_writes                          55267                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22184                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             392.209079                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13575                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22573                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.601382                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      390.500017                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.762695                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.762695                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          405                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          400                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.791016                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              338189                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             338189                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8999                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8999                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1089                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1089                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6               10088                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total              10088                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6              10088                       # number of overall hits
-system.cpu6.l1c.overall_hits::total             10088                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36489                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36489                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23831                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23831                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60320                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60320                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60320                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60320                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    591265797                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    591265797                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    669884291                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    669884291                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1261150088                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1261150088                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1261150088                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1261150088                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45488                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45488                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         24920                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        24920                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70408                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70408                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70408                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70408                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.802168                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.802168                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956300                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.956300                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.856721                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.856721                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.856721                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.856721                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16203.946313                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 28109.785196                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 20907.660610                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 20907.660610                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 20907.660610                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       779089                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      392.209079                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.766033                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.766033                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              337224                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             337224                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8787                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8787                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1092                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1092                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9879                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9879                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9879                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9879                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36436                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36436                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23858                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23858                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60294                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60294                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60294                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60294                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    592887114                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    592887114                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    676055850                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    676055850                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1268942964                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1268942964                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1268942964                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1268942964                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45223                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45223                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         24950                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        24950                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70173                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70173                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70173                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70173                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805696                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.805696                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956232                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.956232                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859219                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859219                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859219                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859219                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       742965                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               66360                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               61020                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    11.740341                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.175762                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9642                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9642                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36489                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36489                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23831                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23831                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60320                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60320                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60320                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60320                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9769                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9769                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5428                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5428                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15197                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15197                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    534211155                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    534211155                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    633170857                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    633170857                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1167382012                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1167382012                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1167382012                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1167382012                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    633249047                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    633249047                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    972097686                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    972097686                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1605346733                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1605346733                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.802168                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.802168                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956300                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956300                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.856721                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.856721                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.856721                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.856721                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14640.334210                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14640.334210                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19353.150066                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19353.150066                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19353.150066                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179089.477892                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809                       # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks           9883                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9883                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36436                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36436                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23858                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23858                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60294                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60294                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60294                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60294                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9920                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9920                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5475                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5475                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15395                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15395                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    556451114                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    556451114                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    652198850                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    652198850                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1208649964                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1208649964                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1208649964                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1208649964                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    646733639                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    646733639                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    847369233                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    847369233                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1494102872                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1494102872                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805696                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805696                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956232                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956232                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859219                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859219                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859219                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859219                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99558                       # number of read accesses completed
-system.cpu7.num_writes                          55171                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22301                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             392.314330                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13511                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22696                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.595303                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99427                       # number of read accesses completed
+system.cpu7.num_writes                          55134                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22242                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             391.816785                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13453                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22633                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.594398                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      392.314330                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.766239                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.766239                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              337937                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             337937                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8724                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8724                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1105                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1105                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9829                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9829                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9829                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9829                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36568                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36568                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23906                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23906                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60474                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60474                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60474                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60474                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    596090233                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    596090233                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    664580608                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    664580608                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1260670841                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1260670841                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1260670841                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1260670841                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45292                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45292                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25011                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25011                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70303                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70303                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70303                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70303                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807383                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.807383                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955819                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.955819                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.860191                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.860191                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.860191                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.860191                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 27799.740986                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 20846.493386                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 20846.493386                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       776345                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      391.816785                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.765267                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.765267                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              338054                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             338054                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8636                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8636                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1148                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9784                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9784                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9784                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9784                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36700                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36700                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23832                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23832                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60532                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60532                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60532                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60532                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    601580634                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    601580634                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    672036114                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    672036114                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1273616748                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1273616748                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1273616748                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1273616748                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45336                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45336                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         24980                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        24980                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70316                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70316                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70316                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70316                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.809511                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.809511                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954043                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.954043                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.860857                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.860857                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.860857                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.860857                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       739183                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               66228                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               60836                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    11.722308                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.150421                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9814                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9814                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36568                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36568                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23906                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23906                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60474                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60474                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60474                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60474                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9700                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9700                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5336                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5336                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15036                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15036                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    538984883                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    538984883                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    627714786                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    627714786                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1166699669                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1166699669                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1166699669                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1166699669                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    629180127                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    629180127                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    945700289                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    945700289                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1574880416                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1574880416                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807383                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807383                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955819                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955819                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860191                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.860191                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860191                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.860191                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14739.249699                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 26257.625115                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 26257.625115                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19292.583077                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19292.583077                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19292.583077                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19292.583077                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 64863.930619                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64863.930619                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 177230.189093                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 177230.189093                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 104740.650173                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173                       # average overall mshr uncacheable latency
+system.cpu7.l1c.writebacks::writebacks           9689                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9689                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36700                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36700                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23832                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23832                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60532                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60532                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60532                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60532                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9751                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9751                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5566                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5566                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15317                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15317                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    564880634                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    564880634                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    648206114                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    648206114                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1213086748                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1213086748                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1213086748                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1213086748                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    637373819                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    637373819                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    878019147                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    878019147                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1515392966                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1515392966                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.809511                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.809511                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954043                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954043                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860857                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.860857                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860857                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.860857                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    14031                       # number of replacements
-system.l2c.tags.tagsinuse                  784.967814                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     150152                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14812                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.137186                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13635                       # number of replacements
+system.l2c.tags.tagsinuse                  787.795797                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     163881                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14421                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.364052                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     723.923615                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.649200                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             8.016952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.636701                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.493514                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             7.626072                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             7.131481                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             7.354188                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             8.136089                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.706957                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.007470                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.007829                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.007458                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007318                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.007447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.006964                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.007182                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.007945                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.766570                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          781                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          686                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.762695                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  1978435                       # Number of tag accesses
-system.l2c.tags.data_accesses                 1978435                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0                   10713                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1                   10607                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2                   10697                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3                   10702                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4                   11123                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5                   10597                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6                   10776                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7                   10709                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  85924                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           76544                       # number of Writeback hits
-system.l2c.Writeback_hits::total                76544                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  272                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  268                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  299                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  302                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  259                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  274                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  287                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  307                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2268                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1803                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1734                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1772                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1671                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1762                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1808                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1767                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1864                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                14181                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0                    12516                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12341                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12469                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12373                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12885                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12405                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12543                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12573                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  100105                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12516                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12341                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12469                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12373                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12885                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12405                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12543                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12573                       # number of overall hits
-system.l2c.overall_hits::total                 100105                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0                   745                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1                   785                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2                   742                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3                   727                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4                   760                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5                   712                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6                   735                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   780                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 5986                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               1959                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2034                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2073                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2095                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2075                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1984                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               2104                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               2050                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16374                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4569                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4626                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4511                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4582                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4471                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4493                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4628                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4552                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              36432                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0                   5314                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5411                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5253                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5309                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5231                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5205                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5363                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5332                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 42418                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5314                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5411                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5253                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5309                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5231                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5205                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5363                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5332                       # number of overall misses
-system.l2c.overall_misses::total                42418                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        46187916                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        48036419                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        45900428                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3        44726930                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4        46758924                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5        44218925                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6        45379928                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7        48529420                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      369738890                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0     57866497                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     60355991                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     61207994                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     63805822                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     62183492                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     61767496                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     63498496                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     63160496                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    493846284                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     251689442                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     254959951                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     248273936                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     252714443                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     246321934                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     247674443                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     255400930                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     250363448                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2007398527                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0        297877358                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        302996370                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        294174364                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        297441373                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        293080858                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        291893368                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        300780858                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        298892868                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2377137417                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       297877358                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       302996370                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       294174364                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       297441373                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       293080858                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       291893368                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       300780858                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       298892868                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2377137417                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0               11458                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1               11392                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2               11439                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3               11429                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4               11883                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5               11309                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6               11511                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7               11489                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              91910                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks        76544                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            76544                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2231                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2302                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2372                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2397                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2334                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2258                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2391                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2357                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18642                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6372                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6360                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6283                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6253                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6233                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6301                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6395                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6416                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            50613                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17830                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                17752                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                17722                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17682                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                18116                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17610                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                17906                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17905                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              142523                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17830                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               17752                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               17722                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17682                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               18116                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17610                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               17906                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17905                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             142523                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0           0.065020                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1           0.068908                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2           0.064866                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3           0.063610                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4           0.063957                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5           0.062959                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu6           0.063852                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu7           0.067891                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.065129                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.878082                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.883579                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.873946                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.874009                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.889032                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.878654                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.879967                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.869750                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.878339                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.717043                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.727358                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.717969                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.732768                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.717311                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.713061                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.723690                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.709476                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.719815                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0            0.298037                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.304811                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.296411                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.300249                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.288750                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.295571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.299509                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.297794                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.297622                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.298037                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.304811                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.296411                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.300249                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.288750                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.295571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.299509                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.297794                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.297622                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 61997.202685                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 61192.890446                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 61860.415094                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 61522.599725                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 61524.900000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 62105.231742                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61741.398639                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 62217.205128                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 61767.271968                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 29538.793772                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 29673.545231                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 29526.287506                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 30456.239618                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 29967.947952                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 31132.810484                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 30179.893536                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 30809.998049                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 30160.393551                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 55086.330050                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 55114.559230                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 55037.449789                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 55153.741379                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 55093.252964                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 55124.514356                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 55186.026361                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 55000.757469                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 55099.871734                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 56055.204742                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 55996.372205                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 56001.211498                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 56025.875494                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 56027.692219                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 56079.417483                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 56084.441171                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 56056.426857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 56040.770828                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 56055.204742                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 55996.372205                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 56001.211498                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 56025.875494                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 56027.692219                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 56079.417483                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 56084.441171                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 56056.426857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 56040.770828                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             18299                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     732.377461                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.931961                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             6.975655                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             6.944636                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             7.398268                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.695089                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.188919                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             7.047720                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             7.236089                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.715212                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006769                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.006812                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.006782                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.007225                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.006538                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.006044                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.006883                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.007066                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.769332                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          786                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          654                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  2092959                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2092959                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks           77190                       # number of Writeback hits
+system.l2c.Writeback_hits::total                77190                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0                  242                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  278                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  290                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  299                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  286                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  279                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  254                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  287                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2215                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0                  1757                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1                  1745                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2                  1812                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3                  1725                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu4                  1792                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu5                  1760                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu6                  1718                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu7                  1773                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                14082                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0             10725                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1             10956                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2             10775                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3             10922                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu4             10805                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu5             10917                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu6             10735                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu7             10921                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total            86756                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0                    12482                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1                    12701                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2                    12587                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3                    12647                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu4                    12597                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu5                    12677                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu6                    12453                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu7                    12694                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  100838                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0                   12482                       # number of overall hits
+system.l2c.overall_hits::cpu1                   12701                       # number of overall hits
+system.l2c.overall_hits::cpu2                   12587                       # number of overall hits
+system.l2c.overall_hits::cpu3                   12647                       # number of overall hits
+system.l2c.overall_hits::cpu4                   12597                       # number of overall hits
+system.l2c.overall_hits::cpu5                   12677                       # number of overall hits
+system.l2c.overall_hits::cpu6                   12453                       # number of overall hits
+system.l2c.overall_hits::cpu7                   12694                       # number of overall hits
+system.l2c.overall_hits::total                 100838                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0               2065                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               2004                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               2022                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               2044                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               2054                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               2029                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               2097                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7               2076                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             16391                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0                4632                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1                4551                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2                4580                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3                4616                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4                4586                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5                4561                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6                4720                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7                4602                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              36848                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0             688                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1             704                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2             710                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3             732                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu4             671                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu5             651                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu6             677                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu7             715                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           5548                       # number of ReadSharedReq misses
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+system.l2c.UpgradeReq_miss_latency::cpu1     61176995                       # number of UpgradeReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu3     63986497                       # number of UpgradeReq miss cycles
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+system.l2c.overall_miss_latency::total     2361100187                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks        77190                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total            77190                       # number of Writeback accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu0        0.895102                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.878177                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.874567                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.872386                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.877778                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.879116                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.891961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.878544                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.880952                       # miss rate for UpgradeReq accesses
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+system.l2c.demand_miss_rate::cpu0            0.298843                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.295991                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::total          0.295991                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 29710.886683                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 30527.442615                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 29045.246785                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 31304.548434                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 28750.481500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 28813.697388                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 30681.205532                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 29830.199422                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 29835.179367                       # average UpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 54760.119030                       # average ReadExReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 61878.031903                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 55778.068985                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu5 55621.132003                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu7 55773.617077                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 55691.579088                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 55778.068985                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 55691.579088                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             18273                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     3476                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     3257                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      5.264384                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      5.610378                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6720                       # number of writebacks
-system.l2c.writebacks::total                     6720                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                  9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2                  8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                  3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu4                 15                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                58                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks                6215                       # number of writebacks
+system.l2c.writebacks::total                     6215                       # number of writebacks
+system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu6               3                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              4                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                8                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                4                       # number of ReadExReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
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+system.l2c.ReadExReq_mshr_hits::cpu3                1                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                7                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu5                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              35                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                   5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                   8                       # number of demand (read+write) MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                5                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              32                       # number of ReadExReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu4           10                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu5            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu6            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu7            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           55                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                   8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                  17                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                  10                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu7                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 93                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                  5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                  8                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                 87                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                  8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                 17                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                 10                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu7                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                93                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              738                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              776                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              734                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              724                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              745                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              706                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              731                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              774                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            5928                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1959                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2034                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2073                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2095                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          2074                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1984                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          2101                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          2050                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        16370                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4565                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4622                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4503                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4580                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4467                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4488                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4624                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4548                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         36397                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5303                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5398                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5237                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5304                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5212                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5194                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              5355                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5322                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            42325                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5303                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5398                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5237                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5304                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5212                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5194                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             5355                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5322                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           42325                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0         9834                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1         9869                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2         9727                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3         9854                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu4         9778                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu5         9927                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu6         9769                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu7         9700                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        78458                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0         5517                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1         5460                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2         5550                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3         5367                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu4         5370                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu5         5497                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu6         5427                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu7         5336                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        43524                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0        15351                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1        15329                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2        15277                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3        15221                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu4        15148                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu5        15424                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu6        15196                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu7        15036                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       121982                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     37081908                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     38421892                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     36752422                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     35943926                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     37213921                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     35460411                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu7     38946899                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    296266797                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     82978964                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     86239947                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     87750966                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     88854787                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     87819107                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     83999460                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     88854959                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     87064968                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    693563158                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    196462368                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu2    193595340                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    197409379                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    192312836                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    193341369                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    199367330                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    195358866                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1566898373                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    233544276                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu3    233353305                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    229526757                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    228801780                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    235812748                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    234305765                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1863165170                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    233544276                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    237472777                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    230347762                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    233353305                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    229526757                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    228801780                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    235812748                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    234305765                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1863165170                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    419590422                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    420411799                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    414525738                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    420114597                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    417359247                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    423042782                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    416304244                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    412865244                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3344214073                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    244799897                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    243732417                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    247505386                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    237594430                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    238425396                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    244815873                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    242422406                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    237975886                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1937271691                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    664390319                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    664144216                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    662031124                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    657709027                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    655784643                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    667858655                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    658726650                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    650841130                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5281485764                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.064409                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.068118                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.064166                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.063348                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.062695                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.062428                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.063504                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.067369                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.064498                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.878082                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.883579                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.873946                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.874009                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.888603                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.878654                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.878712                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.869750                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.878125                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.716416                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.726730                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.716696                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.732448                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.716669                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.712268                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.723065                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.708853                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.719124                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.297420                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.304078                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.295508                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.299966                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.287701                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.294946                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.299062                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.297235                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.296970                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.297420                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.304078                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.295508                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.299966                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.287701                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.294946                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.299062                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.297235                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.296970                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50246.487805                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49512.747423                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50071.419619                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49646.306630                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49951.571812                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.211048                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49856.932969                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50318.990956                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49977.529858                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42357.817254                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42399.187316                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42330.422576                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42412.786158                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42342.867406                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42338.437500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42291.746311                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42470.716098                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42367.938790                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43036.663308                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43065.963868                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42992.524983                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43102.484498                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43051.899709                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43079.627674                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43115.772059                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42954.895778                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 43050.206693                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 44040.029417                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 43992.733790                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 43984.678633                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43995.721154                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 44038.134497                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 44051.170581                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 44035.994024                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 44025.885945                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 44020.441110                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 44040.029417                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 43992.733790                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 43984.678633                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43995.721154                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 44038.134497                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 44051.170581                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 44035.994024                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 44025.885945                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 44020.441110                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42667.319707                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42599.229811                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42615.990336                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42633.914857                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42683.498364                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42615.370404                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42614.826901                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42563.427216                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42624.258495                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 44371.922603                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 44639.636813                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 44595.565045                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 44269.504379                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44399.515084                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44536.269420                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 44669.689700                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 44598.179535                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 44510.423927                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 43279.937398                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 43325.997521                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 43335.152451                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038                       # average overall mshr uncacheable latency
+system.l2c.overall_mshr_hits::total                87                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         1195                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         1195                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          2064                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          2004                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          2022                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          2044                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          2053                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          2028                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          2097                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          2076                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        16388                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4627                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4548                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4577                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4615                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4579                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4556                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4715                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4599                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         36816                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0          683                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1          697                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2          705                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3          723                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu4          661                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu5          644                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu6          672                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu7          708                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total         5493                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5310                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5245                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5282                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5338                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5240                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5200                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5387                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5307                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            42309                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5310                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5245                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5282                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5338                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5240                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5200                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5387                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5307                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           42309                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0         9914                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1         9790                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2         9904                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3        10012                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu4         9864                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu5         9627                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu6         9920                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu7         9751                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        78782                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0         5585                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1         5520                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2         5375                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3         5452                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu4         5416                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu5         5446                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu6         5475                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu7         5563                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        43832                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0        15499                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1        15310                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2        15279                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3        15464                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu4        15280                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu5        15073                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu6        15395                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu7        15314                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       122614                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     91133472                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     88462987                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     89280980                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     90268986                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     90591474                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     89517985                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     92579479                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     91580988                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    723416351                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    207502416                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    203985411                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    204607928                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    206817424                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    205245434                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    203808925                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    210680914                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    205992916                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1648641368                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     35739912                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     36064422                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     36944907                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     37169425                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     34229921                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     33582416                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     35467415                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     37159907                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    286358325                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    243242328                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    240049833                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    241552835                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    243986849                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    239475355                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    237391341                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    246148329                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    243152823                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1934999693                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    243242328                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    240049833                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    241552835                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    243986849                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    239475355                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    237391341                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    246148329                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    243152823                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1934999693                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    440524373                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    434529373                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    439498845                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    444350349                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    438452875                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    427687869                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    440147866                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    432536724                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3497728274                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    254487945                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    251283938                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    245260938                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    249610444                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    246551945                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    247817429                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    250267435                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    254241933                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1999522007                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    695012318                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    685813311                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    684759783                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    693960793                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    685004820                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    675505298                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    690415301                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    686778657                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5497250281                       # number of overall MSHR uncacheable cycles
+system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.894668                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.878177                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.874567                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.872386                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.877350                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.878683                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.891961                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.878544                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.880791                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.724213                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.722363                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.716051                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.727803                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717937                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720772                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.732370                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.721412                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.722875                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.059844                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.059777                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.061384                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062039                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.057598                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.055671                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.058885                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.060846                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.059510                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.298281                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.292103                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.295463                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.296638                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.293492                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.290681                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.301793                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.294653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.295384                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.298281                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.292103                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.295463                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.296638                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.293492                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.290681                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.301793                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.294653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.295384                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 45652.180962                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 45734.942754                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 45734.942754                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               84372                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84365                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43521                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43519                       # Transaction distribution
-system.membus.trans_dist::Writeback              6720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60428                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           49463                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             49409                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3325                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       425122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 425122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1143411                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1143411                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            57048                       # Total snoops (count)
-system.membus.snoop_fanout::samples            253034                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               78781                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84254                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43831                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43828                       # Transaction distribution
+system.membus.trans_dist::Writeback              6215                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1216                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            61094                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           50117                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49522                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3101                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5483                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       427442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 427442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1069738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1069738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            57394                       # Total snoops (count)
+system.membus.snoop_fanout::samples            254906                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  253034    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  254906    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              253034                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           288296633                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              60.9                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          308136269                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             65.1                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq             369990                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            369967                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            6                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43524                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43518                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback            76544                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29606                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29605                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           161002                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          160999                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120638                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120231                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120590                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120464                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120699                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120288                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120457                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120419                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                963786                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1770551                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1757664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1763883                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1765044                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1785450                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1756799                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1766043                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1776312                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14141746                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          320975                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           687560                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.membus.snoop_fanout::total              254906                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           291050214                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              56.4                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          309370624                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             59.9                       # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq              78782                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            371328                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43832                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43827                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback            83405                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           20435                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29579                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29579                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           161223                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          161218                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       292561                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       122545                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122537                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122267                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122810                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122614                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       122506                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122579                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122756                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                980614                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1769994                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1778957                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1770860                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1783783                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1787183                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1781792                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1778656                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1778193                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14229418                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          335158                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           800908                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            7.017024                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.129362                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
@@ -1769,29 +1778,29 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                 687560    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                 787273     98.30%     98.30% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                  13635      1.70%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             687560                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          445191055                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             94.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         101323906                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         101013875                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            21.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         101243878                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         101066643                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            21.3                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         101367492                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         100955896                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            21.3                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         101182766                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         101290842                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            21.4                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::max_value              8                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total             800908                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          495395322                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             95.9                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         101110391                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         101309873                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         101121441                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         101199500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         101216377                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         101535375                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            19.7                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         101020631                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            19.6                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         101318353                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            19.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 987ba828d..8965da370 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.133634                       # Number of seconds simulated
-sim_ticks                                133634149500                       # Number of ticks simulated
-final_tick                               133634149500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.133625                       # Number of seconds simulated
+sim_ticks                                133625300500                       # Number of ticks simulated
+final_tick                               133625300500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1329181                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1329181                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2010669405                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301232                       # Number of bytes of host memory used
-host_seconds                                    66.46                       # Real time elapsed on the host
+host_inst_rate                                1195401                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1195401                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1808178963                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302688                       # Number of bytes of host memory used
+host_seconds                                    73.90                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            432896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10136896                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10569792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       432896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          432896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7294848                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7294848                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6764                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158389                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165153                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          113982                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               113982                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3239411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75855581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                79094992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3239411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3239411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54588202                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54588202                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54588202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3239411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75855581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              133683195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            419712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10136000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10555712                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       419712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          419712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7316416                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7316416                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                164933                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114319                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114319                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3140962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             75853899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                78994861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3140962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3140962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54753224                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54753224                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54753224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3140962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            75853899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              133748085                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        267268299                       # number of cpu cycles simulated
+system.cpu.numCycles                        267250601                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88340673                       # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs                      34987415                       # nu
 system.cpu.num_load_insts                    20366786                       # Number of load instructions
 system.cpu.num_store_insts                   14620629                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  267268299                       # Number of busy cycles
+system.cpu.num_busy_cycles                  267250601                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13754477                       # Number of branches fetched
@@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   88438073                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            200248                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4078.863526                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4078.862376                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            34685671                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            169.741568                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         936464000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4078.863526                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         936464500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4078.862376                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995816                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995816                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data       204344                       # n
 system.cpu.dcache.demand_misses::total         204344                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       204344                       # number of overall misses
 system.cpu.dcache.overall_misses::total        204344                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1945427000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1945427000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   7363527000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   7363527000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   9308954000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   9308954000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   9308954000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   9308954000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1944960000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1944960000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   7363504500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   7363504500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9308464500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9308464500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9308464500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9308464500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_miss_rate::total     0.005857                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005857                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45555.308695                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45555.308695                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32007.372544                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32007.372544                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.743638                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.743638                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45552.913225                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45552.913225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45552.913225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45552.913225                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168375                       # number of writebacks
-system.cpu.dcache.writebacks::total            168375                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       168314                       # number of writebacks
+system.cpu.dcache.writebacks::total            168314                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143578                       # number of WriteReq MSHR misses
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       204344
 system.cpu.dcache.demand_mshr_misses::total       204344                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204344                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204344                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1854278000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1854278000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7148160000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   7148160000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9002438000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9002438000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9002438000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   9002438000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1884194000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1884194000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7219926500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7219926500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9104120500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9104120500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9104120500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9104120500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
@@ -226,27 +226,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31007.372544                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31007.372544                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50285.743638                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50285.743638                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44552.913225                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44552.913225                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44552.913225                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44552.913225                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             74391                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1871.686268                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1871.687345                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             76436                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1156.021220                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1871.686268                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.913909                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.913909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1871.687345                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.913910                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.913910                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2045                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          191                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1708                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998535                       # Percentage of cache occupancy per task id
@@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst        76436                       # n
 system.cpu.icache.demand_misses::total          76436                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        76436                       # number of overall misses
 system.cpu.icache.overall_misses::total         76436                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1277887500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1277887500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1277887500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1277887500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1277887500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1277887500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1269528000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1269528000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1269528000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1269528000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1269528000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1269528000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     88438074                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     88438074                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     88438074                       # number of demand (read+write) accesses
@@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000864
 system.cpu.icache.demand_miss_rate::total     0.000864                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000864                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000864                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16718.398399                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16718.398399                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16609.032393                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16609.032393                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16609.032393                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16609.032393                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16609.032393                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16609.032393                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -302,117 +302,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        76436
 system.cpu.icache.demand_mshr_misses::total        76436                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        76436                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        76436                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1163233500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1163233500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1163233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1163233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1163233500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1163233500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1193092000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1193092000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1193092000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1193092000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1193092000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1193092000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000864                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000864                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000864                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15609.032393                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15609.032393                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15609.032393                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15609.032393                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15609.032393                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15609.032393                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           131235                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30728.805700                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             142024                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           163291                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.869760                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           131016                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30726.483059                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             246631                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           163072                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.512406                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1874.509533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1555.853974                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.833082                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057205                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.047481                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.937769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 27128.298594                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1976.305001                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1621.879464                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.827890                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060312                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32056                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          654                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          655                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9977                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        21193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          117                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        21188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          122                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978271                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3900109                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3900109                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        69672                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        33258                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         102930                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168375                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168375                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12697                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12697                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        69672                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        45955                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          115627                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        69672                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        45955                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         115627                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         6764                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        27508                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        34272                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130881                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130881                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         6764                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158389                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        165153                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         6764                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158389                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       165153                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    355241500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1444303000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1799544500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6871263500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6871263500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    355241500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   8315566500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   8670808000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    355241500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   8315566500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   8670808000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        76436                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        60766                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       137202                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168375                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168375                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.tag_accesses          4750002                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4750002                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       168314                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168314                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12698                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12698                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        69878                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        69878                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33271                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        33271                       # number of ReadSharedReq hits
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+system.cpu.l2cache.overall_hits::total         115847                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130880                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130880                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6558                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         6558                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27495                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27495                       # number of ReadSharedReq misses
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+system.cpu.l2cache.overall_misses::cpu.data       158375                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       164933                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6871230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6871230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    344676500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    344676500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1443699500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1443699500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    344676500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8314930000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8659606500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    344676500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8314930000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8659606500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       168314                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168314                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       143578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        76436                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        76436                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        60766                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        60766                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        76436                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       204344                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       280780                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        76436                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       204344                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       280780                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.088492                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.452687                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.249792                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911567                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911567                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088492                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.775110                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.588194                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088492                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.775110                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.588194                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911560                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911560                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.085797                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.085797                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.452473                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.452473                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.085797                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.775041                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.587410                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.085797                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.775041                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.587410                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.233038                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.233038                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52558.173224                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52558.173224                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52507.710493                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52507.710493                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52558.173224                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.531176                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52503.783354                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52558.173224                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.531176                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52503.783354                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -421,105 +427,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       113982                       # number of writebacks
-system.cpu.l2cache.writebacks::total           113982                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         6764                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27508                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        34272                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         6764                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158389                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       165153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         6764                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158389                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       165153                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    274073000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1114207000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1388280000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5300691500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5300691500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    274073000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6414898500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   6688971500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    274073000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6414898500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   6688971500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088492                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.452687                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.249792                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911567                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911567                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088492                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775110                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.588194                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088492                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775110                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.588194                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       114319                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114319                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1879                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1879                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130880                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130880                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6558                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6558                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27495                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27495                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         6558                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158375                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       164933                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         6558                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158375                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       164933                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5562430500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5562430500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    279096500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    279096500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1168749500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1168749500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    279096500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6731180000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7010276500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    279096500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6731180000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   7010276500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911560                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911560                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.085797                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.085797                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.452473                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452473                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.085797                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775041                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.587410                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.085797                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775041                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.587410                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.233038                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.233038                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42558.173224                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42558.173224                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42507.710493                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42507.710493                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42558.173224                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.531176                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42503.783354                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         137202                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        137202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168375                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       282633                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       123022                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143578                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143578                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       152872                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       577063                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            729935                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        76436                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        60766                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       227263                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       608936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            836199                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4891904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23854016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           28745920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       449155                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23850112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           28742016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      131016                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       686435                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.190864                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.392983                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             449155    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             555419     80.91%     80.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             131016     19.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         449155                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      392952500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         686435                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      446023500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy     114654000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     306516000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               34272                       # Transaction distribution
-system.membus.trans_dist::ReadResp              34272                       # Transaction distribution
-system.membus.trans_dist::Writeback            113982                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130881                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130881                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       444288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 444288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17864640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17864640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              34053                       # Transaction distribution
+system.membus.trans_dist::Writeback            114319                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14713                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130880                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130880                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34053                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       458898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 458898                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17872128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17872128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            279135                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294098                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  279135    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294098    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              279135                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           748161500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294098                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           751484676                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          825765500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          824727676                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 90d753109..22fc38403 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.127293                       # Number of seconds simulated
-sim_ticks                                127293406500                       # Number of ticks simulated
-final_tick                               127293406500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                127292683500                       # Number of ticks simulated
+final_tick                               127292683500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 627920                       # Simulator instruction rate (inst/s)
-host_op_rate                                   801678                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1135795886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 312172                       # Number of bytes of host memory used
-host_seconds                                   112.07                       # Real time elapsed on the host
+host_inst_rate                                 884807                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1129650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1600449674                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320712                       # Number of bytes of host memory used
+host_seconds                                    79.54                       # Real time elapsed on the host
 sim_insts                                    70373629                       # Number of instructions simulated
 sim_ops                                      89847363                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            255488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            252800                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7924480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8179968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       255488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          255488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5370176                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5370176                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3992                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total              8177280                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       252800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          252800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5511360                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5511360                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3950                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             123820                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                127812                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83909                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83909                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2007080                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             62253656                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                64260736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2007080                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2007080                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          42187385                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               42187385                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          42187385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2007080                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            62253656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              106448121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                127770                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86115                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86115                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1985974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             62254010                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                64239984                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1985974                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1985974                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          43296754                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               43296754                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          43296754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1985974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            62254010                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              107536738                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        254586813                       # number of cpu cycles simulated
+system.cpu.numCycles                        254585367                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70373629                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                      43422001                       # nu
 system.cpu.num_load_insts                    22866262                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               254586812.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               254585366.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          13741486                       # Number of branches fetched
@@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   90690084                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            155902                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.389329                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42608169                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4076.389202                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42608158                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            266.304385                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1061071000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389329                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.avg_refs            266.304316                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1061071500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389202                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995212                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995212                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3191                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          857                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3190                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22749839                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22749839                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     22749833                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22749833                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83623                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83623                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83618                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83618                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42492708                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42492708                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42576331                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42576331                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        30228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         30228                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      42492702                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42492702                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42576320                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42576320                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        30234                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         30234                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        40121                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        40121                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       137260                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         137260                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       177381                       # number of overall misses
-system.cpu.dcache.overall_misses::total        177381                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    517066000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    517066000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689116000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5689116000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   6206182000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   6206182000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   6206182000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   6206182000                       # number of overall miss cycles
+system.cpu.dcache.SoftPFReq_misses::cpu.data        40126                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        40126                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       137266                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         137266                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       177392                       # number of overall misses
+system.cpu.dcache.overall_misses::total        177392                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    516863000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    516863000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689129500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5689129500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   6205992500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   6205992500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   6205992500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   6205992500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
@@ -280,20 +280,20 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001327
 system.cpu.dcache.ReadReq_miss_rate::total     0.001327                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324226                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.324226                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324266                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.324266                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.003220                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.003220                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.004149                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.004149                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45214.789451                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34987.862285                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45211.432547                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34984.624448                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128239                       # number of writebacks
-system.cpu.dcache.writebacks::total            128239                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1120                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1120                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1120                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1120                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1120                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1120                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks       128193                       # number of writebacks
+system.cpu.dcache.writebacks::total            128193                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1126                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1126                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1126                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1126                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
@@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       136140
 system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    457995500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    457995500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5528568000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5528568000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1058278000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1058278000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5986563500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5986563500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7044841500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7044841500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    472117000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    472117000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5582097500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5582097500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1070376500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1070376500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6054214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6054214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7124591000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7124591000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
@@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             16890                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1733.672960                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1733.672092                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126162                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             18908                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           4131.910408                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1733.672960                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1733.672092                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.846520                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.846520                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
@@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst        18908                       # n
 system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
 system.cpu.icache.overall_misses::total         18908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    413935000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    413935000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    413935000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    413935000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    413935000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    413935000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    412325000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    412325000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    412325000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    412325000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    412325000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    412325000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     78145070                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     78145070                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     78145070                       # number of demand (read+write) accesses
@@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000242
 system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21892.056272                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21892.056272                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21806.907129                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21806.907129                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -418,117 +418,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        18908
 system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    385573000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    385573000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    385573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    385573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    385573000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    385573000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    393417000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    393417000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    393417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    393417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    393417000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    393417000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            94693                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30351.005772                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              74295                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           125788                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.590637                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            94651                       # number of replacements
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+system.cpu.l2cache.tags.total_refs             114091                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           125746                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.907313                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1151.768393                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1402.369526                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.848293                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035149                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_blocks::cpu.data  1482.597680                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31095                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1359                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        15103                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13917                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          607                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1360                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13873                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948944                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2689980                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2689980                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        14916                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        31426                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          46342                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       128239                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128239                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses          3016794                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3016794                       # Number of data accesses
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 system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        14916                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.data        36178                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          51094                       # number of overall hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data       102280                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       102280                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3992                       # number of demand (read+write) misses
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 system.cpu.l2cache.demand_misses::cpu.data       123820                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.data       123820                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       127812                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    210047000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1133331500                       # number of ReadReq miss cycles
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data       107032                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       107032                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        18908                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        18908                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        52966                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        52966                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        18908                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       159998                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       178906                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        18908                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       159998                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.211128                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.406676                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.355233                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955602                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.955602                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.211128                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.208906                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.208906                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.406676                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.406676                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.208906                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.773885                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.714409                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.211128                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.714174                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.208906                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.773885                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.714409                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.714174                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -537,105 +543,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83909                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83909                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3992                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21540                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        25532                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        86115                       # number of writebacks
+system.cpu.l2cache.writebacks::total            86115                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1102                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1102                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102280                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       102280                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3992                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3950                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3950                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21540                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21540                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3950                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       123820                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       127812                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3992                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       127770                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3950                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       123820                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       127812                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    161778000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    873989500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1035767500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4142346500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4142346500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    161778000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5016336000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5178114000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    161778000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5016336000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5178114000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.406676                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.355233                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total       127770                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4348853500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4348853500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    168471500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    168471500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    917668500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    917668500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    168471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5266522000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5434993500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    168471500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5266522000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5434993500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955602                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955602                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.208906                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.208906                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.406676                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.406676                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.208906                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773885                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.714409                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.714174                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.208906                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773885                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.714409                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.714174                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128239                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       214308                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        49439                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       107032                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       107032                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        37816                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       448235                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            486051                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        18908                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        52966                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        53606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473302                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            526908                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1210112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18447168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           19657280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       307145                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18444224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           19654336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       94651                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       446349                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.212056                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.408765                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             307145    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             351698     78.79%     78.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              94651     21.21%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         307145                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      281811500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         446349                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      304042000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      28362000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     239997000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               25532                       # Transaction distribution
-system.membus.trans_dist::ReadResp              25532                       # Transaction distribution
-system.membus.trans_dist::Writeback             83909                       # Transaction distribution
+system.membus.trans_dist::ReadResp              25490                       # Transaction distribution
+system.membus.trans_dist::Writeback             86115                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6526                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       339533                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 339533                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13550144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13550144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         25490                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       348181                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 348181                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13688640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13688640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            214640                       # Request fanout histogram
+system.membus.snoop_fanout::samples            220592                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  214640    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  220592    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              214640                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           566253984                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              220592                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           568748288                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          642220500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          641607492                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 718e317fa..e9eb9ae35 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,44 +1,44 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.202242                       # Number of seconds simulated
-sim_ticks                                202242028500                       # Number of ticks simulated
-final_tick                               202242028500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.202233                       # Number of seconds simulated
+sim_ticks                                202232894500                       # Number of ticks simulated
+final_tick                               202232894500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1201078                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1216630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1807368744                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300888                       # Number of bytes of host memory used
-host_seconds                                   111.90                       # Real time elapsed on the host
+host_inst_rate                                1204132                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1219723                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1811881435                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302340                       # Number of bytes of host memory used
+host_seconds                                   111.61                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            591488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7826624                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8418112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       591488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          591488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5303552                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5303552                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               9242                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             122291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                131533                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           82868                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                82868                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2924654                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             38699295                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                41623950                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2924654                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2924654                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          26223788                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               26223788                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          26223788                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2924654                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38699295                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               67847737                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            575680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7827008                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8402688                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       575680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          575680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5453120                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5453120                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               8995                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             122297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                131292                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           85205                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                85205                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2846619                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38702942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                41549561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2846619                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2846619                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          26964555                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               26964555                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          26964555                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2846619                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38702942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               68514116                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        404484057                       # number of cpu cycles simulated
+system.cpu.numCycles                        404465789                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   134398962                       # Number of instructions committed
@@ -57,7 +57,7 @@ system.cpu.num_mem_refs                      58160248                       # nu
 system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               404484056.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               404465788.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
@@ -97,18 +97,18 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  136293798                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            146582                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.648320                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4087.647933                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            57960842                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            384.666919                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         769041000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.648320                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         769041500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.647933                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          529                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3530                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          530                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3529                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         116373718                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        116373718                       # Number of data accesses
@@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data       150663                       # n
 system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
 system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1475000000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1475000000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5619674000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5619674000                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1475169000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1475169000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5620115500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5620115500                       # number of WriteReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::cpu.data       405000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::total       405000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7094674000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7094674000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7094674000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7094674000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7095284500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7095284500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7095284500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7095284500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
@@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086                       # average WriteReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        27000                       # average SwapReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::total        27000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47089.690236                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47089.690236                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47093.742326                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47093.742326                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -180,8 +180,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       123970                       # number of writebacks
-system.cpu.dcache.writebacks::total            123970                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       123896                       # number of writebacks
+system.cpu.dcache.writebacks::total            123896                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       105164                       # number of WriteReq MSHR misses
@@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       150663
 system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1406751500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1406751500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5461928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5461928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       382500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total       382500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6868679500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6868679500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6868679500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6868679500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1429670000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1429670000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5514951500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5514951500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       390000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       390000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6944621500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6944621500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6944621500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6944621500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
@@ -212,29 +212,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        25500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        25500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        26000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        26000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            184976                       # number of replacements
-system.cpu.icache.tags.tagsinuse          2004.815289                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          2004.814775                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366547                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs            187024                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs            718.445478                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      143972077000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  2004.815289                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.978914                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.978914                       # Average percentage of cache occupancy
+system.cpu.icache.tags.warmup_cycle      143962972500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  2004.814775                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.978913                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.978913                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          456                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1427                       # Occupied blocks per task id
@@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst       187024                       # n
 system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
 system.cpu.icache.overall_misses::total        187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2819561500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2819561500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2819561500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2819561500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2819561500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2819561500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2809817000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2809817000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2809817000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2809817000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2809817000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2809817000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    134553571                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    134553571                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    134553571                       # number of demand (read+write) accesses
@@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001390
 system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15075.934105                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15075.934105                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15023.831166                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15023.831166                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -291,117 +291,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       187024
 system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2539025500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2539025500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2539025500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2539025500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2539025500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2539025500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2622793000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2622793000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2622793000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2622793000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2622793000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2622793000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            98540                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30850.758845                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             226933                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129534                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.751918                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            98298                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30848.444766                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             433066                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129294                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.349467                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3385.945467                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1219.264265                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.800951                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.103331                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.037209                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.941490                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        30994                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          533                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12212                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17536                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          585                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.945862                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3928089                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3928089                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       177782                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total         202246                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       123970                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       123970                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         3923                       # number of ReadExReq hits
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-system.cpu.l2cache.overall_hits::total         206169                       # number of overall hits
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    485290500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1104380500                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total       232523                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       123970                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       123970                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3594.810202                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1299.805624                       # Average occupied blocks per requestor
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 system.cpu.l2cache.demand_accesses::cpu.data       150678                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data       150678                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       337702                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.049416                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.962702                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.389494                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.962730                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.962730                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.048095                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.048095                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.462384                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.462384                       # miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.overall_miss_rate::total     0.388781                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52503.115772                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52503.115772                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52539.688716                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52539.688716                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.087841                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.087841                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52539.688716                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.282991                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52505.777199                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52539.688716                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.282991                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52505.777199                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -410,105 +416,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        82868                       # number of writebacks
-system.cpu.l2cache.writebacks::total            82868                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9242                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21035                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        30277                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101256                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       101256                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9242                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       122291                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       131533                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9242                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       122291                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       131533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    374386000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    851960500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1226346500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4100868000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4100868000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    374386000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4952828500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5327214500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    374386000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4952828500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5327214500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.049416                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.462318                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.130211                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.962702                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.962702                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.049416                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.811605                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.389494                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.049416                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.811605                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.389494                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        85205                       # number of writebacks
+system.cpu.l2cache.writebacks::total            85205                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1630                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1630                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101259                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       101259                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8995                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8995                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21038                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21038                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8995                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       122297                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       131292                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8995                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       122297                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       131292                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4303823000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4303823000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    382644500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    382644500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    894201000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    894201000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    382644500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5198024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5580668500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    382644500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5198024000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5580668500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.962730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.962730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.048095                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.048095                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.462384                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.462384                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.048095                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.811645                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.388781                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.048095                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.811645                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.388781                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42503.115772                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42503.115772                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42539.688716                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42539.688716                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.087841                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.087841                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42539.688716                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42503.282991                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.777199                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         232523                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        232523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       123970                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       209101                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       220689                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       105179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       105179                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       374048                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       425326                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            799374                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       187024                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        45499                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       558971                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       447925                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1006896                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11969536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     17577472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           29547008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       461672                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     17572736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           29542272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       98298                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       767558                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.128066                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.334163                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             461672    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             669260     87.19%     87.19% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              98298     12.81%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         461672                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      354806000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         767558                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      458526000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy     280536000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     226017000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               30277                       # Transaction distribution
-system.membus.trans_dist::ReadResp              30277                       # Transaction distribution
-system.membus.trans_dist::Writeback             82868                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            101256                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           101256                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       345934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 345934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13721664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13721664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              30033                       # Transaction distribution
+system.membus.trans_dist::Writeback             85205                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            11182                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            101259                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           101259                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30033                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       358971                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 358971                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13855808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13855808                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            214401                       # Request fanout histogram
+system.membus.snoop_fanout::samples            227790                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  214401    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  227790    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              214401                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           558284500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              227790                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           569073488                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          657665500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          656842488                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index b30732380..45eadd1aa 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000180                       # Number of seconds simulated
-sim_ticks                                      180391                       # Number of ticks simulated
-final_tick                                     180391                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000182                       # Number of seconds simulated
+sim_ticks                                      181651                       # Number of ticks simulated
+final_tick                                     181651                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2115130                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447992                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                2259116                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 450116                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        54784                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              54784                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        49408                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           49408                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          856                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 856                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          772                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                772                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    303695861                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             303695861                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    273893930                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            273893930                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    577589791                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            577589791                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         856                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        772                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       856                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      772                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  46080                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    8704                       # Total number of bytes read from write queue
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        55232                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              55232                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        49600                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           49600                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          863                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 863                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          775                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                775                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    304055579                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             304055579                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    273051070                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            273051070                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    577106650                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            577106650                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         863                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        775                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       863                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      775                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  46400                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    8832                       # Total number of bytes read from write queue
 system.mem_ctrls.bytesWritten                   41792                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   54784                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                49408                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    136                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    92                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytesReadSys                   55232                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                49600                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    138                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    94                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               208                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1               240                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               223                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0               209                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1               243                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               224                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                49                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
@@ -51,8 +51,8 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               188                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               213                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               190                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               211                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2               206                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                46                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
@@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        180206                       # Total gap between requests
+system.mem_ctrls.totGap                        181412                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   856                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   863                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  772                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     595                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     121                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  775                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     599                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     122                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       4                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -143,7 +143,7 @@ system.mem_ctrls.wrQLenPdf::23                     38                       # Wh
 system.mem_ctrls.wrQLenPdf::24                     40                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                     39                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::26                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     37                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     38                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     37                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                     37                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                     37                       # What write queue length does an incoming req see
@@ -181,16 +181,16 @@ system.mem_ctrls.wrQLenPdf::61                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.bytesPerActivate::samples          136                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    643.294118                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   479.730496                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   374.748392                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    644.235294                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   480.374054                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   374.900762                       # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::0-127           10      7.35%      7.35% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::128-255           25     18.38%     25.74% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::256-383            7      5.15%     30.88% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::384-511           10      7.35%     38.24% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::512-639            8      5.88%     44.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            7      5.15%     49.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           10      7.35%     56.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            6      4.41%     48.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895           11      8.09%     56.62% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::896-1023            7      5.15%     61.76% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::1024-1151           52     38.24%    100.00% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::total          136                       # Bytes accessed per row activation
@@ -216,38 +216,38 @@ system.mem_ctrls.wrPerTurnAround::17                1      2.70%     24.32% # Wr
 system.mem_ctrls.wrPerTurnAround::18               24     64.86%     89.19% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::19                4     10.81%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            37                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         6996                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   20676                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3600                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         9.72                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         6696                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   20471                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3625                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         9.24                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   28.72                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       255.45                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       231.67                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    303.70                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    273.89                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   28.24                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       255.43                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       230.07                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    304.06                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    273.05                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         3.81                       # Data bus utilization in percentage
+system.mem_ctrls.busUtil                         3.79                       # Data bus utilization in percentage
 system.mem_ctrls.busUtilRead                     2.00                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    1.81                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtilWrite                    1.80                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.28                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.66                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      589                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      24.68                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      593                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                     645                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.81                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                94.85                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                        110.69                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    88.14                       # Row buffer hit rate, read and write combined
+system.mem_ctrls.readRowHitRate                 81.79                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                94.71                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                        110.75                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    88.05                       # Row buffer hit rate, read and write combined
 system.mem_ctrls_0.actEnergy                  1028160                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_0.preEnergy                   571200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 8910720                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 8935680                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                6770304                       # Energy for write commands per rank (pJ)
 system.mem_ctrls_0.refreshEnergy             11696880                       # Energy for refresh commands per rank (pJ)
 system.mem_ctrls_0.actBackEnergy            121998240                       # Energy for active background per rank (pJ)
 system.mem_ctrls_0.preBackEnergy               586800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy              151562304                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            845.120967                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE          348                       # Time in different power states
+system.mem_ctrls_0.totalEnergy              151587264                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            845.260146                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE          392                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          5980                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT        173024                       # Time in different power states
@@ -269,172 +269,172 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       #
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples         1008                      
-system.ruby.outstanding_req_hist::mean      15.793651                      
-system.ruby.outstanding_req_hist::gmean     15.695353                      
-system.ruby.outstanding_req_hist::stdev      1.131423                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.69% |           2      0.20%      0.89% |           2      0.20%      1.09% |           2      0.20%      1.29% |          88      8.73%     10.02% |         907     89.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          1008                      
+system.ruby.outstanding_req_hist::samples         1014                      
+system.ruby.outstanding_req_hist::mean      15.795858                      
+system.ruby.outstanding_req_hist::gmean     15.698068                      
+system.ruby.outstanding_req_hist::stdev      1.128795                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.49% |           2      0.20%      0.69% |           2      0.20%      0.89% |           2      0.20%      1.08% |           2      0.20%      1.28% |          86      8.48%      9.76% |         915     90.24%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          1014                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples                 993                      
-system.ruby.latency_hist::mean            2869.644512                      
-system.ruby.latency_hist::gmean           1439.923884                      
-system.ruby.latency_hist::stdev           1437.510562                      
-system.ruby.latency_hist                 |         203     20.44%     20.44% |           6      0.60%     21.05% |         136     13.70%     34.74% |         530     53.37%     88.12% |         116     11.68%     99.80% |           2      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                   993                      
+system.ruby.latency_hist::samples                1000                      
+system.ruby.latency_hist::mean            2871.187000                      
+system.ruby.latency_hist::gmean           1437.111770                      
+system.ruby.latency_hist::stdev           1430.830977                      
+system.ruby.latency_hist                 |         202     20.20%     20.20% |           6      0.60%     20.80% |         139     13.90%     34.70% |         535     53.50%     88.20% |         116     11.60%     99.80% |           2      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  1000                      
 system.ruby.hit_latency_hist::bucket_size          512                      
 system.ruby.hit_latency_hist::max_bucket         5119                      
-system.ruby.hit_latency_hist::samples             140                      
-system.ruby.hit_latency_hist::mean         712.971429                      
-system.ruby.hit_latency_hist::gmean         27.405302                      
-system.ruby.hit_latency_hist::stdev       1358.773103                      
-system.ruby.hit_latency_hist             |         110     78.57%     78.57% |           2      1.43%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1      0.71%     80.71% |           9      6.43%     87.14% |          10      7.14%     94.29% |           4      2.86%     97.14% |           4      2.86%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               140                      
+system.ruby.hit_latency_hist::samples             141                      
+system.ruby.hit_latency_hist::mean         724.687943                      
+system.ruby.hit_latency_hist::gmean         26.569121                      
+system.ruby.hit_latency_hist::stdev       1368.603016                      
+system.ruby.hit_latency_hist             |         110     78.01%     78.01% |           2      1.42%     79.43% |           0      0.00%     79.43% |           0      0.00%     79.43% |           1      0.71%     80.14% |          10      7.09%     87.23% |          10      7.09%     94.33% |           4      2.84%     97.16% |           4      2.84%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               141                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples            853                      
-system.ruby.miss_latency_hist::mean       3223.611958                      
-system.ruby.miss_latency_hist::gmean      2758.799775                      
-system.ruby.miss_latency_hist::stdev      1102.294906                      
-system.ruby.miss_latency_hist            |          91     10.67%     10.67% |           6      0.70%     11.37% |         126     14.77%     26.14% |         516     60.49%     86.64% |         112     13.13%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              853                      
-system.ruby.Directory.incomplete_times            853                      
+system.ruby.miss_latency_hist::samples            859                      
+system.ruby.miss_latency_hist::mean       3223.522701                      
+system.ruby.miss_latency_hist::gmean      2766.758930                      
+system.ruby.miss_latency_hist::stdev      1093.907352                      
+system.ruby.miss_latency_hist            |          90     10.48%     10.48% |           6      0.70%     11.18% |         128     14.90%     26.08% |         521     60.65%     86.73% |         112     13.04%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              859                      
+system.ruby.Directory.incomplete_times            859                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           80                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          854                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          934                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           82                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          859                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          941                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           58                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           58                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           57                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses          855                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses          912                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            7                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.L1Icache.demand_misses           57                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           57                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           55                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses          861                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses          916                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            8                       # Number of times a store aliased with a pending load
 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           86                       # Number of times a store aliased with a pending store
 system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            5                       # Number of times a load aliased with a pending store
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     2.513845                      
-system.ruby.network.routers0.msg_count.Request_Control::2          858                      
-system.ruby.network.routers0.msg_count.Response_Data::4          856                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2          851                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5          852                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         6864                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6808                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6816                      
-system.ruby.network.routers1.percent_links_utilized     2.513291                      
-system.ruby.network.routers1.msg_count.Request_Control::2          856                      
-system.ruby.network.routers1.msg_count.Response_Data::4          856                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2          850                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5          851                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         6848                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6800                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6808                      
-system.ruby.network.routers2.percent_links_utilized     2.513429                      
-system.ruby.network.routers2.msg_count.Request_Control::2          856                      
-system.ruby.network.routers2.msg_count.Response_Data::4          856                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2          851                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5          851                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         6848                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6808                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6808                      
-system.ruby.network.msg_count.Request_Control         2570                      
-system.ruby.network.msg_count.Response_Data         2568                      
-system.ruby.network.msg_count.Writeback_Data         2316                      
-system.ruby.network.msg_count.Writeback_Control         5330                      
-system.ruby.network.msg_count.Unblock_Control         2554                      
-system.ruby.network.msg_byte.Request_Control        20560                      
-system.ruby.network.msg_byte.Response_Data       184896                      
-system.ruby.network.msg_byte.Writeback_Data       166752                      
-system.ruby.network.msg_byte.Writeback_Control        42640                      
-system.ruby.network.msg_byte.Unblock_Control        20432                      
-system.ruby.network.routers0.throttle0.link_utilization     2.370684                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          856                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers0.throttle1.link_utilization     2.657006                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          858                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          851                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          852                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         6864                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6808                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6816                      
-system.ruby.network.routers1.throttle0.link_utilization     2.655897                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          856                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          850                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          851                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         6848                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6800                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6808                      
-system.ruby.network.routers1.throttle1.link_utilization     2.370684                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          856                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers2.throttle0.link_utilization     2.370684                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          856                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          849                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        61632                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6792                      
-system.ruby.network.routers2.throttle1.link_utilization     2.656175                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          856                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          772                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          851                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          851                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         6848                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        55584                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6808                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6808                      
+system.ruby.network.routers0.percent_links_utilized     2.514299                      
+system.ruby.network.routers0.msg_count.Request_Control::2          863                      
+system.ruby.network.routers0.msg_count.Response_Data::4          863                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5          777                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2          856                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5          857                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5        55944                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6848                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6856                      
+system.ruby.network.routers1.percent_links_utilized     2.512786                      
+system.ruby.network.routers1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers1.msg_count.Response_Data::4          863                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5          776                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5          856                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5        55872                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6848                      
+system.ruby.network.routers2.percent_links_utilized     2.513061                      
+system.ruby.network.routers2.msg_count.Request_Control::2          863                      
+system.ruby.network.routers2.msg_count.Response_Data::4          863                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5          776                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2          856                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5          857                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5        55872                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6848                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6856                      
+system.ruby.network.msg_count.Request_Control         2589                      
+system.ruby.network.msg_count.Response_Data         2589                      
+system.ruby.network.msg_count.Writeback_Data         2329                      
+system.ruby.network.msg_count.Writeback_Control         5366                      
+system.ruby.network.msg_count.Unblock_Control         2570                      
+system.ruby.network.msg_byte.Request_Control        20712                      
+system.ruby.network.msg_byte.Response_Data       186408                      
+system.ruby.network.msg_byte.Writeback_Data       167688                      
+system.ruby.network.msg_byte.Writeback_Control        42928                      
+system.ruby.network.msg_byte.Unblock_Control        20560                      
+system.ruby.network.routers0.throttle0.link_utilization     2.373232                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          863                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers0.throttle1.link_utilization     2.655367                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          777                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          856                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          857                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        55944                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6848                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6856                      
+system.ruby.network.routers1.throttle0.link_utilization     2.652339                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          863                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          776                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          856                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        55872                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6848                      
+system.ruby.network.routers1.throttle1.link_utilization     2.373232                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          863                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers2.throttle0.link_utilization     2.373232                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          863                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          855                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        62136                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6840                      
+system.ruby.network.routers2.throttle1.link_utilization     2.652889                      
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          776                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          856                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           78                      
+system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          857                      
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        55872                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6848                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          624                      
+system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6856                      
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples               42                      
-system.ruby.LD.latency_hist::mean         3027.476190                      
-system.ruby.LD.latency_hist::gmean        1653.479867                      
-system.ruby.LD.latency_hist::stdev        1407.091452                      
-system.ruby.LD.latency_hist              |           5     11.90%     11.90% |           2      4.76%     16.67% |           1      2.38%     19.05% |           0      0.00%     19.05% |           0      0.00%     19.05% |           5     11.90%     30.95% |          11     26.19%     57.14% |          14     33.33%     90.48% |           1      2.38%     92.86% |           3      7.14%    100.00%
-system.ruby.LD.latency_hist::total                 42                      
+system.ruby.LD.latency_hist::samples               43                      
+system.ruby.LD.latency_hist::mean         2957.116279                      
+system.ruby.LD.latency_hist::gmean        1414.337715                      
+system.ruby.LD.latency_hist::stdev        1464.799632                      
+system.ruby.LD.latency_hist              |           6     13.95%     13.95% |           2      4.65%     18.60% |           1      2.33%     20.93% |           0      0.00%     20.93% |           0      0.00%     20.93% |           5     11.63%     32.56% |          11     25.58%     58.14% |          14     32.56%     90.70% |           1      2.33%     93.02% |           3      6.98%    100.00%
+system.ruby.LD.latency_hist::total                 43                      
 system.ruby.LD.hit_latency_hist::bucket_size           64                      
 system.ruby.LD.hit_latency_hist::max_bucket          639                      
-system.ruby.LD.hit_latency_hist::samples            4                      
-system.ruby.LD.hit_latency_hist::mean             142                      
-system.ruby.LD.hit_latency_hist::gmean       6.410729                      
-system.ruby.LD.hit_latency_hist::stdev     280.668250                      
-system.ruby.LD.hit_latency_hist          |           3     75.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              4                      
+system.ruby.LD.hit_latency_hist::samples            5                      
+system.ruby.LD.hit_latency_hist::mean             114                      
+system.ruby.LD.hit_latency_hist::gmean       5.078459                      
+system.ruby.LD.hit_latency_hist::stdev            251                      
+system.ruby.LD.hit_latency_hist          |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              5                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
 system.ruby.LD.miss_latency_hist::samples           38                      
@@ -445,36 +445,36 @@ system.ruby.LD.miss_latency_hist         |           2      5.26%      5.26% |
 system.ruby.LD.miss_latency_hist::total            38                      
 system.ruby.ST.latency_hist::bucket_size         1024                      
 system.ruby.ST.latency_hist::max_bucket         10239                      
-system.ruby.ST.latency_hist::samples              890                      
-system.ruby.ST.latency_hist::mean         3023.052809                      
-system.ruby.ST.latency_hist::gmean        1627.027590                      
-system.ruby.ST.latency_hist::stdev        1328.502697                      
-system.ruby.ST.latency_hist              |         138     15.51%     15.51% |           5      0.56%     16.07% |         131     14.72%     30.79% |         503     56.52%     87.30% |         111     12.47%     99.78% |           2      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                890                      
+system.ruby.ST.latency_hist::samples              896                      
+system.ruby.ST.latency_hist::mean         3023.541295                      
+system.ruby.ST.latency_hist::gmean        1629.541922                      
+system.ruby.ST.latency_hist::stdev        1321.027864                      
+system.ruby.ST.latency_hist              |         137     15.29%     15.29% |           5      0.56%     15.85% |         134     14.96%     30.80% |         507     56.58%     87.39% |         111     12.39%     99.78% |           2      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total                896                      
 system.ruby.ST.hit_latency_hist::bucket_size          512                      
 system.ruby.ST.hit_latency_hist::max_bucket         5119                      
-system.ruby.ST.hit_latency_hist::samples          122                      
-system.ruby.ST.hit_latency_hist::mean      712.459016                      
-system.ruby.ST.hit_latency_hist::gmean      27.014946                      
-system.ruby.ST.hit_latency_hist::stdev    1340.432607                      
-system.ruby.ST.hit_latency_hist          |          96     78.69%     78.69% |           1      0.82%     79.51% |           0      0.00%     79.51% |           0      0.00%     79.51% |           1      0.82%     80.33% |           9      7.38%     87.70% |          10      8.20%     95.90% |           2      1.64%     97.54% |           3      2.46%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            122                      
+system.ruby.ST.hit_latency_hist::samples          121                      
+system.ruby.ST.hit_latency_hist::mean      709.628099                      
+system.ruby.ST.hit_latency_hist::gmean      25.582566                      
+system.ruby.ST.hit_latency_hist::stdev    1339.163079                      
+system.ruby.ST.hit_latency_hist          |          95     78.51%     78.51% |           1      0.83%     79.34% |           0      0.00%     79.34% |           0      0.00%     79.34% |           1      0.83%     80.17% |          10      8.26%     88.43% |           9      7.44%     95.87% |           2      1.65%     97.52% |           3      2.48%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total            121                      
 system.ruby.ST.miss_latency_hist::bucket_size         1024                      
 system.ruby.ST.miss_latency_hist::max_bucket        10239                      
-system.ruby.ST.miss_latency_hist::samples          768                      
-system.ruby.ST.miss_latency_hist::mean    3390.100260                      
-system.ruby.ST.miss_latency_hist::gmean   3119.766603                      
-system.ruby.ST.miss_latency_hist::stdev    882.096753                      
-system.ruby.ST.miss_latency_hist         |          41      5.34%      5.34% |           5      0.65%      5.99% |         121     15.76%     21.74% |         491     63.93%     85.68% |         108     14.06%     99.74% |           2      0.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           768                      
+system.ruby.ST.miss_latency_hist::samples          775                      
+system.ruby.ST.miss_latency_hist::mean    3384.810323                      
+system.ruby.ST.miss_latency_hist::gmean   3117.032073                      
+system.ruby.ST.miss_latency_hist::stdev    878.738069                      
+system.ruby.ST.miss_latency_hist         |          41      5.29%      5.29% |           5      0.65%      5.94% |         123     15.87%     21.81% |         496     64.00%     85.81% |         108     13.94%     99.74% |           2      0.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total           775                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
 system.ruby.IFETCH.latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist::samples           58                      
-system.ruby.IFETCH.latency_hist::mean      343.913793                      
-system.ruby.IFETCH.latency_hist::gmean     189.679476                      
-system.ruby.IFETCH.latency_hist::stdev     245.446052                      
-system.ruby.IFETCH.latency_hist          |          14     24.14%     24.14% |           9     15.52%     39.66% |          10     17.24%     56.90% |          11     18.97%     75.86% |           6     10.34%     86.21% |           6     10.34%     96.55% |           1      1.72%     98.28% |           1      1.72%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total             58                      
+system.ruby.IFETCH.latency_hist::samples           57                      
+system.ruby.IFETCH.latency_hist::mean      343.526316                      
+system.ruby.IFETCH.latency_hist::gmean     188.406917                      
+system.ruby.IFETCH.latency_hist::stdev     245.127161                      
+system.ruby.IFETCH.latency_hist          |          14     24.56%     24.56% |           8     14.04%     38.60% |          10     17.54%     56.14% |          12     21.05%     77.19% |           5      8.77%     85.96% |           6     10.53%     96.49% |           1      1.75%     98.25% |           1      1.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total             57                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket          159                      
 system.ruby.IFETCH.hit_latency_hist::samples           11                      
@@ -485,60 +485,60 @@ system.ruby.IFETCH.hit_latency_hist      |           8     72.73%     72.73% |
 system.ruby.IFETCH.hit_latency_hist::total           11                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist::samples           47                      
-system.ruby.IFETCH.miss_latency_hist::mean   416.127660                      
-system.ruby.IFETCH.miss_latency_hist::gmean   348.839643                      
-system.ruby.IFETCH.miss_latency_hist::stdev   214.528058                      
-system.ruby.IFETCH.miss_latency_hist     |           3      6.38%      6.38% |           9     19.15%     25.53% |          10     21.28%     46.81% |          11     23.40%     70.21% |           6     12.77%     82.98% |           6     12.77%     95.74% |           1      2.13%     97.87% |           1      2.13%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           47                      
+system.ruby.IFETCH.miss_latency_hist::samples           46                      
+system.ruby.IFETCH.miss_latency_hist::mean   417.217391                      
+system.ruby.IFETCH.miss_latency_hist::gmean   350.554490                      
+system.ruby.IFETCH.miss_latency_hist::stdev   213.226527                      
+system.ruby.IFETCH.miss_latency_hist     |           3      6.52%      6.52% |           8     17.39%     23.91% |          10     21.74%     45.65% |          12     26.09%     71.74% |           5     10.87%     82.61% |           6     13.04%     95.65% |           1      2.17%     97.83% |           1      2.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total           46                      
 system.ruby.FLUSH.latency_hist::bucket_size          512                      
 system.ruby.FLUSH.latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.latency_hist::samples             3                      
-system.ruby.FLUSH.latency_hist::mean      3979.666667                      
-system.ruby.FLUSH.latency_hist::gmean     3955.937145                      
-system.ruby.FLUSH.latency_hist::stdev      544.674521                      
-system.ruby.FLUSH.latency_hist           |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.latency_hist::total               3                      
+system.ruby.FLUSH.latency_hist::samples             4                      
+system.ruby.FLUSH.latency_hist::mean      3839.250000                      
+system.ruby.FLUSH.latency_hist::gmean     3813.994404                      
+system.ruby.FLUSH.latency_hist::stdev      525.972987                      
+system.ruby.FLUSH.latency_hist           |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.latency_hist::total               4                      
 system.ruby.FLUSH.hit_latency_hist::bucket_size          512                      
 system.ruby.FLUSH.hit_latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.hit_latency_hist::samples            3                      
-system.ruby.FLUSH.hit_latency_hist::mean  3979.666667                      
-system.ruby.FLUSH.hit_latency_hist::gmean  3955.937145                      
-system.ruby.FLUSH.hit_latency_hist::stdev   544.674521                      
-system.ruby.FLUSH.hit_latency_hist       |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.hit_latency_hist::total            3                      
+system.ruby.FLUSH.hit_latency_hist::samples            4                      
+system.ruby.FLUSH.hit_latency_hist::mean  3839.250000                      
+system.ruby.FLUSH.hit_latency_hist::gmean  3813.994404                      
+system.ruby.FLUSH.hit_latency_hist::stdev   525.972987                      
+system.ruby.FLUSH.hit_latency_hist       |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.hit_latency_hist::total            4                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size          512                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket         5119                      
-system.ruby.L1Cache.hit_mach_latency_hist::samples           83                      
-system.ruby.L1Cache.hit_mach_latency_hist::mean   166.963855                      
-system.ruby.L1Cache.hit_mach_latency_hist::gmean     6.137177                      
-system.ruby.L1Cache.hit_mach_latency_hist::stdev   748.877672                      
-system.ruby.L1Cache.hit_mach_latency_hist |          80     96.39%     96.39% |           0      0.00%     96.39% |           0      0.00%     96.39% |           0      0.00%     96.39% |           0      0.00%     96.39% |           0      0.00%     96.39% |           0      0.00%     96.39% |           2      2.41%     98.80% |           1      1.20%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total           83                      
+system.ruby.L1Cache.hit_mach_latency_hist::samples           86                      
+system.ruby.L1Cache.hit_mach_latency_hist::mean   200.941860                      
+system.ruby.L1Cache.hit_mach_latency_hist::gmean     6.465766                      
+system.ruby.L1Cache.hit_mach_latency_hist::stdev   815.375069                      
+system.ruby.L1Cache.hit_mach_latency_hist |          82     95.35%     95.35% |           0      0.00%     95.35% |           0      0.00%     95.35% |           0      0.00%     95.35% |           0      0.00%     95.35% |           0      0.00%     95.35% |           1      1.16%     96.51% |           2      2.33%     98.84% |           1      1.16%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total           86                      
 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size          512                      
 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket         5119                      
-system.ruby.L2Cache.hit_mach_latency_hist::samples           57                      
-system.ruby.L2Cache.hit_mach_latency_hist::mean  1508.035088                      
-system.ruby.L2Cache.hit_mach_latency_hist::gmean   242.175752                      
-system.ruby.L2Cache.hit_mach_latency_hist::stdev  1635.914870                      
-system.ruby.L2Cache.hit_mach_latency_hist |          30     52.63%     52.63% |           2      3.51%     56.14% |           0      0.00%     56.14% |           0      0.00%     56.14% |           1      1.75%     57.89% |           9     15.79%     73.68% |          10     17.54%     91.23% |           2      3.51%     94.74% |           3      5.26%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total           57                      
+system.ruby.L2Cache.hit_mach_latency_hist::samples           55                      
+system.ruby.L2Cache.hit_mach_latency_hist::mean  1543.636364                      
+system.ruby.L2Cache.hit_mach_latency_hist::gmean   242.142059                      
+system.ruby.L2Cache.hit_mach_latency_hist::stdev  1640.017066                      
+system.ruby.L2Cache.hit_mach_latency_hist |          28     50.91%     50.91% |           2      3.64%     54.55% |           0      0.00%     54.55% |           0      0.00%     54.55% |           1      1.82%     56.36% |          10     18.18%     74.55% |           9     16.36%     90.91% |           2      3.64%     94.55% |           3      5.45%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total           55                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size         1024                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket        10239                      
-system.ruby.Directory.miss_mach_latency_hist::samples          853                      
-system.ruby.Directory.miss_mach_latency_hist::mean  3223.611958                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  2758.799775                      
-system.ruby.Directory.miss_mach_latency_hist::stdev  1102.294906                      
-system.ruby.Directory.miss_mach_latency_hist |          91     10.67%     10.67% |           6      0.70%     11.37% |         126     14.77%     26.14% |         516     60.49%     86.64% |         112     13.13%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total          853                      
+system.ruby.Directory.miss_mach_latency_hist::samples          859                      
+system.ruby.Directory.miss_mach_latency_hist::mean  3223.522701                      
+system.ruby.Directory.miss_mach_latency_hist::gmean  2766.758930                      
+system.ruby.Directory.miss_mach_latency_hist::stdev  1093.907352                      
+system.ruby.Directory.miss_mach_latency_hist |          90     10.48%     10.48% |           6      0.70%     11.18% |         128     14.90%     26.08% |         521     60.65%     86.73% |         112     13.04%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total          859                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            3                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean     1.666667                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     1.442250                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev     1.154701                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            3                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            4                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean     1.750000                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     1.565085                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev     0.957427                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           2     50.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            4                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size           64                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket          639                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples            1                      
@@ -557,28 +557,28 @@ system.ruby.LD.Directory.miss_type_mach_latency_hist |           2      5.26%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total           38                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket          159                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           77                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean    24.857143                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     5.046843                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    43.930781                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          61     79.22%     79.22% |           0      0.00%     79.22% |           0      0.00%     79.22% |           0      0.00%     79.22% |           0      0.00%     79.22% |           0      0.00%     79.22% |           9     11.69%     90.91% |           7      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           77                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           78                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean    24.576923                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     5.013300                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    43.714695                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          62     79.49%     79.49% |           0      0.00%     79.49% |           0      0.00%     79.49% |           0      0.00%     79.49% |           0      0.00%     79.49% |           0      0.00%     79.49% |           9     11.54%     91.03% |           7      8.97%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           78                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           45                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1889.022222                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   476.752241                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1641.523495                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          19     42.22%     42.22% |           1      2.22%     44.44% |           0      0.00%     44.44% |           0      0.00%     44.44% |           1      2.22%     46.67% |           9     20.00%     66.67% |          10     22.22%     88.89% |           2      4.44%     93.33% |           3      6.67%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           45                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           43                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1952.279070                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   491.923320                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1633.364659                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          17     39.53%     39.53% |           1      2.33%     41.86% |           0      0.00%     41.86% |           0      0.00%     41.86% |           1      2.33%     44.19% |          10     23.26%     67.44% |           9     20.93%     88.37% |           2      4.65%     93.02% |           3      6.98%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           43                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          768                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3390.100260                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  3119.766603                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   882.096753                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          41      5.34%      5.34% |           5      0.65%      5.99% |         121     15.76%     21.74% |         491     63.93%     85.68% |         108     14.06%     99.74% |           2      0.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total          768                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          775                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3384.810323                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  3117.032073                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   878.738069                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          41      5.29%      5.29% |           5      0.65%      5.94% |         123     15.87%     21.81% |         496     64.00%     85.81% |         108     13.94%     99.74% |           2      0.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total          775                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket          159                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples           11                      
@@ -589,96 +589,96 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist |           8     72.73%
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total           11                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           47                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   416.127660                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   348.839643                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   214.528058                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           3      6.38%      6.38% |           9     19.15%     25.53% |          10     21.28%     46.81% |          11     23.40%     70.21% |           6     12.77%     82.98% |           6     12.77%     95.74% |           1      2.13%     97.87% |           1      2.13%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           47                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           46                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   417.217391                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   350.554490                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   213.226527                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           3      6.52%      6.52% |           8     17.39%     23.91% |          10     21.74%     45.65% |          12     26.09%     71.74% |           5     10.87%     82.61% |           6     13.04%     95.65% |           1      2.17%     97.83% |           1      2.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           46                      
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples            3                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean  3979.666667                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean  3955.937145                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev   544.674521                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total            3                      
-system.ruby.Directory_Controller.GETX             768      0.00%      0.00%
-system.ruby.Directory_Controller.GETS              88      0.00%      0.00%
-system.ruby.Directory_Controller.PUT              927      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM          851      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean           77      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          772      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          856      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          772      0.00%      0.00%
-system.ruby.Directory_Controller.GETF               3      0.00%      0.00%
-system.ruby.Directory_Controller.PUTF               3      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT           846      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX           768      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS            85      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETF             3      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.PUT           81      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM          851      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data          853      0.00%      0.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples            4                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean  3839.250000                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean  3813.994404                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev   525.972987                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total            4                      
+system.ruby.Directory_Controller.GETX             775      0.00%      0.00%
+system.ruby.Directory_Controller.GETS              87      0.00%      0.00%
+system.ruby.Directory_Controller.PUT              933      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM          856      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean           78      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          775      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          863      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          775      0.00%      0.00%
+system.ruby.Directory_Controller.GETF               4      0.00%      0.00%
+system.ruby.Directory_Controller.PUTF               4      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT           851      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX           775      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS            84      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETF             4      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.PUT           82      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM          856      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data          859      0.00%      0.00%
 system.ruby.Directory_Controller.WB.GETS            2      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           77      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          772      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           78      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          775      0.00%      0.00%
 system.ruby.Directory_Controller.WB_E_W.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack          772      0.00%      0.00%
-system.ruby.Directory_Controller.NO_F.PUTF            3      0.00%      0.00%
-system.ruby.Directory_Controller.NO_F_W.Memory_Data            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                44      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              65      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              914      0.00%      0.00%
-system.ruby.L1Cache_Controller.L2_Replacement          848      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_to_L2         15989      0.00%      0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D           46      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack          775      0.00%      0.00%
+system.ruby.Directory_Controller.NO_F.PUTF            4      0.00%      0.00%
+system.ruby.Directory_Controller.NO_F_W.Memory_Data            4      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                45      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              64      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              920      0.00%      0.00%
+system.ruby.L1Cache_Controller.L2_Replacement          854      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_to_L2         16018      0.00%      0.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D           44      0.00%      0.00%
 system.ruby.L1Cache_Controller.Trigger_L2_to_L1I           11      0.00%      0.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1           57      0.00%      0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data          856      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack          849      0.00%      0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers          856      0.00%      0.00%
-system.ruby.L1Cache_Controller.Flush_line            3      0.00%      0.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1           55      0.00%      0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data          863      0.00%      0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack          855      0.00%      0.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers          862      0.00%      0.00%
+system.ruby.L1Cache_Controller.Flush_line            4      0.00%      0.00%
 system.ruby.L1Cache_Controller.I.Load              38      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch            47      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            770      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Flush_line            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement           74      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2           84      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D           10      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Load              2      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Store            77      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement          774      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2          823      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Ifetch            46      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Store            777      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Flush_line            4      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement           75      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2           83      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D            8      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Load              3      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Store            78      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement          779      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2          828      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D           36      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I           11      0.00%      0.00%
 system.ruby.L1Cache_Controller.MR.Load              1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MR.Store             9      0.00%      0.00%
+system.ruby.L1Cache_Controller.MR.Store             7      0.00%      0.00%
 system.ruby.L1Cache_Controller.MR.L1_to_L2           40      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMR.Ifetch           11      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMR.Store           36      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2           63      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2         9575      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data          768      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2           61      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2         9608      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data          775      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.L1_to_L2          412      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers           85      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers           83      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM_W.Load            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2         4225      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers          768      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2         4233      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers          775      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.L1_to_L2          594      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data           85      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data           84      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Load              2      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Ifetch            6      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack          846      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack          851      0.00%      0.00%
 system.ruby.L1Cache_Controller.MT.Store             2      0.00%      0.00%
 system.ruby.L1Cache_Controller.MT.L1_to_L2           52      0.00%      0.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1           10      0.00%      0.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1            8      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMT.Ifetch            1      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMT.Store           20      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2          121      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2          107      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1           47      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI_F.Writeback_Ack            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM_F.Exclusive_Data            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            3      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI_F.Writeback_Ack            4      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM_F.Exclusive_Data            4      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            4      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index 5b3332128..e85a7a6f9 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                             8616438631                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263800                       # Number of bytes of host memory used
-host_seconds                                    11.61                       # Real time elapsed on the host
+host_tick_rate                             8340026204                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263964                       # Number of bytes of host memory used
+host_seconds                                    11.99                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu              106649408                       # Number of bytes read from this memory
@@ -29,7 +29,7 @@ system.physmem.readBursts                     1666397                       # Nu
 system.physmem.writeBursts                    1666879                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                106648000                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 106676864                       # Total number of bytes written to DRAM
+system.physmem.bytesWritten                 106676992                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                 106649408                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys              106680256                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
@@ -40,14 +40,14 @@ system.physmem.perBankRdBursts::1              103995                       # Pe
 system.physmem.perBankRdBursts::2              104918                       # Per bank write bursts
 system.physmem.perBankRdBursts::3              104597                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              103869                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              103935                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              103648                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              104313                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              103868                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              103934                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              103649                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              104312                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              103869                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              104354                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             103835                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             104272                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             104077                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             104273                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             104076                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             104035                       # Per bank write bursts
 system.physmem.perBankRdBursts::14             104583                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             104046                       # Per bank write bursts
@@ -56,17 +56,17 @@ system.physmem.perBankWrBursts::1              104091                       # Pe
 system.physmem.perBankWrBursts::2              104175                       # Per bank write bursts
 system.physmem.perBankWrBursts::3              103885                       # Per bank write bursts
 system.physmem.perBankWrBursts::4              104730                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104507                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              104082                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              104509                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              104084                       # Per bank write bursts
 system.physmem.perBankWrBursts::7              104226                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              104320                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              104319                       # Per bank write bursts
 system.physmem.perBankWrBursts::9              104219                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             104228                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             103702                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             104104                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             103983                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             104227                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             103701                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             104102                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             103984                       # Per bank write bursts
 system.physmem.perBankWrBursts::14             104296                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             103921                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             103923                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
 system.physmem.totGap                     99999956143                       # Total gap between requests
@@ -84,20 +84,20 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1666879                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    750686                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    769672                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     84683                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     33857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     13541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3883                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       720                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    753402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    771059                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     83025                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32311                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     12865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6959                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1736                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       711                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       362                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    15175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    37870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    87757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   105663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   108535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   113878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   112245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   107898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   105677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   126067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   107322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   108328                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   108001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   100239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   100135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   100039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   100007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    12106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    15091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    39564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    91518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   104735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   104786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   114835                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   116330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   106236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   102201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   124996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   116244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   105513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   101800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   100156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   100074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    99950                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    99852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
@@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      3296308                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       64.716127                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      64.192082                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      23.993116                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3288370     99.76%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         5783      0.18%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples      3296341                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       64.715538                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      64.191659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      23.992392                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3288436     99.76%     99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         5750      0.17%     99.93% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639           32      0.00%     99.94% # Bytes accessed per row activation
@@ -193,41 +193,41 @@ system.physmem.bytesPerActivate::640-767           32      0.00%     99.94% # By
 system.physmem.bytesPerActivate::768-895           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151         1963      0.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        3296308                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         99265                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.787065                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       15.442881                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      105.996031                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          99264    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::total        3296341                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         99183                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.800984                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       15.462609                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      106.039262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          99182    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           99265                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         99265                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.791679                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.710831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.758038                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              78980     79.56%     79.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               3022      3.04%     82.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3011      3.03%     85.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1773      1.79%     87.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               1415      1.43%     88.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21               8615      8.68%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22               2003      2.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                293      0.30%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 66      0.07%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 33      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 21      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 21      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  8      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           99265                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    60762575042                       # Total ticks spent queuing
-system.physmem.totMemAccLat               92007106292                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.rdPerTurnAround::total           99183                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         99183                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.805582                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.725629                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.745457                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              77723     78.36%     78.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               3827      3.86%     82.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3399      3.43%     85.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1646      1.66%     87.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                640      0.65%     87.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21              10486     10.57%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22               1261      1.27%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 65      0.07%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 41      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 31      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 25      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 19      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           99183                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    59888739257                       # Total ticks spent queuing
+system.physmem.totMemAccLat               91133270507                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   8331875000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       36463.93                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       35939.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  55213.93                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  54689.53                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1066.48                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                        1066.77                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1066.49                       # Average system read bandwidth in MiByte/s
@@ -236,41 +236,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       8.33                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      8.33                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.71                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      32179                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                      4705                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      32158                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                      4696                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                    1.93                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                   0.28                       # Row buffer hit rate for writes
 system.physmem.avgGap                        30000.50                       # Average gap between requests
 system.physmem.pageHitRate                       1.11                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                12463295040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 6800409000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6499701000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5404592160                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                12463748640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 6800656500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6499693200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5404585680                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             6531436080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            67776382665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              546474000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             106022289945                       # Total energy per rank (pJ)
-system.physmem_0.averagePower             1060.232773                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE      531628571                       # Time in different power states
+system.physmem_0.actBackEnergy            67774130595                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              548449500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             106022700195                       # Total energy per rank (pJ)
+system.physmem_0.averagePower             1060.236875                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE      533126864                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      3339180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     96128273929                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     96126775636                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                12456559080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 6796733625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6497875800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5396304240                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                12456264240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 6796572750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6497883600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5396252400                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             6531436080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            67774932585                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              547746000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             106001587410                       # Total energy per rank (pJ)
-system.physmem_1.averagePower             1060.025746                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE      534269274                       # Time in different power states
+system.physmem_1.actBackEnergy            67770272835                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              551833500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             106000515405                       # Total energy per rank (pJ)
+system.physmem_1.averagePower             1060.015025                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE      539825532                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      3339180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     96125633226                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     96120321460                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.numPackets                         3333276                       # Number of packets generated
 system.cpu.numRetries                               0                       # Number of retries
@@ -285,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port    213329664
 system.membus.pkt_size::total               213329664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.reqLayer0.occupancy         11679751447                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization              11.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        11028299087                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy        11025639931                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             11.0                       # Layer utilization (%)
 system.monitor.readBurstLengthHist::samples      1666397                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
@@ -339,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79            0      0.00%    100.00% #
 system.monitor.writeBurstLengthHist::total      1666879                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::mean     1066494080                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  1063154851.723305                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev  107909478.113936                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean  1063154807.297242                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev  107909912.518316                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
@@ -392,34 +392,34 @@ system.monitor.writeBandwidthHist::total          100                       # Hi
 system.monitor.averageWriteBandwidth       1066802560      0.00%      0.00% # Average write bandwidth (bytes/s)
 system.monitor.totalWrittenBytes            106680256                       # Number of bytes written
 system.monitor.readLatencyHist::samples       1666397                       # Read request-response latency
-system.monitor.readLatencyHist::mean     78736.863581                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    73318.978124                       # Read request-response latency
-system.monitor.readLatencyHist::stdev    40691.515724                       # Read request-response latency
+system.monitor.readLatencyHist::mean     80828.076592                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    75646.741335                       # Read request-response latency
+system.monitor.readLatencyHist::stdev    40157.798719                       # Read request-response latency
 system.monitor.readLatencyHist::0-32767            22      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535       439224     26.36%     26.36% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303      1018381     61.11%     87.47% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071        80826      4.85%     92.32% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839        59766      3.59%     95.91% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607        27643      1.66%     97.57% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375         9933      0.60%     98.16% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143         7785      0.47%     98.63% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911         7834      0.47%     99.10% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679         7851      0.47%     99.57% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447         3709      0.22%     99.79% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215         1488      0.09%     99.88% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983          851      0.05%     99.93% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751          701      0.04%     99.98% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519          330      0.02%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287           51      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::524288-557055            2      0.00%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535       453129     27.19%     27.19% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303      1001108     60.08%     87.27% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071        83302      5.00%     92.27% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839        62543      3.75%     96.02% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607        26583      1.60%     97.62% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375         8788      0.53%     98.14% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143         7679      0.46%     98.61% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911         7849      0.47%     99.08% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679         7873      0.47%     99.55% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447         4044      0.24%     99.79% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215         1554      0.09%     99.88% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983          891      0.05%     99.94% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751          671      0.04%     99.98% # Read request-response latency
+system.monitor.readLatencyHist::458752-491519          316      0.02%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::491520-524287           44      0.00%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::524288-557055            1      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::557056-589823            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::589824-622591            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::622592-655359            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::total         1666397                       # Read request-response latency
 system.monitor.writeLatencyHist::samples      1666878                       # Write request-response latency
-system.monitor.writeLatencyHist::mean    17579.367741                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean   17571.346759                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev     555.431458                       # Write request-response latency
+system.monitor.writeLatencyHist::mean    19578.682028                       # Write request-response latency
+system.monitor.writeLatencyHist::gmean   19571.486505                       # Write request-response latency
+system.monitor.writeLatencyHist::stdev     552.701557                       # Write request-response latency
 system.monitor.writeLatencyHist::0-2047             0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::2048-4095            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::4096-6143            0      0.00%      0.00% # Write request-response latency
@@ -428,11 +428,11 @@ system.monitor.writeLatencyHist::8192-10239            0      0.00%      0.00% #
 system.monitor.writeLatencyHist::10240-12287            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::12288-14335            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::14336-16383            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::16384-18431      1620268     97.20%     97.20% # Write request-response latency
-system.monitor.writeLatencyHist::18432-20479        30675      1.84%     99.04% # Write request-response latency
-system.monitor.writeLatencyHist::20480-22527        12936      0.78%     99.82% # Write request-response latency
-system.monitor.writeLatencyHist::22528-24575         2999      0.18%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::24576-26623            0      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::16384-18431            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::18432-20479      1622054     97.31%     97.31% # Write request-response latency
+system.monitor.writeLatencyHist::20480-22527        29447      1.77%     99.08% # Write request-response latency
+system.monitor.writeLatencyHist::22528-24575        12825      0.77%     99.85% # Write request-response latency
+system.monitor.writeLatencyHist::24576-26623         2552      0.15%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::26624-28671            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::28672-30719            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::30720-32767            0      0.00%    100.00% # Write request-response latency
@@ -526,15 +526,15 @@ system.monitor.ittReqReq::min_value             28000                       # Re
 system.monitor.ittReqReq::max_value           1041309                       # Request-to-request inter transaction time
 system.monitor.ittReqReq::total               3333275                       # Request-to-request inter transaction time
 system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean     1.260000                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean     1.290000                       # Outstanding read transactions
 system.monitor.outstandingReadsHist::gmean            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev     1.284091                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::0             26     26.00%     26.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1             43     43.00%     69.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2             22     22.00%     91.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              4      4.00%     95.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              1      1.00%     96.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              3      3.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev     1.216843                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::0             22     22.00%     22.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1             46     46.00%     68.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2             23     23.00%     91.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3              5      5.00%     96.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::4              1      1.00%     97.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::5              2      2.00%     99.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::6              0      0.00%     99.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::7              0      0.00%     99.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::8              1      1.00%    100.00% # Outstanding read transactions
@@ -551,11 +551,11 @@ system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Ou
 system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
 system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean     0.320000                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::mean     0.340000                       # Outstanding write transactions
 system.monitor.outstandingWritesHist::gmean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev     0.468826                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0            68     68.00%     68.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1            32     32.00%    100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::stdev     0.476095                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::0            66     66.00%     66.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::1            34     34.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
index e54e02dca..2416b8ce8 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            31050955853                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209576                       # Number of bytes of host memory used
-host_seconds                                     3.22                       # Real time elapsed on the host
+host_tick_rate                            16305869412                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265756                       # Number of bytes of host memory used
+host_seconds                                     6.13                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu                     64                       # Number of bytes read from this memory
@@ -191,8 +191,8 @@ system.monitor.writeBandwidthHist::total          100                       # Hi
 system.monitor.averageWriteBandwidth          8533120      0.00%      0.00% # Average write bandwidth (bytes/s)
 system.monitor.totalWrittenBytes               853312                       # Number of bytes written
 system.monitor.readLatencyHist::samples             1                       # Read request-response latency
-system.monitor.readLatencyHist::mean            30000                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    30000.000000                       # Read request-response latency
+system.monitor.readLatencyHist::mean            32000                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    32000.000000                       # Read request-response latency
 system.monitor.readLatencyHist::stdev             nan                       # Read request-response latency
 system.monitor.readLatencyHist::0-2047              0      0.00%      0.00% # Read request-response latency
 system.monitor.readLatencyHist::2048-4095            0      0.00%      0.00% # Read request-response latency
@@ -208,16 +208,16 @@ system.monitor.readLatencyHist::20480-22527            0      0.00%      0.00% #
 system.monitor.readLatencyHist::22528-24575            0      0.00%      0.00% # Read request-response latency
 system.monitor.readLatencyHist::24576-26623            0      0.00%      0.00% # Read request-response latency
 system.monitor.readLatencyHist::26624-28671            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::28672-30719            1    100.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::30720-32767            0      0.00%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::28672-30719            0      0.00%      0.00% # Read request-response latency
+system.monitor.readLatencyHist::30720-32767            1    100.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::32768-34815            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::34816-36863            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::36864-38911            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::38912-40959            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::total               1                       # Read request-response latency
 system.monitor.writeLatencyHist::samples        13333                       # Write request-response latency
-system.monitor.writeLatencyHist::mean    30000.024601                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean   30000.024467                       # Write request-response latency
+system.monitor.writeLatencyHist::mean    32000.024601                       # Write request-response latency
+system.monitor.writeLatencyHist::gmean   32000.024475                       # Write request-response latency
 system.monitor.writeLatencyHist::stdev       2.840599                       # Write request-response latency
 system.monitor.writeLatencyHist::0-2047             0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::2048-4095            0      0.00%      0.00% # Write request-response latency
@@ -233,8 +233,8 @@ system.monitor.writeLatencyHist::20480-22527            0      0.00%      0.00%
 system.monitor.writeLatencyHist::22528-24575            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::24576-26623            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::26624-28671            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::28672-30719        13333    100.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::30720-32767            0      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::28672-30719            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::30720-32767        13333    100.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::32768-34815            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::34816-36863            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::36864-38911            0      0.00%    100.00% # Write request-response latency
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 85445221a..925ba174e 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118729                       # Nu
 sim_ticks                                118729316500                       # Number of ticks simulated
 final_tick                               118729316500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1507080                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1507080                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1946992285                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297820                       # Number of bytes of host memory used
-host_seconds                                    60.98                       # Real time elapsed on the host
+host_inst_rate                                1465795                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1465795                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1893656296                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298240                       # Number of bytes of host memory used
+host_seconds                                    62.70                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   91903089                       # Class of executed instruction
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1442.043377                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1442.043368                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          11918.613585                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1442.043377                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1442.043368                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.352061                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.352061                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
@@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2223
 system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     23186500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     23186500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     92426000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     92426000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    115612500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    115612500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    115612500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    115612500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     23424000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     23424000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     93300000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     93300000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    116724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    116724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    116724000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    116724000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
@@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53375.286041                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53375.286041                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52507.422402                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52507.422402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52507.422402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52507.422402                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              6681                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1418.052759                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1418.052751                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            91894580                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              8510                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          10798.423032                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1418.052759                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1418.052751                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.692409                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.692409                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
@@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         8510
 system.cpu.icache.demand_mshr_misses::total         8510                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         8510                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         8510                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    207947500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    207947500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    207947500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    207947500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    207947500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    207947500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    212202500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    212202500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    212202500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    212202500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    212202500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    212202500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000093                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000093                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24935.663925                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24935.663925                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24935.663925                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24935.663925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24935.663925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24935.663925                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2074.070538                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               5956                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2074.070486                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              12687                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3109                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.915729                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.080733                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks    17.795177                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1705.017985                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   351.257376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1705.017940                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   351.257369                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052033                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010720                       # Average percentage of cache occupancy
@@ -337,72 +337,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          221
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          703                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2096                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.094879                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            91577                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           91577                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses           145425                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          145425                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5889                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         5889                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           53                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           53                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         5889                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total            5968                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         5889                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
 system.cpu.l2cache.overall_hits::total           5968                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2621                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3043                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1722                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1722                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2621                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2621                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          422                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          422                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2621                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         2144                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          4765                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2621                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         4765                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    137603000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     22155000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    159758000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     90405000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total     90405000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    137603000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    137603000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     22155000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     22155000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst    137603000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data    112560000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total    250163000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst    137603000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    112560000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    250163000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         8510                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         8985                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8510                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8510                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          475                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          475                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         8510                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total        10733                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         8510                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total        10733                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.307991                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.338676                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.307991                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.307991                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.888421                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.307991                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.443958                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.307991                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.443958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.190767                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.190767                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932                       # average overall miss latency
@@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2621                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3043                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2621                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2621                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          422                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          422                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2621                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         4765                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2621                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         4765                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106150500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17091000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    123241500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     69741000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     69741000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106150500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     86832000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    192982500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106150500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     86832000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    192982500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.338676                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     73185000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     73185000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    111393000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    111393000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     17935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     17935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    111393000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     91120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    202513000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    111393000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     91120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    202513000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.307991                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.888421                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.443958                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.443958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.190767                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.190767                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.190767                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.104932                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           8985                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          8985                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1748                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1748                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17020                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4553                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             21573                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         8510                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          475                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23701                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4603                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             28304                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       544640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149120                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             693760                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        10840                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        17571                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              10840    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              17571    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          10840                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5527000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          17571                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        8892500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      12765000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3334500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3043                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3043                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1722                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3043                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         9530                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   9530                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       304960                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index c495da061..dfc2f4ccb 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.230173                       # Nu
 sim_ticks                                230173358500                       # Number of ticks simulated
 final_tick                               230173358500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 794003                       # Simulator instruction rate (inst/s)
-host_op_rate                                   837080                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1063522318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308720                       # Number of bytes of host memory used
-host_seconds                                   216.43                       # Real time elapsed on the host
+host_inst_rate                                1194511                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1259316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1599980237                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316228                       # Number of bytes of host memory used
+host_seconds                                   143.86                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  181650743                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.619271                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1363.619267                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619271                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619267                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332915                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332915                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
@@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1788
 system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34437000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34437000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     58544500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     58544500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92981500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     92981500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     93035000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     93035000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34781000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34781000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59094500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     59094500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        54000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     93875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     93875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     93929500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     93929500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1506                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1147.992594                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1147.992590                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857002                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3051                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          62227.794821                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1147.992594                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1147.992590                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.560543                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.560543                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
@@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3051
 system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    107794500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    107794500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    107794500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    107794500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    107794500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    107794500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    109320000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    109320000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    109320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    109320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    109320000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    109320000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1675.663342                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               1380                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1675.663321                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2846                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             2369                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.582524                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.201351                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks     3.037779                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.036747                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   503.588816                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.036732                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   503.588811                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
@@ -447,72 +447,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          320
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1679                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.072296                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            42317                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           42317                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses            54045                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           54045                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1322                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1322                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           57                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           57                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         1322                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           65                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total            1387                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         1322                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           65                       # number of overall hits
 system.cpu.l2cache.overall_hits::total           1387                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1729                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2361                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1092                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1092                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1729                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1729                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          632                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          632                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         1729                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         1724                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          3453                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     90862500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     33203000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    124065500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     57360500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total     57360500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     90862500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     90862500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     33203000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     33203000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     90862500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data     90563500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total    181426000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     90862500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data     90563500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    181426000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         3051                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          689                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         3740                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1100                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         3051                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         3051                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          689                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          689                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         3051                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         1789                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total         4840                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         3051                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         1789                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total         4840                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.566699                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.917271                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.631283                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992727                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.566699                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.566699                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.917271                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.917271                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.566699                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.963667                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.713430                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065                       # average overall miss latency
@@ -527,84 +533,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1729                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          632                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2361                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1092                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1729                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1729                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          632                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          632                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         1729                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1724                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         3453                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1729                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1724                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3453                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     70024500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25596000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     95620500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     44226000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     44226000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     70024500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     69822000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    139846500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     70024500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     69822000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    139846500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.917271                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.631283                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     46440500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     46440500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     73572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     73572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     26883000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     26883000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     73572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     73323500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    146896000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     73572500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     73323500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    146896000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992727                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.566699                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.917271                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.917271                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.713430                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.713430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         1466                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1100                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1100                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         6102                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3594                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              9696                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         3051                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          689                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         7550                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3612                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             11162                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       195264                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       115520                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             310784                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         4856                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         6386                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4856    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               6386    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           4856                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        2444000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           6386                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        3209000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       4576500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2683500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2361                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         6906                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   6906                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       220992                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index e9f2af2a4..221e57a79 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270563                       # Nu
 sim_ticks                                270563082500                       # Number of ticks simulated
 final_tick                               270563082500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1283602                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1283603                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1795321724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297332                       # Number of bytes of host memory used
-host_seconds                                   150.70                       # Real time elapsed on the host
+host_inst_rate                                1293394                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1293395                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1809017316                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297764                       # Number of bytes of host memory used
+host_seconds                                   149.56                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  193445773                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 2                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1237.203936                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1237.203933                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            76732337                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1576                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          48688.031091                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1237.203936                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1237.203933                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.302052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.302052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1574                       # Occupied blocks per task id
@@ -187,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1575
 system.cpu.dcache.demand_mshr_misses::total         1575                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1575                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1575                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26643000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     26643000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57619500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     57619500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        53500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        53500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     84262500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     84262500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     84262500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     84262500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26892000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     26892000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     58158000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     58158000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        54000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        54000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     85050000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     85050000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     85050000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     85050000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000057                       # mshr miss rate for WriteReq accesses
@@ -207,24 +207,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000021
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000021                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000021                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        53500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        53500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        54000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        54000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10362                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1591.579164                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1591.579161                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           193433248                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             12288                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          15741.638021                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1591.579164                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1591.579161                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.777138                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.777138                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1926                       # Occupied blocks per task id
@@ -286,34 +286,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        12288
 system.cpu.icache.demand_mshr_misses::total        12288                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        12288                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        12288                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    292386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    292386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    292386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    292386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    292386500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    292386500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    298530500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    298530500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    298530500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    298530500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    298530500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    298530500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000064                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000064                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000064                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2678.340853                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8691                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2678.340822                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              19053                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4097                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.121308                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.650476                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks     0.000453                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2275.282913                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   403.057487                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2275.282887                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   403.057483                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069436                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
@@ -325,67 +325,72 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          625                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2688                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.125031                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           116103                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          116103                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses           198999                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          198999                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total            2                       # number of Writeback hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8691                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8691                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         8691                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total            8691                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         8691                       # number of overall hits
 system.cpu.l2cache.overall_hits::total           8691                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3597                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4095                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1078                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1078                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3597                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3597                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          498                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          498                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         3597                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         1576                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          5173                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         3597                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1576                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5173                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    188843000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     26145000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    214988000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56595000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total     56595000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    188843000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    188843000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     26145000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     26145000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst    188843000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data     82740000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total    271583000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst    188843000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data     82740000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    271583000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        12288                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          498                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        12786                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks            2                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total            2                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1078                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1078                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12288                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        12288                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          498                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          498                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        12288                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         1576                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total        13864                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        12288                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         1576                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total        13864                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.292725                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.320272                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.292725                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.292725                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.292725                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.373125                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.292725                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.373125                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656                       # average overall miss latency
@@ -400,84 +405,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4095                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1078                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3597                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3597                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          498                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          498                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         3597                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1576                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3597                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1576                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    145678500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     20169000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    165847500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     43659000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     43659000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    145678500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     63828000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    209506500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    145678500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     63828000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    209506500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.320272                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     45815000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     45815000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    152873000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    152873000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     21165000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     21165000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    152873000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     66980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    219853000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    152873000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     66980000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    219853000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.292725                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.373125                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.373125                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          12786                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         12786                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        10362                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1078                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1078                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24576                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12288                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          498                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        34938                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             27730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             38092                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       786432                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       100992                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             887424                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13866                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        24228                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              13866    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              24228    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13866                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        6935000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          24228                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       12116000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      18432000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2364000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4095                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4095                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1078                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1078                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4095                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10346                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  10346                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       331072                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index af03b59c5..395ca7a25 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250954                       # Nu
 sim_ticks                                250953957500                       # Number of ticks simulated
 final_tick                               250953957500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 582427                       # Simulator instruction rate (inst/s)
-host_op_rate                                   976201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1106694320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282016                       # Number of bytes of host memory used
-host_seconds                                   226.76                       # Real time elapsed on the host
+host_inst_rate                                 750520                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1257940                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1426094126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 340216                       # Number of bytes of host memory used
+host_seconds                                   175.97                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -93,12 +93,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  221363385                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                41                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.457564                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1363.457561                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            77195831                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1905                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          40522.745932                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.457564                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.457561                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332875                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332875                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1864                       # Occupied blocks per task id
@@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1905
 system.cpu.dcache.demand_mshr_misses::total         1905                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1905                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1905                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17202000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     17202000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     84297000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     84297000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    101499000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    101499000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    101499000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    101499000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17365500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17365500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85086000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85086000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    102451500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    102451500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    102451500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    102451500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000077                       # mshr miss rate for WriteReq accesses
@@ -192,22 +192,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2836                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1455.296636                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1455.296632                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           173489673                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4694                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          36959.879207                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1455.296636                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1455.296632                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.710594                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.710594                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
@@ -269,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         4694
 system.cpu.icache.demand_mshr_misses::total         4694                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4694                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4694                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    173278500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    173278500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    173278500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    173278500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    173278500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    173278500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    175625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    175625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    175625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    175625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175625500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    175625500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000027                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2058.178675                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               1862                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2058.178650                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               4732                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3164                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.588496                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.495575                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks     0.021744                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1829.978570                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   228.178361                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1829.978548                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   228.178359                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055847                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
@@ -308,72 +308,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          513
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          516                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2064                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.096558                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            57590                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           57590                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         1854                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data            7                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           1861                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses            80550                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           80550                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks            7                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total            7                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            3                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            3                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1854                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1854                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data            7                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total            7                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         1854                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           10                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total            1864                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         1854                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           10                       # number of overall hits
 system.cpu.l2cache.overall_hits::total           1864                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2840                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          320                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3160                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1575                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1575                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2840                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2840                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          320                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          320                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2840                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         1895                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          4735                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2840                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1895                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         4735                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    149117500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16801500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    165919000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     82687500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total     82687500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    149117500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    149117500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     16801500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     16801500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst    149117500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data     99489000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total    248606500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst    149117500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data     99489000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    248606500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4694                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          327                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5021                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks            7                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total            7                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4694                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4694                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          327                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          327                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         4694                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total         6599                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         4694                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total         6599                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.605028                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.978593                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.629357                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.998099                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.998099                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.605028                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.605028                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.978593                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.978593                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.605028                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.994751                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.717533                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.605028                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.994751                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.717533                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672                       # average overall miss latency
@@ -388,84 +394,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2840                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          320                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3160                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1575                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1575                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2840                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2840                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          320                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          320                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2840                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1895                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         4735                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2840                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1895                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         4735                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    115020000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12960000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    127980000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     63787500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     63787500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    115020000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     76747500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    191767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    115020000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     76747500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    191767500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.978593                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.629357                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     66937500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     66937500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    120717500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    120717500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     13601500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     13601500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    120717500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     80539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    201256500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    120717500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     80539000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    201256500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.998099                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.998099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.605028                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.978593                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.978593                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.717533                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.717533                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           5021                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          5021                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1578                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1578                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9388                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3817                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             13205                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4694                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          327                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12224                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3851                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             16075                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       300416                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       122368                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             422784                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6606                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9476                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               6606    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               9476    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6606                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        3310000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9476                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        4745000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       7041000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2857500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3160                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3160                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1575                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1575                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3160                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         9470                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total         9470                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   9470                       # Packet count per connected master and slave (bytes)